1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33#include <asm/fixmap.h> 34#include <asm/export.h> 35 36/* Macro to make the code more readable. */ 37#ifdef CONFIG_8xx_CPU6 38#define SPRN_MI_TWC_ADDR 0x2b80 39#define SPRN_MI_RPN_ADDR 0x2d80 40#define SPRN_MD_TWC_ADDR 0x3b80 41#define SPRN_MD_RPN_ADDR 0x3d80 42 43#define MTSPR_CPU6(spr, reg, treg) \ 44 li treg, spr##_ADDR; \ 45 stw treg, 12(r0); \ 46 lwz treg, 12(r0); \ 47 mtspr spr, reg 48#else 49#define MTSPR_CPU6(spr, reg, treg) \ 50 mtspr spr, reg 51#endif 52 53/* Macro to test if an address is a kernel address */ 54#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 55#define IS_KERNEL(tmp, addr) \ 56 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */ 57#define BRANCH_UNLESS_KERNEL(label) beq label 58#else 59#define IS_KERNEL(tmp, addr) \ 60 rlwinm tmp, addr, 16, 16, 31; \ 61 cmpli cr0, tmp, PAGE_OFFSET >> 16 62#define BRANCH_UNLESS_KERNEL(label) blt label 63#endif 64 65 66/* 67 * Value for the bits that have fixed value in RPN entries. 68 * Also used for tagging DAR for DTLBerror. 69 */ 70#ifdef CONFIG_PPC_16K_PAGES 71#define RPN_PATTERN (0x00f0 | MD_SPS16K) 72#else 73#define RPN_PATTERN 0x00f0 74#endif 75 76 __HEAD 77_ENTRY(_stext); 78_ENTRY(_start); 79 80/* MPC8xx 81 * This port was done on an MBX board with an 860. Right now I only 82 * support an ELF compressed (zImage) boot from EPPC-Bug because the 83 * code there loads up some registers before calling us: 84 * r3: ptr to board info data 85 * r4: initrd_start or if no initrd then 0 86 * r5: initrd_end - unused if r4 is 0 87 * r6: Start of command line string 88 * r7: End of command line string 89 * 90 * I decided to use conditional compilation instead of checking PVR and 91 * adding more processor specific branches around code I don't need. 92 * Since this is an embedded processor, I also appreciate any memory 93 * savings I can get. 94 * 95 * The MPC8xx does not have any BATs, but it supports large page sizes. 96 * We first initialize the MMU to support 8M byte pages, then load one 97 * entry into each of the instruction and data TLBs to map the first 98 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 99 * the "internal" processor registers before MMU_init is called. 100 * 101 * -- Dan 102 */ 103 .globl __start 104__start: 105 mr r31,r3 /* save device tree ptr */ 106 107 /* We have to turn on the MMU right away so we get cache modes 108 * set correctly. 109 */ 110 bl initial_mmu 111 112/* We now have the lower 8 Meg mapped into TLB entries, and the caches 113 * ready to work. 114 */ 115 116turn_on_mmu: 117 mfmsr r0 118 ori r0,r0,MSR_DR|MSR_IR 119 mtspr SPRN_SRR1,r0 120 lis r0,start_here@h 121 ori r0,r0,start_here@l 122 mtspr SPRN_SRR0,r0 123 SYNC 124 rfi /* enables MMU */ 125 126/* 127 * Exception entry code. This code runs with address translation 128 * turned off, i.e. using physical addresses. 129 * We assume sprg3 has the physical address of the current 130 * task's thread_struct. 131 */ 132#define EXCEPTION_PROLOG \ 133 EXCEPTION_PROLOG_0; \ 134 mfcr r10; \ 135 EXCEPTION_PROLOG_1; \ 136 EXCEPTION_PROLOG_2 137 138#define EXCEPTION_PROLOG_0 \ 139 mtspr SPRN_SPRG_SCRATCH0,r10; \ 140 mtspr SPRN_SPRG_SCRATCH1,r11 141 142#define EXCEPTION_PROLOG_1 \ 143 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 144 andi. r11,r11,MSR_PR; \ 145 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 146 beq 1f; \ 147 mfspr r11,SPRN_SPRG_THREAD; \ 148 lwz r11,THREAD_INFO-THREAD(r11); \ 149 addi r11,r11,THREAD_SIZE; \ 150 tophys(r11,r11); \ 1511: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 152 153 154#define EXCEPTION_PROLOG_2 \ 155 stw r10,_CCR(r11); /* save registers */ \ 156 stw r12,GPR12(r11); \ 157 stw r9,GPR9(r11); \ 158 mfspr r10,SPRN_SPRG_SCRATCH0; \ 159 stw r10,GPR10(r11); \ 160 mfspr r12,SPRN_SPRG_SCRATCH1; \ 161 stw r12,GPR11(r11); \ 162 mflr r10; \ 163 stw r10,_LINK(r11); \ 164 mfspr r12,SPRN_SRR0; \ 165 mfspr r9,SPRN_SRR1; \ 166 stw r1,GPR1(r11); \ 167 stw r1,0(r11); \ 168 tovirt(r1,r11); /* set new kernel sp */ \ 169 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 170 MTMSRD(r10); /* (except for mach check in rtas) */ \ 171 stw r0,GPR0(r11); \ 172 SAVE_4GPRS(3, r11); \ 173 SAVE_2GPRS(7, r11) 174 175/* 176 * Exception exit code. 177 */ 178#define EXCEPTION_EPILOG_0 \ 179 mfspr r10,SPRN_SPRG_SCRATCH0; \ 180 mfspr r11,SPRN_SPRG_SCRATCH1 181 182/* 183 * Note: code which follows this uses cr0.eq (set if from kernel), 184 * r11, r12 (SRR0), and r9 (SRR1). 185 * 186 * Note2: once we have set r1 we are in a position to take exceptions 187 * again, and we could thus set MSR:RI at that point. 188 */ 189 190/* 191 * Exception vectors. 192 */ 193#define EXCEPTION(n, label, hdlr, xfer) \ 194 . = n; \ 195label: \ 196 EXCEPTION_PROLOG; \ 197 addi r3,r1,STACK_FRAME_OVERHEAD; \ 198 xfer(n, hdlr) 199 200#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 201 li r10,trap; \ 202 stw r10,_TRAP(r11); \ 203 li r10,MSR_KERNEL; \ 204 copyee(r10, r9); \ 205 bl tfer; \ 206i##n: \ 207 .long hdlr; \ 208 .long ret 209 210#define COPY_EE(d, s) rlwimi d,s,0,16,16 211#define NOCOPY(d, s) 212 213#define EXC_XFER_STD(n, hdlr) \ 214 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 215 ret_from_except_full) 216 217#define EXC_XFER_LITE(n, hdlr) \ 218 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 219 ret_from_except) 220 221#define EXC_XFER_EE(n, hdlr) \ 222 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 223 ret_from_except_full) 224 225#define EXC_XFER_EE_LITE(n, hdlr) \ 226 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 227 ret_from_except) 228 229/* System reset */ 230 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD) 231 232/* Machine check */ 233 . = 0x200 234MachineCheck: 235 EXCEPTION_PROLOG 236 mfspr r4,SPRN_DAR 237 stw r4,_DAR(r11) 238 li r5,RPN_PATTERN 239 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 240 mfspr r5,SPRN_DSISR 241 stw r5,_DSISR(r11) 242 addi r3,r1,STACK_FRAME_OVERHEAD 243 EXC_XFER_STD(0x200, machine_check_exception) 244 245/* Data access exception. 246 * This is "never generated" by the MPC8xx. 247 */ 248 . = 0x300 249DataAccess: 250 251/* Instruction access exception. 252 * This is "never generated" by the MPC8xx. 253 */ 254 . = 0x400 255InstructionAccess: 256 257/* External interrupt */ 258 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 259 260/* Alignment exception */ 261 . = 0x600 262Alignment: 263 EXCEPTION_PROLOG 264 mfspr r4,SPRN_DAR 265 stw r4,_DAR(r11) 266 li r5,RPN_PATTERN 267 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 268 mfspr r5,SPRN_DSISR 269 stw r5,_DSISR(r11) 270 addi r3,r1,STACK_FRAME_OVERHEAD 271 EXC_XFER_EE(0x600, alignment_exception) 272 273/* Program check exception */ 274 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 275 276/* No FPU on MPC8xx. This exception is not supposed to happen. 277*/ 278 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 279 280/* Decrementer */ 281 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 282 283 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 284 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 285 286/* System call */ 287 . = 0xc00 288SystemCall: 289 EXCEPTION_PROLOG 290 EXC_XFER_EE_LITE(0xc00, DoSyscall) 291 292/* Single step - not used on 601 */ 293 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 294 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 295 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 296 297/* On the MPC8xx, this is a software emulation interrupt. It occurs 298 * for all unimplemented and illegal instructions. 299 */ 300 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 301 302 . = 0x1100 303/* 304 * For the MPC8xx, this is a software tablewalk to load the instruction 305 * TLB. The task switch loads the M_TW register with the pointer to the first 306 * level table. 307 * If we discover there is no second level table (value is zero) or if there 308 * is an invalid pte, we load that into the TLB, which causes another fault 309 * into the TLB Error interrupt where we can handle such problems. 310 * We have to use the MD_xxx registers for the tablewalk because the 311 * equivalent MI_xxx registers only perform the attribute functions. 312 */ 313 314#ifdef CONFIG_8xx_CPU15 315#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ 316 addi tmp, addr, PAGE_SIZE; \ 317 tlbie tmp; \ 318 addi tmp, addr, -PAGE_SIZE; \ 319 tlbie tmp 320#else 321#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) 322#endif 323 324InstructionTLBMiss: 325#if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) 326 mtspr SPRN_SPRG_SCRATCH2, r3 327#endif 328 EXCEPTION_PROLOG_0 329 330 /* If we are faulting a kernel address, we have to use the 331 * kernel page tables. 332 */ 333 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 334 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) 335#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) 336 /* Only modules will cause ITLB Misses as we always 337 * pin the first 8MB of kernel memory */ 338 mfcr r3 339 IS_KERNEL(r11, r10) 340#endif 341 mfspr r11, SPRN_M_TW /* Get level 1 table */ 342#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) 343 BRANCH_UNLESS_KERNEL(3f) 344 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3453: 346 mtcr r3 347#endif 348 /* Insert level 1 index */ 349 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 350 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 351 352 /* Extract level 2 index */ 353 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 354 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 355 lwz r10, 0(r10) /* Get the pte */ 356 357 /* Insert the APG into the TWC from the Linux PTE. */ 358 rlwimi r11, r10, 0, 25, 26 359 /* Load the MI_TWC with the attributes for this "segment." */ 360 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ 361 362#ifdef CONFIG_SWAP 363 rlwinm r11, r10, 32-5, _PAGE_PRESENT 364 and r11, r11, r10 365 rlwimi r10, r11, 0, _PAGE_PRESENT 366#endif 367 li r11, RPN_PATTERN 368 /* The Linux PTE won't go exactly into the MMU TLB. 369 * Software indicator bits 20-23 and 28 must be clear. 370 * Software indicator bits 24, 25, 26, and 27 must be 371 * set. All other Linux PTE bits control the behavior 372 * of the MMU. 373 */ 374 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */ 375 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */ 376 377 /* Restore registers */ 378#if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) 379 mfspr r3, SPRN_SPRG_SCRATCH2 380#endif 381 EXCEPTION_EPILOG_0 382 rfi 383 384 . = 0x1200 385DataStoreTLBMiss: 386 mtspr SPRN_SPRG_SCRATCH2, r3 387 EXCEPTION_PROLOG_0 388 mfcr r3 389 390 /* If we are faulting a kernel address, we have to use the 391 * kernel page tables. 392 */ 393 mfspr r10, SPRN_MD_EPN 394 rlwinm r10, r10, 16, 0xfff8 395 cmpli cr0, r10, PAGE_OFFSET@h 396 mfspr r11, SPRN_M_TW /* Get level 1 table */ 397 blt+ 3f 398#ifndef CONFIG_PIN_TLB_IMMR 399 cmpli cr0, r10, VIRT_IMMR_BASE@h 400#endif 401_ENTRY(DTLBMiss_cmp) 402 cmpli cr7, r10, (PAGE_OFFSET + 0x1800000)@h 403 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 404#ifndef CONFIG_PIN_TLB_IMMR 405_ENTRY(DTLBMiss_jmp) 406 beq- DTLBMissIMMR 407#endif 408 blt cr7, DTLBMissLinear 4093: 410 mtcr r3 411 mfspr r10, SPRN_MD_EPN 412 413 /* Insert level 1 index */ 414 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 415 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 416 417 /* We have a pte table, so load fetch the pte from the table. 418 */ 419 /* Extract level 2 index */ 420 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 421 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 422 lwz r10, 0(r10) /* Get the pte */ 423 424 /* Insert the Guarded flag and APG into the TWC from the Linux PTE. 425 * It is bit 26-27 of both the Linux PTE and the TWC (at least 426 * I got that right :-). It will be better when we can put 427 * this into the Linux pgd/pmd and load it in the operation 428 * above. 429 */ 430 rlwimi r11, r10, 0, 26, 27 431 /* Insert the WriteThru flag into the TWC from the Linux PTE. 432 * It is bit 25 in the Linux PTE and bit 30 in the TWC 433 */ 434 rlwimi r11, r10, 32-5, 30, 30 435 MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 436 437 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 438 * We also need to know if the insn is a load/store, so: 439 * Clear _PAGE_PRESENT and load that which will 440 * trap into DTLB Error with store bit set accordinly. 441 */ 442 /* PRESENT=0x1, ACCESSED=0x20 443 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 444 * r10 = (r10 & ~PRESENT) | r11; 445 */ 446#ifdef CONFIG_SWAP 447 rlwinm r11, r10, 32-5, _PAGE_PRESENT 448 and r11, r11, r10 449 rlwimi r10, r11, 0, _PAGE_PRESENT 450#endif 451 /* The Linux PTE won't go exactly into the MMU TLB. 452 * Software indicator bits 22 and 28 must be clear. 453 * Software indicator bits 24, 25, 26, and 27 must be 454 * set. All other Linux PTE bits control the behavior 455 * of the MMU. 456 */ 457 li r11, RPN_PATTERN 458 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 459 rlwimi r10, r11, 0, 20, 20 /* clear 20 */ 460 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ 461 462 /* Restore registers */ 463 mfspr r3, SPRN_SPRG_SCRATCH2 464 mtspr SPRN_DAR, r11 /* Tag DAR */ 465 EXCEPTION_EPILOG_0 466 rfi 467 468 469/* This is an instruction TLB error on the MPC8xx. This could be due 470 * to many reasons, such as executing guarded memory or illegal instruction 471 * addresses. There is nothing to do but handle a big time error fault. 472 */ 473 . = 0x1300 474InstructionTLBError: 475 EXCEPTION_PROLOG 476 mr r4,r12 477 mr r5,r9 478 andis. r10,r5,0x4000 479 beq+ 1f 480 tlbie r4 481 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 4821: EXC_XFER_LITE(0x400, handle_page_fault) 483 484/* This is the data TLB error on the MPC8xx. This could be due to 485 * many reasons, including a dirty update to a pte. We bail out to 486 * a higher level function that can handle it. 487 */ 488 . = 0x1400 489DataTLBError: 490 EXCEPTION_PROLOG_0 491 mfcr r10 492 493 mfspr r11, SPRN_DAR 494 cmpwi cr0, r11, RPN_PATTERN 495 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 496DARFixed:/* Return from dcbx instruction bug workaround */ 497 EXCEPTION_PROLOG_1 498 EXCEPTION_PROLOG_2 499 mfspr r5,SPRN_DSISR 500 stw r5,_DSISR(r11) 501 mfspr r4,SPRN_DAR 502 andis. r10,r5,0x4000 503 beq+ 1f 504 tlbie r4 5051: li r10,RPN_PATTERN 506 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 507 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 508 EXC_XFER_LITE(0x300, handle_page_fault) 509 510 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 511 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 512 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 513 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 514 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 515 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 516 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 517 518/* On the MPC8xx, these next four traps are used for development 519 * support of breakpoints and such. Someday I will get around to 520 * using them. 521 */ 522 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 523 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 524 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 525 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 526 527 . = 0x2000 528 529/* 530 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM. 531 * not enough space in the DataStoreTLBMiss area. 532 */ 533DTLBMissIMMR: 534 mtcr r3 535 /* Set 512k byte guarded page and mark it valid */ 536 li r10, MD_PS512K | MD_GUARDED | MD_SVALID 537 MTSPR_CPU6(SPRN_MD_TWC, r10, r11) 538 mfspr r10, SPRN_IMMR /* Get current IMMR */ 539 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ 540 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 541 _PAGE_PRESENT | _PAGE_NO_CACHE 542 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 543 544 li r11, RPN_PATTERN 545 mtspr SPRN_DAR, r11 /* Tag DAR */ 546 mfspr r3, SPRN_SPRG_SCRATCH2 547 EXCEPTION_EPILOG_0 548 rfi 549 550DTLBMissLinear: 551 mtcr r3 552 /* Set 8M byte page and mark it valid */ 553 li r11, MD_PS8MEG | MD_SVALID 554 MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 555 rlwinm r10, r10, 16, 0x0f800000 /* 8xx supports max 256Mb RAM */ 556 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 557 _PAGE_PRESENT 558 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 559 560 li r11, RPN_PATTERN 561 mtspr SPRN_DAR, r11 /* Tag DAR */ 562 mfspr r3, SPRN_SPRG_SCRATCH2 563 EXCEPTION_EPILOG_0 564 rfi 565 566/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 567 * by decoding the registers used by the dcbx instruction and adding them. 568 * DAR is set to the calculated address. 569 */ 570 /* define if you don't want to use self modifying code */ 571#define NO_SELF_MODIFYING_CODE 572FixupDAR:/* Entry point for dcbx workaround. */ 573 mtspr SPRN_SPRG_SCRATCH2, r10 574 /* fetch instruction from memory. */ 575 mfspr r10, SPRN_SRR0 576 IS_KERNEL(r11, r10) 577 mfspr r11, SPRN_M_TW /* Get level 1 table */ 578 BRANCH_UNLESS_KERNEL(3f) 579 rlwinm r11, r10, 16, 0xfff8 580_ENTRY(FixupDAR_cmp) 581 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 582 /* create physical page address from effective address */ 583 tophys(r11, r10) 584 blt- cr7, 201f 585 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 586 /* Insert level 1 index */ 5873: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 588 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 589 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ 590 /* Insert level 2 index */ 591 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 592 lwz r11, 0(r11) /* Get the pte */ 593 /* concat physical page address(r11) and page offset(r10) */ 594 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 595201: lwz r11,0(r11) 596/* Check if it really is a dcbx instruction. */ 597/* dcbt and dcbtst does not generate DTLB Misses/Errors, 598 * no need to include them here */ 599 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 600 rlwinm r10, r10, 0, 21, 5 601 cmpwi cr0, r10, 2028 /* Is dcbz? */ 602 beq+ 142f 603 cmpwi cr0, r10, 940 /* Is dcbi? */ 604 beq+ 142f 605 cmpwi cr0, r10, 108 /* Is dcbst? */ 606 beq+ 144f /* Fix up store bit! */ 607 cmpwi cr0, r10, 172 /* Is dcbf? */ 608 beq+ 142f 609 cmpwi cr0, r10, 1964 /* Is icbi? */ 610 beq+ 142f 611141: mfspr r10,SPRN_SPRG_SCRATCH2 612 b DARFixed /* Nope, go back to normal TLB processing */ 613 614144: mfspr r10, SPRN_DSISR 615 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 616 mtspr SPRN_DSISR, r10 617142: /* continue, it was a dcbx, dcbi instruction. */ 618#ifndef NO_SELF_MODIFYING_CODE 619 andis. r10,r11,0x1f /* test if reg RA is r0 */ 620 li r10,modified_instr@l 621 dcbtst r0,r10 /* touch for store */ 622 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 623 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 624 ori r11,r11,532 625 stw r11,0(r10) /* store add/and instruction */ 626 dcbf 0,r10 /* flush new instr. to memory. */ 627 icbi 0,r10 /* invalidate instr. cache line */ 628 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ 629 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ 630 isync /* Wait until new instr is loaded from memory */ 631modified_instr: 632 .space 4 /* this is where the add instr. is stored */ 633 bne+ 143f 634 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 635143: mtdar r10 /* store faulting EA in DAR */ 636 mfspr r10,SPRN_SPRG_SCRATCH2 637 b DARFixed /* Go back to normal TLB handling */ 638#else 639 mfctr r10 640 mtdar r10 /* save ctr reg in DAR */ 641 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 642 addi r10, r10, 150f@l /* add start of table */ 643 mtctr r10 /* load ctr with jump address */ 644 xor r10, r10, r10 /* sum starts at zero */ 645 bctr /* jump into table */ 646150: 647 add r10, r10, r0 ;b 151f 648 add r10, r10, r1 ;b 151f 649 add r10, r10, r2 ;b 151f 650 add r10, r10, r3 ;b 151f 651 add r10, r10, r4 ;b 151f 652 add r10, r10, r5 ;b 151f 653 add r10, r10, r6 ;b 151f 654 add r10, r10, r7 ;b 151f 655 add r10, r10, r8 ;b 151f 656 add r10, r10, r9 ;b 151f 657 mtctr r11 ;b 154f /* r10 needs special handling */ 658 mtctr r11 ;b 153f /* r11 needs special handling */ 659 add r10, r10, r12 ;b 151f 660 add r10, r10, r13 ;b 151f 661 add r10, r10, r14 ;b 151f 662 add r10, r10, r15 ;b 151f 663 add r10, r10, r16 ;b 151f 664 add r10, r10, r17 ;b 151f 665 add r10, r10, r18 ;b 151f 666 add r10, r10, r19 ;b 151f 667 add r10, r10, r20 ;b 151f 668 add r10, r10, r21 ;b 151f 669 add r10, r10, r22 ;b 151f 670 add r10, r10, r23 ;b 151f 671 add r10, r10, r24 ;b 151f 672 add r10, r10, r25 ;b 151f 673 add r10, r10, r26 ;b 151f 674 add r10, r10, r27 ;b 151f 675 add r10, r10, r28 ;b 151f 676 add r10, r10, r29 ;b 151f 677 add r10, r10, r30 ;b 151f 678 add r10, r10, r31 679151: 680 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 681 beq 152f /* if reg RA is zero, don't add it */ 682 addi r11, r11, 150b@l /* add start of table */ 683 mtctr r11 /* load ctr with jump address */ 684 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 685 bctr /* jump into table */ 686152: 687 mfdar r11 688 mtctr r11 /* restore ctr reg from DAR */ 689 mtdar r10 /* save fault EA to DAR */ 690 mfspr r10,SPRN_SPRG_SCRATCH2 691 b DARFixed /* Go back to normal TLB handling */ 692 693 /* special handling for r10,r11 since these are modified already */ 694153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 695 add r10, r10, r11 /* add it */ 696 mfctr r11 /* restore r11 */ 697 b 151b 698154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 699 add r10, r10, r11 /* add it */ 700 mfctr r11 /* restore r11 */ 701 b 151b 702#endif 703 704/* 705 * This is where the main kernel code starts. 706 */ 707start_here: 708 /* ptr to current */ 709 lis r2,init_task@h 710 ori r2,r2,init_task@l 711 712 /* ptr to phys current thread */ 713 tophys(r4,r2) 714 addi r4,r4,THREAD /* init task's THREAD */ 715 mtspr SPRN_SPRG_THREAD,r4 716 717 /* stack */ 718 lis r1,init_thread_union@ha 719 addi r1,r1,init_thread_union@l 720 li r0,0 721 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 722 723 bl early_init /* We have to do this with MMU on */ 724 725/* 726 * Decide what sort of machine this is and initialize the MMU. 727 */ 728 li r3,0 729 mr r4,r31 730 bl machine_init 731 bl MMU_init 732 733/* 734 * Go back to running unmapped so we can load up new values 735 * and change to using our exception vectors. 736 * On the 8xx, all we have to do is invalidate the TLB to clear 737 * the old 8M byte TLB mappings and load the page table base register. 738 */ 739 /* The right way to do this would be to track it down through 740 * init's THREAD like the context switch code does, but this is 741 * easier......until someone changes init's static structures. 742 */ 743 lis r6, swapper_pg_dir@ha 744 tophys(r6,r6) 745#ifdef CONFIG_8xx_CPU6 746 lis r4, cpu6_errata_word@h 747 ori r4, r4, cpu6_errata_word@l 748 li r3, 0x3f80 749 stw r3, 12(r4) 750 lwz r3, 12(r4) 751#endif 752 mtspr SPRN_M_TW, r6 753 lis r4,2f@h 754 ori r4,r4,2f@l 755 tophys(r4,r4) 756 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 757 mtspr SPRN_SRR0,r4 758 mtspr SPRN_SRR1,r3 759 rfi 760/* Load up the kernel context */ 7612: 762 SYNC /* Force all PTE updates to finish */ 763 tlbia /* Clear all TLB entries */ 764 sync /* wait for tlbia/tlbie to finish */ 765 TLBSYNC /* ... on all CPUs */ 766 767 /* set up the PTE pointers for the Abatron bdiGDB. 768 */ 769 tovirt(r6,r6) 770 lis r5, abatron_pteptrs@h 771 ori r5, r5, abatron_pteptrs@l 772 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 773 tophys(r5,r5) 774 stw r6, 0(r5) 775 776/* Now turn on the MMU for real! */ 777 li r4,MSR_KERNEL 778 lis r3,start_kernel@h 779 ori r3,r3,start_kernel@l 780 mtspr SPRN_SRR0,r3 781 mtspr SPRN_SRR1,r4 782 rfi /* enable MMU and jump to start_kernel */ 783 784/* Set up the initial MMU state so we can do the first level of 785 * kernel initialization. This maps the first 8 MBytes of memory 1:1 786 * virtual to physical. Also, set the cache mode since that is defined 787 * by TLB entries and perform any additional mapping (like of the IMMR). 788 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 789 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 790 * these mappings is mapped by page tables. 791 */ 792initial_mmu: 793 li r8, 0 794 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 795 lis r10, MD_RESETVAL@h 796#ifndef CONFIG_8xx_COPYBACK 797 oris r10, r10, MD_WTDEF@h 798#endif 799 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 800 801 tlbia /* Invalidate all TLB entries */ 802/* Always pin the first 8 MB ITLB to prevent ITLB 803 misses while mucking around with SRR0/SRR1 in asm 804*/ 805 lis r8, MI_RSV4I@h 806 ori r8, r8, 0x1c00 807 808 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 809 810#ifdef CONFIG_PIN_TLB 811 oris r10, r10, MD_RSV4I@h 812 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 813#endif 814 815 /* Now map the lower 8 Meg into the ITLB. */ 816 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 817 ori r8, r8, MI_EVALID /* Mark it valid */ 818 mtspr SPRN_MI_EPN, r8 819 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */ 820 ori r8, r8, MI_SVALID /* Make it valid */ 821 mtspr SPRN_MI_TWC, r8 822 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 823 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 824 825 lis r8, MI_APG_INIT@h /* Set protection modes */ 826 ori r8, r8, MI_APG_INIT@l 827 mtspr SPRN_MI_AP, r8 828 lis r8, MD_APG_INIT@h 829 ori r8, r8, MD_APG_INIT@l 830 mtspr SPRN_MD_AP, r8 831 832 /* Map a 512k page for the IMMR to get the processor 833 * internal registers (among other things). 834 */ 835#ifdef CONFIG_PIN_TLB_IMMR 836 ori r10, r10, 0x1c00 837 mtspr SPRN_MD_CTR, r10 838 839 mfspr r9, 638 /* Get current IMMR */ 840 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */ 841 842 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */ 843 ori r8, r8, MD_EVALID /* Mark it valid */ 844 mtspr SPRN_MD_EPN, r8 845 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */ 846 ori r8, r8, MD_SVALID /* Make it valid */ 847 mtspr SPRN_MD_TWC, r8 848 mr r8, r9 /* Create paddr for TLB */ 849 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 850 mtspr SPRN_MD_RPN, r8 851#endif 852 853 /* Since the cache is enabled according to the information we 854 * just loaded into the TLB, invalidate and enable the caches here. 855 * We should probably check/set other modes....later. 856 */ 857 lis r8, IDC_INVALL@h 858 mtspr SPRN_IC_CST, r8 859 mtspr SPRN_DC_CST, r8 860 lis r8, IDC_ENABLE@h 861 mtspr SPRN_IC_CST, r8 862#ifdef CONFIG_8xx_COPYBACK 863 mtspr SPRN_DC_CST, r8 864#else 865 /* For a debug option, I left this here to easily enable 866 * the write through cache mode 867 */ 868 lis r8, DC_SFWT@h 869 mtspr SPRN_DC_CST, r8 870 lis r8, IDC_ENABLE@h 871 mtspr SPRN_DC_CST, r8 872#endif 873 blr 874 875 876/* 877 * We put a few things here that have to be page-aligned. 878 * This stuff goes at the beginning of the data segment, 879 * which is page-aligned. 880 */ 881 .data 882 .globl sdata 883sdata: 884 .globl empty_zero_page 885 .align PAGE_SHIFT 886empty_zero_page: 887 .space PAGE_SIZE 888EXPORT_SYMBOL(empty_zero_page) 889 890 .globl swapper_pg_dir 891swapper_pg_dir: 892 .space PGD_TABLE_SIZE 893 894/* Room for two PTE table poiners, usually the kernel and current user 895 * pointer to their respective root page table (pgdir). 896 */ 897abatron_pteptrs: 898 .space 8 899 900#ifdef CONFIG_8xx_CPU6 901 .globl cpu6_errata_word 902cpu6_errata_word: 903 .space 16 904#endif 905 906