1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33 34/* Macro to make the code more readable. */ 35#ifdef CONFIG_8xx_CPU6 36#define SPRN_MI_TWC_ADDR 0x2b80 37#define SPRN_MI_RPN_ADDR 0x2d80 38#define SPRN_MD_TWC_ADDR 0x3b80 39#define SPRN_MD_RPN_ADDR 0x3d80 40 41#define MTSPR_CPU6(spr, reg, treg) \ 42 li treg, spr##_ADDR; \ 43 stw treg, 12(r0); \ 44 lwz treg, 12(r0); \ 45 mtspr spr, reg 46#else 47#define MTSPR_CPU6(spr, reg, treg) \ 48 mtspr spr, reg 49#endif 50 51/* Macro to test if an address is a kernel address */ 52#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 53#define IS_KERNEL(tmp, addr) \ 54 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */ 55#define BRANCH_UNLESS_KERNEL(label) beq label 56#else 57#define IS_KERNEL(tmp, addr) \ 58 rlwinm tmp, addr, 16, 16, 31; \ 59 cmpli cr0, tmp, PAGE_OFFSET >> 16 60#define BRANCH_UNLESS_KERNEL(label) blt label 61#endif 62 63 64/* 65 * Value for the bits that have fixed value in RPN entries. 66 * Also used for tagging DAR for DTLBerror. 67 */ 68#ifdef CONFIG_PPC_16K_PAGES 69#define RPN_PATTERN (0x00f0 | MD_SPS16K) 70#else 71#define RPN_PATTERN 0x00f0 72#endif 73 74 __HEAD 75_ENTRY(_stext); 76_ENTRY(_start); 77 78/* MPC8xx 79 * This port was done on an MBX board with an 860. Right now I only 80 * support an ELF compressed (zImage) boot from EPPC-Bug because the 81 * code there loads up some registers before calling us: 82 * r3: ptr to board info data 83 * r4: initrd_start or if no initrd then 0 84 * r5: initrd_end - unused if r4 is 0 85 * r6: Start of command line string 86 * r7: End of command line string 87 * 88 * I decided to use conditional compilation instead of checking PVR and 89 * adding more processor specific branches around code I don't need. 90 * Since this is an embedded processor, I also appreciate any memory 91 * savings I can get. 92 * 93 * The MPC8xx does not have any BATs, but it supports large page sizes. 94 * We first initialize the MMU to support 8M byte pages, then load one 95 * entry into each of the instruction and data TLBs to map the first 96 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 97 * the "internal" processor registers before MMU_init is called. 98 * 99 * -- Dan 100 */ 101 .globl __start 102__start: 103 mr r31,r3 /* save device tree ptr */ 104 105 /* We have to turn on the MMU right away so we get cache modes 106 * set correctly. 107 */ 108 bl initial_mmu 109 110/* We now have the lower 8 Meg mapped into TLB entries, and the caches 111 * ready to work. 112 */ 113 114turn_on_mmu: 115 mfmsr r0 116 ori r0,r0,MSR_DR|MSR_IR 117 mtspr SPRN_SRR1,r0 118 lis r0,start_here@h 119 ori r0,r0,start_here@l 120 mtspr SPRN_SRR0,r0 121 SYNC 122 rfi /* enables MMU */ 123 124/* 125 * Exception entry code. This code runs with address translation 126 * turned off, i.e. using physical addresses. 127 * We assume sprg3 has the physical address of the current 128 * task's thread_struct. 129 */ 130#define EXCEPTION_PROLOG \ 131 EXCEPTION_PROLOG_0; \ 132 mfcr r10; \ 133 EXCEPTION_PROLOG_1; \ 134 EXCEPTION_PROLOG_2 135 136#define EXCEPTION_PROLOG_0 \ 137 mtspr SPRN_SPRG_SCRATCH0,r10; \ 138 mtspr SPRN_SPRG_SCRATCH1,r11 139 140#define EXCEPTION_PROLOG_1 \ 141 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 142 andi. r11,r11,MSR_PR; \ 143 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 144 beq 1f; \ 145 mfspr r11,SPRN_SPRG_THREAD; \ 146 lwz r11,THREAD_INFO-THREAD(r11); \ 147 addi r11,r11,THREAD_SIZE; \ 148 tophys(r11,r11); \ 1491: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 150 151 152#define EXCEPTION_PROLOG_2 \ 153 CLR_TOP32(r11); \ 154 stw r10,_CCR(r11); /* save registers */ \ 155 stw r12,GPR12(r11); \ 156 stw r9,GPR9(r11); \ 157 mfspr r10,SPRN_SPRG_SCRATCH0; \ 158 stw r10,GPR10(r11); \ 159 mfspr r12,SPRN_SPRG_SCRATCH1; \ 160 stw r12,GPR11(r11); \ 161 mflr r10; \ 162 stw r10,_LINK(r11); \ 163 mfspr r12,SPRN_SRR0; \ 164 mfspr r9,SPRN_SRR1; \ 165 stw r1,GPR1(r11); \ 166 stw r1,0(r11); \ 167 tovirt(r1,r11); /* set new kernel sp */ \ 168 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 169 MTMSRD(r10); /* (except for mach check in rtas) */ \ 170 stw r0,GPR0(r11); \ 171 SAVE_4GPRS(3, r11); \ 172 SAVE_2GPRS(7, r11) 173 174/* 175 * Exception exit code. 176 */ 177#define EXCEPTION_EPILOG_0 \ 178 mfspr r10,SPRN_SPRG_SCRATCH0; \ 179 mfspr r11,SPRN_SPRG_SCRATCH1 180 181/* 182 * Note: code which follows this uses cr0.eq (set if from kernel), 183 * r11, r12 (SRR0), and r9 (SRR1). 184 * 185 * Note2: once we have set r1 we are in a position to take exceptions 186 * again, and we could thus set MSR:RI at that point. 187 */ 188 189/* 190 * Exception vectors. 191 */ 192#define EXCEPTION(n, label, hdlr, xfer) \ 193 . = n; \ 194label: \ 195 EXCEPTION_PROLOG; \ 196 addi r3,r1,STACK_FRAME_OVERHEAD; \ 197 xfer(n, hdlr) 198 199#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 200 li r10,trap; \ 201 stw r10,_TRAP(r11); \ 202 li r10,MSR_KERNEL; \ 203 copyee(r10, r9); \ 204 bl tfer; \ 205i##n: \ 206 .long hdlr; \ 207 .long ret 208 209#define COPY_EE(d, s) rlwimi d,s,0,16,16 210#define NOCOPY(d, s) 211 212#define EXC_XFER_STD(n, hdlr) \ 213 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 214 ret_from_except_full) 215 216#define EXC_XFER_LITE(n, hdlr) \ 217 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 218 ret_from_except) 219 220#define EXC_XFER_EE(n, hdlr) \ 221 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 222 ret_from_except_full) 223 224#define EXC_XFER_EE_LITE(n, hdlr) \ 225 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 226 ret_from_except) 227 228/* System reset */ 229 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 230 231/* Machine check */ 232 . = 0x200 233MachineCheck: 234 EXCEPTION_PROLOG 235 mfspr r4,SPRN_DAR 236 stw r4,_DAR(r11) 237 li r5,RPN_PATTERN 238 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 239 mfspr r5,SPRN_DSISR 240 stw r5,_DSISR(r11) 241 addi r3,r1,STACK_FRAME_OVERHEAD 242 EXC_XFER_STD(0x200, machine_check_exception) 243 244/* Data access exception. 245 * This is "never generated" by the MPC8xx. 246 */ 247 . = 0x300 248DataAccess: 249 250/* Instruction access exception. 251 * This is "never generated" by the MPC8xx. 252 */ 253 . = 0x400 254InstructionAccess: 255 256/* External interrupt */ 257 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 258 259/* Alignment exception */ 260 . = 0x600 261Alignment: 262 EXCEPTION_PROLOG 263 mfspr r4,SPRN_DAR 264 stw r4,_DAR(r11) 265 li r5,RPN_PATTERN 266 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 267 mfspr r5,SPRN_DSISR 268 stw r5,_DSISR(r11) 269 addi r3,r1,STACK_FRAME_OVERHEAD 270 EXC_XFER_EE(0x600, alignment_exception) 271 272/* Program check exception */ 273 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 274 275/* No FPU on MPC8xx. This exception is not supposed to happen. 276*/ 277 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 278 279/* Decrementer */ 280 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 281 282 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 283 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 284 285/* System call */ 286 . = 0xc00 287SystemCall: 288 EXCEPTION_PROLOG 289 EXC_XFER_EE_LITE(0xc00, DoSyscall) 290 291/* Single step - not used on 601 */ 292 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 293 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 294 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 295 296/* On the MPC8xx, this is a software emulation interrupt. It occurs 297 * for all unimplemented and illegal instructions. 298 */ 299 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 300 301 . = 0x1100 302/* 303 * For the MPC8xx, this is a software tablewalk to load the instruction 304 * TLB. The task switch loads the M_TW register with the pointer to the first 305 * level table. 306 * If we discover there is no second level table (value is zero) or if there 307 * is an invalid pte, we load that into the TLB, which causes another fault 308 * into the TLB Error interrupt where we can handle such problems. 309 * We have to use the MD_xxx registers for the tablewalk because the 310 * equivalent MI_xxx registers only perform the attribute functions. 311 */ 312 313#ifdef CONFIG_8xx_CPU15 314#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ 315 addi tmp, addr, PAGE_SIZE; \ 316 tlbie tmp; \ 317 addi tmp, addr, -PAGE_SIZE; \ 318 tlbie tmp 319#else 320#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) 321#endif 322 323InstructionTLBMiss: 324#ifdef CONFIG_8xx_CPU6 325 mtspr SPRN_SPRG_SCRATCH2, r3 326#endif 327 EXCEPTION_PROLOG_0 328 329 /* If we are faulting a kernel address, we have to use the 330 * kernel page tables. 331 */ 332#ifdef CONFIG_MODULES 333 /* Only modules will cause ITLB Misses as we always 334 * pin the first 8MB of kernel memory */ 335 mfspr r11, SPRN_SRR0 /* Get effective address of fault */ 336 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) 337 mfcr r10 338 IS_KERNEL(r11, r11) 339 mfspr r11, SPRN_M_TW /* Get level 1 table */ 340 BRANCH_UNLESS_KERNEL(3f) 341 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3423: 343 mtcr r10 344 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 345#else 346 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 347 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) 348 mfspr r11, SPRN_M_TW /* Get level 1 table base address */ 349#endif 350 /* Insert level 1 index */ 351 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 352 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 353 354 /* Extract level 2 index */ 355 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 356 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 357 lwz r10, 0(r10) /* Get the pte */ 358 359 /* Insert the APG into the TWC from the Linux PTE. */ 360 rlwimi r11, r10, 0, 25, 26 361 /* Load the MI_TWC with the attributes for this "segment." */ 362 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ 363 364#ifdef CONFIG_SWAP 365 rlwinm r11, r10, 32-5, _PAGE_PRESENT 366 and r11, r11, r10 367 rlwimi r10, r11, 0, _PAGE_PRESENT 368#endif 369 li r11, RPN_PATTERN 370 /* The Linux PTE won't go exactly into the MMU TLB. 371 * Software indicator bits 20-23 and 28 must be clear. 372 * Software indicator bits 24, 25, 26, and 27 must be 373 * set. All other Linux PTE bits control the behavior 374 * of the MMU. 375 */ 376 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */ 377 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */ 378 379 /* Restore registers */ 380#ifdef CONFIG_8xx_CPU6 381 mfspr r3, SPRN_SPRG_SCRATCH2 382#endif 383 EXCEPTION_EPILOG_0 384 rfi 385 386 . = 0x1200 387DataStoreTLBMiss: 388#ifdef CONFIG_8xx_CPU6 389 mtspr SPRN_SPRG_SCRATCH2, r3 390#endif 391 EXCEPTION_PROLOG_0 392 mfcr r10 393 394 /* If we are faulting a kernel address, we have to use the 395 * kernel page tables. 396 */ 397 mfspr r11, SPRN_MD_EPN 398 IS_KERNEL(r11, r11) 399 mfspr r11, SPRN_M_TW /* Get level 1 table */ 400 BRANCH_UNLESS_KERNEL(3f) 401 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 4023: 403 mtcr r10 404 mfspr r10, SPRN_MD_EPN 405 406 /* Insert level 1 index */ 407 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 408 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 409 410 /* We have a pte table, so load fetch the pte from the table. 411 */ 412 /* Extract level 2 index */ 413 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 414 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 415 lwz r10, 0(r10) /* Get the pte */ 416 417 /* Insert the Guarded flag and APG into the TWC from the Linux PTE. 418 * It is bit 26-27 of both the Linux PTE and the TWC (at least 419 * I got that right :-). It will be better when we can put 420 * this into the Linux pgd/pmd and load it in the operation 421 * above. 422 */ 423 rlwimi r11, r10, 0, 26, 27 424 /* Insert the WriteThru flag into the TWC from the Linux PTE. 425 * It is bit 25 in the Linux PTE and bit 30 in the TWC 426 */ 427 rlwimi r11, r10, 32-5, 30, 30 428 MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 429 430 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 431 * We also need to know if the insn is a load/store, so: 432 * Clear _PAGE_PRESENT and load that which will 433 * trap into DTLB Error with store bit set accordinly. 434 */ 435 /* PRESENT=0x1, ACCESSED=0x20 436 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 437 * r10 = (r10 & ~PRESENT) | r11; 438 */ 439#ifdef CONFIG_SWAP 440 rlwinm r11, r10, 32-5, _PAGE_PRESENT 441 and r11, r11, r10 442 rlwimi r10, r11, 0, _PAGE_PRESENT 443#endif 444 /* The Linux PTE won't go exactly into the MMU TLB. 445 * Software indicator bits 22 and 28 must be clear. 446 * Software indicator bits 24, 25, 26, and 27 must be 447 * set. All other Linux PTE bits control the behavior 448 * of the MMU. 449 */ 450 li r11, RPN_PATTERN 451 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 452 rlwimi r10, r11, 0, 20, 20 /* clear 20 */ 453 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ 454 455 /* Restore registers */ 456#ifdef CONFIG_8xx_CPU6 457 mfspr r3, SPRN_SPRG_SCRATCH2 458#endif 459 mtspr SPRN_DAR, r11 /* Tag DAR */ 460 EXCEPTION_EPILOG_0 461 rfi 462 463/* This is an instruction TLB error on the MPC8xx. This could be due 464 * to many reasons, such as executing guarded memory or illegal instruction 465 * addresses. There is nothing to do but handle a big time error fault. 466 */ 467 . = 0x1300 468InstructionTLBError: 469 EXCEPTION_PROLOG 470 mr r4,r12 471 mr r5,r9 472 andis. r10,r5,0x4000 473 beq+ 1f 474 tlbie r4 475 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 4761: EXC_XFER_LITE(0x400, handle_page_fault) 477 478/* This is the data TLB error on the MPC8xx. This could be due to 479 * many reasons, including a dirty update to a pte. We bail out to 480 * a higher level function that can handle it. 481 */ 482 . = 0x1400 483DataTLBError: 484 EXCEPTION_PROLOG_0 485 mfcr r10 486 487 mfspr r11, SPRN_DAR 488 cmpwi cr0, r11, RPN_PATTERN 489 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 490DARFixed:/* Return from dcbx instruction bug workaround */ 491 EXCEPTION_PROLOG_1 492 EXCEPTION_PROLOG_2 493 mfspr r5,SPRN_DSISR 494 stw r5,_DSISR(r11) 495 mfspr r4,SPRN_DAR 496 andis. r10,r5,0x4000 497 beq+ 1f 498 tlbie r4 4991: li r10,RPN_PATTERN 500 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 501 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 502 EXC_XFER_LITE(0x300, handle_page_fault) 503 504 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 505 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 506 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 507 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 508 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 509 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 510 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 511 512/* On the MPC8xx, these next four traps are used for development 513 * support of breakpoints and such. Someday I will get around to 514 * using them. 515 */ 516 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 517 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 518 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 519 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 520 521 . = 0x2000 522 523/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 524 * by decoding the registers used by the dcbx instruction and adding them. 525 * DAR is set to the calculated address. 526 */ 527 /* define if you don't want to use self modifying code */ 528#define NO_SELF_MODIFYING_CODE 529FixupDAR:/* Entry point for dcbx workaround. */ 530 mtspr SPRN_SPRG_SCRATCH2, r10 531 /* fetch instruction from memory. */ 532 mfspr r10, SPRN_SRR0 533 IS_KERNEL(r11, r10) 534 mfspr r11, SPRN_M_TW /* Get level 1 table */ 535 BRANCH_UNLESS_KERNEL(3f) 536 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 537 /* Insert level 1 index */ 5383: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 539 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 540 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ 541 /* Insert level 2 index */ 542 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 543 lwz r11, 0(r11) /* Get the pte */ 544 /* concat physical page address(r11) and page offset(r10) */ 545 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 546 lwz r11,0(r11) 547/* Check if it really is a dcbx instruction. */ 548/* dcbt and dcbtst does not generate DTLB Misses/Errors, 549 * no need to include them here */ 550 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 551 rlwinm r10, r10, 0, 21, 5 552 cmpwi cr0, r10, 2028 /* Is dcbz? */ 553 beq+ 142f 554 cmpwi cr0, r10, 940 /* Is dcbi? */ 555 beq+ 142f 556 cmpwi cr0, r10, 108 /* Is dcbst? */ 557 beq+ 144f /* Fix up store bit! */ 558 cmpwi cr0, r10, 172 /* Is dcbf? */ 559 beq+ 142f 560 cmpwi cr0, r10, 1964 /* Is icbi? */ 561 beq+ 142f 562141: mfspr r10,SPRN_SPRG_SCRATCH2 563 b DARFixed /* Nope, go back to normal TLB processing */ 564 565144: mfspr r10, SPRN_DSISR 566 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 567 mtspr SPRN_DSISR, r10 568142: /* continue, it was a dcbx, dcbi instruction. */ 569#ifndef NO_SELF_MODIFYING_CODE 570 andis. r10,r11,0x1f /* test if reg RA is r0 */ 571 li r10,modified_instr@l 572 dcbtst r0,r10 /* touch for store */ 573 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 574 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 575 ori r11,r11,532 576 stw r11,0(r10) /* store add/and instruction */ 577 dcbf 0,r10 /* flush new instr. to memory. */ 578 icbi 0,r10 /* invalidate instr. cache line */ 579 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ 580 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ 581 isync /* Wait until new instr is loaded from memory */ 582modified_instr: 583 .space 4 /* this is where the add instr. is stored */ 584 bne+ 143f 585 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 586143: mtdar r10 /* store faulting EA in DAR */ 587 mfspr r10,SPRN_SPRG_SCRATCH2 588 b DARFixed /* Go back to normal TLB handling */ 589#else 590 mfctr r10 591 mtdar r10 /* save ctr reg in DAR */ 592 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 593 addi r10, r10, 150f@l /* add start of table */ 594 mtctr r10 /* load ctr with jump address */ 595 xor r10, r10, r10 /* sum starts at zero */ 596 bctr /* jump into table */ 597150: 598 add r10, r10, r0 ;b 151f 599 add r10, r10, r1 ;b 151f 600 add r10, r10, r2 ;b 151f 601 add r10, r10, r3 ;b 151f 602 add r10, r10, r4 ;b 151f 603 add r10, r10, r5 ;b 151f 604 add r10, r10, r6 ;b 151f 605 add r10, r10, r7 ;b 151f 606 add r10, r10, r8 ;b 151f 607 add r10, r10, r9 ;b 151f 608 mtctr r11 ;b 154f /* r10 needs special handling */ 609 mtctr r11 ;b 153f /* r11 needs special handling */ 610 add r10, r10, r12 ;b 151f 611 add r10, r10, r13 ;b 151f 612 add r10, r10, r14 ;b 151f 613 add r10, r10, r15 ;b 151f 614 add r10, r10, r16 ;b 151f 615 add r10, r10, r17 ;b 151f 616 add r10, r10, r18 ;b 151f 617 add r10, r10, r19 ;b 151f 618 add r10, r10, r20 ;b 151f 619 add r10, r10, r21 ;b 151f 620 add r10, r10, r22 ;b 151f 621 add r10, r10, r23 ;b 151f 622 add r10, r10, r24 ;b 151f 623 add r10, r10, r25 ;b 151f 624 add r10, r10, r26 ;b 151f 625 add r10, r10, r27 ;b 151f 626 add r10, r10, r28 ;b 151f 627 add r10, r10, r29 ;b 151f 628 add r10, r10, r30 ;b 151f 629 add r10, r10, r31 630151: 631 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 632 beq 152f /* if reg RA is zero, don't add it */ 633 addi r11, r11, 150b@l /* add start of table */ 634 mtctr r11 /* load ctr with jump address */ 635 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 636 bctr /* jump into table */ 637152: 638 mfdar r11 639 mtctr r11 /* restore ctr reg from DAR */ 640 mtdar r10 /* save fault EA to DAR */ 641 mfspr r10,SPRN_SPRG_SCRATCH2 642 b DARFixed /* Go back to normal TLB handling */ 643 644 /* special handling for r10,r11 since these are modified already */ 645153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 646 add r10, r10, r11 /* add it */ 647 mfctr r11 /* restore r11 */ 648 b 151b 649154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 650 add r10, r10, r11 /* add it */ 651 mfctr r11 /* restore r11 */ 652 b 151b 653#endif 654 655/* 656 * This is where the main kernel code starts. 657 */ 658start_here: 659 /* ptr to current */ 660 lis r2,init_task@h 661 ori r2,r2,init_task@l 662 663 /* ptr to phys current thread */ 664 tophys(r4,r2) 665 addi r4,r4,THREAD /* init task's THREAD */ 666 mtspr SPRN_SPRG_THREAD,r4 667 668 /* stack */ 669 lis r1,init_thread_union@ha 670 addi r1,r1,init_thread_union@l 671 li r0,0 672 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 673 674 bl early_init /* We have to do this with MMU on */ 675 676/* 677 * Decide what sort of machine this is and initialize the MMU. 678 */ 679 li r3,0 680 mr r4,r31 681 bl machine_init 682 bl MMU_init 683 684/* 685 * Go back to running unmapped so we can load up new values 686 * and change to using our exception vectors. 687 * On the 8xx, all we have to do is invalidate the TLB to clear 688 * the old 8M byte TLB mappings and load the page table base register. 689 */ 690 /* The right way to do this would be to track it down through 691 * init's THREAD like the context switch code does, but this is 692 * easier......until someone changes init's static structures. 693 */ 694 lis r6, swapper_pg_dir@ha 695 tophys(r6,r6) 696#ifdef CONFIG_8xx_CPU6 697 lis r4, cpu6_errata_word@h 698 ori r4, r4, cpu6_errata_word@l 699 li r3, 0x3f80 700 stw r3, 12(r4) 701 lwz r3, 12(r4) 702#endif 703 mtspr SPRN_M_TW, r6 704 lis r4,2f@h 705 ori r4,r4,2f@l 706 tophys(r4,r4) 707 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 708 mtspr SPRN_SRR0,r4 709 mtspr SPRN_SRR1,r3 710 rfi 711/* Load up the kernel context */ 7122: 713 SYNC /* Force all PTE updates to finish */ 714 tlbia /* Clear all TLB entries */ 715 sync /* wait for tlbia/tlbie to finish */ 716 TLBSYNC /* ... on all CPUs */ 717 718 /* set up the PTE pointers for the Abatron bdiGDB. 719 */ 720 tovirt(r6,r6) 721 lis r5, abatron_pteptrs@h 722 ori r5, r5, abatron_pteptrs@l 723 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 724 tophys(r5,r5) 725 stw r6, 0(r5) 726 727/* Now turn on the MMU for real! */ 728 li r4,MSR_KERNEL 729 lis r3,start_kernel@h 730 ori r3,r3,start_kernel@l 731 mtspr SPRN_SRR0,r3 732 mtspr SPRN_SRR1,r4 733 rfi /* enable MMU and jump to start_kernel */ 734 735/* Set up the initial MMU state so we can do the first level of 736 * kernel initialization. This maps the first 8 MBytes of memory 1:1 737 * virtual to physical. Also, set the cache mode since that is defined 738 * by TLB entries and perform any additional mapping (like of the IMMR). 739 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 740 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by 741 * these mappings is mapped by page tables. 742 */ 743initial_mmu: 744 tlbia /* Invalidate all TLB entries */ 745/* Always pin the first 8 MB ITLB to prevent ITLB 746 misses while mucking around with SRR0/SRR1 in asm 747*/ 748 lis r8, MI_RSV4I@h 749 ori r8, r8, 0x1c00 750 751 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 752 753#ifdef CONFIG_PIN_TLB 754 lis r10, (MD_RSV4I | MD_RESETVAL)@h 755 ori r10, r10, 0x1c00 756 mr r8, r10 757#else 758 lis r10, MD_RESETVAL@h 759#endif 760#ifndef CONFIG_8xx_COPYBACK 761 oris r10, r10, MD_WTDEF@h 762#endif 763 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 764 765 /* Now map the lower 8 Meg into the TLBs. For this quick hack, 766 * we can load the instruction and data TLB registers with the 767 * same values. 768 */ 769 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 770 ori r8, r8, MI_EVALID /* Mark it valid */ 771 mtspr SPRN_MI_EPN, r8 772 mtspr SPRN_MD_EPN, r8 773 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */ 774 ori r8, r8, MI_SVALID /* Make it valid */ 775 mtspr SPRN_MI_TWC, r8 776 li r8, MI_PS8MEG /* Set 8M byte page, APG 0 */ 777 ori r8, r8, MI_SVALID /* Make it valid */ 778 mtspr SPRN_MD_TWC, r8 779 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 780 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 781 mtspr SPRN_MD_RPN, r8 782 lis r8, MI_APG_INIT@h /* Set protection modes */ 783 ori r8, r8, MI_APG_INIT@l 784 mtspr SPRN_MI_AP, r8 785 lis r8, MD_APG_INIT@h 786 ori r8, r8, MD_APG_INIT@l 787 mtspr SPRN_MD_AP, r8 788 789 /* Map another 8 MByte at the IMMR to get the processor 790 * internal registers (among other things). 791 */ 792#ifdef CONFIG_PIN_TLB 793 addi r10, r10, 0x0100 794 mtspr SPRN_MD_CTR, r10 795#endif 796 mfspr r9, 638 /* Get current IMMR */ 797 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ 798 799 mr r8, r9 /* Create vaddr for TLB */ 800 ori r8, r8, MD_EVALID /* Mark it valid */ 801 mtspr SPRN_MD_EPN, r8 802 li r8, MD_PS8MEG /* Set 8M byte page */ 803 ori r8, r8, MD_SVALID /* Make it valid */ 804 mtspr SPRN_MD_TWC, r8 805 mr r8, r9 /* Create paddr for TLB */ 806 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 807 mtspr SPRN_MD_RPN, r8 808 809#ifdef CONFIG_PIN_TLB 810 /* Map two more 8M kernel data pages. 811 */ 812 addi r10, r10, 0x0100 813 mtspr SPRN_MD_CTR, r10 814 815 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 816 addis r8, r8, 0x0080 /* Add 8M */ 817 ori r8, r8, MI_EVALID /* Mark it valid */ 818 mtspr SPRN_MD_EPN, r8 819 li r9, MI_PS8MEG /* Set 8M byte page */ 820 ori r9, r9, MI_SVALID /* Make it valid */ 821 mtspr SPRN_MD_TWC, r9 822 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 823 addis r11, r11, 0x0080 /* Add 8M */ 824 mtspr SPRN_MD_RPN, r11 825 826 addi r10, r10, 0x0100 827 mtspr SPRN_MD_CTR, r10 828 829 addis r8, r8, 0x0080 /* Add 8M */ 830 mtspr SPRN_MD_EPN, r8 831 mtspr SPRN_MD_TWC, r9 832 addis r11, r11, 0x0080 /* Add 8M */ 833 mtspr SPRN_MD_RPN, r11 834#endif 835 836 /* Since the cache is enabled according to the information we 837 * just loaded into the TLB, invalidate and enable the caches here. 838 * We should probably check/set other modes....later. 839 */ 840 lis r8, IDC_INVALL@h 841 mtspr SPRN_IC_CST, r8 842 mtspr SPRN_DC_CST, r8 843 lis r8, IDC_ENABLE@h 844 mtspr SPRN_IC_CST, r8 845#ifdef CONFIG_8xx_COPYBACK 846 mtspr SPRN_DC_CST, r8 847#else 848 /* For a debug option, I left this here to easily enable 849 * the write through cache mode 850 */ 851 lis r8, DC_SFWT@h 852 mtspr SPRN_DC_CST, r8 853 lis r8, IDC_ENABLE@h 854 mtspr SPRN_DC_CST, r8 855#endif 856 blr 857 858 859/* 860 * Set up to use a given MMU context. 861 * r3 is context number, r4 is PGD pointer. 862 * 863 * We place the physical address of the new task page directory loaded 864 * into the MMU base register, and set the ASID compare register with 865 * the new "context." 866 */ 867_GLOBAL(set_context) 868 869#ifdef CONFIG_BDI_SWITCH 870 /* Context switch the PTE pointer for the Abatron BDI2000. 871 * The PGDIR is passed as second argument. 872 */ 873 lis r5, KERNELBASE@h 874 lwz r5, 0xf0(r5) 875 stw r4, 0x4(r5) 876#endif 877 878 /* Register M_TW will contain base address of level 1 table minus the 879 * lower part of the kernel PGDIR base address, so that all accesses to 880 * level 1 table are done relative to lower part of kernel PGDIR base 881 * address. 882 */ 883 li r5, (swapper_pg_dir-PAGE_OFFSET)@l 884 sub r4, r4, r5 885 tophys (r4, r4) 886#ifdef CONFIG_8xx_CPU6 887 lis r6, cpu6_errata_word@h 888 ori r6, r6, cpu6_errata_word@l 889 li r7, 0x3f80 890 stw r7, 12(r6) 891 lwz r7, 12(r6) 892#endif 893 mtspr SPRN_M_TW, r4 /* Update pointeur to level 1 table */ 894#ifdef CONFIG_8xx_CPU6 895 li r7, 0x3380 896 stw r7, 12(r6) 897 lwz r7, 12(r6) 898#endif 899 mtspr SPRN_M_CASID, r3 /* Update context */ 900 SYNC 901 blr 902 903#ifdef CONFIG_8xx_CPU6 904/* It's here because it is unique to the 8xx. 905 * It is important we get called with interrupts disabled. I used to 906 * do that, but it appears that all code that calls this already had 907 * interrupt disabled. 908 */ 909 .globl set_dec_cpu6 910set_dec_cpu6: 911 lis r7, cpu6_errata_word@h 912 ori r7, r7, cpu6_errata_word@l 913 li r4, 0x2c00 914 stw r4, 8(r7) 915 lwz r4, 8(r7) 916 mtspr 22, r3 /* Update Decrementer */ 917 SYNC 918 blr 919#endif 920 921/* 922 * We put a few things here that have to be page-aligned. 923 * This stuff goes at the beginning of the data segment, 924 * which is page-aligned. 925 */ 926 .data 927 .globl sdata 928sdata: 929 .globl empty_zero_page 930 .align PAGE_SHIFT 931empty_zero_page: 932 .space PAGE_SIZE 933 934 .globl swapper_pg_dir 935swapper_pg_dir: 936 .space PGD_TABLE_SIZE 937 938/* Room for two PTE table poiners, usually the kernel and current user 939 * pointer to their respective root page table (pgdir). 940 */ 941abatron_pteptrs: 942 .space 8 943 944#ifdef CONFIG_8xx_CPU6 945 .globl cpu6_errata_word 946cpu6_errata_word: 947 .space 16 948#endif 949 950