1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32 33/* Macro to make the code more readable. */ 34#ifdef CONFIG_8xx_CPU6 35#define DO_8xx_CPU6(val, reg) \ 36 li reg, val; \ 37 stw reg, 12(r0); \ 38 lwz reg, 12(r0); 39#else 40#define DO_8xx_CPU6(val, reg) 41#endif 42 __HEAD 43_ENTRY(_stext); 44_ENTRY(_start); 45 46/* MPC8xx 47 * This port was done on an MBX board with an 860. Right now I only 48 * support an ELF compressed (zImage) boot from EPPC-Bug because the 49 * code there loads up some registers before calling us: 50 * r3: ptr to board info data 51 * r4: initrd_start or if no initrd then 0 52 * r5: initrd_end - unused if r4 is 0 53 * r6: Start of command line string 54 * r7: End of command line string 55 * 56 * I decided to use conditional compilation instead of checking PVR and 57 * adding more processor specific branches around code I don't need. 58 * Since this is an embedded processor, I also appreciate any memory 59 * savings I can get. 60 * 61 * The MPC8xx does not have any BATs, but it supports large page sizes. 62 * We first initialize the MMU to support 8M byte pages, then load one 63 * entry into each of the instruction and data TLBs to map the first 64 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 65 * the "internal" processor registers before MMU_init is called. 66 * 67 * The TLB code currently contains a major hack. Since I use the condition 68 * code register, I have to save and restore it. I am out of registers, so 69 * I just store it in memory location 0 (the TLB handlers are not reentrant). 70 * To avoid making any decisions, I need to use the "segment" valid bit 71 * in the first level table, but that would require many changes to the 72 * Linux page directory/table functions that I don't want to do right now. 73 * 74 * I used to use SPRG2 for a temporary register in the TLB handler, but it 75 * has since been put to other uses. I now use a hack to save a register 76 * and the CCR at memory location 0.....Someday I'll fix this..... 77 * -- Dan 78 */ 79 .globl __start 80__start: 81 mr r31,r3 /* save parameters */ 82 mr r30,r4 83 mr r29,r5 84 mr r28,r6 85 mr r27,r7 86 87 /* We have to turn on the MMU right away so we get cache modes 88 * set correctly. 89 */ 90 bl initial_mmu 91 92/* We now have the lower 8 Meg mapped into TLB entries, and the caches 93 * ready to work. 94 */ 95 96turn_on_mmu: 97 mfmsr r0 98 ori r0,r0,MSR_DR|MSR_IR 99 mtspr SPRN_SRR1,r0 100 lis r0,start_here@h 101 ori r0,r0,start_here@l 102 mtspr SPRN_SRR0,r0 103 SYNC 104 rfi /* enables MMU */ 105 106/* 107 * Exception entry code. This code runs with address translation 108 * turned off, i.e. using physical addresses. 109 * We assume sprg3 has the physical address of the current 110 * task's thread_struct. 111 */ 112#define EXCEPTION_PROLOG \ 113 mtspr SPRN_SPRG_SCRATCH0,r10; \ 114 mtspr SPRN_SPRG_SCRATCH1,r11; \ 115 mfcr r10; \ 116 EXCEPTION_PROLOG_1; \ 117 EXCEPTION_PROLOG_2 118 119#define EXCEPTION_PROLOG_1 \ 120 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 121 andi. r11,r11,MSR_PR; \ 122 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 123 beq 1f; \ 124 mfspr r11,SPRN_SPRG_THREAD; \ 125 lwz r11,THREAD_INFO-THREAD(r11); \ 126 addi r11,r11,THREAD_SIZE; \ 127 tophys(r11,r11); \ 1281: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 129 130 131#define EXCEPTION_PROLOG_2 \ 132 CLR_TOP32(r11); \ 133 stw r10,_CCR(r11); /* save registers */ \ 134 stw r12,GPR12(r11); \ 135 stw r9,GPR9(r11); \ 136 mfspr r10,SPRN_SPRG_SCRATCH0; \ 137 stw r10,GPR10(r11); \ 138 mfspr r12,SPRN_SPRG_SCRATCH1; \ 139 stw r12,GPR11(r11); \ 140 mflr r10; \ 141 stw r10,_LINK(r11); \ 142 mfspr r12,SPRN_SRR0; \ 143 mfspr r9,SPRN_SRR1; \ 144 stw r1,GPR1(r11); \ 145 stw r1,0(r11); \ 146 tovirt(r1,r11); /* set new kernel sp */ \ 147 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 148 MTMSRD(r10); /* (except for mach check in rtas) */ \ 149 stw r0,GPR0(r11); \ 150 SAVE_4GPRS(3, r11); \ 151 SAVE_2GPRS(7, r11) 152 153/* 154 * Note: code which follows this uses cr0.eq (set if from kernel), 155 * r11, r12 (SRR0), and r9 (SRR1). 156 * 157 * Note2: once we have set r1 we are in a position to take exceptions 158 * again, and we could thus set MSR:RI at that point. 159 */ 160 161/* 162 * Exception vectors. 163 */ 164#define EXCEPTION(n, label, hdlr, xfer) \ 165 . = n; \ 166label: \ 167 EXCEPTION_PROLOG; \ 168 addi r3,r1,STACK_FRAME_OVERHEAD; \ 169 xfer(n, hdlr) 170 171#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 172 li r10,trap; \ 173 stw r10,_TRAP(r11); \ 174 li r10,MSR_KERNEL; \ 175 copyee(r10, r9); \ 176 bl tfer; \ 177i##n: \ 178 .long hdlr; \ 179 .long ret 180 181#define COPY_EE(d, s) rlwimi d,s,0,16,16 182#define NOCOPY(d, s) 183 184#define EXC_XFER_STD(n, hdlr) \ 185 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 186 ret_from_except_full) 187 188#define EXC_XFER_LITE(n, hdlr) \ 189 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 190 ret_from_except) 191 192#define EXC_XFER_EE(n, hdlr) \ 193 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 194 ret_from_except_full) 195 196#define EXC_XFER_EE_LITE(n, hdlr) \ 197 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 198 ret_from_except) 199 200/* System reset */ 201 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 202 203/* Machine check */ 204 . = 0x200 205MachineCheck: 206 EXCEPTION_PROLOG 207 mfspr r4,SPRN_DAR 208 stw r4,_DAR(r11) 209 li r5,0x00f0 210 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 211 mfspr r5,SPRN_DSISR 212 stw r5,_DSISR(r11) 213 addi r3,r1,STACK_FRAME_OVERHEAD 214 EXC_XFER_STD(0x200, machine_check_exception) 215 216/* Data access exception. 217 * This is "never generated" by the MPC8xx. We jump to it for other 218 * translation errors. 219 */ 220 . = 0x300 221DataAccess: 222 EXCEPTION_PROLOG 223 mfspr r10,SPRN_DSISR 224 stw r10,_DSISR(r11) 225 mr r5,r10 226 mfspr r4,SPRN_DAR 227 li r10,0x00f0 228 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 229 EXC_XFER_EE_LITE(0x300, handle_page_fault) 230 231/* Instruction access exception. 232 * This is "never generated" by the MPC8xx. We jump to it for other 233 * translation errors. 234 */ 235 . = 0x400 236InstructionAccess: 237 EXCEPTION_PROLOG 238 mr r4,r12 239 mr r5,r9 240 EXC_XFER_EE_LITE(0x400, handle_page_fault) 241 242/* External interrupt */ 243 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 244 245/* Alignment exception */ 246 . = 0x600 247Alignment: 248 EXCEPTION_PROLOG 249 mfspr r4,SPRN_DAR 250 stw r4,_DAR(r11) 251 li r5,0x00f0 252 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 253 mfspr r5,SPRN_DSISR 254 stw r5,_DSISR(r11) 255 addi r3,r1,STACK_FRAME_OVERHEAD 256 EXC_XFER_EE(0x600, alignment_exception) 257 258/* Program check exception */ 259 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 260 261/* No FPU on MPC8xx. This exception is not supposed to happen. 262*/ 263 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 264 265/* Decrementer */ 266 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 267 268 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 269 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 270 271/* System call */ 272 . = 0xc00 273SystemCall: 274 EXCEPTION_PROLOG 275 EXC_XFER_EE_LITE(0xc00, DoSyscall) 276 277/* Single step - not used on 601 */ 278 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 279 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 280 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 281 282/* On the MPC8xx, this is a software emulation interrupt. It occurs 283 * for all unimplemented and illegal instructions. 284 */ 285 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 286 287 . = 0x1100 288/* 289 * For the MPC8xx, this is a software tablewalk to load the instruction 290 * TLB. It is modelled after the example in the Motorola manual. The task 291 * switch loads the M_TWB register with the pointer to the first level table. 292 * If we discover there is no second level table (value is zero) or if there 293 * is an invalid pte, we load that into the TLB, which causes another fault 294 * into the TLB Error interrupt where we can handle such problems. 295 * We have to use the MD_xxx registers for the tablewalk because the 296 * equivalent MI_xxx registers only perform the attribute functions. 297 */ 298InstructionTLBMiss: 299#ifdef CONFIG_8xx_CPU6 300 stw r3, 8(r0) 301#endif 302 DO_8xx_CPU6(0x3f80, r3) 303 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 304 mfcr r10 305 stw r10, 0(r0) 306 stw r11, 4(r0) 307 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 308#ifdef CONFIG_8xx_CPU15 309 addi r11, r10, 0x1000 310 tlbie r11 311 addi r11, r10, -0x1000 312 tlbie r11 313#endif 314 DO_8xx_CPU6(0x3780, r3) 315 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ 316 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 317 318 /* If we are faulting a kernel address, we have to use the 319 * kernel page tables. 320 */ 321 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ 322 beq 3f 323 lis r11, swapper_pg_dir@h 324 ori r11, r11, swapper_pg_dir@l 325 rlwimi r10, r11, 0, 2, 19 3263: 327 lwz r11, 0(r10) /* Get the level 1 entry */ 328 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 329 beq 2f /* If zero, don't try to find a pte */ 330 331 /* We have a pte table, so load the MI_TWC with the attributes 332 * for this "segment." 333 */ 334 ori r11,r11,1 /* Set valid bit */ 335 DO_8xx_CPU6(0x2b80, r3) 336 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ 337 DO_8xx_CPU6(0x3b80, r3) 338 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 339 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 340 lwz r10, 0(r11) /* Get the pte */ 341 342 andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT 343 cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT 344 bne- cr0, 2f 345 346 /* Clear PP lsb, 0x400 */ 347 rlwinm r10, r10, 0, 22, 20 348 349 /* The Linux PTE won't go exactly into the MMU TLB. 350 * Software indicator bits 22 and 28 must be clear. 351 * Software indicator bits 24, 25, 26, and 27 must be 352 * set. All other Linux PTE bits control the behavior 353 * of the MMU. 354 */ 355 li r11, 0x00f0 356 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 357 DO_8xx_CPU6(0x2d80, r3) 358 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 359 360 mfspr r10, SPRN_M_TW /* Restore registers */ 361 lwz r11, 0(r0) 362 mtcr r11 363 lwz r11, 4(r0) 364#ifdef CONFIG_8xx_CPU6 365 lwz r3, 8(r0) 366#endif 367 rfi 3682: 369 mfspr r11, SPRN_SRR1 370 /* clear all error bits as TLB Miss 371 * sets a few unconditionally 372 */ 373 rlwinm r11, r11, 0, 0xffff 374 mtspr SPRN_SRR1, r11 375 376 mfspr r10, SPRN_M_TW /* Restore registers */ 377 lwz r11, 0(r0) 378 mtcr r11 379 lwz r11, 4(r0) 380#ifdef CONFIG_8xx_CPU6 381 lwz r3, 8(r0) 382#endif 383 b InstructionAccess 384 385 . = 0x1200 386DataStoreTLBMiss: 387#ifdef CONFIG_8xx_CPU6 388 stw r3, 8(r0) 389#endif 390 DO_8xx_CPU6(0x3f80, r3) 391 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 392 mfcr r10 393 stw r10, 0(r0) 394 stw r11, 4(r0) 395 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 396 397 /* If we are faulting a kernel address, we have to use the 398 * kernel page tables. 399 */ 400 andi. r11, r10, 0x0800 401 beq 3f 402 lis r11, swapper_pg_dir@h 403 ori r11, r11, swapper_pg_dir@l 404 rlwimi r10, r11, 0, 2, 19 4053: 406 lwz r11, 0(r10) /* Get the level 1 entry */ 407 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 408 beq 2f /* If zero, don't try to find a pte */ 409 410 /* We have a pte table, so load fetch the pte from the table. 411 */ 412 ori r11, r11, 1 /* Set valid bit in physical L2 page */ 413 DO_8xx_CPU6(0x3b80, r3) 414 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 415 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ 416 lwz r10, 0(r10) /* Get the pte */ 417 418 /* Insert the Guarded flag into the TWC from the Linux PTE. 419 * It is bit 27 of both the Linux PTE and the TWC (at least 420 * I got that right :-). It will be better when we can put 421 * this into the Linux pgd/pmd and load it in the operation 422 * above. 423 */ 424 rlwimi r11, r10, 0, 27, 27 425 /* Insert the WriteThru flag into the TWC from the Linux PTE. 426 * It is bit 25 in the Linux PTE and bit 30 in the TWC 427 */ 428 rlwimi r11, r10, 32-5, 30, 30 429 DO_8xx_CPU6(0x3b80, r3) 430 mtspr SPRN_MD_TWC, r11 431 432 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 433 * We also need to know if the insn is a load/store, so: 434 * Clear _PAGE_PRESENT and load that which will 435 * trap into DTLB Error with store bit set accordinly. 436 */ 437 /* PRESENT=0x1, ACCESSED=0x20 438 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 439 * r10 = (r10 & ~PRESENT) | r11; 440 */ 441 rlwinm r11, r10, 32-5, _PAGE_PRESENT 442 and r11, r11, r10 443 rlwimi r10, r11, 0, _PAGE_PRESENT 444 445 /* Honour kernel RO, User NA */ 446 /* 0x200 == Extended encoding, bit 22 */ 447 /* r11 = (r10 & _PAGE_USER) >> 2 */ 448 rlwinm r11, r10, 32-2, 0x200 449 or r10, r11, r10 450 /* r11 = (r10 & _PAGE_RW) >> 1 */ 451 rlwinm r11, r10, 32-1, 0x200 452 or r10, r11, r10 453 /* invert RW and 0x200 bits */ 454 xori r10, r10, _PAGE_RW | 0x200 455 456 /* The Linux PTE won't go exactly into the MMU TLB. 457 * Software indicator bits 22 and 28 must be clear. 458 * Software indicator bits 24, 25, 26, and 27 must be 459 * set. All other Linux PTE bits control the behavior 460 * of the MMU. 461 */ 4622: li r11, 0x00f0 463 mtspr SPRN_DAR,r11 /* Tag DAR */ 464 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 465 DO_8xx_CPU6(0x3d80, r3) 466 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 467 468 mfspr r10, SPRN_M_TW /* Restore registers */ 469 lwz r11, 0(r0) 470 mtcr r11 471 lwz r11, 4(r0) 472#ifdef CONFIG_8xx_CPU6 473 lwz r3, 8(r0) 474#endif 475 rfi 476 477/* This is an instruction TLB error on the MPC8xx. This could be due 478 * to many reasons, such as executing guarded memory or illegal instruction 479 * addresses. There is nothing to do but handle a big time error fault. 480 */ 481 . = 0x1300 482InstructionTLBError: 483 b InstructionAccess 484 485/* This is the data TLB error on the MPC8xx. This could be due to 486 * many reasons, including a dirty update to a pte. We can catch that 487 * one here, but anything else is an error. First, we track down the 488 * Linux pte. If it is valid, write access is allowed, but the 489 * page dirty bit is not set, we will set it and reload the TLB. For 490 * any other case, we bail out to a higher level function that can 491 * handle it. 492 */ 493 . = 0x1400 494DataTLBError: 495#ifdef CONFIG_8xx_CPU6 496 stw r3, 8(r0) 497#endif 498 DO_8xx_CPU6(0x3f80, r3) 499 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 500 mfcr r10 501 stw r10, 0(r0) 502 stw r11, 4(r0) 503 504 mfspr r10, SPRN_DAR 505 cmpwi cr0, r10, 0x00f0 506 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 507DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ 508 mfspr r10, SPRN_M_TW /* Restore registers */ 509 lwz r11, 0(r0) 510 mtcr r11 511 lwz r11, 4(r0) 512#ifdef CONFIG_8xx_CPU6 513 lwz r3, 8(r0) 514#endif 515 b DataAccess 516 517 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 518 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 519 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 520 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 521 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 522 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 523 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 524 525/* On the MPC8xx, these next four traps are used for development 526 * support of breakpoints and such. Someday I will get around to 527 * using them. 528 */ 529 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 530 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 531 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 532 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 533 534 . = 0x2000 535 536/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 537 * by decoding the registers used by the dcbx instruction and adding them. 538 * DAR is set to the calculated address and r10 also holds the EA on exit. 539 */ 540 /* define if you don't want to use self modifying code */ 541#define NO_SELF_MODIFYING_CODE 542FixupDAR:/* Entry point for dcbx workaround. */ 543 /* fetch instruction from memory. */ 544 mfspr r10, SPRN_SRR0 545 DO_8xx_CPU6(0x3780, r3) 546 mtspr SPRN_MD_EPN, r10 547 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ 548 cmplwi cr0, r11, 0x0800 549 blt- 3f /* Branch if user space */ 550 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h 551 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l 552 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */ 5533: lwz r11, 0(r11) /* Get the level 1 entry */ 554 DO_8xx_CPU6(0x3b80, r3) 555 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 556 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 557 lwz r11, 0(r11) /* Get the pte */ 558 /* concat physical page address(r11) and page offset(r10) */ 559 rlwimi r11, r10, 0, 20, 31 560 lwz r11,0(r11) 561/* Check if it really is a dcbx instruction. */ 562/* dcbt and dcbtst does not generate DTLB Misses/Errors, 563 * no need to include them here */ 564 srwi r10, r11, 26 /* check if major OP code is 31 */ 565 cmpwi cr0, r10, 31 566 bne- 141f 567 rlwinm r10, r11, 0, 21, 30 568 cmpwi cr0, r10, 2028 /* Is dcbz? */ 569 beq+ 142f 570 cmpwi cr0, r10, 940 /* Is dcbi? */ 571 beq+ 142f 572 cmpwi cr0, r10, 108 /* Is dcbst? */ 573 beq+ 144f /* Fix up store bit! */ 574 cmpwi cr0, r10, 172 /* Is dcbf? */ 575 beq+ 142f 576 cmpwi cr0, r10, 1964 /* Is icbi? */ 577 beq+ 142f 578141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ 579 b DARFixed /* Nope, go back to normal TLB processing */ 580 581144: mfspr r10, SPRN_DSISR 582 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 583 mtspr SPRN_DSISR, r10 584142: /* continue, it was a dcbx, dcbi instruction. */ 585#ifdef CONFIG_8xx_CPU6 586 lwz r3, 8(r0) /* restore r3 from memory */ 587#endif 588#ifndef NO_SELF_MODIFYING_CODE 589 andis. r10,r11,0x1f /* test if reg RA is r0 */ 590 li r10,modified_instr@l 591 dcbtst r0,r10 /* touch for store */ 592 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 593 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 594 ori r11,r11,532 595 stw r11,0(r10) /* store add/and instruction */ 596 dcbf 0,r10 /* flush new instr. to memory. */ 597 icbi 0,r10 /* invalidate instr. cache line */ 598 lwz r11, 4(r0) /* restore r11 from memory */ 599 mfspr r10, SPRN_M_TW /* restore r10 from M_TW */ 600 isync /* Wait until new instr is loaded from memory */ 601modified_instr: 602 .space 4 /* this is where the add instr. is stored */ 603 bne+ 143f 604 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 605143: mtdar r10 /* store faulting EA in DAR */ 606 b DARFixed /* Go back to normal TLB handling */ 607#else 608 mfctr r10 609 mtdar r10 /* save ctr reg in DAR */ 610 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 611 addi r10, r10, 150f@l /* add start of table */ 612 mtctr r10 /* load ctr with jump address */ 613 xor r10, r10, r10 /* sum starts at zero */ 614 bctr /* jump into table */ 615150: 616 add r10, r10, r0 ;b 151f 617 add r10, r10, r1 ;b 151f 618 add r10, r10, r2 ;b 151f 619 add r10, r10, r3 ;b 151f 620 add r10, r10, r4 ;b 151f 621 add r10, r10, r5 ;b 151f 622 add r10, r10, r6 ;b 151f 623 add r10, r10, r7 ;b 151f 624 add r10, r10, r8 ;b 151f 625 add r10, r10, r9 ;b 151f 626 mtctr r11 ;b 154f /* r10 needs special handling */ 627 mtctr r11 ;b 153f /* r11 needs special handling */ 628 add r10, r10, r12 ;b 151f 629 add r10, r10, r13 ;b 151f 630 add r10, r10, r14 ;b 151f 631 add r10, r10, r15 ;b 151f 632 add r10, r10, r16 ;b 151f 633 add r10, r10, r17 ;b 151f 634 add r10, r10, r18 ;b 151f 635 add r10, r10, r19 ;b 151f 636 add r10, r10, r20 ;b 151f 637 add r10, r10, r21 ;b 151f 638 add r10, r10, r22 ;b 151f 639 add r10, r10, r23 ;b 151f 640 add r10, r10, r24 ;b 151f 641 add r10, r10, r25 ;b 151f 642 add r10, r10, r26 ;b 151f 643 add r10, r10, r27 ;b 151f 644 add r10, r10, r28 ;b 151f 645 add r10, r10, r29 ;b 151f 646 add r10, r10, r30 ;b 151f 647 add r10, r10, r31 648151: 649 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 650 beq 152f /* if reg RA is zero, don't add it */ 651 addi r11, r11, 150b@l /* add start of table */ 652 mtctr r11 /* load ctr with jump address */ 653 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 654 bctr /* jump into table */ 655152: 656 mfdar r11 657 mtctr r11 /* restore ctr reg from DAR */ 658 mtdar r10 /* save fault EA to DAR */ 659 b DARFixed /* Go back to normal TLB handling */ 660 661 /* special handling for r10,r11 since these are modified already */ 662153: lwz r11, 4(r0) /* load r11 from memory */ 663 b 155f 664154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */ 665155: add r10, r10, r11 /* add it */ 666 mfctr r11 /* restore r11 */ 667 b 151b 668#endif 669 670 .globl giveup_fpu 671giveup_fpu: 672 blr 673 674/* 675 * This is where the main kernel code starts. 676 */ 677start_here: 678 /* ptr to current */ 679 lis r2,init_task@h 680 ori r2,r2,init_task@l 681 682 /* ptr to phys current thread */ 683 tophys(r4,r2) 684 addi r4,r4,THREAD /* init task's THREAD */ 685 mtspr SPRN_SPRG_THREAD,r4 686 li r3,0 687 /* XXX What is that for ? SPRG2 appears otherwise unused on 8xx */ 688 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */ 689 690 /* stack */ 691 lis r1,init_thread_union@ha 692 addi r1,r1,init_thread_union@l 693 li r0,0 694 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 695 696 bl early_init /* We have to do this with MMU on */ 697 698/* 699 * Decide what sort of machine this is and initialize the MMU. 700 */ 701 mr r3,r31 702 mr r4,r30 703 mr r5,r29 704 mr r6,r28 705 mr r7,r27 706 bl machine_init 707 bl MMU_init 708 709/* 710 * Go back to running unmapped so we can load up new values 711 * and change to using our exception vectors. 712 * On the 8xx, all we have to do is invalidate the TLB to clear 713 * the old 8M byte TLB mappings and load the page table base register. 714 */ 715 /* The right way to do this would be to track it down through 716 * init's THREAD like the context switch code does, but this is 717 * easier......until someone changes init's static structures. 718 */ 719 lis r6, swapper_pg_dir@h 720 ori r6, r6, swapper_pg_dir@l 721 tophys(r6,r6) 722#ifdef CONFIG_8xx_CPU6 723 lis r4, cpu6_errata_word@h 724 ori r4, r4, cpu6_errata_word@l 725 li r3, 0x3980 726 stw r3, 12(r4) 727 lwz r3, 12(r4) 728#endif 729 mtspr SPRN_M_TWB, r6 730 lis r4,2f@h 731 ori r4,r4,2f@l 732 tophys(r4,r4) 733 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 734 mtspr SPRN_SRR0,r4 735 mtspr SPRN_SRR1,r3 736 rfi 737/* Load up the kernel context */ 7382: 739 SYNC /* Force all PTE updates to finish */ 740 tlbia /* Clear all TLB entries */ 741 sync /* wait for tlbia/tlbie to finish */ 742 TLBSYNC /* ... on all CPUs */ 743 744 /* set up the PTE pointers for the Abatron bdiGDB. 745 */ 746 tovirt(r6,r6) 747 lis r5, abatron_pteptrs@h 748 ori r5, r5, abatron_pteptrs@l 749 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 750 tophys(r5,r5) 751 stw r6, 0(r5) 752 753/* Now turn on the MMU for real! */ 754 li r4,MSR_KERNEL 755 lis r3,start_kernel@h 756 ori r3,r3,start_kernel@l 757 mtspr SPRN_SRR0,r3 758 mtspr SPRN_SRR1,r4 759 rfi /* enable MMU and jump to start_kernel */ 760 761/* Set up the initial MMU state so we can do the first level of 762 * kernel initialization. This maps the first 8 MBytes of memory 1:1 763 * virtual to physical. Also, set the cache mode since that is defined 764 * by TLB entries and perform any additional mapping (like of the IMMR). 765 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 766 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by 767 * these mappings is mapped by page tables. 768 */ 769initial_mmu: 770 tlbia /* Invalidate all TLB entries */ 771#ifdef CONFIG_PIN_TLB 772 lis r8, MI_RSV4I@h 773 ori r8, r8, 0x1c00 774#else 775 li r8, 0 776#endif 777 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 778 779#ifdef CONFIG_PIN_TLB 780 lis r10, (MD_RSV4I | MD_RESETVAL)@h 781 ori r10, r10, 0x1c00 782 mr r8, r10 783#else 784 lis r10, MD_RESETVAL@h 785#endif 786#ifndef CONFIG_8xx_COPYBACK 787 oris r10, r10, MD_WTDEF@h 788#endif 789 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 790 791 /* Now map the lower 8 Meg into the TLBs. For this quick hack, 792 * we can load the instruction and data TLB registers with the 793 * same values. 794 */ 795 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 796 ori r8, r8, MI_EVALID /* Mark it valid */ 797 mtspr SPRN_MI_EPN, r8 798 mtspr SPRN_MD_EPN, r8 799 li r8, MI_PS8MEG /* Set 8M byte page */ 800 ori r8, r8, MI_SVALID /* Make it valid */ 801 mtspr SPRN_MI_TWC, r8 802 mtspr SPRN_MD_TWC, r8 803 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 804 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 805 mtspr SPRN_MD_RPN, r8 806 lis r8, MI_Kp@h /* Set the protection mode */ 807 mtspr SPRN_MI_AP, r8 808 mtspr SPRN_MD_AP, r8 809 810 /* Map another 8 MByte at the IMMR to get the processor 811 * internal registers (among other things). 812 */ 813#ifdef CONFIG_PIN_TLB 814 addi r10, r10, 0x0100 815 mtspr SPRN_MD_CTR, r10 816#endif 817 mfspr r9, 638 /* Get current IMMR */ 818 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ 819 820 mr r8, r9 /* Create vaddr for TLB */ 821 ori r8, r8, MD_EVALID /* Mark it valid */ 822 mtspr SPRN_MD_EPN, r8 823 li r8, MD_PS8MEG /* Set 8M byte page */ 824 ori r8, r8, MD_SVALID /* Make it valid */ 825 mtspr SPRN_MD_TWC, r8 826 mr r8, r9 /* Create paddr for TLB */ 827 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 828 mtspr SPRN_MD_RPN, r8 829 830#ifdef CONFIG_PIN_TLB 831 /* Map two more 8M kernel data pages. 832 */ 833 addi r10, r10, 0x0100 834 mtspr SPRN_MD_CTR, r10 835 836 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 837 addis r8, r8, 0x0080 /* Add 8M */ 838 ori r8, r8, MI_EVALID /* Mark it valid */ 839 mtspr SPRN_MD_EPN, r8 840 li r9, MI_PS8MEG /* Set 8M byte page */ 841 ori r9, r9, MI_SVALID /* Make it valid */ 842 mtspr SPRN_MD_TWC, r9 843 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 844 addis r11, r11, 0x0080 /* Add 8M */ 845 mtspr SPRN_MD_RPN, r11 846 847 addis r8, r8, 0x0080 /* Add 8M */ 848 mtspr SPRN_MD_EPN, r8 849 mtspr SPRN_MD_TWC, r9 850 addis r11, r11, 0x0080 /* Add 8M */ 851 mtspr SPRN_MD_RPN, r11 852#endif 853 854 /* Since the cache is enabled according to the information we 855 * just loaded into the TLB, invalidate and enable the caches here. 856 * We should probably check/set other modes....later. 857 */ 858 lis r8, IDC_INVALL@h 859 mtspr SPRN_IC_CST, r8 860 mtspr SPRN_DC_CST, r8 861 lis r8, IDC_ENABLE@h 862 mtspr SPRN_IC_CST, r8 863#ifdef CONFIG_8xx_COPYBACK 864 mtspr SPRN_DC_CST, r8 865#else 866 /* For a debug option, I left this here to easily enable 867 * the write through cache mode 868 */ 869 lis r8, DC_SFWT@h 870 mtspr SPRN_DC_CST, r8 871 lis r8, IDC_ENABLE@h 872 mtspr SPRN_DC_CST, r8 873#endif 874 blr 875 876 877/* 878 * Set up to use a given MMU context. 879 * r3 is context number, r4 is PGD pointer. 880 * 881 * We place the physical address of the new task page directory loaded 882 * into the MMU base register, and set the ASID compare register with 883 * the new "context." 884 */ 885_GLOBAL(set_context) 886 887#ifdef CONFIG_BDI_SWITCH 888 /* Context switch the PTE pointer for the Abatron BDI2000. 889 * The PGDIR is passed as second argument. 890 */ 891 lis r5, KERNELBASE@h 892 lwz r5, 0xf0(r5) 893 stw r4, 0x4(r5) 894#endif 895 896#ifdef CONFIG_8xx_CPU6 897 lis r6, cpu6_errata_word@h 898 ori r6, r6, cpu6_errata_word@l 899 tophys (r4, r4) 900 li r7, 0x3980 901 stw r7, 12(r6) 902 lwz r7, 12(r6) 903 mtspr SPRN_M_TWB, r4 /* Update MMU base address */ 904 li r7, 0x3380 905 stw r7, 12(r6) 906 lwz r7, 12(r6) 907 mtspr SPRN_M_CASID, r3 /* Update context */ 908#else 909 mtspr SPRN_M_CASID,r3 /* Update context */ 910 tophys (r4, r4) 911 mtspr SPRN_M_TWB, r4 /* and pgd */ 912#endif 913 SYNC 914 blr 915 916#ifdef CONFIG_8xx_CPU6 917/* It's here because it is unique to the 8xx. 918 * It is important we get called with interrupts disabled. I used to 919 * do that, but it appears that all code that calls this already had 920 * interrupt disabled. 921 */ 922 .globl set_dec_cpu6 923set_dec_cpu6: 924 lis r7, cpu6_errata_word@h 925 ori r7, r7, cpu6_errata_word@l 926 li r4, 0x2c00 927 stw r4, 8(r7) 928 lwz r4, 8(r7) 929 mtspr 22, r3 /* Update Decrementer */ 930 SYNC 931 blr 932#endif 933 934/* 935 * We put a few things here that have to be page-aligned. 936 * This stuff goes at the beginning of the data segment, 937 * which is page-aligned. 938 */ 939 .data 940 .globl sdata 941sdata: 942 .globl empty_zero_page 943empty_zero_page: 944 .space 4096 945 946 .globl swapper_pg_dir 947swapper_pg_dir: 948 .space 4096 949 950/* Room for two PTE table poiners, usually the kernel and current user 951 * pointer to their respective root page table (pgdir). 952 */ 953abatron_pteptrs: 954 .space 8 955 956#ifdef CONFIG_8xx_CPU6 957 .globl cpu6_errata_word 958cpu6_errata_word: 959 .space 16 960#endif 961 962