1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33#include <asm/fixmap.h> 34#include <asm/export.h> 35 36/* Macro to make the code more readable. */ 37#ifdef CONFIG_8xx_CPU6 38#define SPRN_MI_TWC_ADDR 0x2b80 39#define SPRN_MI_RPN_ADDR 0x2d80 40#define SPRN_MD_TWC_ADDR 0x3b80 41#define SPRN_MD_RPN_ADDR 0x3d80 42 43#define MTSPR_CPU6(spr, reg, treg) \ 44 li treg, spr##_ADDR; \ 45 stw treg, 12(r0); \ 46 lwz treg, 12(r0); \ 47 mtspr spr, reg 48#else 49#define MTSPR_CPU6(spr, reg, treg) \ 50 mtspr spr, reg 51#endif 52 53/* Macro to test if an address is a kernel address */ 54#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 55#define IS_KERNEL(tmp, addr) \ 56 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */ 57#define BRANCH_UNLESS_KERNEL(label) beq label 58#else 59#define IS_KERNEL(tmp, addr) \ 60 rlwinm tmp, addr, 16, 16, 31; \ 61 cmpli cr0, tmp, PAGE_OFFSET >> 16 62#define BRANCH_UNLESS_KERNEL(label) blt label 63#endif 64 65 66/* 67 * Value for the bits that have fixed value in RPN entries. 68 * Also used for tagging DAR for DTLBerror. 69 */ 70#ifdef CONFIG_PPC_16K_PAGES 71#define RPN_PATTERN (0x00f0 | MD_SPS16K) 72#else 73#define RPN_PATTERN 0x00f0 74#endif 75 76#define PAGE_SHIFT_512K 19 77#define PAGE_SHIFT_8M 23 78 79 __HEAD 80_ENTRY(_stext); 81_ENTRY(_start); 82 83/* MPC8xx 84 * This port was done on an MBX board with an 860. Right now I only 85 * support an ELF compressed (zImage) boot from EPPC-Bug because the 86 * code there loads up some registers before calling us: 87 * r3: ptr to board info data 88 * r4: initrd_start or if no initrd then 0 89 * r5: initrd_end - unused if r4 is 0 90 * r6: Start of command line string 91 * r7: End of command line string 92 * 93 * I decided to use conditional compilation instead of checking PVR and 94 * adding more processor specific branches around code I don't need. 95 * Since this is an embedded processor, I also appreciate any memory 96 * savings I can get. 97 * 98 * The MPC8xx does not have any BATs, but it supports large page sizes. 99 * We first initialize the MMU to support 8M byte pages, then load one 100 * entry into each of the instruction and data TLBs to map the first 101 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 102 * the "internal" processor registers before MMU_init is called. 103 * 104 * -- Dan 105 */ 106 .globl __start 107__start: 108 mr r31,r3 /* save device tree ptr */ 109 110 /* We have to turn on the MMU right away so we get cache modes 111 * set correctly. 112 */ 113 bl initial_mmu 114 115/* We now have the lower 8 Meg mapped into TLB entries, and the caches 116 * ready to work. 117 */ 118 119turn_on_mmu: 120 mfmsr r0 121 ori r0,r0,MSR_DR|MSR_IR 122 mtspr SPRN_SRR1,r0 123 lis r0,start_here@h 124 ori r0,r0,start_here@l 125 mtspr SPRN_SRR0,r0 126 SYNC 127 rfi /* enables MMU */ 128 129/* 130 * Exception entry code. This code runs with address translation 131 * turned off, i.e. using physical addresses. 132 * We assume sprg3 has the physical address of the current 133 * task's thread_struct. 134 */ 135#define EXCEPTION_PROLOG \ 136 EXCEPTION_PROLOG_0; \ 137 mfcr r10; \ 138 EXCEPTION_PROLOG_1; \ 139 EXCEPTION_PROLOG_2 140 141#define EXCEPTION_PROLOG_0 \ 142 mtspr SPRN_SPRG_SCRATCH0,r10; \ 143 mtspr SPRN_SPRG_SCRATCH1,r11 144 145#define EXCEPTION_PROLOG_1 \ 146 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 147 andi. r11,r11,MSR_PR; \ 148 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 149 beq 1f; \ 150 mfspr r11,SPRN_SPRG_THREAD; \ 151 lwz r11,THREAD_INFO-THREAD(r11); \ 152 addi r11,r11,THREAD_SIZE; \ 153 tophys(r11,r11); \ 1541: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 155 156 157#define EXCEPTION_PROLOG_2 \ 158 stw r10,_CCR(r11); /* save registers */ \ 159 stw r12,GPR12(r11); \ 160 stw r9,GPR9(r11); \ 161 mfspr r10,SPRN_SPRG_SCRATCH0; \ 162 stw r10,GPR10(r11); \ 163 mfspr r12,SPRN_SPRG_SCRATCH1; \ 164 stw r12,GPR11(r11); \ 165 mflr r10; \ 166 stw r10,_LINK(r11); \ 167 mfspr r12,SPRN_SRR0; \ 168 mfspr r9,SPRN_SRR1; \ 169 stw r1,GPR1(r11); \ 170 stw r1,0(r11); \ 171 tovirt(r1,r11); /* set new kernel sp */ \ 172 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 173 MTMSRD(r10); /* (except for mach check in rtas) */ \ 174 stw r0,GPR0(r11); \ 175 SAVE_4GPRS(3, r11); \ 176 SAVE_2GPRS(7, r11) 177 178/* 179 * Exception exit code. 180 */ 181#define EXCEPTION_EPILOG_0 \ 182 mfspr r10,SPRN_SPRG_SCRATCH0; \ 183 mfspr r11,SPRN_SPRG_SCRATCH1 184 185/* 186 * Note: code which follows this uses cr0.eq (set if from kernel), 187 * r11, r12 (SRR0), and r9 (SRR1). 188 * 189 * Note2: once we have set r1 we are in a position to take exceptions 190 * again, and we could thus set MSR:RI at that point. 191 */ 192 193/* 194 * Exception vectors. 195 */ 196#define EXCEPTION(n, label, hdlr, xfer) \ 197 . = n; \ 198label: \ 199 EXCEPTION_PROLOG; \ 200 addi r3,r1,STACK_FRAME_OVERHEAD; \ 201 xfer(n, hdlr) 202 203#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 204 li r10,trap; \ 205 stw r10,_TRAP(r11); \ 206 li r10,MSR_KERNEL; \ 207 copyee(r10, r9); \ 208 bl tfer; \ 209i##n: \ 210 .long hdlr; \ 211 .long ret 212 213#define COPY_EE(d, s) rlwimi d,s,0,16,16 214#define NOCOPY(d, s) 215 216#define EXC_XFER_STD(n, hdlr) \ 217 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 218 ret_from_except_full) 219 220#define EXC_XFER_LITE(n, hdlr) \ 221 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 222 ret_from_except) 223 224#define EXC_XFER_EE(n, hdlr) \ 225 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 226 ret_from_except_full) 227 228#define EXC_XFER_EE_LITE(n, hdlr) \ 229 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 230 ret_from_except) 231 232/* System reset */ 233 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD) 234 235/* Machine check */ 236 . = 0x200 237MachineCheck: 238 EXCEPTION_PROLOG 239 mfspr r4,SPRN_DAR 240 stw r4,_DAR(r11) 241 li r5,RPN_PATTERN 242 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 243 mfspr r5,SPRN_DSISR 244 stw r5,_DSISR(r11) 245 addi r3,r1,STACK_FRAME_OVERHEAD 246 EXC_XFER_STD(0x200, machine_check_exception) 247 248/* Data access exception. 249 * This is "never generated" by the MPC8xx. 250 */ 251 . = 0x300 252DataAccess: 253 254/* Instruction access exception. 255 * This is "never generated" by the MPC8xx. 256 */ 257 . = 0x400 258InstructionAccess: 259 260/* External interrupt */ 261 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 262 263/* Alignment exception */ 264 . = 0x600 265Alignment: 266 EXCEPTION_PROLOG 267 mfspr r4,SPRN_DAR 268 stw r4,_DAR(r11) 269 li r5,RPN_PATTERN 270 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 271 mfspr r5,SPRN_DSISR 272 stw r5,_DSISR(r11) 273 addi r3,r1,STACK_FRAME_OVERHEAD 274 EXC_XFER_EE(0x600, alignment_exception) 275 276/* Program check exception */ 277 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 278 279/* No FPU on MPC8xx. This exception is not supposed to happen. 280*/ 281 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 282 283/* Decrementer */ 284 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 285 286 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 287 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 288 289/* System call */ 290 . = 0xc00 291SystemCall: 292 EXCEPTION_PROLOG 293 EXC_XFER_EE_LITE(0xc00, DoSyscall) 294 295/* Single step - not used on 601 */ 296 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 297 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 298 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 299 300/* On the MPC8xx, this is a software emulation interrupt. It occurs 301 * for all unimplemented and illegal instructions. 302 */ 303 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 304 305 . = 0x1100 306/* 307 * For the MPC8xx, this is a software tablewalk to load the instruction 308 * TLB. The task switch loads the M_TW register with the pointer to the first 309 * level table. 310 * If we discover there is no second level table (value is zero) or if there 311 * is an invalid pte, we load that into the TLB, which causes another fault 312 * into the TLB Error interrupt where we can handle such problems. 313 * We have to use the MD_xxx registers for the tablewalk because the 314 * equivalent MI_xxx registers only perform the attribute functions. 315 */ 316 317#ifdef CONFIG_8xx_CPU15 318#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ 319 addi tmp, addr, PAGE_SIZE; \ 320 tlbie tmp; \ 321 addi tmp, addr, -PAGE_SIZE; \ 322 tlbie tmp 323#else 324#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) 325#endif 326 327InstructionTLBMiss: 328#if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) || defined (CONFIG_HUGETLB_PAGE) 329 mtspr SPRN_SPRG_SCRATCH2, r3 330#endif 331 EXCEPTION_PROLOG_0 332#ifdef CONFIG_PPC_8xx_PERF_EVENT 333 lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha 334 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) 335 addi r11, r11, 1 336 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) 337#endif 338 339 /* If we are faulting a kernel address, we have to use the 340 * kernel page tables. 341 */ 342 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 343 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) 344 /* Only modules will cause ITLB Misses as we always 345 * pin the first 8MB of kernel memory */ 346#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) || defined (CONFIG_HUGETLB_PAGE) 347 mfcr r3 348#endif 349#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) 350 IS_KERNEL(r11, r10) 351#endif 352 mfspr r11, SPRN_M_TW /* Get level 1 table */ 353#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) 354 BRANCH_UNLESS_KERNEL(3f) 355 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3563: 357#endif 358 /* Insert level 1 index */ 359 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 360 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 361 362 /* Extract level 2 index */ 363 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 364#ifdef CONFIG_HUGETLB_PAGE 365 mtcr r11 366 bt- 28, 10f /* bit 28 = Large page (8M) */ 367 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */ 368#endif 369 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 370 lwz r10, 0(r10) /* Get the pte */ 3714: 372#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) || defined (CONFIG_HUGETLB_PAGE) 373 mtcr r3 374#endif 375 /* Insert the APG into the TWC from the Linux PTE. */ 376 rlwimi r11, r10, 0, 25, 26 377 /* Load the MI_TWC with the attributes for this "segment." */ 378 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ 379 380#if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES) 381 rlwimi r10, r11, 1, MI_SPS16K 382#endif 383#ifdef CONFIG_SWAP 384 rlwinm r11, r10, 32-5, _PAGE_PRESENT 385 and r11, r11, r10 386 rlwimi r10, r11, 0, _PAGE_PRESENT 387#endif 388 li r11, RPN_PATTERN 389 /* The Linux PTE won't go exactly into the MMU TLB. 390 * Software indicator bits 20-23 and 28 must be clear. 391 * Software indicator bits 24, 25, 26, and 27 must be 392 * set. All other Linux PTE bits control the behavior 393 * of the MMU. 394 */ 395#if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES) 396 rlwimi r10, r11, 0, 0x0ff0 /* Set 24-27, clear 20-23 */ 397#else 398 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */ 399#endif 400 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */ 401 402 /* Restore registers */ 403#if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) || defined (CONFIG_HUGETLB_PAGE) 404 mfspr r3, SPRN_SPRG_SCRATCH2 405#endif 406 EXCEPTION_EPILOG_0 407 rfi 408 409#ifdef CONFIG_HUGETLB_PAGE 41010: /* 8M pages */ 411#ifdef CONFIG_PPC_16K_PAGES 412 /* Extract level 2 index */ 413 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 414 /* Add level 2 base */ 415 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 416#else 417 /* Level 2 base */ 418 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK 419#endif 420 lwz r10, 0(r10) /* Get the pte */ 421 rlwinm r11, r11, 0, 0xf 422 b 4b 423 42420: /* 512k pages */ 425 /* Extract level 2 index */ 426 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 427 /* Add level 2 base */ 428 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 429 lwz r10, 0(r10) /* Get the pte */ 430 rlwinm r11, r11, 0, 0xf 431 b 4b 432#endif 433 434 . = 0x1200 435DataStoreTLBMiss: 436 mtspr SPRN_SPRG_SCRATCH2, r3 437 EXCEPTION_PROLOG_0 438#ifdef CONFIG_PPC_8xx_PERF_EVENT 439 lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha 440 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) 441 addi r11, r11, 1 442 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) 443#endif 444 mfcr r3 445 446 /* If we are faulting a kernel address, we have to use the 447 * kernel page tables. 448 */ 449 mfspr r10, SPRN_MD_EPN 450 rlwinm r10, r10, 16, 0xfff8 451 cmpli cr0, r10, PAGE_OFFSET@h 452 mfspr r11, SPRN_M_TW /* Get level 1 table */ 453 blt+ 3f 454#ifndef CONFIG_PIN_TLB_IMMR 455 cmpli cr0, r10, VIRT_IMMR_BASE@h 456#endif 457_ENTRY(DTLBMiss_cmp) 458 cmpli cr7, r10, (PAGE_OFFSET + 0x1800000)@h 459 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 460#ifndef CONFIG_PIN_TLB_IMMR 461_ENTRY(DTLBMiss_jmp) 462 beq- DTLBMissIMMR 463#endif 464 blt cr7, DTLBMissLinear 4653: 466 mfspr r10, SPRN_MD_EPN 467 468 /* Insert level 1 index */ 469 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 470 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 471 472 /* We have a pte table, so load fetch the pte from the table. 473 */ 474 /* Extract level 2 index */ 475 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 476#ifdef CONFIG_HUGETLB_PAGE 477 mtcr r11 478 bt- 28, 10f /* bit 28 = Large page (8M) */ 479 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */ 480#endif 481 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 482 lwz r10, 0(r10) /* Get the pte */ 4834: 484 mtcr r3 485 486 /* Insert the Guarded flag and APG into the TWC from the Linux PTE. 487 * It is bit 26-27 of both the Linux PTE and the TWC (at least 488 * I got that right :-). It will be better when we can put 489 * this into the Linux pgd/pmd and load it in the operation 490 * above. 491 */ 492 rlwimi r11, r10, 0, 26, 27 493 /* Insert the WriteThru flag into the TWC from the Linux PTE. 494 * It is bit 25 in the Linux PTE and bit 30 in the TWC 495 */ 496 rlwimi r11, r10, 32-5, 30, 30 497 MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 498 499 /* In 4k pages mode, SPS (bit 28) in RPN must match PS[1] (bit 29) 500 * In 16k pages mode, SPS is always 1 */ 501#if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES) 502 rlwimi r10, r11, 1, MD_SPS16K 503#endif 504 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 505 * We also need to know if the insn is a load/store, so: 506 * Clear _PAGE_PRESENT and load that which will 507 * trap into DTLB Error with store bit set accordinly. 508 */ 509 /* PRESENT=0x1, ACCESSED=0x20 510 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 511 * r10 = (r10 & ~PRESENT) | r11; 512 */ 513#ifdef CONFIG_SWAP 514 rlwinm r11, r10, 32-5, _PAGE_PRESENT 515 and r11, r11, r10 516 rlwimi r10, r11, 0, _PAGE_PRESENT 517#endif 518 /* The Linux PTE won't go exactly into the MMU TLB. 519 * Software indicator bits 22 and 28 must be clear. 520 * Software indicator bits 24, 25, 26, and 27 must be 521 * set. All other Linux PTE bits control the behavior 522 * of the MMU. 523 */ 524 li r11, RPN_PATTERN 525#if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES) 526 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */ 527#else 528 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 529#endif 530 rlwimi r10, r11, 0, 20, 20 /* clear 20 */ 531 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ 532 533 /* Restore registers */ 534 mfspr r3, SPRN_SPRG_SCRATCH2 535 mtspr SPRN_DAR, r11 /* Tag DAR */ 536 EXCEPTION_EPILOG_0 537 rfi 538 539#ifdef CONFIG_HUGETLB_PAGE 54010: /* 8M pages */ 541 /* Extract level 2 index */ 542#ifdef CONFIG_PPC_16K_PAGES 543 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 544 /* Add level 2 base */ 545 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 546#else 547 /* Level 2 base */ 548 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK 549#endif 550 lwz r10, 0(r10) /* Get the pte */ 551 rlwinm r11, r11, 0, 0xf 552 b 4b 553 55420: /* 512k pages */ 555 /* Extract level 2 index */ 556 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 557 /* Add level 2 base */ 558 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 559 lwz r10, 0(r10) /* Get the pte */ 560 rlwinm r11, r11, 0, 0xf 561 b 4b 562#endif 563 564/* This is an instruction TLB error on the MPC8xx. This could be due 565 * to many reasons, such as executing guarded memory or illegal instruction 566 * addresses. There is nothing to do but handle a big time error fault. 567 */ 568 . = 0x1300 569InstructionTLBError: 570 EXCEPTION_PROLOG 571 mr r4,r12 572 mr r5,r9 573 andis. r10,r5,0x4000 574 beq+ 1f 575 tlbie r4 576itlbie: 577 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 5781: EXC_XFER_LITE(0x400, handle_page_fault) 579 580/* This is the data TLB error on the MPC8xx. This could be due to 581 * many reasons, including a dirty update to a pte. We bail out to 582 * a higher level function that can handle it. 583 */ 584 . = 0x1400 585DataTLBError: 586 EXCEPTION_PROLOG_0 587 mfcr r10 588 589 mfspr r11, SPRN_DAR 590 cmpwi cr0, r11, RPN_PATTERN 591 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 592DARFixed:/* Return from dcbx instruction bug workaround */ 593 EXCEPTION_PROLOG_1 594 EXCEPTION_PROLOG_2 595 mfspr r5,SPRN_DSISR 596 stw r5,_DSISR(r11) 597 mfspr r4,SPRN_DAR 598 andis. r10,r5,0x4000 599 beq+ 1f 600 tlbie r4 601dtlbie: 6021: li r10,RPN_PATTERN 603 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 604 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 605 EXC_XFER_LITE(0x300, handle_page_fault) 606 607 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 608 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 609 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 610 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 611 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 612 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 613 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 614 615/* On the MPC8xx, these next four traps are used for development 616 * support of breakpoints and such. Someday I will get around to 617 * using them. 618 */ 619 . = 0x1c00 620DataBreakpoint: 621 EXCEPTION_PROLOG_0 622 mfcr r10 623 mfspr r11, SPRN_SRR0 624 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l 625 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l 626 beq- cr0, 11f 627 beq- cr7, 11f 628 EXCEPTION_PROLOG_1 629 EXCEPTION_PROLOG_2 630 addi r3,r1,STACK_FRAME_OVERHEAD 631 mfspr r4,SPRN_BAR 632 stw r4,_DAR(r11) 633 mfspr r5,SPRN_DSISR 634 EXC_XFER_EE(0x1c00, do_break) 63511: 636 mtcr r10 637 EXCEPTION_EPILOG_0 638 rfi 639 640#ifdef CONFIG_PPC_8xx_PERF_EVENT 641 . = 0x1d00 642InstructionBreakpoint: 643 EXCEPTION_PROLOG_0 644 lis r10, (instruction_counter - PAGE_OFFSET)@ha 645 lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10) 646 addi r11, r11, -1 647 stw r11, (instruction_counter - PAGE_OFFSET)@l(r10) 648 lis r10, 0xffff 649 ori r10, r10, 0x01 650 mtspr SPRN_COUNTA, r10 651 EXCEPTION_EPILOG_0 652 rfi 653#else 654 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 655#endif 656 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 657 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 658 659 . = 0x2000 660 661/* 662 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM. 663 * not enough space in the DataStoreTLBMiss area. 664 */ 665DTLBMissIMMR: 666 mtcr r3 667 /* Set 512k byte guarded page and mark it valid */ 668 li r10, MD_PS512K | MD_GUARDED | MD_SVALID 669 MTSPR_CPU6(SPRN_MD_TWC, r10, r11) 670 mfspr r10, SPRN_IMMR /* Get current IMMR */ 671 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ 672 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 673 _PAGE_PRESENT | _PAGE_NO_CACHE 674 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 675 676 li r11, RPN_PATTERN 677 mtspr SPRN_DAR, r11 /* Tag DAR */ 678 mfspr r3, SPRN_SPRG_SCRATCH2 679 EXCEPTION_EPILOG_0 680 rfi 681 682DTLBMissLinear: 683 mtcr r3 684 /* Set 8M byte page and mark it valid */ 685 li r11, MD_PS8MEG | MD_SVALID 686 MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 687 rlwinm r10, r10, 16, 0x0f800000 /* 8xx supports max 256Mb RAM */ 688 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 689 _PAGE_PRESENT 690 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 691 692 li r11, RPN_PATTERN 693 mtspr SPRN_DAR, r11 /* Tag DAR */ 694 mfspr r3, SPRN_SPRG_SCRATCH2 695 EXCEPTION_EPILOG_0 696 rfi 697 698/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 699 * by decoding the registers used by the dcbx instruction and adding them. 700 * DAR is set to the calculated address. 701 */ 702 /* define if you don't want to use self modifying code */ 703#define NO_SELF_MODIFYING_CODE 704FixupDAR:/* Entry point for dcbx workaround. */ 705 mtspr SPRN_SPRG_SCRATCH2, r10 706 /* fetch instruction from memory. */ 707 mfspr r10, SPRN_SRR0 708 IS_KERNEL(r11, r10) 709 mfspr r11, SPRN_M_TW /* Get level 1 table */ 710 BRANCH_UNLESS_KERNEL(3f) 711 rlwinm r11, r10, 16, 0xfff8 712_ENTRY(FixupDAR_cmp) 713 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 714 /* create physical page address from effective address */ 715 tophys(r11, r10) 716 blt- cr7, 201f 717 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 718 /* Insert level 1 index */ 7193: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 720 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 721 mtcr r11 722 bt 28,200f /* bit 28 = Large page (8M) */ 723 bt 29,202f /* bit 29 = Large page (8M or 512K) */ 724 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ 725 /* Insert level 2 index */ 726 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 727 lwz r11, 0(r11) /* Get the pte */ 728 /* concat physical page address(r11) and page offset(r10) */ 729 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 730201: lwz r11,0(r11) 731/* Check if it really is a dcbx instruction. */ 732/* dcbt and dcbtst does not generate DTLB Misses/Errors, 733 * no need to include them here */ 734 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 735 rlwinm r10, r10, 0, 21, 5 736 cmpwi cr0, r10, 2028 /* Is dcbz? */ 737 beq+ 142f 738 cmpwi cr0, r10, 940 /* Is dcbi? */ 739 beq+ 142f 740 cmpwi cr0, r10, 108 /* Is dcbst? */ 741 beq+ 144f /* Fix up store bit! */ 742 cmpwi cr0, r10, 172 /* Is dcbf? */ 743 beq+ 142f 744 cmpwi cr0, r10, 1964 /* Is icbi? */ 745 beq+ 142f 746141: mfspr r10,SPRN_SPRG_SCRATCH2 747 b DARFixed /* Nope, go back to normal TLB processing */ 748 749 /* concat physical page address(r11) and page offset(r10) */ 750200: 751#ifdef CONFIG_PPC_16K_PAGES 752 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 753 rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 754#else 755 rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK 756#endif 757 lwz r11, 0(r11) /* Get the pte */ 758 /* concat physical page address(r11) and page offset(r10) */ 759 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31 760 b 201b 761 762202: 763 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 764 rlwimi r11, r10, 32 - (PAGE_SHIFT_512K - 2), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 765 lwz r11, 0(r11) /* Get the pte */ 766 /* concat physical page address(r11) and page offset(r10) */ 767 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31 768 b 201b 769 770144: mfspr r10, SPRN_DSISR 771 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 772 mtspr SPRN_DSISR, r10 773142: /* continue, it was a dcbx, dcbi instruction. */ 774#ifndef NO_SELF_MODIFYING_CODE 775 andis. r10,r11,0x1f /* test if reg RA is r0 */ 776 li r10,modified_instr@l 777 dcbtst r0,r10 /* touch for store */ 778 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 779 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 780 ori r11,r11,532 781 stw r11,0(r10) /* store add/and instruction */ 782 dcbf 0,r10 /* flush new instr. to memory. */ 783 icbi 0,r10 /* invalidate instr. cache line */ 784 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ 785 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ 786 isync /* Wait until new instr is loaded from memory */ 787modified_instr: 788 .space 4 /* this is where the add instr. is stored */ 789 bne+ 143f 790 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 791143: mtdar r10 /* store faulting EA in DAR */ 792 mfspr r10,SPRN_SPRG_SCRATCH2 793 b DARFixed /* Go back to normal TLB handling */ 794#else 795 mfctr r10 796 mtdar r10 /* save ctr reg in DAR */ 797 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 798 addi r10, r10, 150f@l /* add start of table */ 799 mtctr r10 /* load ctr with jump address */ 800 xor r10, r10, r10 /* sum starts at zero */ 801 bctr /* jump into table */ 802150: 803 add r10, r10, r0 ;b 151f 804 add r10, r10, r1 ;b 151f 805 add r10, r10, r2 ;b 151f 806 add r10, r10, r3 ;b 151f 807 add r10, r10, r4 ;b 151f 808 add r10, r10, r5 ;b 151f 809 add r10, r10, r6 ;b 151f 810 add r10, r10, r7 ;b 151f 811 add r10, r10, r8 ;b 151f 812 add r10, r10, r9 ;b 151f 813 mtctr r11 ;b 154f /* r10 needs special handling */ 814 mtctr r11 ;b 153f /* r11 needs special handling */ 815 add r10, r10, r12 ;b 151f 816 add r10, r10, r13 ;b 151f 817 add r10, r10, r14 ;b 151f 818 add r10, r10, r15 ;b 151f 819 add r10, r10, r16 ;b 151f 820 add r10, r10, r17 ;b 151f 821 add r10, r10, r18 ;b 151f 822 add r10, r10, r19 ;b 151f 823 add r10, r10, r20 ;b 151f 824 add r10, r10, r21 ;b 151f 825 add r10, r10, r22 ;b 151f 826 add r10, r10, r23 ;b 151f 827 add r10, r10, r24 ;b 151f 828 add r10, r10, r25 ;b 151f 829 add r10, r10, r26 ;b 151f 830 add r10, r10, r27 ;b 151f 831 add r10, r10, r28 ;b 151f 832 add r10, r10, r29 ;b 151f 833 add r10, r10, r30 ;b 151f 834 add r10, r10, r31 835151: 836 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 837 beq 152f /* if reg RA is zero, don't add it */ 838 addi r11, r11, 150b@l /* add start of table */ 839 mtctr r11 /* load ctr with jump address */ 840 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 841 bctr /* jump into table */ 842152: 843 mfdar r11 844 mtctr r11 /* restore ctr reg from DAR */ 845 mtdar r10 /* save fault EA to DAR */ 846 mfspr r10,SPRN_SPRG_SCRATCH2 847 b DARFixed /* Go back to normal TLB handling */ 848 849 /* special handling for r10,r11 since these are modified already */ 850153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 851 add r10, r10, r11 /* add it */ 852 mfctr r11 /* restore r11 */ 853 b 151b 854154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 855 add r10, r10, r11 /* add it */ 856 mfctr r11 /* restore r11 */ 857 b 151b 858#endif 859 860/* 861 * This is where the main kernel code starts. 862 */ 863start_here: 864 /* ptr to current */ 865 lis r2,init_task@h 866 ori r2,r2,init_task@l 867 868 /* ptr to phys current thread */ 869 tophys(r4,r2) 870 addi r4,r4,THREAD /* init task's THREAD */ 871 mtspr SPRN_SPRG_THREAD,r4 872 873 /* stack */ 874 lis r1,init_thread_union@ha 875 addi r1,r1,init_thread_union@l 876 li r0,0 877 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 878 879 bl early_init /* We have to do this with MMU on */ 880 881/* 882 * Decide what sort of machine this is and initialize the MMU. 883 */ 884 li r3,0 885 mr r4,r31 886 bl machine_init 887 bl MMU_init 888 889/* 890 * Go back to running unmapped so we can load up new values 891 * and change to using our exception vectors. 892 * On the 8xx, all we have to do is invalidate the TLB to clear 893 * the old 8M byte TLB mappings and load the page table base register. 894 */ 895 /* The right way to do this would be to track it down through 896 * init's THREAD like the context switch code does, but this is 897 * easier......until someone changes init's static structures. 898 */ 899 lis r6, swapper_pg_dir@ha 900 tophys(r6,r6) 901#ifdef CONFIG_8xx_CPU6 902 lis r4, cpu6_errata_word@h 903 ori r4, r4, cpu6_errata_word@l 904 li r3, 0x3f80 905 stw r3, 12(r4) 906 lwz r3, 12(r4) 907#endif 908 mtspr SPRN_M_TW, r6 909 lis r4,2f@h 910 ori r4,r4,2f@l 911 tophys(r4,r4) 912 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 913 mtspr SPRN_SRR0,r4 914 mtspr SPRN_SRR1,r3 915 rfi 916/* Load up the kernel context */ 9172: 918 SYNC /* Force all PTE updates to finish */ 919 tlbia /* Clear all TLB entries */ 920 sync /* wait for tlbia/tlbie to finish */ 921 TLBSYNC /* ... on all CPUs */ 922 923 /* set up the PTE pointers for the Abatron bdiGDB. 924 */ 925 tovirt(r6,r6) 926 lis r5, abatron_pteptrs@h 927 ori r5, r5, abatron_pteptrs@l 928 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 929 tophys(r5,r5) 930 stw r6, 0(r5) 931 932/* Now turn on the MMU for real! */ 933 li r4,MSR_KERNEL 934 lis r3,start_kernel@h 935 ori r3,r3,start_kernel@l 936 mtspr SPRN_SRR0,r3 937 mtspr SPRN_SRR1,r4 938 rfi /* enable MMU and jump to start_kernel */ 939 940/* Set up the initial MMU state so we can do the first level of 941 * kernel initialization. This maps the first 8 MBytes of memory 1:1 942 * virtual to physical. Also, set the cache mode since that is defined 943 * by TLB entries and perform any additional mapping (like of the IMMR). 944 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 945 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 946 * these mappings is mapped by page tables. 947 */ 948initial_mmu: 949 li r8, 0 950 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 951 lis r10, MD_RESETVAL@h 952#ifndef CONFIG_8xx_COPYBACK 953 oris r10, r10, MD_WTDEF@h 954#endif 955 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 956 957 tlbia /* Invalidate all TLB entries */ 958/* Always pin the first 8 MB ITLB to prevent ITLB 959 misses while mucking around with SRR0/SRR1 in asm 960*/ 961 lis r8, MI_RSV4I@h 962 ori r8, r8, 0x1c00 963 964 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 965 966#ifdef CONFIG_PIN_TLB 967 oris r10, r10, MD_RSV4I@h 968 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 969#endif 970 971 /* Now map the lower 8 Meg into the ITLB. */ 972 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 973 ori r8, r8, MI_EVALID /* Mark it valid */ 974 mtspr SPRN_MI_EPN, r8 975 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */ 976 ori r8, r8, MI_SVALID /* Make it valid */ 977 mtspr SPRN_MI_TWC, r8 978 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 979 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 980 981 lis r8, MI_APG_INIT@h /* Set protection modes */ 982 ori r8, r8, MI_APG_INIT@l 983 mtspr SPRN_MI_AP, r8 984 lis r8, MD_APG_INIT@h 985 ori r8, r8, MD_APG_INIT@l 986 mtspr SPRN_MD_AP, r8 987 988 /* Map a 512k page for the IMMR to get the processor 989 * internal registers (among other things). 990 */ 991#ifdef CONFIG_PIN_TLB_IMMR 992 ori r10, r10, 0x1c00 993 mtspr SPRN_MD_CTR, r10 994 995 mfspr r9, 638 /* Get current IMMR */ 996 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */ 997 998 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */ 999 ori r8, r8, MD_EVALID /* Mark it valid */ 1000 mtspr SPRN_MD_EPN, r8 1001 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */ 1002 ori r8, r8, MD_SVALID /* Make it valid */ 1003 mtspr SPRN_MD_TWC, r8 1004 mr r8, r9 /* Create paddr for TLB */ 1005 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 1006 mtspr SPRN_MD_RPN, r8 1007#endif 1008 1009 /* Since the cache is enabled according to the information we 1010 * just loaded into the TLB, invalidate and enable the caches here. 1011 * We should probably check/set other modes....later. 1012 */ 1013 lis r8, IDC_INVALL@h 1014 mtspr SPRN_IC_CST, r8 1015 mtspr SPRN_DC_CST, r8 1016 lis r8, IDC_ENABLE@h 1017 mtspr SPRN_IC_CST, r8 1018#ifdef CONFIG_8xx_COPYBACK 1019 mtspr SPRN_DC_CST, r8 1020#else 1021 /* For a debug option, I left this here to easily enable 1022 * the write through cache mode 1023 */ 1024 lis r8, DC_SFWT@h 1025 mtspr SPRN_DC_CST, r8 1026 lis r8, IDC_ENABLE@h 1027 mtspr SPRN_DC_CST, r8 1028#endif 1029 /* Disable debug mode entry on breakpoints */ 1030 mfspr r8, SPRN_DER 1031#ifdef CONFIG_PPC_8xx_PERF_EVENT 1032 rlwinm r8, r8, 0, ~0xc 1033#else 1034 rlwinm r8, r8, 0, ~0x8 1035#endif 1036 mtspr SPRN_DER, r8 1037 blr 1038 1039 1040/* 1041 * We put a few things here that have to be page-aligned. 1042 * This stuff goes at the beginning of the data segment, 1043 * which is page-aligned. 1044 */ 1045 .data 1046 .globl sdata 1047sdata: 1048 .globl empty_zero_page 1049 .align PAGE_SHIFT 1050empty_zero_page: 1051 .space PAGE_SIZE 1052EXPORT_SYMBOL(empty_zero_page) 1053 1054 .globl swapper_pg_dir 1055swapper_pg_dir: 1056 .space PGD_TABLE_SIZE 1057 1058/* Room for two PTE table poiners, usually the kernel and current user 1059 * pointer to their respective root page table (pgdir). 1060 */ 1061abatron_pteptrs: 1062 .space 8 1063 1064#ifdef CONFIG_8xx_CPU6 1065 .globl cpu6_errata_word 1066cpu6_errata_word: 1067 .space 16 1068#endif 1069 1070#ifdef CONFIG_PPC_8xx_PERF_EVENT 1071 .globl itlb_miss_counter 1072itlb_miss_counter: 1073 .space 4 1074 1075 .globl dtlb_miss_counter 1076dtlb_miss_counter: 1077 .space 4 1078 1079 .globl instruction_counter 1080instruction_counter: 1081 .space 4 1082#endif 1083