1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33#include <asm/export.h> 34#include <asm/code-patching-asm.h> 35 36#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 37/* By simply checking Address >= 0x80000000, we know if its a kernel address */ 38#define SIMPLE_KERNEL_ADDRESS 1 39#endif 40 41/* 42 * We need an ITLB miss handler for kernel addresses if: 43 * - Either we have modules 44 * - Or we have not pinned the first 8M 45 */ 46#if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \ 47 defined(CONFIG_DEBUG_PAGEALLOC) 48#define ITLB_MISS_KERNEL 1 49#endif 50 51/* 52 * Value for the bits that have fixed value in RPN entries. 53 * Also used for tagging DAR for DTLBerror. 54 */ 55#define RPN_PATTERN 0x00f0 56 57#define PAGE_SHIFT_512K 19 58#define PAGE_SHIFT_8M 23 59 60 __HEAD 61_ENTRY(_stext); 62_ENTRY(_start); 63 64/* MPC8xx 65 * This port was done on an MBX board with an 860. Right now I only 66 * support an ELF compressed (zImage) boot from EPPC-Bug because the 67 * code there loads up some registers before calling us: 68 * r3: ptr to board info data 69 * r4: initrd_start or if no initrd then 0 70 * r5: initrd_end - unused if r4 is 0 71 * r6: Start of command line string 72 * r7: End of command line string 73 * 74 * I decided to use conditional compilation instead of checking PVR and 75 * adding more processor specific branches around code I don't need. 76 * Since this is an embedded processor, I also appreciate any memory 77 * savings I can get. 78 * 79 * The MPC8xx does not have any BATs, but it supports large page sizes. 80 * We first initialize the MMU to support 8M byte pages, then load one 81 * entry into each of the instruction and data TLBs to map the first 82 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 83 * the "internal" processor registers before MMU_init is called. 84 * 85 * -- Dan 86 */ 87 .globl __start 88__start: 89 mr r31,r3 /* save device tree ptr */ 90 91 /* We have to turn on the MMU right away so we get cache modes 92 * set correctly. 93 */ 94 bl initial_mmu 95 96/* We now have the lower 8 Meg mapped into TLB entries, and the caches 97 * ready to work. 98 */ 99 100turn_on_mmu: 101 mfmsr r0 102 ori r0,r0,MSR_DR|MSR_IR 103 mtspr SPRN_SRR1,r0 104 lis r0,start_here@h 105 ori r0,r0,start_here@l 106 mtspr SPRN_SRR0,r0 107 rfi /* enables MMU */ 108 109/* 110 * Exception entry code. This code runs with address translation 111 * turned off, i.e. using physical addresses. 112 * We assume sprg3 has the physical address of the current 113 * task's thread_struct. 114 */ 115#define EXCEPTION_PROLOG \ 116 mtspr SPRN_SPRG_SCRATCH0, r10; \ 117 mtspr SPRN_SPRG_SCRATCH1, r11; \ 118 mfcr r10; \ 119 EXCEPTION_PROLOG_1; \ 120 EXCEPTION_PROLOG_2 121 122#define EXCEPTION_PROLOG_1 \ 123 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 124 andi. r11,r11,MSR_PR; \ 125 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 126 beq 1f; \ 127 mfspr r11,SPRN_SPRG_THREAD; \ 128 lwz r11,THREAD_INFO-THREAD(r11); \ 129 addi r11,r11,THREAD_SIZE; \ 130 tophys(r11,r11); \ 1311: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 132 133 134#define EXCEPTION_PROLOG_2 \ 135 stw r10,_CCR(r11); /* save registers */ \ 136 stw r12,GPR12(r11); \ 137 stw r9,GPR9(r11); \ 138 mfspr r10,SPRN_SPRG_SCRATCH0; \ 139 stw r10,GPR10(r11); \ 140 mfspr r12,SPRN_SPRG_SCRATCH1; \ 141 stw r12,GPR11(r11); \ 142 mflr r10; \ 143 stw r10,_LINK(r11); \ 144 mfspr r12,SPRN_SRR0; \ 145 mfspr r9,SPRN_SRR1; \ 146 stw r1,GPR1(r11); \ 147 stw r1,0(r11); \ 148 tovirt(r1,r11); /* set new kernel sp */ \ 149 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 150 mtmsr r10; \ 151 stw r0,GPR0(r11); \ 152 SAVE_4GPRS(3, r11); \ 153 SAVE_2GPRS(7, r11) 154 155/* 156 * Note: code which follows this uses cr0.eq (set if from kernel), 157 * r11, r12 (SRR0), and r9 (SRR1). 158 * 159 * Note2: once we have set r1 we are in a position to take exceptions 160 * again, and we could thus set MSR:RI at that point. 161 */ 162 163/* 164 * Exception vectors. 165 */ 166#define EXCEPTION(n, label, hdlr, xfer) \ 167 . = n; \ 168label: \ 169 EXCEPTION_PROLOG; \ 170 addi r3,r1,STACK_FRAME_OVERHEAD; \ 171 xfer(n, hdlr) 172 173#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 174 li r10,trap; \ 175 stw r10,_TRAP(r11); \ 176 li r10,MSR_KERNEL; \ 177 copyee(r10, r9); \ 178 bl tfer; \ 179i##n: \ 180 .long hdlr; \ 181 .long ret 182 183#define COPY_EE(d, s) rlwimi d,s,0,16,16 184#define NOCOPY(d, s) 185 186#define EXC_XFER_STD(n, hdlr) \ 187 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 188 ret_from_except_full) 189 190#define EXC_XFER_LITE(n, hdlr) \ 191 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 192 ret_from_except) 193 194#define EXC_XFER_EE(n, hdlr) \ 195 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 196 ret_from_except_full) 197 198#define EXC_XFER_EE_LITE(n, hdlr) \ 199 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 200 ret_from_except) 201 202/* System reset */ 203 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD) 204 205/* Machine check */ 206 . = 0x200 207MachineCheck: 208 EXCEPTION_PROLOG 209 mfspr r4,SPRN_DAR 210 stw r4,_DAR(r11) 211 li r5,RPN_PATTERN 212 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 213 mfspr r5,SPRN_DSISR 214 stw r5,_DSISR(r11) 215 addi r3,r1,STACK_FRAME_OVERHEAD 216 EXC_XFER_STD(0x200, machine_check_exception) 217 218/* Data access exception. 219 * This is "never generated" by the MPC8xx. 220 */ 221 . = 0x300 222DataAccess: 223 224/* Instruction access exception. 225 * This is "never generated" by the MPC8xx. 226 */ 227 . = 0x400 228InstructionAccess: 229 230/* External interrupt */ 231 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 232 233/* Alignment exception */ 234 . = 0x600 235Alignment: 236 EXCEPTION_PROLOG 237 mfspr r4,SPRN_DAR 238 stw r4,_DAR(r11) 239 li r5,RPN_PATTERN 240 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 241 mfspr r5,SPRN_DSISR 242 stw r5,_DSISR(r11) 243 addi r3,r1,STACK_FRAME_OVERHEAD 244 EXC_XFER_EE(0x600, alignment_exception) 245 246/* Program check exception */ 247 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 248 249/* No FPU on MPC8xx. This exception is not supposed to happen. 250*/ 251 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 252 253/* Decrementer */ 254 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 255 256 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 257 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 258 259/* System call */ 260 . = 0xc00 261SystemCall: 262 EXCEPTION_PROLOG 263 EXC_XFER_EE_LITE(0xc00, DoSyscall) 264 265/* Single step - not used on 601 */ 266 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 267 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 268 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 269 270/* On the MPC8xx, this is a software emulation interrupt. It occurs 271 * for all unimplemented and illegal instructions. 272 */ 273 EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD) 274 275 . = 0x1100 276/* 277 * For the MPC8xx, this is a software tablewalk to load the instruction 278 * TLB. The task switch loads the M_TW register with the pointer to the first 279 * level table. 280 * If we discover there is no second level table (value is zero) or if there 281 * is an invalid pte, we load that into the TLB, which causes another fault 282 * into the TLB Error interrupt where we can handle such problems. 283 * We have to use the MD_xxx registers for the tablewalk because the 284 * equivalent MI_xxx registers only perform the attribute functions. 285 */ 286 287#ifdef CONFIG_8xx_CPU15 288#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ 289 addi tmp, addr, PAGE_SIZE; \ 290 tlbie tmp; \ 291 addi tmp, addr, -PAGE_SIZE; \ 292 tlbie tmp 293#else 294#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) 295#endif 296 297InstructionTLBMiss: 298 mtspr SPRN_SPRG_SCRATCH0, r10 299 mtspr SPRN_SPRG_SCRATCH1, r11 300#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 301 mtspr SPRN_SPRG_SCRATCH2, r12 302#endif 303 304 /* If we are faulting a kernel address, we have to use the 305 * kernel page tables. 306 */ 307 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 308 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) 309 /* Only modules will cause ITLB Misses as we always 310 * pin the first 8MB of kernel memory */ 311#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 312 mfcr r12 313#endif 314#ifdef ITLB_MISS_KERNEL 315#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT) 316 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ 317#else 318 rlwinm r11, r10, 16, 0xfff8 319 cmpli cr0, r11, PAGE_OFFSET@h 320#ifndef CONFIG_PIN_TLB_TEXT 321 /* It is assumed that kernel code fits into the first 8M page */ 3220: cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h 323 patch_site 0b, patch__itlbmiss_linmem_top 324#endif 325#endif 326#endif 327 mfspr r11, SPRN_M_TW /* Get level 1 table */ 328#ifdef ITLB_MISS_KERNEL 329#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT) 330 beq+ 3f 331#else 332 blt+ 3f 333#endif 334#ifndef CONFIG_PIN_TLB_TEXT 335 blt cr7, ITLBMissLinear 336#endif 337 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3383: 339#endif 340 /* Insert level 1 index */ 341 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 342 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 343 344 /* Extract level 2 index */ 345 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 346#ifdef CONFIG_HUGETLB_PAGE 347 mtcr r11 348 bt- 28, 10f /* bit 28 = Large page (8M) */ 349 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */ 350#endif 351 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 352 lwz r10, 0(r10) /* Get the pte */ 3534: 354#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 355 mtcr r12 356#endif 357 /* Load the MI_TWC with the attributes for this "segment." */ 358 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ 359 360#ifdef CONFIG_SWAP 361 rlwinm r11, r10, 32-5, _PAGE_PRESENT 362 and r11, r11, r10 363 rlwimi r10, r11, 0, _PAGE_PRESENT 364#endif 365 li r11, RPN_PATTERN | 0x200 366 /* The Linux PTE won't go exactly into the MMU TLB. 367 * Software indicator bits 20 and 23 must be clear. 368 * Software indicator bits 22, 24, 25, 26, and 27 must be 369 * set. All other Linux PTE bits control the behavior 370 * of the MMU. 371 */ 372 rlwimi r11, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ 373 rlwimi r10, r11, 0, 0x0ff0 /* Set 22, 24-27, clear 20,23 */ 374 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 375 376 /* Restore registers */ 3770: mfspr r10, SPRN_SPRG_SCRATCH0 378 mfspr r11, SPRN_SPRG_SCRATCH1 379#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 380 mfspr r12, SPRN_SPRG_SCRATCH2 381#endif 382 rfi 383 patch_site 0b, patch__itlbmiss_exit_1 384 385#ifdef CONFIG_PERF_EVENTS 386 patch_site 0f, patch__itlbmiss_perf 3870: lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha 388 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) 389 addi r11, r11, 1 390 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) 391#endif 392 mfspr r10, SPRN_SPRG_SCRATCH0 393 mfspr r11, SPRN_SPRG_SCRATCH1 394#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 395 mfspr r12, SPRN_SPRG_SCRATCH2 396#endif 397 rfi 398 399#ifdef CONFIG_HUGETLB_PAGE 40010: /* 8M pages */ 401#ifdef CONFIG_PPC_16K_PAGES 402 /* Extract level 2 index */ 403 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 404 /* Add level 2 base */ 405 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 406#else 407 /* Level 2 base */ 408 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK 409#endif 410 lwz r10, 0(r10) /* Get the pte */ 411 b 4b 412 41320: /* 512k pages */ 414 /* Extract level 2 index */ 415 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 416 /* Add level 2 base */ 417 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 418 lwz r10, 0(r10) /* Get the pte */ 419 b 4b 420#endif 421 422 . = 0x1200 423DataStoreTLBMiss: 424 mtspr SPRN_SPRG_SCRATCH0, r10 425 mtspr SPRN_SPRG_SCRATCH1, r11 426 mtspr SPRN_SPRG_SCRATCH2, r12 427 mfcr r12 428 429 /* If we are faulting a kernel address, we have to use the 430 * kernel page tables. 431 */ 432 mfspr r10, SPRN_MD_EPN 433 rlwinm r11, r10, 16, 0xfff8 434 cmpli cr0, r11, PAGE_OFFSET@h 435 mfspr r11, SPRN_M_TW /* Get level 1 table */ 436 blt+ 3f 437 rlwinm r11, r10, 16, 0xfff8 438#ifndef CONFIG_PIN_TLB_IMMR 439 cmpli cr0, r11, VIRT_IMMR_BASE@h 440#endif 4410: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 442 patch_site 0b, patch__dtlbmiss_linmem_top 443#ifndef CONFIG_PIN_TLB_IMMR 4440: beq- DTLBMissIMMR 445 patch_site 0b, patch__dtlbmiss_immr_jmp 446#endif 447 blt cr7, DTLBMissLinear 448 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 4493: 450 451 /* Insert level 1 index */ 452 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 453 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 454 455 /* We have a pte table, so load fetch the pte from the table. 456 */ 457 /* Extract level 2 index */ 458 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 459#ifdef CONFIG_HUGETLB_PAGE 460 mtcr r11 461 bt- 28, 10f /* bit 28 = Large page (8M) */ 462 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */ 463#endif 464 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 465 lwz r10, 0(r10) /* Get the pte */ 4664: 467 mtcr r12 468 469 /* Insert the Guarded flag into the TWC from the Linux PTE. 470 * It is bit 27 of both the Linux PTE and the TWC (at least 471 * I got that right :-). It will be better when we can put 472 * this into the Linux pgd/pmd and load it in the operation 473 * above. 474 */ 475 rlwimi r11, r10, 0, _PAGE_GUARDED 476 mtspr SPRN_MD_TWC, r11 477 478 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 479 * We also need to know if the insn is a load/store, so: 480 * Clear _PAGE_PRESENT and load that which will 481 * trap into DTLB Error with store bit set accordinly. 482 */ 483 /* PRESENT=0x1, ACCESSED=0x20 484 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 485 * r10 = (r10 & ~PRESENT) | r11; 486 */ 487#ifdef CONFIG_SWAP 488 rlwinm r11, r10, 32-5, _PAGE_PRESENT 489 and r11, r11, r10 490 rlwimi r10, r11, 0, _PAGE_PRESENT 491#endif 492 /* The Linux PTE won't go exactly into the MMU TLB. 493 * Software indicator bits 24, 25, 26, and 27 must be 494 * set. All other Linux PTE bits control the behavior 495 * of the MMU. 496 */ 497 li r11, RPN_PATTERN 498 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */ 499 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 500 501 /* Restore registers */ 502 mtspr SPRN_DAR, r11 /* Tag DAR */ 503 5040: mfspr r10, SPRN_SPRG_SCRATCH0 505 mfspr r11, SPRN_SPRG_SCRATCH1 506 mfspr r12, SPRN_SPRG_SCRATCH2 507 rfi 508 patch_site 0b, patch__dtlbmiss_exit_1 509 510#ifdef CONFIG_PERF_EVENTS 511 patch_site 0f, patch__dtlbmiss_perf 5120: lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha 513 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) 514 addi r11, r11, 1 515 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) 516#endif 517 mfspr r10, SPRN_SPRG_SCRATCH0 518 mfspr r11, SPRN_SPRG_SCRATCH1 519 mfspr r12, SPRN_SPRG_SCRATCH2 520 rfi 521 522#ifdef CONFIG_HUGETLB_PAGE 52310: /* 8M pages */ 524 /* Extract level 2 index */ 525#ifdef CONFIG_PPC_16K_PAGES 526 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 527 /* Add level 2 base */ 528 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 529#else 530 /* Level 2 base */ 531 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK 532#endif 533 lwz r10, 0(r10) /* Get the pte */ 534 b 4b 535 53620: /* 512k pages */ 537 /* Extract level 2 index */ 538 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 539 /* Add level 2 base */ 540 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 541 lwz r10, 0(r10) /* Get the pte */ 542 b 4b 543#endif 544 545/* This is an instruction TLB error on the MPC8xx. This could be due 546 * to many reasons, such as executing guarded memory or illegal instruction 547 * addresses. There is nothing to do but handle a big time error fault. 548 */ 549 . = 0x1300 550InstructionTLBError: 551 EXCEPTION_PROLOG 552 mr r4,r12 553 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ 554 andis. r10,r9,SRR1_ISI_NOPT@h 555 beq+ 1f 556 tlbie r4 557itlbie: 558 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 5591: EXC_XFER_LITE(0x400, handle_page_fault) 560 561/* This is the data TLB error on the MPC8xx. This could be due to 562 * many reasons, including a dirty update to a pte. We bail out to 563 * a higher level function that can handle it. 564 */ 565 . = 0x1400 566DataTLBError: 567 mtspr SPRN_SPRG_SCRATCH0, r10 568 mtspr SPRN_SPRG_SCRATCH1, r11 569 mfcr r10 570 571 mfspr r11, SPRN_DAR 572 cmpwi cr0, r11, RPN_PATTERN 573 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 574DARFixed:/* Return from dcbx instruction bug workaround */ 575 EXCEPTION_PROLOG_1 576 EXCEPTION_PROLOG_2 577 mfspr r5,SPRN_DSISR 578 stw r5,_DSISR(r11) 579 mfspr r4,SPRN_DAR 580 andis. r10,r5,DSISR_NOHPTE@h 581 beq+ 1f 582 tlbie r4 583dtlbie: 5841: li r10,RPN_PATTERN 585 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 586 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 587 EXC_XFER_LITE(0x300, handle_page_fault) 588 589 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 590 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 591 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 592 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 593 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 594 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 595 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 596 597/* On the MPC8xx, these next four traps are used for development 598 * support of breakpoints and such. Someday I will get around to 599 * using them. 600 */ 601 . = 0x1c00 602DataBreakpoint: 603 mtspr SPRN_SPRG_SCRATCH0, r10 604 mtspr SPRN_SPRG_SCRATCH1, r11 605 mfcr r10 606 mfspr r11, SPRN_SRR0 607 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l 608 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l 609 beq- cr0, 11f 610 beq- cr7, 11f 611 EXCEPTION_PROLOG_1 612 EXCEPTION_PROLOG_2 613 addi r3,r1,STACK_FRAME_OVERHEAD 614 mfspr r4,SPRN_BAR 615 stw r4,_DAR(r11) 616 mfspr r5,SPRN_DSISR 617 EXC_XFER_EE(0x1c00, do_break) 61811: 619 mtcr r10 620 mfspr r10, SPRN_SPRG_SCRATCH0 621 mfspr r11, SPRN_SPRG_SCRATCH1 622 rfi 623 624#ifdef CONFIG_PERF_EVENTS 625 . = 0x1d00 626InstructionBreakpoint: 627 mtspr SPRN_SPRG_SCRATCH0, r10 628 mtspr SPRN_SPRG_SCRATCH1, r11 629 lis r10, (instruction_counter - PAGE_OFFSET)@ha 630 lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10) 631 addi r11, r11, -1 632 stw r11, (instruction_counter - PAGE_OFFSET)@l(r10) 633 lis r10, 0xffff 634 ori r10, r10, 0x01 635 mtspr SPRN_COUNTA, r10 636 mfspr r10, SPRN_SPRG_SCRATCH0 637 mfspr r11, SPRN_SPRG_SCRATCH1 638 rfi 639#else 640 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 641#endif 642 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 643 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 644 645 . = 0x2000 646 647/* 648 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM. 649 * not enough space in the DataStoreTLBMiss area. 650 */ 651DTLBMissIMMR: 652 mtcr r12 653 /* Set 512k byte guarded page and mark it valid */ 654 li r10, MD_PS512K | MD_GUARDED | MD_SVALID 655 mtspr SPRN_MD_TWC, r10 656 mfspr r10, SPRN_IMMR /* Get current IMMR */ 657 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ 658 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ 659 _PAGE_PRESENT | _PAGE_NO_CACHE 660 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 661 662 li r11, RPN_PATTERN 663 mtspr SPRN_DAR, r11 /* Tag DAR */ 664 6650: mfspr r10, SPRN_SPRG_SCRATCH0 666 mfspr r11, SPRN_SPRG_SCRATCH1 667 mfspr r12, SPRN_SPRG_SCRATCH2 668 rfi 669 patch_site 0b, patch__dtlbmiss_exit_2 670 671DTLBMissLinear: 672 mtcr r12 673 /* Set 8M byte page and mark it valid */ 674 li r11, MD_PS8MEG | MD_SVALID 675 mtspr SPRN_MD_TWC, r11 676 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 677 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ 678 _PAGE_PRESENT 679 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 680 681 li r11, RPN_PATTERN 682 mtspr SPRN_DAR, r11 /* Tag DAR */ 683 6840: mfspr r10, SPRN_SPRG_SCRATCH0 685 mfspr r11, SPRN_SPRG_SCRATCH1 686 mfspr r12, SPRN_SPRG_SCRATCH2 687 rfi 688 patch_site 0b, patch__dtlbmiss_exit_3 689 690#ifndef CONFIG_PIN_TLB_TEXT 691ITLBMissLinear: 692 mtcr r12 693 /* Set 8M byte page and mark it valid */ 694 li r11, MI_PS8MEG | MI_SVALID 695 mtspr SPRN_MI_TWC, r11 696 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 697 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ 698 _PAGE_PRESENT 699 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 700 7010: mfspr r10, SPRN_SPRG_SCRATCH0 702 mfspr r11, SPRN_SPRG_SCRATCH1 703 mfspr r12, SPRN_SPRG_SCRATCH2 704 rfi 705 patch_site 0b, patch__itlbmiss_exit_2 706#endif 707 708/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 709 * by decoding the registers used by the dcbx instruction and adding them. 710 * DAR is set to the calculated address. 711 */ 712 /* define if you don't want to use self modifying code */ 713#define NO_SELF_MODIFYING_CODE 714FixupDAR:/* Entry point for dcbx workaround. */ 715 mtspr SPRN_SPRG_SCRATCH2, r10 716 /* fetch instruction from memory. */ 717 mfspr r10, SPRN_SRR0 718 rlwinm r11, r10, 16, 0xfff8 719 cmpli cr0, r11, PAGE_OFFSET@h 720 mfspr r11, SPRN_M_TW /* Get level 1 table */ 721 blt+ 3f 722 rlwinm r11, r10, 16, 0xfff8 723 7240: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 725 patch_site 0b, patch__fixupdar_linmem_top 726 727 /* create physical page address from effective address */ 728 tophys(r11, r10) 729 blt- cr7, 201f 730 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 731 /* Insert level 1 index */ 7323: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 733 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 734 mtcr r11 735 bt 28,200f /* bit 28 = Large page (8M) */ 736 bt 29,202f /* bit 29 = Large page (8M or 512K) */ 737 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ 738 /* Insert level 2 index */ 739 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 740 lwz r11, 0(r11) /* Get the pte */ 741 /* concat physical page address(r11) and page offset(r10) */ 742 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 743201: lwz r11,0(r11) 744/* Check if it really is a dcbx instruction. */ 745/* dcbt and dcbtst does not generate DTLB Misses/Errors, 746 * no need to include them here */ 747 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 748 rlwinm r10, r10, 0, 21, 5 749 cmpwi cr0, r10, 2028 /* Is dcbz? */ 750 beq+ 142f 751 cmpwi cr0, r10, 940 /* Is dcbi? */ 752 beq+ 142f 753 cmpwi cr0, r10, 108 /* Is dcbst? */ 754 beq+ 144f /* Fix up store bit! */ 755 cmpwi cr0, r10, 172 /* Is dcbf? */ 756 beq+ 142f 757 cmpwi cr0, r10, 1964 /* Is icbi? */ 758 beq+ 142f 759141: mfspr r10,SPRN_SPRG_SCRATCH2 760 b DARFixed /* Nope, go back to normal TLB processing */ 761 762 /* concat physical page address(r11) and page offset(r10) */ 763200: 764#ifdef CONFIG_PPC_16K_PAGES 765 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 766 rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 767#else 768 rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK 769#endif 770 lwz r11, 0(r11) /* Get the pte */ 771 /* concat physical page address(r11) and page offset(r10) */ 772 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31 773 b 201b 774 775202: 776 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 777 rlwimi r11, r10, 32 - (PAGE_SHIFT_512K - 2), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 778 lwz r11, 0(r11) /* Get the pte */ 779 /* concat physical page address(r11) and page offset(r10) */ 780 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31 781 b 201b 782 783144: mfspr r10, SPRN_DSISR 784 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 785 mtspr SPRN_DSISR, r10 786142: /* continue, it was a dcbx, dcbi instruction. */ 787#ifndef NO_SELF_MODIFYING_CODE 788 andis. r10,r11,0x1f /* test if reg RA is r0 */ 789 li r10,modified_instr@l 790 dcbtst r0,r10 /* touch for store */ 791 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 792 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 793 ori r11,r11,532 794 stw r11,0(r10) /* store add/and instruction */ 795 dcbf 0,r10 /* flush new instr. to memory. */ 796 icbi 0,r10 /* invalidate instr. cache line */ 797 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ 798 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ 799 isync /* Wait until new instr is loaded from memory */ 800modified_instr: 801 .space 4 /* this is where the add instr. is stored */ 802 bne+ 143f 803 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 804143: mtdar r10 /* store faulting EA in DAR */ 805 mfspr r10,SPRN_SPRG_SCRATCH2 806 b DARFixed /* Go back to normal TLB handling */ 807#else 808 mfctr r10 809 mtdar r10 /* save ctr reg in DAR */ 810 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 811 addi r10, r10, 150f@l /* add start of table */ 812 mtctr r10 /* load ctr with jump address */ 813 xor r10, r10, r10 /* sum starts at zero */ 814 bctr /* jump into table */ 815150: 816 add r10, r10, r0 ;b 151f 817 add r10, r10, r1 ;b 151f 818 add r10, r10, r2 ;b 151f 819 add r10, r10, r3 ;b 151f 820 add r10, r10, r4 ;b 151f 821 add r10, r10, r5 ;b 151f 822 add r10, r10, r6 ;b 151f 823 add r10, r10, r7 ;b 151f 824 add r10, r10, r8 ;b 151f 825 add r10, r10, r9 ;b 151f 826 mtctr r11 ;b 154f /* r10 needs special handling */ 827 mtctr r11 ;b 153f /* r11 needs special handling */ 828 add r10, r10, r12 ;b 151f 829 add r10, r10, r13 ;b 151f 830 add r10, r10, r14 ;b 151f 831 add r10, r10, r15 ;b 151f 832 add r10, r10, r16 ;b 151f 833 add r10, r10, r17 ;b 151f 834 add r10, r10, r18 ;b 151f 835 add r10, r10, r19 ;b 151f 836 add r10, r10, r20 ;b 151f 837 add r10, r10, r21 ;b 151f 838 add r10, r10, r22 ;b 151f 839 add r10, r10, r23 ;b 151f 840 add r10, r10, r24 ;b 151f 841 add r10, r10, r25 ;b 151f 842 add r10, r10, r26 ;b 151f 843 add r10, r10, r27 ;b 151f 844 add r10, r10, r28 ;b 151f 845 add r10, r10, r29 ;b 151f 846 add r10, r10, r30 ;b 151f 847 add r10, r10, r31 848151: 849 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 850 beq 152f /* if reg RA is zero, don't add it */ 851 addi r11, r11, 150b@l /* add start of table */ 852 mtctr r11 /* load ctr with jump address */ 853 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 854 bctr /* jump into table */ 855152: 856 mfdar r11 857 mtctr r11 /* restore ctr reg from DAR */ 858 mtdar r10 /* save fault EA to DAR */ 859 mfspr r10,SPRN_SPRG_SCRATCH2 860 b DARFixed /* Go back to normal TLB handling */ 861 862 /* special handling for r10,r11 since these are modified already */ 863153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 864 add r10, r10, r11 /* add it */ 865 mfctr r11 /* restore r11 */ 866 b 151b 867154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 868 add r10, r10, r11 /* add it */ 869 mfctr r11 /* restore r11 */ 870 b 151b 871#endif 872 873/* 874 * This is where the main kernel code starts. 875 */ 876start_here: 877 /* ptr to current */ 878 lis r2,init_task@h 879 ori r2,r2,init_task@l 880 881 /* ptr to phys current thread */ 882 tophys(r4,r2) 883 addi r4,r4,THREAD /* init task's THREAD */ 884 mtspr SPRN_SPRG_THREAD,r4 885 886 /* stack */ 887 lis r1,init_thread_union@ha 888 addi r1,r1,init_thread_union@l 889 li r0,0 890 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 891 892 lis r6, swapper_pg_dir@ha 893 tophys(r6,r6) 894 mtspr SPRN_M_TW, r6 895 896 bl early_init /* We have to do this with MMU on */ 897 898/* 899 * Decide what sort of machine this is and initialize the MMU. 900 */ 901 li r3,0 902 mr r4,r31 903 bl machine_init 904 bl MMU_init 905 906/* 907 * Go back to running unmapped so we can load up new values 908 * and change to using our exception vectors. 909 * On the 8xx, all we have to do is invalidate the TLB to clear 910 * the old 8M byte TLB mappings and load the page table base register. 911 */ 912 /* The right way to do this would be to track it down through 913 * init's THREAD like the context switch code does, but this is 914 * easier......until someone changes init's static structures. 915 */ 916 lis r4,2f@h 917 ori r4,r4,2f@l 918 tophys(r4,r4) 919 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 920 mtspr SPRN_SRR0,r4 921 mtspr SPRN_SRR1,r3 922 rfi 923/* Load up the kernel context */ 9242: 925 tlbia /* Clear all TLB entries */ 926 sync /* wait for tlbia/tlbie to finish */ 927 928 /* set up the PTE pointers for the Abatron bdiGDB. 929 */ 930 tovirt(r6,r6) 931 lis r5, abatron_pteptrs@h 932 ori r5, r5, abatron_pteptrs@l 933 stw r5, 0xf0(0) /* Must match your Abatron config file */ 934 tophys(r5,r5) 935 stw r6, 0(r5) 936 937/* Now turn on the MMU for real! */ 938 li r4,MSR_KERNEL 939 lis r3,start_kernel@h 940 ori r3,r3,start_kernel@l 941 mtspr SPRN_SRR0,r3 942 mtspr SPRN_SRR1,r4 943 rfi /* enable MMU and jump to start_kernel */ 944 945/* Set up the initial MMU state so we can do the first level of 946 * kernel initialization. This maps the first 8 MBytes of memory 1:1 947 * virtual to physical. Also, set the cache mode since that is defined 948 * by TLB entries and perform any additional mapping (like of the IMMR). 949 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 950 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 951 * these mappings is mapped by page tables. 952 */ 953initial_mmu: 954 li r8, 0 955 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 956 lis r10, MD_RESETVAL@h 957#ifndef CONFIG_8xx_COPYBACK 958 oris r10, r10, MD_WTDEF@h 959#endif 960 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 961 962 tlbia /* Invalidate all TLB entries */ 963#ifdef CONFIG_PIN_TLB_TEXT 964 lis r8, MI_RSV4I@h 965 ori r8, r8, 0x1c00 966 967 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 968#endif 969 970#ifdef CONFIG_PIN_TLB_DATA 971 oris r10, r10, MD_RSV4I@h 972 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 973#endif 974 975 /* Now map the lower 8 Meg into the ITLB. */ 976 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 977 ori r8, r8, MI_EVALID /* Mark it valid */ 978 mtspr SPRN_MI_EPN, r8 979 li r8, MI_PS8MEG /* Set 8M byte page */ 980 ori r8, r8, MI_SVALID /* Make it valid */ 981 mtspr SPRN_MI_TWC, r8 982 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 983 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 984 985 lis r8, MI_APG_INIT@h /* Set protection modes */ 986 ori r8, r8, MI_APG_INIT@l 987 mtspr SPRN_MI_AP, r8 988 lis r8, MD_APG_INIT@h 989 ori r8, r8, MD_APG_INIT@l 990 mtspr SPRN_MD_AP, r8 991 992 /* Map a 512k page for the IMMR to get the processor 993 * internal registers (among other things). 994 */ 995#ifdef CONFIG_PIN_TLB_IMMR 996 oris r10, r10, MD_RSV4I@h 997 ori r10, r10, 0x1c00 998 mtspr SPRN_MD_CTR, r10 999 1000 mfspr r9, 638 /* Get current IMMR */ 1001 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */ 1002 1003 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */ 1004 ori r8, r8, MD_EVALID /* Mark it valid */ 1005 mtspr SPRN_MD_EPN, r8 1006 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */ 1007 ori r8, r8, MD_SVALID /* Make it valid */ 1008 mtspr SPRN_MD_TWC, r8 1009 mr r8, r9 /* Create paddr for TLB */ 1010 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 1011 mtspr SPRN_MD_RPN, r8 1012#endif 1013 1014 /* Since the cache is enabled according to the information we 1015 * just loaded into the TLB, invalidate and enable the caches here. 1016 * We should probably check/set other modes....later. 1017 */ 1018 lis r8, IDC_INVALL@h 1019 mtspr SPRN_IC_CST, r8 1020 mtspr SPRN_DC_CST, r8 1021 lis r8, IDC_ENABLE@h 1022 mtspr SPRN_IC_CST, r8 1023#ifdef CONFIG_8xx_COPYBACK 1024 mtspr SPRN_DC_CST, r8 1025#else 1026 /* For a debug option, I left this here to easily enable 1027 * the write through cache mode 1028 */ 1029 lis r8, DC_SFWT@h 1030 mtspr SPRN_DC_CST, r8 1031 lis r8, IDC_ENABLE@h 1032 mtspr SPRN_DC_CST, r8 1033#endif 1034 /* Disable debug mode entry on breakpoints */ 1035 mfspr r8, SPRN_DER 1036#ifdef CONFIG_PERF_EVENTS 1037 rlwinm r8, r8, 0, ~0xc 1038#else 1039 rlwinm r8, r8, 0, ~0x8 1040#endif 1041 mtspr SPRN_DER, r8 1042 blr 1043 1044 1045/* 1046 * We put a few things here that have to be page-aligned. 1047 * This stuff goes at the beginning of the data segment, 1048 * which is page-aligned. 1049 */ 1050 .data 1051 .globl sdata 1052sdata: 1053 .globl empty_zero_page 1054 .align PAGE_SHIFT 1055empty_zero_page: 1056 .space PAGE_SIZE 1057EXPORT_SYMBOL(empty_zero_page) 1058 1059 .globl swapper_pg_dir 1060swapper_pg_dir: 1061 .space PGD_TABLE_SIZE 1062 1063/* Room for two PTE table poiners, usually the kernel and current user 1064 * pointer to their respective root page table (pgdir). 1065 */ 1066abatron_pteptrs: 1067 .space 8 1068 1069#ifdef CONFIG_PERF_EVENTS 1070 .globl itlb_miss_counter 1071itlb_miss_counter: 1072 .space 4 1073 1074 .globl dtlb_miss_counter 1075dtlb_miss_counter: 1076 .space 4 1077 1078 .globl instruction_counter 1079instruction_counter: 1080 .space 4 1081#endif 1082