xref: /openbmc/linux/arch/powerpc/kernel/head_8xx.S (revision 3c6a73cc) 
1/*
2 *  PowerPC version
3 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 *  Low-level exception handlers and MMU support
7 *  rewritten by Paul Mackerras.
8 *    Copyright (C) 1996 Paul Mackerras.
9 *  MPC8xx modifications by Dan Malek
10 *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 *  This file contains low-level support and setup for PowerPC 8xx
13 *  embedded processors, including trap and interrupt dispatch.
14 *
15 *  This program is free software; you can redistribute it and/or
16 *  modify it under the terms of the GNU General Public License
17 *  as published by the Free Software Foundation; either version
18 *  2 of the License, or (at your option) any later version.
19 *
20 */
21
22#include <linux/init.h>
23#include <asm/processor.h>
24#include <asm/page.h>
25#include <asm/mmu.h>
26#include <asm/cache.h>
27#include <asm/pgtable.h>
28#include <asm/cputable.h>
29#include <asm/thread_info.h>
30#include <asm/ppc_asm.h>
31#include <asm/asm-offsets.h>
32#include <asm/ptrace.h>
33
34/* Macro to make the code more readable. */
35#ifdef CONFIG_8xx_CPU6
36#define DO_8xx_CPU6(val, reg)	\
37	li	reg, val;	\
38	stw	reg, 12(r0);	\
39	lwz	reg, 12(r0);
40#else
41#define DO_8xx_CPU6(val, reg)
42#endif
43	__HEAD
44_ENTRY(_stext);
45_ENTRY(_start);
46
47/* MPC8xx
48 * This port was done on an MBX board with an 860.  Right now I only
49 * support an ELF compressed (zImage) boot from EPPC-Bug because the
50 * code there loads up some registers before calling us:
51 *   r3: ptr to board info data
52 *   r4: initrd_start or if no initrd then 0
53 *   r5: initrd_end - unused if r4 is 0
54 *   r6: Start of command line string
55 *   r7: End of command line string
56 *
57 * I decided to use conditional compilation instead of checking PVR and
58 * adding more processor specific branches around code I don't need.
59 * Since this is an embedded processor, I also appreciate any memory
60 * savings I can get.
61 *
62 * The MPC8xx does not have any BATs, but it supports large page sizes.
63 * We first initialize the MMU to support 8M byte pages, then load one
64 * entry into each of the instruction and data TLBs to map the first
65 * 8M 1:1.  I also mapped an additional I/O space 1:1 so we can get to
66 * the "internal" processor registers before MMU_init is called.
67 *
68 * The TLB code currently contains a major hack.  Since I use the condition
69 * code register, I have to save and restore it.  I am out of registers, so
70 * I just store it in memory location 0 (the TLB handlers are not reentrant).
71 * To avoid making any decisions, I need to use the "segment" valid bit
72 * in the first level table, but that would require many changes to the
73 * Linux page directory/table functions that I don't want to do right now.
74 *
75 *	-- Dan
76 */
77	.globl	__start
78__start:
79	mr	r31,r3			/* save device tree ptr */
80
81	/* We have to turn on the MMU right away so we get cache modes
82	 * set correctly.
83	 */
84	bl	initial_mmu
85
86/* We now have the lower 8 Meg mapped into TLB entries, and the caches
87 * ready to work.
88 */
89
90turn_on_mmu:
91	mfmsr	r0
92	ori	r0,r0,MSR_DR|MSR_IR
93	mtspr	SPRN_SRR1,r0
94	lis	r0,start_here@h
95	ori	r0,r0,start_here@l
96	mtspr	SPRN_SRR0,r0
97	SYNC
98	rfi				/* enables MMU */
99
100/*
101 * Exception entry code.  This code runs with address translation
102 * turned off, i.e. using physical addresses.
103 * We assume sprg3 has the physical address of the current
104 * task's thread_struct.
105 */
106#define EXCEPTION_PROLOG	\
107	EXCEPTION_PROLOG_0;	\
108	EXCEPTION_PROLOG_1;	\
109	EXCEPTION_PROLOG_2
110
111#define EXCEPTION_PROLOG_0	\
112	mtspr	SPRN_SPRG_SCRATCH0,r10;	\
113	mtspr	SPRN_SPRG_SCRATCH1,r11;	\
114	mfcr	r10
115
116#define EXCEPTION_PROLOG_1	\
117	mfspr	r11,SPRN_SRR1;		/* check whether user or kernel */ \
118	andi.	r11,r11,MSR_PR;	\
119	tophys(r11,r1);			/* use tophys(r1) if kernel */ \
120	beq	1f;		\
121	mfspr	r11,SPRN_SPRG_THREAD;	\
122	lwz	r11,THREAD_INFO-THREAD(r11);	\
123	addi	r11,r11,THREAD_SIZE;	\
124	tophys(r11,r11);	\
1251:	subi	r11,r11,INT_FRAME_SIZE	/* alloc exc. frame */
126
127
128#define EXCEPTION_PROLOG_2	\
129	CLR_TOP32(r11);		\
130	stw	r10,_CCR(r11);		/* save registers */ \
131	stw	r12,GPR12(r11);	\
132	stw	r9,GPR9(r11);	\
133	mfspr	r10,SPRN_SPRG_SCRATCH0;	\
134	stw	r10,GPR10(r11);	\
135	mfspr	r12,SPRN_SPRG_SCRATCH1;	\
136	stw	r12,GPR11(r11);	\
137	mflr	r10;		\
138	stw	r10,_LINK(r11);	\
139	mfspr	r12,SPRN_SRR0;	\
140	mfspr	r9,SPRN_SRR1;	\
141	stw	r1,GPR1(r11);	\
142	stw	r1,0(r11);	\
143	tovirt(r1,r11);			/* set new kernel sp */	\
144	li	r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
145	MTMSRD(r10);			/* (except for mach check in rtas) */ \
146	stw	r0,GPR0(r11);	\
147	SAVE_4GPRS(3, r11);	\
148	SAVE_2GPRS(7, r11)
149
150/*
151 * Exception exit code.
152 */
153#define EXCEPTION_EPILOG_0	\
154	mtcr	r10;		\
155	mfspr	r10,SPRN_SPRG_SCRATCH0;	\
156	mfspr	r11,SPRN_SPRG_SCRATCH1
157
158/*
159 * Note: code which follows this uses cr0.eq (set if from kernel),
160 * r11, r12 (SRR0), and r9 (SRR1).
161 *
162 * Note2: once we have set r1 we are in a position to take exceptions
163 * again, and we could thus set MSR:RI at that point.
164 */
165
166/*
167 * Exception vectors.
168 */
169#define EXCEPTION(n, label, hdlr, xfer)		\
170	. = n;					\
171label:						\
172	EXCEPTION_PROLOG;			\
173	addi	r3,r1,STACK_FRAME_OVERHEAD;	\
174	xfer(n, hdlr)
175
176#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret)	\
177	li	r10,trap;					\
178	stw	r10,_TRAP(r11);					\
179	li	r10,MSR_KERNEL;					\
180	copyee(r10, r9);					\
181	bl	tfer;						\
182i##n:								\
183	.long	hdlr;						\
184	.long	ret
185
186#define COPY_EE(d, s)		rlwimi d,s,0,16,16
187#define NOCOPY(d, s)
188
189#define EXC_XFER_STD(n, hdlr)		\
190	EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full,	\
191			  ret_from_except_full)
192
193#define EXC_XFER_LITE(n, hdlr)		\
194	EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
195			  ret_from_except)
196
197#define EXC_XFER_EE(n, hdlr)		\
198	EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
199			  ret_from_except_full)
200
201#define EXC_XFER_EE_LITE(n, hdlr)	\
202	EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
203			  ret_from_except)
204
205/* System reset */
206	EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
207
208/* Machine check */
209	. = 0x200
210MachineCheck:
211	EXCEPTION_PROLOG
212	mfspr r4,SPRN_DAR
213	stw r4,_DAR(r11)
214	li r5,0x00f0
215	mtspr SPRN_DAR,r5	/* Tag DAR, to be used in DTLB Error */
216	mfspr r5,SPRN_DSISR
217	stw r5,_DSISR(r11)
218	addi r3,r1,STACK_FRAME_OVERHEAD
219	EXC_XFER_STD(0x200, machine_check_exception)
220
221/* Data access exception.
222 * This is "never generated" by the MPC8xx.  We jump to it for other
223 * translation errors.
224 */
225	. = 0x300
226DataAccess:
227	EXCEPTION_PROLOG
228	mfspr	r10,SPRN_DSISR
229	stw	r10,_DSISR(r11)
230	mr	r5,r10
231	mfspr	r4,SPRN_DAR
232	li	r10,0x00f0
233	mtspr	SPRN_DAR,r10	/* Tag DAR, to be used in DTLB Error */
234	EXC_XFER_LITE(0x300, handle_page_fault)
235
236/* Instruction access exception.
237 * This is "never generated" by the MPC8xx.  We jump to it for other
238 * translation errors.
239 */
240	. = 0x400
241InstructionAccess:
242	EXCEPTION_PROLOG
243	mr	r4,r12
244	mr	r5,r9
245	EXC_XFER_LITE(0x400, handle_page_fault)
246
247/* External interrupt */
248	EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
249
250/* Alignment exception */
251	. = 0x600
252Alignment:
253	EXCEPTION_PROLOG
254	mfspr	r4,SPRN_DAR
255	stw	r4,_DAR(r11)
256	li	r5,0x00f0
257	mtspr	SPRN_DAR,r5	/* Tag DAR, to be used in DTLB Error */
258	mfspr	r5,SPRN_DSISR
259	stw	r5,_DSISR(r11)
260	addi	r3,r1,STACK_FRAME_OVERHEAD
261	EXC_XFER_EE(0x600, alignment_exception)
262
263/* Program check exception */
264	EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
265
266/* No FPU on MPC8xx.  This exception is not supposed to happen.
267*/
268	EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
269
270/* Decrementer */
271	EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
272
273	EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
274	EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
275
276/* System call */
277	. = 0xc00
278SystemCall:
279	EXCEPTION_PROLOG
280	EXC_XFER_EE_LITE(0xc00, DoSyscall)
281
282/* Single step - not used on 601 */
283	EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
284	EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
285	EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
286
287/* On the MPC8xx, this is a software emulation interrupt.  It occurs
288 * for all unimplemented and illegal instructions.
289 */
290	EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
291
292	. = 0x1100
293/*
294 * For the MPC8xx, this is a software tablewalk to load the instruction
295 * TLB.  It is modelled after the example in the Motorola manual.  The task
296 * switch loads the M_TWB register with the pointer to the first level table.
297 * If we discover there is no second level table (value is zero) or if there
298 * is an invalid pte, we load that into the TLB, which causes another fault
299 * into the TLB Error interrupt where we can handle such problems.
300 * We have to use the MD_xxx registers for the tablewalk because the
301 * equivalent MI_xxx registers only perform the attribute functions.
302 */
303InstructionTLBMiss:
304#ifdef CONFIG_8xx_CPU6
305	stw	r3, 8(r0)
306#endif
307	EXCEPTION_PROLOG_0
308	mtspr	SPRN_SPRG_SCRATCH2, r10
309	mfspr	r10, SPRN_SRR0	/* Get effective address of fault */
310#ifdef CONFIG_8xx_CPU15
311	addi	r11, r10, 0x1000
312	tlbie	r11
313	addi	r11, r10, -0x1000
314	tlbie	r11
315#endif
316	DO_8xx_CPU6(0x3780, r3)
317	mtspr	SPRN_MD_EPN, r10	/* Have to use MD_EPN for walk, MI_EPN can't */
318	mfspr	r10, SPRN_M_TWB	/* Get level 1 table entry address */
319
320	/* If we are faulting a kernel address, we have to use the
321	 * kernel page tables.
322	 */
323#ifdef CONFIG_MODULES
324	/* Only modules will cause ITLB Misses as we always
325	 * pin the first 8MB of kernel memory */
326	andi.	r11, r10, 0x0800	/* Address >= 0x80000000 */
327	beq	3f
328	lis	r11, swapper_pg_dir@h
329	ori	r11, r11, swapper_pg_dir@l
330	rlwimi	r10, r11, 0, 2, 19
3313:
332#endif
333	lwz	r11, 0(r10)	/* Get the level 1 entry */
334	rlwinm.	r10, r11,0,0,19	/* Extract page descriptor page address */
335	beq	2f		/* If zero, don't try to find a pte */
336
337	/* We have a pte table, so load the MI_TWC with the attributes
338	 * for this "segment."
339	 */
340	ori	r11,r11,1		/* Set valid bit */
341	DO_8xx_CPU6(0x2b80, r3)
342	mtspr	SPRN_MI_TWC, r11	/* Set segment attributes */
343	DO_8xx_CPU6(0x3b80, r3)
344	mtspr	SPRN_MD_TWC, r11	/* Load pte table base address */
345	mfspr	r11, SPRN_MD_TWC	/* ....and get the pte address */
346	lwz	r10, 0(r11)	/* Get the pte */
347
348#ifdef CONFIG_SWAP
349	andi.	r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
350	cmpwi	cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
351	bne-	cr0, 2f
352#endif
353	/* The Linux PTE won't go exactly into the MMU TLB.
354	 * Software indicator bits 21 and 28 must be clear.
355	 * Software indicator bits 24, 25, 26, and 27 must be
356	 * set.  All other Linux PTE bits control the behavior
357	 * of the MMU.
358	 */
359	li	r11, 0x00f0
360	rlwimi	r10, r11, 0, 0x07f8	/* Set 24-27, clear 21-23,28 */
361	DO_8xx_CPU6(0x2d80, r3)
362	mtspr	SPRN_MI_RPN, r10	/* Update TLB entry */
363
364	/* Restore registers */
365#ifdef CONFIG_8xx_CPU6
366	lwz	r3, 8(r0)
367#endif
368	mfspr	r10, SPRN_SPRG_SCRATCH2
369	EXCEPTION_EPILOG_0
370	rfi
3712:
372	mfspr	r11, SPRN_SRR1
373	/* clear all error bits as TLB Miss
374	 * sets a few unconditionally
375	*/
376	rlwinm	r11, r11, 0, 0xffff
377	mtspr	SPRN_SRR1, r11
378
379	/* Restore registers */
380#ifdef CONFIG_8xx_CPU6
381	lwz	r3, 8(r0)
382#endif
383	mfspr	r10, SPRN_SPRG_SCRATCH2
384	EXCEPTION_EPILOG_0
385	b	InstructionAccess
386
387	. = 0x1200
388DataStoreTLBMiss:
389#ifdef CONFIG_8xx_CPU6
390	stw	r3, 8(r0)
391#endif
392	EXCEPTION_PROLOG_0
393	mtspr	SPRN_SPRG_SCRATCH2, r10
394	mfspr	r10, SPRN_M_TWB	/* Get level 1 table entry address */
395
396	/* If we are faulting a kernel address, we have to use the
397	 * kernel page tables.
398	 */
399	andi.	r11, r10, 0x0800
400	beq	3f
401	lis	r11, swapper_pg_dir@h
402	ori	r11, r11, swapper_pg_dir@l
403	rlwimi	r10, r11, 0, 2, 19
4043:
405	lwz	r11, 0(r10)	/* Get the level 1 entry */
406	rlwinm.	r10, r11,0,0,19	/* Extract page descriptor page address */
407	beq	2f		/* If zero, don't try to find a pte */
408
409	/* We have a pte table, so load fetch the pte from the table.
410	 */
411	ori	r11, r11, 1	/* Set valid bit in physical L2 page */
412	DO_8xx_CPU6(0x3b80, r3)
413	mtspr	SPRN_MD_TWC, r11	/* Load pte table base address */
414	mfspr	r10, SPRN_MD_TWC	/* ....and get the pte address */
415	lwz	r10, 0(r10)	/* Get the pte */
416
417	/* Insert the Guarded flag into the TWC from the Linux PTE.
418	 * It is bit 27 of both the Linux PTE and the TWC (at least
419	 * I got that right :-).  It will be better when we can put
420	 * this into the Linux pgd/pmd and load it in the operation
421	 * above.
422	 */
423	rlwimi	r11, r10, 0, 27, 27
424	/* Insert the WriteThru flag into the TWC from the Linux PTE.
425	 * It is bit 25 in the Linux PTE and bit 30 in the TWC
426	 */
427	rlwimi	r11, r10, 32-5, 30, 30
428	DO_8xx_CPU6(0x3b80, r3)
429	mtspr	SPRN_MD_TWC, r11
430
431	/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
432	 * We also need to know if the insn is a load/store, so:
433	 * Clear _PAGE_PRESENT and load that which will
434	 * trap into DTLB Error with store bit set accordinly.
435	 */
436	/* PRESENT=0x1, ACCESSED=0x20
437	 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
438	 * r10 = (r10 & ~PRESENT) | r11;
439	 */
440#ifdef CONFIG_SWAP
441	rlwinm	r11, r10, 32-5, _PAGE_PRESENT
442	and	r11, r11, r10
443	rlwimi	r10, r11, 0, _PAGE_PRESENT
444#endif
445	/* Honour kernel RO, User NA */
446	/* 0x200 == Extended encoding, bit 22 */
447	rlwimi	r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */
448	/* r11 =  (r10 & _PAGE_RW) >> 1 */
449	rlwinm	r11, r10, 32-1, 0x200
450	or	r10, r11, r10
451	/* invert RW and 0x200 bits */
452	xori	r10, r10, _PAGE_RW | 0x200
453
454	/* The Linux PTE won't go exactly into the MMU TLB.
455	 * Software indicator bits 22 and 28 must be clear.
456	 * Software indicator bits 24, 25, 26, and 27 must be
457	 * set.  All other Linux PTE bits control the behavior
458	 * of the MMU.
459	 */
4602:	li	r11, 0x00f0
461	rlwimi	r10, r11, 0, 24, 28	/* Set 24-27, clear 28 */
462	DO_8xx_CPU6(0x3d80, r3)
463	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */
464
465	/* Restore registers */
466#ifdef CONFIG_8xx_CPU6
467	lwz	r3, 8(r0)
468#endif
469	mtspr	SPRN_DAR, r11	/* Tag DAR */
470	mfspr	r10, SPRN_SPRG_SCRATCH2
471	EXCEPTION_EPILOG_0
472	rfi
473
474/* This is an instruction TLB error on the MPC8xx.  This could be due
475 * to many reasons, such as executing guarded memory or illegal instruction
476 * addresses.  There is nothing to do but handle a big time error fault.
477 */
478	. = 0x1300
479InstructionTLBError:
480	b	InstructionAccess
481
482/* This is the data TLB error on the MPC8xx.  This could be due to
483 * many reasons, including a dirty update to a pte.  We bail out to
484 * a higher level function that can handle it.
485 */
486	. = 0x1400
487DataTLBError:
488	EXCEPTION_PROLOG_0
489
490	mfspr	r11, SPRN_DAR
491	cmpwi	cr0, r11, 0x00f0
492	beq-	FixupDAR	/* must be a buggy dcbX, icbi insn. */
493DARFixed:/* Return from dcbx instruction bug workaround */
494	EXCEPTION_EPILOG_0
495	b	DataAccess
496
497	EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
498	EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
499	EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
500	EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
501	EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
502	EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
503	EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
504
505/* On the MPC8xx, these next four traps are used for development
506 * support of breakpoints and such.  Someday I will get around to
507 * using them.
508 */
509	EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
510	EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
511	EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
512	EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
513
514	. = 0x2000
515
516/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
517 * by decoding the registers used by the dcbx instruction and adding them.
518 * DAR is set to the calculated address.
519 */
520 /* define if you don't want to use self modifying code */
521#define NO_SELF_MODIFYING_CODE
522FixupDAR:/* Entry point for dcbx workaround. */
523#ifdef CONFIG_8xx_CPU6
524	stw	r3, 8(r0)
525#endif
526	mtspr	SPRN_SPRG_SCRATCH2, r10
527	/* fetch instruction from memory. */
528	mfspr	r10, SPRN_SRR0
529	andis.	r11, r10, 0x8000	/* Address >= 0x80000000 */
530	DO_8xx_CPU6(0x3780, r3)
531	mtspr	SPRN_MD_EPN, r10
532	mfspr	r11, SPRN_M_TWB	/* Get level 1 table entry address */
533	beq-	3f		/* Branch if user space */
534	lis	r11, (swapper_pg_dir-PAGE_OFFSET)@h
535	ori	r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
536	rlwimi	r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */
5373:	lwz	r11, 0(r11)	/* Get the level 1 entry */
538	DO_8xx_CPU6(0x3b80, r3)
539	mtspr	SPRN_MD_TWC, r11	/* Load pte table base address */
540	mfspr	r11, SPRN_MD_TWC	/* ....and get the pte address */
541	lwz	r11, 0(r11)	/* Get the pte */
542#ifdef CONFIG_8xx_CPU6
543	lwz	r3, 8(r0)	/* restore r3 from memory */
544#endif
545	/* concat physical page address(r11) and page offset(r10) */
546	rlwimi	r11, r10, 0, 20, 31
547	lwz	r11,0(r11)
548/* Check if it really is a dcbx instruction. */
549/* dcbt and dcbtst does not generate DTLB Misses/Errors,
550 * no need to include them here */
551	xoris	r10, r11, 0x7c00	/* check if major OP code is 31 */
552	rlwinm	r10, r10, 0, 21, 5
553	cmpwi	cr0, r10, 2028	/* Is dcbz? */
554	beq+	142f
555	cmpwi	cr0, r10, 940	/* Is dcbi? */
556	beq+	142f
557	cmpwi	cr0, r10, 108	/* Is dcbst? */
558	beq+	144f		/* Fix up store bit! */
559	cmpwi	cr0, r10, 172	/* Is dcbf? */
560	beq+	142f
561	cmpwi	cr0, r10, 1964	/* Is icbi? */
562	beq+	142f
563141:	mfspr	r10,SPRN_SPRG_SCRATCH2
564	b	DARFixed	/* Nope, go back to normal TLB processing */
565
566144:	mfspr	r10, SPRN_DSISR
567	rlwinm	r10, r10,0,7,5	/* Clear store bit for buggy dcbst insn */
568	mtspr	SPRN_DSISR, r10
569142:	/* continue, it was a dcbx, dcbi instruction. */
570#ifndef NO_SELF_MODIFYING_CODE
571	andis.	r10,r11,0x1f	/* test if reg RA is r0 */
572	li	r10,modified_instr@l
573	dcbtst	r0,r10		/* touch for store */
574	rlwinm	r11,r11,0,0,20	/* Zero lower 10 bits */
575	oris	r11,r11,640	/* Transform instr. to a "add r10,RA,RB" */
576	ori	r11,r11,532
577	stw	r11,0(r10)	/* store add/and instruction */
578	dcbf	0,r10		/* flush new instr. to memory. */
579	icbi	0,r10		/* invalidate instr. cache line */
580	mfspr	r11, SPRN_SPRG_SCRATCH1	/* restore r11 */
581	mfspr	r10, SPRN_SPRG_SCRATCH0	/* restore r10 */
582	isync			/* Wait until new instr is loaded from memory */
583modified_instr:
584	.space	4		/* this is where the add instr. is stored */
585	bne+	143f
586	subf	r10,r0,r10	/* r10=r10-r0, only if reg RA is r0 */
587143:	mtdar	r10		/* store faulting EA in DAR */
588	mfspr	r10,SPRN_SPRG_SCRATCH2
589	b	DARFixed	/* Go back to normal TLB handling */
590#else
591	mfctr	r10
592	mtdar	r10			/* save ctr reg in DAR */
593	rlwinm	r10, r11, 24, 24, 28	/* offset into jump table for reg RB */
594	addi	r10, r10, 150f@l	/* add start of table */
595	mtctr	r10			/* load ctr with jump address */
596	xor	r10, r10, r10		/* sum starts at zero */
597	bctr				/* jump into table */
598150:
599	add	r10, r10, r0	;b	151f
600	add	r10, r10, r1	;b	151f
601	add	r10, r10, r2	;b	151f
602	add	r10, r10, r3	;b	151f
603	add	r10, r10, r4	;b	151f
604	add	r10, r10, r5	;b	151f
605	add	r10, r10, r6	;b	151f
606	add	r10, r10, r7	;b	151f
607	add	r10, r10, r8	;b	151f
608	add	r10, r10, r9	;b	151f
609	mtctr	r11	;b	154f	/* r10 needs special handling */
610	mtctr	r11	;b	153f	/* r11 needs special handling */
611	add	r10, r10, r12	;b	151f
612	add	r10, r10, r13	;b	151f
613	add	r10, r10, r14	;b	151f
614	add	r10, r10, r15	;b	151f
615	add	r10, r10, r16	;b	151f
616	add	r10, r10, r17	;b	151f
617	add	r10, r10, r18	;b	151f
618	add	r10, r10, r19	;b	151f
619	add	r10, r10, r20	;b	151f
620	add	r10, r10, r21	;b	151f
621	add	r10, r10, r22	;b	151f
622	add	r10, r10, r23	;b	151f
623	add	r10, r10, r24	;b	151f
624	add	r10, r10, r25	;b	151f
625	add	r10, r10, r26	;b	151f
626	add	r10, r10, r27	;b	151f
627	add	r10, r10, r28	;b	151f
628	add	r10, r10, r29	;b	151f
629	add	r10, r10, r30	;b	151f
630	add	r10, r10, r31
631151:
632	rlwinm. r11,r11,19,24,28	/* offset into jump table for reg RA */
633	beq	152f			/* if reg RA is zero, don't add it */
634	addi	r11, r11, 150b@l	/* add start of table */
635	mtctr	r11			/* load ctr with jump address */
636	rlwinm	r11,r11,0,16,10		/* make sure we don't execute this more than once */
637	bctr				/* jump into table */
638152:
639	mfdar	r11
640	mtctr	r11			/* restore ctr reg from DAR */
641	mtdar	r10			/* save fault EA to DAR */
642	mfspr	r10,SPRN_SPRG_SCRATCH2
643	b	DARFixed		/* Go back to normal TLB handling */
644
645	/* special handling for r10,r11 since these are modified already */
646153:	mfspr	r11, SPRN_SPRG_SCRATCH1	/* load r11 from SPRN_SPRG_SCRATCH1 */
647	add	r10, r10, r11	/* add it */
648	mfctr	r11		/* restore r11 */
649	b	151b
650154:	mfspr	r11, SPRN_SPRG_SCRATCH0	/* load r10 from SPRN_SPRG_SCRATCH0 */
651	add	r10, r10, r11	/* add it */
652	mfctr	r11		/* restore r11 */
653	b	151b
654#endif
655
656/*
657 * This is where the main kernel code starts.
658 */
659start_here:
660	/* ptr to current */
661	lis	r2,init_task@h
662	ori	r2,r2,init_task@l
663
664	/* ptr to phys current thread */
665	tophys(r4,r2)
666	addi	r4,r4,THREAD	/* init task's THREAD */
667	mtspr	SPRN_SPRG_THREAD,r4
668
669	/* stack */
670	lis	r1,init_thread_union@ha
671	addi	r1,r1,init_thread_union@l
672	li	r0,0
673	stwu	r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
674
675	bl	early_init	/* We have to do this with MMU on */
676
677/*
678 * Decide what sort of machine this is and initialize the MMU.
679 */
680	li	r3,0
681	mr	r4,r31
682	bl	machine_init
683	bl	MMU_init
684
685/*
686 * Go back to running unmapped so we can load up new values
687 * and change to using our exception vectors.
688 * On the 8xx, all we have to do is invalidate the TLB to clear
689 * the old 8M byte TLB mappings and load the page table base register.
690 */
691	/* The right way to do this would be to track it down through
692	 * init's THREAD like the context switch code does, but this is
693	 * easier......until someone changes init's static structures.
694	 */
695	lis	r6, swapper_pg_dir@h
696	ori	r6, r6, swapper_pg_dir@l
697	tophys(r6,r6)
698#ifdef CONFIG_8xx_CPU6
699	lis	r4, cpu6_errata_word@h
700	ori	r4, r4, cpu6_errata_word@l
701	li	r3, 0x3980
702	stw	r3, 12(r4)
703	lwz	r3, 12(r4)
704#endif
705	mtspr	SPRN_M_TWB, r6
706	lis	r4,2f@h
707	ori	r4,r4,2f@l
708	tophys(r4,r4)
709	li	r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
710	mtspr	SPRN_SRR0,r4
711	mtspr	SPRN_SRR1,r3
712	rfi
713/* Load up the kernel context */
7142:
715	SYNC			/* Force all PTE updates to finish */
716	tlbia			/* Clear all TLB entries */
717	sync			/* wait for tlbia/tlbie to finish */
718	TLBSYNC			/* ... on all CPUs */
719
720	/* set up the PTE pointers for the Abatron bdiGDB.
721	*/
722	tovirt(r6,r6)
723	lis	r5, abatron_pteptrs@h
724	ori	r5, r5, abatron_pteptrs@l
725	stw	r5, 0xf0(r0)	/* Must match your Abatron config file */
726	tophys(r5,r5)
727	stw	r6, 0(r5)
728
729/* Now turn on the MMU for real! */
730	li	r4,MSR_KERNEL
731	lis	r3,start_kernel@h
732	ori	r3,r3,start_kernel@l
733	mtspr	SPRN_SRR0,r3
734	mtspr	SPRN_SRR1,r4
735	rfi			/* enable MMU and jump to start_kernel */
736
737/* Set up the initial MMU state so we can do the first level of
738 * kernel initialization.  This maps the first 8 MBytes of memory 1:1
739 * virtual to physical.  Also, set the cache mode since that is defined
740 * by TLB entries and perform any additional mapping (like of the IMMR).
741 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
742 * 24 Mbytes of data, and the 8M IMMR space.  Anything not covered by
743 * these mappings is mapped by page tables.
744 */
745initial_mmu:
746	tlbia			/* Invalidate all TLB entries */
747/* Always pin the first 8 MB ITLB to prevent ITLB
748   misses while mucking around with SRR0/SRR1 in asm
749*/
750	lis	r8, MI_RSV4I@h
751	ori	r8, r8, 0x1c00
752
753	mtspr	SPRN_MI_CTR, r8	/* Set instruction MMU control */
754
755#ifdef CONFIG_PIN_TLB
756	lis	r10, (MD_RSV4I | MD_RESETVAL)@h
757	ori	r10, r10, 0x1c00
758	mr	r8, r10
759#else
760	lis	r10, MD_RESETVAL@h
761#endif
762#ifndef CONFIG_8xx_COPYBACK
763	oris	r10, r10, MD_WTDEF@h
764#endif
765	mtspr	SPRN_MD_CTR, r10	/* Set data TLB control */
766
767	/* Now map the lower 8 Meg into the TLBs.  For this quick hack,
768	 * we can load the instruction and data TLB registers with the
769	 * same values.
770	 */
771	lis	r8, KERNELBASE@h	/* Create vaddr for TLB */
772	ori	r8, r8, MI_EVALID	/* Mark it valid */
773	mtspr	SPRN_MI_EPN, r8
774	mtspr	SPRN_MD_EPN, r8
775	li	r8, MI_PS8MEG		/* Set 8M byte page */
776	ori	r8, r8, MI_SVALID	/* Make it valid */
777	mtspr	SPRN_MI_TWC, r8
778	mtspr	SPRN_MD_TWC, r8
779	li	r8, MI_BOOTINIT		/* Create RPN for address 0 */
780	mtspr	SPRN_MI_RPN, r8		/* Store TLB entry */
781	mtspr	SPRN_MD_RPN, r8
782	lis	r8, MI_Kp@h		/* Set the protection mode */
783	mtspr	SPRN_MI_AP, r8
784	mtspr	SPRN_MD_AP, r8
785
786	/* Map another 8 MByte at the IMMR to get the processor
787	 * internal registers (among other things).
788	 */
789#ifdef CONFIG_PIN_TLB
790	addi	r10, r10, 0x0100
791	mtspr	SPRN_MD_CTR, r10
792#endif
793	mfspr	r9, 638			/* Get current IMMR */
794	andis.	r9, r9, 0xff80		/* Get 8Mbyte boundary */
795
796	mr	r8, r9			/* Create vaddr for TLB */
797	ori	r8, r8, MD_EVALID	/* Mark it valid */
798	mtspr	SPRN_MD_EPN, r8
799	li	r8, MD_PS8MEG		/* Set 8M byte page */
800	ori	r8, r8, MD_SVALID	/* Make it valid */
801	mtspr	SPRN_MD_TWC, r8
802	mr	r8, r9			/* Create paddr for TLB */
803	ori	r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
804	mtspr	SPRN_MD_RPN, r8
805
806#ifdef CONFIG_PIN_TLB
807	/* Map two more 8M kernel data pages.
808	*/
809	addi	r10, r10, 0x0100
810	mtspr	SPRN_MD_CTR, r10
811
812	lis	r8, KERNELBASE@h	/* Create vaddr for TLB */
813	addis	r8, r8, 0x0080		/* Add 8M */
814	ori	r8, r8, MI_EVALID	/* Mark it valid */
815	mtspr	SPRN_MD_EPN, r8
816	li	r9, MI_PS8MEG		/* Set 8M byte page */
817	ori	r9, r9, MI_SVALID	/* Make it valid */
818	mtspr	SPRN_MD_TWC, r9
819	li	r11, MI_BOOTINIT	/* Create RPN for address 0 */
820	addis	r11, r11, 0x0080	/* Add 8M */
821	mtspr	SPRN_MD_RPN, r11
822
823	addi	r10, r10, 0x0100
824	mtspr	SPRN_MD_CTR, r10
825
826	addis	r8, r8, 0x0080		/* Add 8M */
827	mtspr	SPRN_MD_EPN, r8
828	mtspr	SPRN_MD_TWC, r9
829	addis	r11, r11, 0x0080	/* Add 8M */
830	mtspr	SPRN_MD_RPN, r11
831#endif
832
833	/* Since the cache is enabled according to the information we
834	 * just loaded into the TLB, invalidate and enable the caches here.
835	 * We should probably check/set other modes....later.
836	 */
837	lis	r8, IDC_INVALL@h
838	mtspr	SPRN_IC_CST, r8
839	mtspr	SPRN_DC_CST, r8
840	lis	r8, IDC_ENABLE@h
841	mtspr	SPRN_IC_CST, r8
842#ifdef CONFIG_8xx_COPYBACK
843	mtspr	SPRN_DC_CST, r8
844#else
845	/* For a debug option, I left this here to easily enable
846	 * the write through cache mode
847	 */
848	lis	r8, DC_SFWT@h
849	mtspr	SPRN_DC_CST, r8
850	lis	r8, IDC_ENABLE@h
851	mtspr	SPRN_DC_CST, r8
852#endif
853	blr
854
855
856/*
857 * Set up to use a given MMU context.
858 * r3 is context number, r4 is PGD pointer.
859 *
860 * We place the physical address of the new task page directory loaded
861 * into the MMU base register, and set the ASID compare register with
862 * the new "context."
863 */
864_GLOBAL(set_context)
865
866#ifdef CONFIG_BDI_SWITCH
867	/* Context switch the PTE pointer for the Abatron BDI2000.
868	 * The PGDIR is passed as second argument.
869	 */
870	lis	r5, KERNELBASE@h
871	lwz	r5, 0xf0(r5)
872	stw	r4, 0x4(r5)
873#endif
874
875#ifdef CONFIG_8xx_CPU6
876	lis	r6, cpu6_errata_word@h
877	ori	r6, r6, cpu6_errata_word@l
878	tophys	(r4, r4)
879	li	r7, 0x3980
880	stw	r7, 12(r6)
881	lwz	r7, 12(r6)
882        mtspr   SPRN_M_TWB, r4               /* Update MMU base address */
883	li	r7, 0x3380
884	stw	r7, 12(r6)
885	lwz	r7, 12(r6)
886        mtspr   SPRN_M_CASID, r3             /* Update context */
887#else
888        mtspr   SPRN_M_CASID,r3		/* Update context */
889	tophys	(r4, r4)
890	mtspr	SPRN_M_TWB, r4		/* and pgd */
891#endif
892	SYNC
893	blr
894
895#ifdef CONFIG_8xx_CPU6
896/* It's here because it is unique to the 8xx.
897 * It is important we get called with interrupts disabled.  I used to
898 * do that, but it appears that all code that calls this already had
899 * interrupt disabled.
900 */
901	.globl	set_dec_cpu6
902set_dec_cpu6:
903	lis	r7, cpu6_errata_word@h
904	ori	r7, r7, cpu6_errata_word@l
905	li	r4, 0x2c00
906	stw	r4, 8(r7)
907	lwz	r4, 8(r7)
908        mtspr   22, r3		/* Update Decrementer */
909	SYNC
910	blr
911#endif
912
913/*
914 * We put a few things here that have to be page-aligned.
915 * This stuff goes at the beginning of the data segment,
916 * which is page-aligned.
917 */
918	.data
919	.globl	sdata
920sdata:
921	.globl	empty_zero_page
922empty_zero_page:
923	.space	4096
924
925	.globl	swapper_pg_dir
926swapper_pg_dir:
927	.space	4096
928
929/* Room for two PTE table poiners, usually the kernel and current user
930 * pointer to their respective root page table (pgdir).
931 */
932abatron_pteptrs:
933	.space	8
934
935#ifdef CONFIG_8xx_CPU6
936	.globl	cpu6_errata_word
937cpu6_errata_word:
938	.space	16
939#endif
940
941