1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Low-level exception handlers and MMU support 8 * rewritten by Paul Mackerras. 9 * Copyright (C) 1996 Paul Mackerras. 10 * MPC8xx modifications by Dan Malek 11 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 12 * 13 * This file contains low-level support and setup for PowerPC 8xx 14 * embedded processors, including trap and interrupt dispatch. 15 */ 16 17#include <linux/init.h> 18#include <linux/magic.h> 19#include <linux/pgtable.h> 20#include <linux/sizes.h> 21#include <linux/linkage.h> 22 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/cputable.h> 28#include <asm/thread_info.h> 29#include <asm/ppc_asm.h> 30#include <asm/asm-offsets.h> 31#include <asm/ptrace.h> 32#include <asm/export.h> 33#include <asm/code-patching-asm.h> 34#include <asm/interrupt.h> 35 36/* 37 * Value for the bits that have fixed value in RPN entries. 38 * Also used for tagging DAR for DTLBerror. 39 */ 40#define RPN_PATTERN 0x00f0 41 42#include "head_32.h" 43 44.macro compare_to_kernel_boundary scratch, addr 45#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 46/* By simply checking Address >= 0x80000000, we know if its a kernel address */ 47 not. \scratch, \addr 48#else 49 rlwinm \scratch, \addr, 16, 0xfff8 50 cmpli cr0, \scratch, PAGE_OFFSET@h 51#endif 52.endm 53 54#define PAGE_SHIFT_512K 19 55#define PAGE_SHIFT_8M 23 56 57 __HEAD 58_GLOBAL(_stext); 59_GLOBAL(_start); 60 61/* MPC8xx 62 * This port was done on an MBX board with an 860. Right now I only 63 * support an ELF compressed (zImage) boot from EPPC-Bug because the 64 * code there loads up some registers before calling us: 65 * r3: ptr to board info data 66 * r4: initrd_start or if no initrd then 0 67 * r5: initrd_end - unused if r4 is 0 68 * r6: Start of command line string 69 * r7: End of command line string 70 * 71 * I decided to use conditional compilation instead of checking PVR and 72 * adding more processor specific branches around code I don't need. 73 * Since this is an embedded processor, I also appreciate any memory 74 * savings I can get. 75 * 76 * The MPC8xx does not have any BATs, but it supports large page sizes. 77 * We first initialize the MMU to support 8M byte pages, then load one 78 * entry into each of the instruction and data TLBs to map the first 79 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 80 * the "internal" processor registers before MMU_init is called. 81 * 82 * -- Dan 83 */ 84 .globl __start 85__start: 86 mr r31,r3 /* save device tree ptr */ 87 88 /* We have to turn on the MMU right away so we get cache modes 89 * set correctly. 90 */ 91 bl initial_mmu 92 93/* We now have the lower 8 Meg mapped into TLB entries, and the caches 94 * ready to work. 95 */ 96 97turn_on_mmu: 98 mfmsr r0 99 ori r0,r0,MSR_DR|MSR_IR 100 mtspr SPRN_SRR1,r0 101 lis r0,start_here@h 102 ori r0,r0,start_here@l 103 mtspr SPRN_SRR0,r0 104 rfi /* enables MMU */ 105 106 107#ifdef CONFIG_PERF_EVENTS 108 .align 4 109 110 .globl itlb_miss_counter 111itlb_miss_counter: 112 .space 4 113 114 .globl dtlb_miss_counter 115dtlb_miss_counter: 116 .space 4 117 118 .globl instruction_counter 119instruction_counter: 120 .space 4 121#endif 122 123/* System reset */ 124 EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, system_reset_exception) 125 126/* Machine check */ 127 START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck) 128 EXCEPTION_PROLOG INTERRUPT_MACHINE_CHECK MachineCheck handle_dar_dsisr=1 129 prepare_transfer_to_handler 130 bl machine_check_exception 131 b interrupt_return 132 133/* External interrupt */ 134 EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ) 135 136/* Alignment exception */ 137 START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment) 138 EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1 139 prepare_transfer_to_handler 140 bl alignment_exception 141 REST_NVGPRS(r1) 142 b interrupt_return 143 144/* Program check exception */ 145 START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck) 146 EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck 147 prepare_transfer_to_handler 148 bl program_check_exception 149 REST_NVGPRS(r1) 150 b interrupt_return 151 152/* Decrementer */ 153 EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt) 154 155/* System call */ 156 START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall) 157 SYSCALL_ENTRY INTERRUPT_SYSCALL 158 159/* Single step - not used on 601 */ 160 EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception) 161 162/* On the MPC8xx, this is a software emulation interrupt. It occurs 163 * for all unimplemented and illegal instructions. 164 */ 165 START_EXCEPTION(INTERRUPT_SOFT_EMU_8xx, SoftEmu) 166 EXCEPTION_PROLOG INTERRUPT_SOFT_EMU_8xx SoftEmu 167 prepare_transfer_to_handler 168 bl emulation_assist_interrupt 169 REST_NVGPRS(r1) 170 b interrupt_return 171 172/* 173 * For the MPC8xx, this is a software tablewalk to load the instruction 174 * TLB. The task switch loads the M_TWB register with the pointer to the first 175 * level table. 176 * If we discover there is no second level table (value is zero) or if there 177 * is an invalid pte, we load that into the TLB, which causes another fault 178 * into the TLB Error interrupt where we can handle such problems. 179 * We have to use the MD_xxx registers for the tablewalk because the 180 * equivalent MI_xxx registers only perform the attribute functions. 181 */ 182 183#ifdef CONFIG_8xx_CPU15 184#define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp) \ 185 addi tmp, addr, PAGE_SIZE; \ 186 tlbie tmp; \ 187 addi tmp, addr, -PAGE_SIZE; \ 188 tlbie tmp 189#else 190#define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp) 191#endif 192 193 START_EXCEPTION(INTERRUPT_INST_TLB_MISS_8xx, InstructionTLBMiss) 194 mtspr SPRN_SPRG_SCRATCH2, r10 195 mtspr SPRN_M_TW, r11 196 197 /* If we are faulting a kernel address, we have to use the 198 * kernel page tables. 199 */ 200 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 201 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) 202 mtspr SPRN_MD_EPN, r10 203#ifdef CONFIG_MODULES 204 mfcr r11 205 compare_to_kernel_boundary r10, r10 206#endif 207 mfspr r10, SPRN_M_TWB /* Get level 1 table */ 208#ifdef CONFIG_MODULES 209 blt+ 3f 210 rlwinm r10, r10, 0, 20, 31 211 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha 2123: 213 mtcr r11 214#endif 215 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */ 216 mtspr SPRN_MD_TWC, r11 217 mfspr r10, SPRN_MD_TWC 218 lwz r10, 0(r10) /* Get the pte */ 219 rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED 220 rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K 221 mtspr SPRN_MI_TWC, r11 222 /* The Linux PTE won't go exactly into the MMU TLB. 223 * Software indicator bits 20 and 23 must be clear. 224 * Software indicator bits 22, 24, 25, 26, and 27 must be 225 * set. All other Linux PTE bits control the behavior 226 * of the MMU. 227 */ 228 rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */ 229 rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ 230 ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */ 231 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 232 233 /* Restore registers */ 2340: mfspr r10, SPRN_SPRG_SCRATCH2 235 mfspr r11, SPRN_M_TW 236 rfi 237 patch_site 0b, patch__itlbmiss_exit_1 238 239#ifdef CONFIG_PERF_EVENTS 240 patch_site 0f, patch__itlbmiss_perf 2410: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) 242 addi r10, r10, 1 243 stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) 244 mfspr r10, SPRN_SPRG_SCRATCH2 245 mfspr r11, SPRN_M_TW 246 rfi 247#endif 248 249 START_EXCEPTION(INTERRUPT_DATA_TLB_MISS_8xx, DataStoreTLBMiss) 250 mtspr SPRN_SPRG_SCRATCH2, r10 251 mtspr SPRN_M_TW, r11 252 mfcr r11 253 254 /* If we are faulting a kernel address, we have to use the 255 * kernel page tables. 256 */ 257 mfspr r10, SPRN_MD_EPN 258 compare_to_kernel_boundary r10, r10 259 mfspr r10, SPRN_M_TWB /* Get level 1 table */ 260 blt+ 3f 261 rlwinm r10, r10, 0, 20, 31 262 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha 2633: 264 mtcr r11 265 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */ 266 267 mtspr SPRN_MD_TWC, r11 268 mfspr r10, SPRN_MD_TWC 269 lwz r10, 0(r10) /* Get the pte */ 270 271 /* Insert Guarded and Accessed flags into the TWC from the Linux PTE. 272 * It is bit 27 of both the Linux PTE and the TWC (at least 273 * I got that right :-). It will be better when we can put 274 * this into the Linux pgd/pmd and load it in the operation 275 * above. 276 */ 277 rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED 278 rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K 279 mtspr SPRN_MD_TWC, r11 280 281 /* The Linux PTE won't go exactly into the MMU TLB. 282 * Software indicator bits 24, 25, 26, and 27 must be 283 * set. All other Linux PTE bits control the behavior 284 * of the MMU. 285 */ 286 li r11, RPN_PATTERN 287 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */ 288 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 289 mtspr SPRN_DAR, r11 /* Tag DAR */ 290 291 /* Restore registers */ 292 2930: mfspr r10, SPRN_SPRG_SCRATCH2 294 mfspr r11, SPRN_M_TW 295 rfi 296 patch_site 0b, patch__dtlbmiss_exit_1 297 298#ifdef CONFIG_PERF_EVENTS 299 patch_site 0f, patch__dtlbmiss_perf 3000: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) 301 addi r10, r10, 1 302 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) 303 mfspr r10, SPRN_SPRG_SCRATCH2 304 mfspr r11, SPRN_M_TW 305 rfi 306#endif 307 308/* This is an instruction TLB error on the MPC8xx. This could be due 309 * to many reasons, such as executing guarded memory or illegal instruction 310 * addresses. There is nothing to do but handle a big time error fault. 311 */ 312 START_EXCEPTION(INTERRUPT_INST_TLB_ERROR_8xx, InstructionTLBError) 313 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 314 EXCEPTION_PROLOG INTERRUPT_INST_STORAGE InstructionTLBError 315 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ 316 andis. r10,r9,SRR1_ISI_NOPT@h 317 beq+ .Litlbie 318 tlbie r12 319.Litlbie: 320 stw r12, _DAR(r11) 321 stw r5, _DSISR(r11) 322 prepare_transfer_to_handler 323 bl do_page_fault 324 b interrupt_return 325 326/* This is the data TLB error on the MPC8xx. This could be due to 327 * many reasons, including a dirty update to a pte. We bail out to 328 * a higher level function that can handle it. 329 */ 330 START_EXCEPTION(INTERRUPT_DATA_TLB_ERROR_8xx, DataTLBError) 331 EXCEPTION_PROLOG_0 handle_dar_dsisr=1 332 mfspr r11, SPRN_DAR 333 cmpwi cr1, r11, RPN_PATTERN 334 beq- cr1, FixupDAR /* must be a buggy dcbX, icbi insn. */ 335DARFixed:/* Return from dcbx instruction bug workaround */ 336 EXCEPTION_PROLOG_1 337 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 338 EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataTLBError handle_dar_dsisr=1 339 lwz r4, _DAR(r11) 340 lwz r5, _DSISR(r11) 341 andis. r10,r5,DSISR_NOHPTE@h 342 beq+ .Ldtlbie 343 tlbie r4 344.Ldtlbie: 345 prepare_transfer_to_handler 346 bl do_page_fault 347 b interrupt_return 348 349#ifdef CONFIG_VMAP_STACK 350 vmap_stack_overflow_exception 351#endif 352 353/* On the MPC8xx, these next four traps are used for development 354 * support of breakpoints and such. Someday I will get around to 355 * using them. 356 */ 357 START_EXCEPTION(INTERRUPT_DATA_BREAKPOINT_8xx, DataBreakpoint) 358 EXCEPTION_PROLOG_0 handle_dar_dsisr=1 359 mfspr r11, SPRN_SRR0 360 cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l 361 cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l 362 cror 4*cr1+eq, 4*cr1+eq, 4*cr7+eq 363 bne cr1, 1f 364 mtcr r10 365 mfspr r10, SPRN_SPRG_SCRATCH0 366 mfspr r11, SPRN_SPRG_SCRATCH1 367 rfi 368 3691: EXCEPTION_PROLOG_1 370 EXCEPTION_PROLOG_2 INTERRUPT_DATA_BREAKPOINT_8xx DataBreakpoint handle_dar_dsisr=1 371 mfspr r4,SPRN_BAR 372 stw r4,_DAR(r11) 373 prepare_transfer_to_handler 374 bl do_break 375 REST_NVGPRS(r1) 376 b interrupt_return 377 378#ifdef CONFIG_PERF_EVENTS 379 START_EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, InstructionBreakpoint) 380 mtspr SPRN_SPRG_SCRATCH0, r10 381 lwz r10, (instruction_counter - PAGE_OFFSET)@l(0) 382 addi r10, r10, -1 383 stw r10, (instruction_counter - PAGE_OFFSET)@l(0) 384 lis r10, 0xffff 385 ori r10, r10, 0x01 386 mtspr SPRN_COUNTA, r10 387 mfspr r10, SPRN_SPRG_SCRATCH0 388 rfi 389#else 390 EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, Trap_1d, unknown_exception) 391#endif 392 EXCEPTION(0x1e00, Trap_1e, unknown_exception) 393 EXCEPTION(0x1f00, Trap_1f, unknown_exception) 394 395 __HEAD 396 . = 0x2000 397 398/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 399 * by decoding the registers used by the dcbx instruction and adding them. 400 * DAR is set to the calculated address. 401 */ 402FixupDAR:/* Entry point for dcbx workaround. */ 403 mtspr SPRN_M_TW, r10 404 /* fetch instruction from memory. */ 405 mfspr r10, SPRN_SRR0 406 mtspr SPRN_MD_EPN, r10 407 rlwinm r11, r10, 16, 0xfff8 408 cmpli cr1, r11, PAGE_OFFSET@h 409 mfspr r11, SPRN_M_TWB /* Get level 1 table */ 410 blt+ cr1, 3f 411 412 /* create physical page address from effective address */ 413 tophys(r11, r10) 414 mfspr r11, SPRN_M_TWB /* Get level 1 table */ 415 rlwinm r11, r11, 0, 20, 31 416 oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha 4173: 418 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 419 mtspr SPRN_MD_TWC, r11 420 mtcrf 0x01, r11 421 mfspr r11, SPRN_MD_TWC 422 lwz r11, 0(r11) /* Get the pte */ 423 bt 28,200f /* bit 28 = Large page (8M) */ 424 /* concat physical page address(r11) and page offset(r10) */ 425 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 426201: lwz r11,0(r11) 427/* Check if it really is a dcbx instruction. */ 428/* dcbt and dcbtst does not generate DTLB Misses/Errors, 429 * no need to include them here */ 430 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 431 rlwinm r10, r10, 0, 21, 5 432 cmpwi cr1, r10, 2028 /* Is dcbz? */ 433 beq+ cr1, 142f 434 cmpwi cr1, r10, 940 /* Is dcbi? */ 435 beq+ cr1, 142f 436 cmpwi cr1, r10, 108 /* Is dcbst? */ 437 beq+ cr1, 144f /* Fix up store bit! */ 438 cmpwi cr1, r10, 172 /* Is dcbf? */ 439 beq+ cr1, 142f 440 cmpwi cr1, r10, 1964 /* Is icbi? */ 441 beq+ cr1, 142f 442141: mfspr r10,SPRN_M_TW 443 b DARFixed /* Nope, go back to normal TLB processing */ 444 445200: 446 /* concat physical page address(r11) and page offset(r10) */ 447 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31 448 b 201b 449 450144: mfspr r10, SPRN_DSISR 451 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 452 mtspr SPRN_DSISR, r10 453142: /* continue, it was a dcbx, dcbi instruction. */ 454 mfctr r10 455 mtdar r10 /* save ctr reg in DAR */ 456 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 457 addi r10, r10, 150f@l /* add start of table */ 458 mtctr r10 /* load ctr with jump address */ 459 xor r10, r10, r10 /* sum starts at zero */ 460 bctr /* jump into table */ 461150: 462 add r10, r10, r0 ;b 151f 463 add r10, r10, r1 ;b 151f 464 add r10, r10, r2 ;b 151f 465 add r10, r10, r3 ;b 151f 466 add r10, r10, r4 ;b 151f 467 add r10, r10, r5 ;b 151f 468 add r10, r10, r6 ;b 151f 469 add r10, r10, r7 ;b 151f 470 add r10, r10, r8 ;b 151f 471 add r10, r10, r9 ;b 151f 472 mtctr r11 ;b 154f /* r10 needs special handling */ 473 mtctr r11 ;b 153f /* r11 needs special handling */ 474 add r10, r10, r12 ;b 151f 475 add r10, r10, r13 ;b 151f 476 add r10, r10, r14 ;b 151f 477 add r10, r10, r15 ;b 151f 478 add r10, r10, r16 ;b 151f 479 add r10, r10, r17 ;b 151f 480 add r10, r10, r18 ;b 151f 481 add r10, r10, r19 ;b 151f 482 add r10, r10, r20 ;b 151f 483 add r10, r10, r21 ;b 151f 484 add r10, r10, r22 ;b 151f 485 add r10, r10, r23 ;b 151f 486 add r10, r10, r24 ;b 151f 487 add r10, r10, r25 ;b 151f 488 add r10, r10, r26 ;b 151f 489 add r10, r10, r27 ;b 151f 490 add r10, r10, r28 ;b 151f 491 add r10, r10, r29 ;b 151f 492 add r10, r10, r30 ;b 151f 493 add r10, r10, r31 494151: 495 rlwinm r11,r11,19,24,28 /* offset into jump table for reg RA */ 496 cmpwi cr1, r11, 0 497 beq cr1, 152f /* if reg RA is zero, don't add it */ 498 addi r11, r11, 150b@l /* add start of table */ 499 mtctr r11 /* load ctr with jump address */ 500 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 501 bctr /* jump into table */ 502152: 503 mfdar r11 504 mtctr r11 /* restore ctr reg from DAR */ 505 mfspr r11, SPRN_SPRG_THREAD 506 stw r10, DAR(r11) 507 mfspr r10, SPRN_DSISR 508 stw r10, DSISR(r11) 509 mfspr r10,SPRN_M_TW 510 b DARFixed /* Go back to normal TLB handling */ 511 512 /* special handling for r10,r11 since these are modified already */ 513153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 514 add r10, r10, r11 /* add it */ 515 mfctr r11 /* restore r11 */ 516 b 151b 517154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 518 add r10, r10, r11 /* add it */ 519 mfctr r11 /* restore r11 */ 520 b 151b 521 522/* 523 * This is where the main kernel code starts. 524 */ 525start_here: 526 /* ptr to current */ 527 lis r2,init_task@h 528 ori r2,r2,init_task@l 529 530 /* ptr to phys current thread */ 531 tophys(r4,r2) 532 addi r4,r4,THREAD /* init task's THREAD */ 533 mtspr SPRN_SPRG_THREAD,r4 534 535 /* stack */ 536 lis r1,init_thread_union@ha 537 addi r1,r1,init_thread_union@l 538 lis r0, STACK_END_MAGIC@h 539 ori r0, r0, STACK_END_MAGIC@l 540 stw r0, 0(r1) 541 li r0,0 542 stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1) 543 544 lis r6, swapper_pg_dir@ha 545 tophys(r6,r6) 546 mtspr SPRN_M_TWB, r6 547 548 bl early_init /* We have to do this with MMU on */ 549 550/* 551 * Decide what sort of machine this is and initialize the MMU. 552 */ 553#ifdef CONFIG_KASAN 554 bl kasan_early_init 555#endif 556 li r3,0 557 mr r4,r31 558 bl machine_init 559 bl MMU_init 560 561/* 562 * Go back to running unmapped so we can load up new values 563 * and change to using our exception vectors. 564 * On the 8xx, all we have to do is invalidate the TLB to clear 565 * the old 8M byte TLB mappings and load the page table base register. 566 */ 567 /* The right way to do this would be to track it down through 568 * init's THREAD like the context switch code does, but this is 569 * easier......until someone changes init's static structures. 570 */ 571 lis r4,2f@h 572 ori r4,r4,2f@l 573 tophys(r4,r4) 574 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 575 mtspr SPRN_SRR0,r4 576 mtspr SPRN_SRR1,r3 577 rfi 578/* Load up the kernel context */ 5792: 580#ifdef CONFIG_PIN_TLB_IMMR 581 lis r0, MD_TWAM@h 582 oris r0, r0, 0x1f00 583 mtspr SPRN_MD_CTR, r0 584 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID) 585 tlbie r0 586 mtspr SPRN_MD_EPN, r0 587 LOAD_REG_IMMEDIATE(r0, MD_SVALID | MD_PS512K | MD_GUARDED) 588 mtspr SPRN_MD_TWC, r0 589 mfspr r0, SPRN_IMMR 590 rlwinm r0, r0, 0, 0xfff80000 591 ori r0, r0, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \ 592 _PAGE_NO_CACHE | _PAGE_PRESENT 593 mtspr SPRN_MD_RPN, r0 594 lis r0, (MD_TWAM | MD_RSV4I)@h 595 mtspr SPRN_MD_CTR, r0 596#endif 597#if !defined(CONFIG_PIN_TLB_DATA) && !defined(CONFIG_PIN_TLB_IMMR) 598 lis r0, MD_TWAM@h 599 mtspr SPRN_MD_CTR, r0 600#endif 601 tlbia /* Clear all TLB entries */ 602 sync /* wait for tlbia/tlbie to finish */ 603 604 /* set up the PTE pointers for the Abatron bdiGDB. 605 */ 606 lis r5, abatron_pteptrs@h 607 ori r5, r5, abatron_pteptrs@l 608 stw r5, 0xf0(0) /* Must match your Abatron config file */ 609 tophys(r5,r5) 610 lis r6, swapper_pg_dir@h 611 ori r6, r6, swapper_pg_dir@l 612 stw r6, 0(r5) 613 614/* Now turn on the MMU for real! */ 615 li r4,MSR_KERNEL 616 lis r3,start_kernel@h 617 ori r3,r3,start_kernel@l 618 mtspr SPRN_SRR0,r3 619 mtspr SPRN_SRR1,r4 620 rfi /* enable MMU and jump to start_kernel */ 621 622/* Set up the initial MMU state so we can do the first level of 623 * kernel initialization. This maps the first 8 MBytes of memory 1:1 624 * virtual to physical. Also, set the cache mode since that is defined 625 * by TLB entries and perform any additional mapping (like of the IMMR). 626 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 627 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 628 * these mappings is mapped by page tables. 629 */ 630SYM_FUNC_START_LOCAL(initial_mmu) 631 li r8, 0 632 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 633 lis r10, MD_TWAM@h 634 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 635 636 tlbia /* Invalidate all TLB entries */ 637 638 lis r8, MI_APG_INIT@h /* Set protection modes */ 639 ori r8, r8, MI_APG_INIT@l 640 mtspr SPRN_MI_AP, r8 641 lis r8, MD_APG_INIT@h 642 ori r8, r8, MD_APG_INIT@l 643 mtspr SPRN_MD_AP, r8 644 645 /* Map the lower RAM (up to 32 Mbytes) into the ITLB and DTLB */ 646 lis r8, MI_RSV4I@h 647 ori r8, r8, 0x1c00 648 oris r12, r10, MD_RSV4I@h 649 ori r12, r12, 0x1c00 650 li r9, 4 /* up to 4 pages of 8M */ 651 mtctr r9 652 lis r9, KERNELBASE@h /* Create vaddr for TLB */ 653 li r10, MI_PS8MEG | _PMD_ACCESSED | MI_SVALID 654 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 6551: 656 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 657 addi r8, r8, 0x100 658 ori r0, r9, MI_EVALID /* Mark it valid */ 659 mtspr SPRN_MI_EPN, r0 660 mtspr SPRN_MI_TWC, r10 661 mtspr SPRN_MI_RPN, r11 /* Store TLB entry */ 662 mtspr SPRN_MD_CTR, r12 663 addi r12, r12, 0x100 664 mtspr SPRN_MD_EPN, r0 665 mtspr SPRN_MD_TWC, r10 666 mtspr SPRN_MD_RPN, r11 667 addis r9, r9, 0x80 668 addis r11, r11, 0x80 669 670 bdnz 1b 671 672 /* Since the cache is enabled according to the information we 673 * just loaded into the TLB, invalidate and enable the caches here. 674 * We should probably check/set other modes....later. 675 */ 676 lis r8, IDC_INVALL@h 677 mtspr SPRN_IC_CST, r8 678 mtspr SPRN_DC_CST, r8 679 lis r8, IDC_ENABLE@h 680 mtspr SPRN_IC_CST, r8 681 mtspr SPRN_DC_CST, r8 682 /* Disable debug mode entry on breakpoints */ 683 mfspr r8, SPRN_DER 684#ifdef CONFIG_PERF_EVENTS 685 rlwinm r8, r8, 0, ~0xc 686#else 687 rlwinm r8, r8, 0, ~0x8 688#endif 689 mtspr SPRN_DER, r8 690 blr 691SYM_FUNC_END(initial_mmu) 692 693_GLOBAL(mmu_pin_tlb) 694 lis r9, (1f - PAGE_OFFSET)@h 695 ori r9, r9, (1f - PAGE_OFFSET)@l 696 mfmsr r10 697 mflr r11 698 li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI) 699 rlwinm r0, r10, 0, ~MSR_RI 700 rlwinm r0, r0, 0, ~MSR_EE 701 mtmsr r0 702 isync 703 .align 4 704 mtspr SPRN_SRR0, r9 705 mtspr SPRN_SRR1, r12 706 rfi 7071: 708 li r5, 0 709 lis r6, MD_TWAM@h 710 mtspr SPRN_MI_CTR, r5 711 mtspr SPRN_MD_CTR, r6 712 tlbia 713 714 LOAD_REG_IMMEDIATE(r5, 28 << 8) 715 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET) 716 LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED) 717 LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT) 718 LOAD_REG_ADDR(r9, _sinittext) 719 li r0, 4 720 mtctr r0 721 7222: ori r0, r6, MI_EVALID 723 mtspr SPRN_MI_CTR, r5 724 mtspr SPRN_MI_EPN, r0 725 mtspr SPRN_MI_TWC, r7 726 mtspr SPRN_MI_RPN, r8 727 addi r5, r5, 0x100 728 addis r6, r6, SZ_8M@h 729 addis r8, r8, SZ_8M@h 730 cmplw r6, r9 731 bdnzt lt, 2b 732 lis r0, MI_RSV4I@h 733 mtspr SPRN_MI_CTR, r0 734 735 LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM) 736#ifdef CONFIG_PIN_TLB_DATA 737 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET) 738 LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED) 739 li r8, 0 740#ifdef CONFIG_PIN_TLB_IMMR 741 li r0, 3 742#else 743 li r0, 4 744#endif 745 mtctr r0 746 cmpwi r4, 0 747 beq 4f 748 LOAD_REG_ADDR(r9, _sinittext) 749 7502: ori r0, r6, MD_EVALID 751 ori r12, r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT 752 mtspr SPRN_MD_CTR, r5 753 mtspr SPRN_MD_EPN, r0 754 mtspr SPRN_MD_TWC, r7 755 mtspr SPRN_MD_RPN, r12 756 addi r5, r5, 0x100 757 addis r6, r6, SZ_8M@h 758 addis r8, r8, SZ_8M@h 759 cmplw r6, r9 760 bdnzt lt, 2b 7614: 7622: ori r0, r6, MD_EVALID 763 ori r12, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT 764 mtspr SPRN_MD_CTR, r5 765 mtspr SPRN_MD_EPN, r0 766 mtspr SPRN_MD_TWC, r7 767 mtspr SPRN_MD_RPN, r12 768 addi r5, r5, 0x100 769 addis r6, r6, SZ_8M@h 770 addis r8, r8, SZ_8M@h 771 cmplw r6, r3 772 bdnzt lt, 2b 773#endif 774#ifdef CONFIG_PIN_TLB_IMMR 775 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID) 776 LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED | _PMD_ACCESSED) 777 mfspr r8, SPRN_IMMR 778 rlwinm r8, r8, 0, 0xfff80000 779 ori r8, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \ 780 _PAGE_NO_CACHE | _PAGE_PRESENT 781 mtspr SPRN_MD_CTR, r5 782 mtspr SPRN_MD_EPN, r0 783 mtspr SPRN_MD_TWC, r7 784 mtspr SPRN_MD_RPN, r8 785#endif 786#if defined(CONFIG_PIN_TLB_IMMR) || defined(CONFIG_PIN_TLB_DATA) 787 lis r0, (MD_RSV4I | MD_TWAM)@h 788 mtspr SPRN_MD_CTR, r0 789#endif 790 mtspr SPRN_SRR1, r10 791 mtspr SPRN_SRR0, r11 792 rfi 793