1*dfc3095cSChristophe Leroy/* SPDX-License-Identifier: GPL-2.0-or-later */ 2*dfc3095cSChristophe Leroy/* 3*dfc3095cSChristophe Leroy * Kernel execution entry point code. 4*dfc3095cSChristophe Leroy * 5*dfc3095cSChristophe Leroy * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 6*dfc3095cSChristophe Leroy * Initial PowerPC version. 7*dfc3095cSChristophe Leroy * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 8*dfc3095cSChristophe Leroy * Rewritten for PReP 9*dfc3095cSChristophe Leroy * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 10*dfc3095cSChristophe Leroy * Low-level exception handers, MMU support, and rewrite. 11*dfc3095cSChristophe Leroy * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 12*dfc3095cSChristophe Leroy * PowerPC 8xx modifications. 13*dfc3095cSChristophe Leroy * Copyright (c) 1998-1999 TiVo, Inc. 14*dfc3095cSChristophe Leroy * PowerPC 403GCX modifications. 15*dfc3095cSChristophe Leroy * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 16*dfc3095cSChristophe Leroy * PowerPC 403GCX/405GP modifications. 17*dfc3095cSChristophe Leroy * Copyright 2000 MontaVista Software Inc. 18*dfc3095cSChristophe Leroy * PPC405 modifications 19*dfc3095cSChristophe Leroy * PowerPC 403GCX/405GP modifications. 20*dfc3095cSChristophe Leroy * Author: MontaVista Software, Inc. 21*dfc3095cSChristophe Leroy * frank_rowand@mvista.com or source@mvista.com 22*dfc3095cSChristophe Leroy * debbie_chu@mvista.com 23*dfc3095cSChristophe Leroy * Copyright 2002-2004 MontaVista Software, Inc. 24*dfc3095cSChristophe Leroy * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> 25*dfc3095cSChristophe Leroy * Copyright 2004 Freescale Semiconductor, Inc 26*dfc3095cSChristophe Leroy * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> 27*dfc3095cSChristophe Leroy */ 28*dfc3095cSChristophe Leroy 29*dfc3095cSChristophe Leroy#include <linux/init.h> 30*dfc3095cSChristophe Leroy#include <linux/threads.h> 31*dfc3095cSChristophe Leroy#include <linux/pgtable.h> 32*dfc3095cSChristophe Leroy#include <asm/processor.h> 33*dfc3095cSChristophe Leroy#include <asm/page.h> 34*dfc3095cSChristophe Leroy#include <asm/mmu.h> 35*dfc3095cSChristophe Leroy#include <asm/cputable.h> 36*dfc3095cSChristophe Leroy#include <asm/thread_info.h> 37*dfc3095cSChristophe Leroy#include <asm/ppc_asm.h> 38*dfc3095cSChristophe Leroy#include <asm/asm-offsets.h> 39*dfc3095cSChristophe Leroy#include <asm/cache.h> 40*dfc3095cSChristophe Leroy#include <asm/ptrace.h> 41*dfc3095cSChristophe Leroy#include <asm/export.h> 42*dfc3095cSChristophe Leroy#include <asm/feature-fixups.h> 43*dfc3095cSChristophe Leroy#include "head_booke.h" 44*dfc3095cSChristophe Leroy 45*dfc3095cSChristophe Leroy/* As with the other PowerPC ports, it is expected that when code 46*dfc3095cSChristophe Leroy * execution begins here, the following registers contain valid, yet 47*dfc3095cSChristophe Leroy * optional, information: 48*dfc3095cSChristophe Leroy * 49*dfc3095cSChristophe Leroy * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 50*dfc3095cSChristophe Leroy * r4 - Starting address of the init RAM disk 51*dfc3095cSChristophe Leroy * r5 - Ending address of the init RAM disk 52*dfc3095cSChristophe Leroy * r6 - Start of kernel command line string (e.g. "mem=128") 53*dfc3095cSChristophe Leroy * r7 - End of kernel command line string 54*dfc3095cSChristophe Leroy * 55*dfc3095cSChristophe Leroy */ 56*dfc3095cSChristophe Leroy __HEAD 57*dfc3095cSChristophe Leroy_GLOBAL(_stext); 58*dfc3095cSChristophe Leroy_GLOBAL(_start); 59*dfc3095cSChristophe Leroy /* 60*dfc3095cSChristophe Leroy * Reserve a word at a fixed location to store the address 61*dfc3095cSChristophe Leroy * of abatron_pteptrs 62*dfc3095cSChristophe Leroy */ 63*dfc3095cSChristophe Leroy nop 64*dfc3095cSChristophe Leroy 65*dfc3095cSChristophe Leroy /* Translate device tree address to physical, save in r30/r31 */ 66*dfc3095cSChristophe Leroy bl get_phys_addr 67*dfc3095cSChristophe Leroy mr r30,r3 68*dfc3095cSChristophe Leroy mr r31,r4 69*dfc3095cSChristophe Leroy 70*dfc3095cSChristophe Leroy li r25,0 /* phys kernel start (low) */ 71*dfc3095cSChristophe Leroy li r24,0 /* CPU number */ 72*dfc3095cSChristophe Leroy li r23,0 /* phys kernel start (high) */ 73*dfc3095cSChristophe Leroy 74*dfc3095cSChristophe Leroy#ifdef CONFIG_RELOCATABLE 75*dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */ 76*dfc3095cSChristophe Leroy 77*dfc3095cSChristophe Leroy /* Translate _stext address to physical, save in r23/r25 */ 78*dfc3095cSChristophe Leroy bl get_phys_addr 79*dfc3095cSChristophe Leroy mr r23,r3 80*dfc3095cSChristophe Leroy mr r25,r4 81*dfc3095cSChristophe Leroy 82*dfc3095cSChristophe Leroy bcl 20,31,$+4 83*dfc3095cSChristophe Leroy0: mflr r8 84*dfc3095cSChristophe Leroy addis r3,r8,(is_second_reloc - 0b)@ha 85*dfc3095cSChristophe Leroy lwz r19,(is_second_reloc - 0b)@l(r3) 86*dfc3095cSChristophe Leroy 87*dfc3095cSChristophe Leroy /* Check if this is the second relocation. */ 88*dfc3095cSChristophe Leroy cmpwi r19,1 89*dfc3095cSChristophe Leroy bne 1f 90*dfc3095cSChristophe Leroy 91*dfc3095cSChristophe Leroy /* 92*dfc3095cSChristophe Leroy * For the second relocation, we already get the real memstart_addr 93*dfc3095cSChristophe Leroy * from device tree. So we will map PAGE_OFFSET to memstart_addr, 94*dfc3095cSChristophe Leroy * then the virtual address of start kernel should be: 95*dfc3095cSChristophe Leroy * PAGE_OFFSET + (kernstart_addr - memstart_addr) 96*dfc3095cSChristophe Leroy * Since the offset between kernstart_addr and memstart_addr should 97*dfc3095cSChristophe Leroy * never be beyond 1G, so we can just use the lower 32bit of them 98*dfc3095cSChristophe Leroy * for the calculation. 99*dfc3095cSChristophe Leroy */ 100*dfc3095cSChristophe Leroy lis r3,PAGE_OFFSET@h 101*dfc3095cSChristophe Leroy 102*dfc3095cSChristophe Leroy addis r4,r8,(kernstart_addr - 0b)@ha 103*dfc3095cSChristophe Leroy addi r4,r4,(kernstart_addr - 0b)@l 104*dfc3095cSChristophe Leroy lwz r5,4(r4) 105*dfc3095cSChristophe Leroy 106*dfc3095cSChristophe Leroy addis r6,r8,(memstart_addr - 0b)@ha 107*dfc3095cSChristophe Leroy addi r6,r6,(memstart_addr - 0b)@l 108*dfc3095cSChristophe Leroy lwz r7,4(r6) 109*dfc3095cSChristophe Leroy 110*dfc3095cSChristophe Leroy subf r5,r7,r5 111*dfc3095cSChristophe Leroy add r3,r3,r5 112*dfc3095cSChristophe Leroy b 2f 113*dfc3095cSChristophe Leroy 114*dfc3095cSChristophe Leroy1: 115*dfc3095cSChristophe Leroy /* 116*dfc3095cSChristophe Leroy * We have the runtime (virtual) address of our base. 117*dfc3095cSChristophe Leroy * We calculate our shift of offset from a 64M page. 118*dfc3095cSChristophe Leroy * We could map the 64M page we belong to at PAGE_OFFSET and 119*dfc3095cSChristophe Leroy * get going from there. 120*dfc3095cSChristophe Leroy */ 121*dfc3095cSChristophe Leroy lis r4,KERNELBASE@h 122*dfc3095cSChristophe Leroy ori r4,r4,KERNELBASE@l 123*dfc3095cSChristophe Leroy rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */ 124*dfc3095cSChristophe Leroy rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */ 125*dfc3095cSChristophe Leroy subf r3,r5,r6 /* r3 = r6 - r5 */ 126*dfc3095cSChristophe Leroy add r3,r4,r3 /* Required Virtual Address */ 127*dfc3095cSChristophe Leroy 128*dfc3095cSChristophe Leroy2: bl relocate 129*dfc3095cSChristophe Leroy 130*dfc3095cSChristophe Leroy /* 131*dfc3095cSChristophe Leroy * For the second relocation, we already set the right tlb entries 132*dfc3095cSChristophe Leroy * for the kernel space, so skip the code in 85xx_entry_mapping.S 133*dfc3095cSChristophe Leroy */ 134*dfc3095cSChristophe Leroy cmpwi r19,1 135*dfc3095cSChristophe Leroy beq set_ivor 136*dfc3095cSChristophe Leroy#endif 137*dfc3095cSChristophe Leroy 138*dfc3095cSChristophe Leroy/* We try to not make any assumptions about how the boot loader 139*dfc3095cSChristophe Leroy * setup or used the TLBs. We invalidate all mappings from the 140*dfc3095cSChristophe Leroy * boot loader and load a single entry in TLB1[0] to map the 141*dfc3095cSChristophe Leroy * first 64M of kernel memory. Any boot info passed from the 142*dfc3095cSChristophe Leroy * bootloader needs to live in this first 64M. 143*dfc3095cSChristophe Leroy * 144*dfc3095cSChristophe Leroy * Requirement on bootloader: 145*dfc3095cSChristophe Leroy * - The page we're executing in needs to reside in TLB1 and 146*dfc3095cSChristophe Leroy * have IPROT=1. If not an invalidate broadcast could 147*dfc3095cSChristophe Leroy * evict the entry we're currently executing in. 148*dfc3095cSChristophe Leroy * 149*dfc3095cSChristophe Leroy * r3 = Index of TLB1 were executing in 150*dfc3095cSChristophe Leroy * r4 = Current MSR[IS] 151*dfc3095cSChristophe Leroy * r5 = Index of TLB1 temp mapping 152*dfc3095cSChristophe Leroy * 153*dfc3095cSChristophe Leroy * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] 154*dfc3095cSChristophe Leroy * if needed 155*dfc3095cSChristophe Leroy */ 156*dfc3095cSChristophe Leroy 157*dfc3095cSChristophe Leroy_GLOBAL(__early_start) 158*dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr) 159*dfc3095cSChristophe Leroy lwz r20,0(r20) 160*dfc3095cSChristophe Leroy 161*dfc3095cSChristophe Leroy#define ENTRY_MAPPING_BOOT_SETUP 162*dfc3095cSChristophe Leroy#include "85xx_entry_mapping.S" 163*dfc3095cSChristophe Leroy#undef ENTRY_MAPPING_BOOT_SETUP 164*dfc3095cSChristophe Leroy 165*dfc3095cSChristophe Leroyset_ivor: 166*dfc3095cSChristophe Leroy /* Establish the interrupt vector offsets */ 167*dfc3095cSChristophe Leroy SET_IVOR(0, CriticalInput); 168*dfc3095cSChristophe Leroy SET_IVOR(1, MachineCheck); 169*dfc3095cSChristophe Leroy SET_IVOR(2, DataStorage); 170*dfc3095cSChristophe Leroy SET_IVOR(3, InstructionStorage); 171*dfc3095cSChristophe Leroy SET_IVOR(4, ExternalInput); 172*dfc3095cSChristophe Leroy SET_IVOR(5, Alignment); 173*dfc3095cSChristophe Leroy SET_IVOR(6, Program); 174*dfc3095cSChristophe Leroy SET_IVOR(7, FloatingPointUnavailable); 175*dfc3095cSChristophe Leroy SET_IVOR(8, SystemCall); 176*dfc3095cSChristophe Leroy SET_IVOR(9, AuxillaryProcessorUnavailable); 177*dfc3095cSChristophe Leroy SET_IVOR(10, Decrementer); 178*dfc3095cSChristophe Leroy SET_IVOR(11, FixedIntervalTimer); 179*dfc3095cSChristophe Leroy SET_IVOR(12, WatchdogTimer); 180*dfc3095cSChristophe Leroy SET_IVOR(13, DataTLBError); 181*dfc3095cSChristophe Leroy SET_IVOR(14, InstructionTLBError); 182*dfc3095cSChristophe Leroy SET_IVOR(15, DebugCrit); 183*dfc3095cSChristophe Leroy 184*dfc3095cSChristophe Leroy /* Establish the interrupt vector base */ 185*dfc3095cSChristophe Leroy lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 186*dfc3095cSChristophe Leroy mtspr SPRN_IVPR,r4 187*dfc3095cSChristophe Leroy 188*dfc3095cSChristophe Leroy /* Setup the defaults for TLB entries */ 189*dfc3095cSChristophe Leroy li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 190*dfc3095cSChristophe Leroy mtspr SPRN_MAS4, r2 191*dfc3095cSChristophe Leroy 192*dfc3095cSChristophe Leroy#if !defined(CONFIG_BDI_SWITCH) 193*dfc3095cSChristophe Leroy /* 194*dfc3095cSChristophe Leroy * The Abatron BDI JTAG debugger does not tolerate others 195*dfc3095cSChristophe Leroy * mucking with the debug registers. 196*dfc3095cSChristophe Leroy */ 197*dfc3095cSChristophe Leroy lis r2,DBCR0_IDM@h 198*dfc3095cSChristophe Leroy mtspr SPRN_DBCR0,r2 199*dfc3095cSChristophe Leroy isync 200*dfc3095cSChristophe Leroy /* clear any residual debug events */ 201*dfc3095cSChristophe Leroy li r2,-1 202*dfc3095cSChristophe Leroy mtspr SPRN_DBSR,r2 203*dfc3095cSChristophe Leroy#endif 204*dfc3095cSChristophe Leroy 205*dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 206*dfc3095cSChristophe Leroy /* Check to see if we're the second processor, and jump 207*dfc3095cSChristophe Leroy * to the secondary_start code if so 208*dfc3095cSChristophe Leroy */ 209*dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r24, boot_cpuid) 210*dfc3095cSChristophe Leroy lwz r24, 0(r24) 211*dfc3095cSChristophe Leroy cmpwi r24, -1 212*dfc3095cSChristophe Leroy mfspr r24,SPRN_PIR 213*dfc3095cSChristophe Leroy bne __secondary_start 214*dfc3095cSChristophe Leroy#endif 215*dfc3095cSChristophe Leroy 216*dfc3095cSChristophe Leroy /* 217*dfc3095cSChristophe Leroy * This is where the main kernel code starts. 218*dfc3095cSChristophe Leroy */ 219*dfc3095cSChristophe Leroy 220*dfc3095cSChristophe Leroy /* ptr to current */ 221*dfc3095cSChristophe Leroy lis r2,init_task@h 222*dfc3095cSChristophe Leroy ori r2,r2,init_task@l 223*dfc3095cSChristophe Leroy 224*dfc3095cSChristophe Leroy /* ptr to current thread */ 225*dfc3095cSChristophe Leroy addi r4,r2,THREAD /* init task's THREAD */ 226*dfc3095cSChristophe Leroy mtspr SPRN_SPRG_THREAD,r4 227*dfc3095cSChristophe Leroy 228*dfc3095cSChristophe Leroy /* stack */ 229*dfc3095cSChristophe Leroy lis r1,init_thread_union@h 230*dfc3095cSChristophe Leroy ori r1,r1,init_thread_union@l 231*dfc3095cSChristophe Leroy li r0,0 232*dfc3095cSChristophe Leroy stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 233*dfc3095cSChristophe Leroy 234*dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 235*dfc3095cSChristophe Leroy stw r24, TASK_CPU(r2) 236*dfc3095cSChristophe Leroy#endif 237*dfc3095cSChristophe Leroy 238*dfc3095cSChristophe Leroy bl early_init 239*dfc3095cSChristophe Leroy 240*dfc3095cSChristophe Leroy#ifdef CONFIG_KASAN 241*dfc3095cSChristophe Leroy bl kasan_early_init 242*dfc3095cSChristophe Leroy#endif 243*dfc3095cSChristophe Leroy#ifdef CONFIG_RELOCATABLE 244*dfc3095cSChristophe Leroy mr r3,r30 245*dfc3095cSChristophe Leroy mr r4,r31 246*dfc3095cSChristophe Leroy#ifdef CONFIG_PHYS_64BIT 247*dfc3095cSChristophe Leroy mr r5,r23 248*dfc3095cSChristophe Leroy mr r6,r25 249*dfc3095cSChristophe Leroy#else 250*dfc3095cSChristophe Leroy mr r5,r25 251*dfc3095cSChristophe Leroy#endif 252*dfc3095cSChristophe Leroy bl relocate_init 253*dfc3095cSChristophe Leroy#endif 254*dfc3095cSChristophe Leroy 255*dfc3095cSChristophe Leroy#ifdef CONFIG_DYNAMIC_MEMSTART 256*dfc3095cSChristophe Leroy lis r3,kernstart_addr@ha 257*dfc3095cSChristophe Leroy la r3,kernstart_addr@l(r3) 258*dfc3095cSChristophe Leroy#ifdef CONFIG_PHYS_64BIT 259*dfc3095cSChristophe Leroy stw r23,0(r3) 260*dfc3095cSChristophe Leroy stw r25,4(r3) 261*dfc3095cSChristophe Leroy#else 262*dfc3095cSChristophe Leroy stw r25,0(r3) 263*dfc3095cSChristophe Leroy#endif 264*dfc3095cSChristophe Leroy#endif 265*dfc3095cSChristophe Leroy 266*dfc3095cSChristophe Leroy/* 267*dfc3095cSChristophe Leroy * Decide what sort of machine this is and initialize the MMU. 268*dfc3095cSChristophe Leroy */ 269*dfc3095cSChristophe Leroy mr r3,r30 270*dfc3095cSChristophe Leroy mr r4,r31 271*dfc3095cSChristophe Leroy bl machine_init 272*dfc3095cSChristophe Leroy bl MMU_init 273*dfc3095cSChristophe Leroy 274*dfc3095cSChristophe Leroy /* Setup PTE pointers for the Abatron bdiGDB */ 275*dfc3095cSChristophe Leroy lis r6, swapper_pg_dir@h 276*dfc3095cSChristophe Leroy ori r6, r6, swapper_pg_dir@l 277*dfc3095cSChristophe Leroy lis r5, abatron_pteptrs@h 278*dfc3095cSChristophe Leroy ori r5, r5, abatron_pteptrs@l 279*dfc3095cSChristophe Leroy lis r3, kernstart_virt_addr@ha 280*dfc3095cSChristophe Leroy lwz r4, kernstart_virt_addr@l(r3) 281*dfc3095cSChristophe Leroy stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ 282*dfc3095cSChristophe Leroy stw r6, 0(r5) 283*dfc3095cSChristophe Leroy 284*dfc3095cSChristophe Leroy /* Let's move on */ 285*dfc3095cSChristophe Leroy lis r4,start_kernel@h 286*dfc3095cSChristophe Leroy ori r4,r4,start_kernel@l 287*dfc3095cSChristophe Leroy lis r3,MSR_KERNEL@h 288*dfc3095cSChristophe Leroy ori r3,r3,MSR_KERNEL@l 289*dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r4 290*dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r3 291*dfc3095cSChristophe Leroy rfi /* change context and jump to start_kernel */ 292*dfc3095cSChristophe Leroy 293*dfc3095cSChristophe Leroy/* Macros to hide the PTE size differences 294*dfc3095cSChristophe Leroy * 295*dfc3095cSChristophe Leroy * FIND_PTE -- walks the page tables given EA & pgdir pointer 296*dfc3095cSChristophe Leroy * r10 -- EA of fault 297*dfc3095cSChristophe Leroy * r11 -- PGDIR pointer 298*dfc3095cSChristophe Leroy * r12 -- free 299*dfc3095cSChristophe Leroy * label 2: is the bailout case 300*dfc3095cSChristophe Leroy * 301*dfc3095cSChristophe Leroy * if we find the pte (fall through): 302*dfc3095cSChristophe Leroy * r11 is low pte word 303*dfc3095cSChristophe Leroy * r12 is pointer to the pte 304*dfc3095cSChristophe Leroy * r10 is the pshift from the PGD, if we're a hugepage 305*dfc3095cSChristophe Leroy */ 306*dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 307*dfc3095cSChristophe Leroy#ifdef CONFIG_HUGETLB_PAGE 308*dfc3095cSChristophe Leroy#define FIND_PTE \ 309*dfc3095cSChristophe Leroy rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ 310*dfc3095cSChristophe Leroy lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ 311*dfc3095cSChristophe Leroy rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 312*dfc3095cSChristophe Leroy blt 1000f; /* Normal non-huge page */ \ 313*dfc3095cSChristophe Leroy beq 2f; /* Bail if no table */ \ 314*dfc3095cSChristophe Leroy oris r11, r11, PD_HUGE@h; /* Put back address bit */ \ 315*dfc3095cSChristophe Leroy andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \ 316*dfc3095cSChristophe Leroy xor r12, r10, r11; /* drop size bits from pointer */ \ 317*dfc3095cSChristophe Leroy b 1001f; \ 318*dfc3095cSChristophe Leroy1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ 319*dfc3095cSChristophe Leroy li r10, 0; /* clear r10 */ \ 320*dfc3095cSChristophe Leroy1001: lwz r11, 4(r12); /* Get pte entry */ 321*dfc3095cSChristophe Leroy#else 322*dfc3095cSChristophe Leroy#define FIND_PTE \ 323*dfc3095cSChristophe Leroy rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ 324*dfc3095cSChristophe Leroy lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ 325*dfc3095cSChristophe Leroy rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 326*dfc3095cSChristophe Leroy beq 2f; /* Bail if no table */ \ 327*dfc3095cSChristophe Leroy rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ 328*dfc3095cSChristophe Leroy lwz r11, 4(r12); /* Get pte entry */ 329*dfc3095cSChristophe Leroy#endif /* HUGEPAGE */ 330*dfc3095cSChristophe Leroy#else /* !PTE_64BIT */ 331*dfc3095cSChristophe Leroy#define FIND_PTE \ 332*dfc3095cSChristophe Leroy rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ 333*dfc3095cSChristophe Leroy lwz r11, 0(r11); /* Get L1 entry */ \ 334*dfc3095cSChristophe Leroy rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ 335*dfc3095cSChristophe Leroy beq 2f; /* Bail if no table */ \ 336*dfc3095cSChristophe Leroy rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ 337*dfc3095cSChristophe Leroy lwz r11, 0(r12); /* Get Linux PTE */ 338*dfc3095cSChristophe Leroy#endif 339*dfc3095cSChristophe Leroy 340*dfc3095cSChristophe Leroy/* 341*dfc3095cSChristophe Leroy * Interrupt vector entry code 342*dfc3095cSChristophe Leroy * 343*dfc3095cSChristophe Leroy * The Book E MMUs are always on so we don't need to handle 344*dfc3095cSChristophe Leroy * interrupts in real mode as with previous PPC processors. In 345*dfc3095cSChristophe Leroy * this case we handle interrupts in the kernel virtual address 346*dfc3095cSChristophe Leroy * space. 347*dfc3095cSChristophe Leroy * 348*dfc3095cSChristophe Leroy * Interrupt vectors are dynamically placed relative to the 349*dfc3095cSChristophe Leroy * interrupt prefix as determined by the address of interrupt_base. 350*dfc3095cSChristophe Leroy * The interrupt vectors offsets are programmed using the labels 351*dfc3095cSChristophe Leroy * for each interrupt vector entry. 352*dfc3095cSChristophe Leroy * 353*dfc3095cSChristophe Leroy * Interrupt vectors must be aligned on a 16 byte boundary. 354*dfc3095cSChristophe Leroy * We align on a 32 byte cache line boundary for good measure. 355*dfc3095cSChristophe Leroy */ 356*dfc3095cSChristophe Leroy 357*dfc3095cSChristophe Leroyinterrupt_base: 358*dfc3095cSChristophe Leroy /* Critical Input Interrupt */ 359*dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) 360*dfc3095cSChristophe Leroy 361*dfc3095cSChristophe Leroy /* Machine Check Interrupt */ 362*dfc3095cSChristophe Leroy MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 363*dfc3095cSChristophe Leroy 364*dfc3095cSChristophe Leroy /* Data Storage Interrupt */ 365*dfc3095cSChristophe Leroy START_EXCEPTION(DataStorage) 366*dfc3095cSChristophe Leroy NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE) 367*dfc3095cSChristophe Leroy mfspr r5,SPRN_ESR /* Grab the ESR, save it */ 368*dfc3095cSChristophe Leroy stw r5,_ESR(r11) 369*dfc3095cSChristophe Leroy mfspr r4,SPRN_DEAR /* Grab the DEAR, save it */ 370*dfc3095cSChristophe Leroy stw r4, _DEAR(r11) 371*dfc3095cSChristophe Leroy andis. r10,r5,(ESR_ILK|ESR_DLK)@h 372*dfc3095cSChristophe Leroy bne 1f 373*dfc3095cSChristophe Leroy prepare_transfer_to_handler 374*dfc3095cSChristophe Leroy bl do_page_fault 375*dfc3095cSChristophe Leroy b interrupt_return 376*dfc3095cSChristophe Leroy1: 377*dfc3095cSChristophe Leroy prepare_transfer_to_handler 378*dfc3095cSChristophe Leroy bl CacheLockingException 379*dfc3095cSChristophe Leroy b interrupt_return 380*dfc3095cSChristophe Leroy 381*dfc3095cSChristophe Leroy /* Instruction Storage Interrupt */ 382*dfc3095cSChristophe Leroy INSTRUCTION_STORAGE_EXCEPTION 383*dfc3095cSChristophe Leroy 384*dfc3095cSChristophe Leroy /* External Input Interrupt */ 385*dfc3095cSChristophe Leroy EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ) 386*dfc3095cSChristophe Leroy 387*dfc3095cSChristophe Leroy /* Alignment Interrupt */ 388*dfc3095cSChristophe Leroy ALIGNMENT_EXCEPTION 389*dfc3095cSChristophe Leroy 390*dfc3095cSChristophe Leroy /* Program Interrupt */ 391*dfc3095cSChristophe Leroy PROGRAM_EXCEPTION 392*dfc3095cSChristophe Leroy 393*dfc3095cSChristophe Leroy /* Floating Point Unavailable Interrupt */ 394*dfc3095cSChristophe Leroy#ifdef CONFIG_PPC_FPU 395*dfc3095cSChristophe Leroy FP_UNAVAILABLE_EXCEPTION 396*dfc3095cSChristophe Leroy#else 397*dfc3095cSChristophe Leroy EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, unknown_exception) 398*dfc3095cSChristophe Leroy#endif 399*dfc3095cSChristophe Leroy 400*dfc3095cSChristophe Leroy /* System Call Interrupt */ 401*dfc3095cSChristophe Leroy START_EXCEPTION(SystemCall) 402*dfc3095cSChristophe Leroy SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1 403*dfc3095cSChristophe Leroy 404*dfc3095cSChristophe Leroy /* Auxiliary Processor Unavailable Interrupt */ 405*dfc3095cSChristophe Leroy EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, unknown_exception) 406*dfc3095cSChristophe Leroy 407*dfc3095cSChristophe Leroy /* Decrementer Interrupt */ 408*dfc3095cSChristophe Leroy DECREMENTER_EXCEPTION 409*dfc3095cSChristophe Leroy 410*dfc3095cSChristophe Leroy /* Fixed Internal Timer Interrupt */ 411*dfc3095cSChristophe Leroy /* TODO: Add FIT support */ 412*dfc3095cSChristophe Leroy EXCEPTION(0x3100, FIT, FixedIntervalTimer, unknown_exception) 413*dfc3095cSChristophe Leroy 414*dfc3095cSChristophe Leroy /* Watchdog Timer Interrupt */ 415*dfc3095cSChristophe Leroy#ifdef CONFIG_BOOKE_WDT 416*dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException) 417*dfc3095cSChristophe Leroy#else 418*dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception) 419*dfc3095cSChristophe Leroy#endif 420*dfc3095cSChristophe Leroy 421*dfc3095cSChristophe Leroy /* Data TLB Error Interrupt */ 422*dfc3095cSChristophe Leroy START_EXCEPTION(DataTLBError) 423*dfc3095cSChristophe Leroy mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 424*dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 425*dfc3095cSChristophe Leroy stw r11, THREAD_NORMSAVE(0)(r10) 426*dfc3095cSChristophe Leroy#ifdef CONFIG_KVM_BOOKE_HV 427*dfc3095cSChristophe LeroyBEGIN_FTR_SECTION 428*dfc3095cSChristophe Leroy mfspr r11, SPRN_SRR1 429*dfc3095cSChristophe LeroyEND_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 430*dfc3095cSChristophe Leroy#endif 431*dfc3095cSChristophe Leroy stw r12, THREAD_NORMSAVE(1)(r10) 432*dfc3095cSChristophe Leroy stw r13, THREAD_NORMSAVE(2)(r10) 433*dfc3095cSChristophe Leroy mfcr r13 434*dfc3095cSChristophe Leroy stw r13, THREAD_NORMSAVE(3)(r10) 435*dfc3095cSChristophe Leroy DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 436*dfc3095cSChristophe LeroySTART_BTB_FLUSH_SECTION 437*dfc3095cSChristophe Leroy mfspr r11, SPRN_SRR1 438*dfc3095cSChristophe Leroy andi. r10,r11,MSR_PR 439*dfc3095cSChristophe Leroy beq 1f 440*dfc3095cSChristophe Leroy BTB_FLUSH(r10) 441*dfc3095cSChristophe Leroy1: 442*dfc3095cSChristophe LeroyEND_BTB_FLUSH_SECTION 443*dfc3095cSChristophe Leroy mfspr r10, SPRN_DEAR /* Get faulting address */ 444*dfc3095cSChristophe Leroy 445*dfc3095cSChristophe Leroy /* If we are faulting a kernel address, we have to use the 446*dfc3095cSChristophe Leroy * kernel page tables. 447*dfc3095cSChristophe Leroy */ 448*dfc3095cSChristophe Leroy lis r11, PAGE_OFFSET@h 449*dfc3095cSChristophe Leroy cmplw 5, r10, r11 450*dfc3095cSChristophe Leroy blt 5, 3f 451*dfc3095cSChristophe Leroy lis r11, swapper_pg_dir@h 452*dfc3095cSChristophe Leroy ori r11, r11, swapper_pg_dir@l 453*dfc3095cSChristophe Leroy 454*dfc3095cSChristophe Leroy mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 455*dfc3095cSChristophe Leroy rlwinm r12,r12,0,16,1 456*dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r12 457*dfc3095cSChristophe Leroy 458*dfc3095cSChristophe Leroy b 4f 459*dfc3095cSChristophe Leroy 460*dfc3095cSChristophe Leroy /* Get the PGD for the current thread */ 461*dfc3095cSChristophe Leroy3: 462*dfc3095cSChristophe Leroy mfspr r11,SPRN_SPRG_THREAD 463*dfc3095cSChristophe Leroy lwz r11,PGDIR(r11) 464*dfc3095cSChristophe Leroy 465*dfc3095cSChristophe Leroy#ifdef CONFIG_PPC_KUAP 466*dfc3095cSChristophe Leroy mfspr r12, SPRN_MAS1 467*dfc3095cSChristophe Leroy rlwinm. r12,r12,0,0x3fff0000 468*dfc3095cSChristophe Leroy beq 2f /* KUAP fault */ 469*dfc3095cSChristophe Leroy#endif 470*dfc3095cSChristophe Leroy 471*dfc3095cSChristophe Leroy4: 472*dfc3095cSChristophe Leroy /* Mask of required permission bits. Note that while we 473*dfc3095cSChristophe Leroy * do copy ESR:ST to _PAGE_RW position as trying to write 474*dfc3095cSChristophe Leroy * to an RO page is pretty common, we don't do it with 475*dfc3095cSChristophe Leroy * _PAGE_DIRTY. We could do it, but it's a fairly rare 476*dfc3095cSChristophe Leroy * event so I'd rather take the overhead when it happens 477*dfc3095cSChristophe Leroy * rather than adding an instruction here. We should measure 478*dfc3095cSChristophe Leroy * whether the whole thing is worth it in the first place 479*dfc3095cSChristophe Leroy * as we could avoid loading SPRN_ESR completely in the first 480*dfc3095cSChristophe Leroy * place... 481*dfc3095cSChristophe Leroy * 482*dfc3095cSChristophe Leroy * TODO: Is it worth doing that mfspr & rlwimi in the first 483*dfc3095cSChristophe Leroy * place or can we save a couple of instructions here ? 484*dfc3095cSChristophe Leroy */ 485*dfc3095cSChristophe Leroy mfspr r12,SPRN_ESR 486*dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 487*dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT 488*dfc3095cSChristophe Leroy oris r13,r13,_PAGE_ACCESSED@h 489*dfc3095cSChristophe Leroy#else 490*dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT|_PAGE_ACCESSED 491*dfc3095cSChristophe Leroy#endif 492*dfc3095cSChristophe Leroy rlwimi r13,r12,11,29,29 493*dfc3095cSChristophe Leroy 494*dfc3095cSChristophe Leroy FIND_PTE 495*dfc3095cSChristophe Leroy andc. r13,r13,r11 /* Check permission */ 496*dfc3095cSChristophe Leroy 497*dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 498*dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 499*dfc3095cSChristophe Leroy subf r13,r11,r12 /* create false data dep */ 500*dfc3095cSChristophe Leroy lwzx r13,r11,r13 /* Get upper pte bits */ 501*dfc3095cSChristophe Leroy#else 502*dfc3095cSChristophe Leroy lwz r13,0(r12) /* Get upper pte bits */ 503*dfc3095cSChristophe Leroy#endif 504*dfc3095cSChristophe Leroy#endif 505*dfc3095cSChristophe Leroy 506*dfc3095cSChristophe Leroy bne 2f /* Bail if permission/valid mismatch */ 507*dfc3095cSChristophe Leroy 508*dfc3095cSChristophe Leroy /* Jump to common tlb load */ 509*dfc3095cSChristophe Leroy b finish_tlb_load 510*dfc3095cSChristophe Leroy2: 511*dfc3095cSChristophe Leroy /* The bailout. Restore registers to pre-exception conditions 512*dfc3095cSChristophe Leroy * and call the heavyweights to help us out. 513*dfc3095cSChristophe Leroy */ 514*dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 515*dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(3)(r10) 516*dfc3095cSChristophe Leroy mtcr r11 517*dfc3095cSChristophe Leroy lwz r13, THREAD_NORMSAVE(2)(r10) 518*dfc3095cSChristophe Leroy lwz r12, THREAD_NORMSAVE(1)(r10) 519*dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(0)(r10) 520*dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_RSCRATCH0 521*dfc3095cSChristophe Leroy b DataStorage 522*dfc3095cSChristophe Leroy 523*dfc3095cSChristophe Leroy /* Instruction TLB Error Interrupt */ 524*dfc3095cSChristophe Leroy /* 525*dfc3095cSChristophe Leroy * Nearly the same as above, except we get our 526*dfc3095cSChristophe Leroy * information from different registers and bailout 527*dfc3095cSChristophe Leroy * to a different point. 528*dfc3095cSChristophe Leroy */ 529*dfc3095cSChristophe Leroy START_EXCEPTION(InstructionTLBError) 530*dfc3095cSChristophe Leroy mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 531*dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 532*dfc3095cSChristophe Leroy stw r11, THREAD_NORMSAVE(0)(r10) 533*dfc3095cSChristophe Leroy#ifdef CONFIG_KVM_BOOKE_HV 534*dfc3095cSChristophe LeroyBEGIN_FTR_SECTION 535*dfc3095cSChristophe Leroy mfspr r11, SPRN_SRR1 536*dfc3095cSChristophe LeroyEND_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 537*dfc3095cSChristophe Leroy#endif 538*dfc3095cSChristophe Leroy stw r12, THREAD_NORMSAVE(1)(r10) 539*dfc3095cSChristophe Leroy stw r13, THREAD_NORMSAVE(2)(r10) 540*dfc3095cSChristophe Leroy mfcr r13 541*dfc3095cSChristophe Leroy stw r13, THREAD_NORMSAVE(3)(r10) 542*dfc3095cSChristophe Leroy DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 543*dfc3095cSChristophe LeroySTART_BTB_FLUSH_SECTION 544*dfc3095cSChristophe Leroy mfspr r11, SPRN_SRR1 545*dfc3095cSChristophe Leroy andi. r10,r11,MSR_PR 546*dfc3095cSChristophe Leroy beq 1f 547*dfc3095cSChristophe Leroy BTB_FLUSH(r10) 548*dfc3095cSChristophe Leroy1: 549*dfc3095cSChristophe LeroyEND_BTB_FLUSH_SECTION 550*dfc3095cSChristophe Leroy 551*dfc3095cSChristophe Leroy mfspr r10, SPRN_SRR0 /* Get faulting address */ 552*dfc3095cSChristophe Leroy 553*dfc3095cSChristophe Leroy /* If we are faulting a kernel address, we have to use the 554*dfc3095cSChristophe Leroy * kernel page tables. 555*dfc3095cSChristophe Leroy */ 556*dfc3095cSChristophe Leroy lis r11, PAGE_OFFSET@h 557*dfc3095cSChristophe Leroy cmplw 5, r10, r11 558*dfc3095cSChristophe Leroy blt 5, 3f 559*dfc3095cSChristophe Leroy lis r11, swapper_pg_dir@h 560*dfc3095cSChristophe Leroy ori r11, r11, swapper_pg_dir@l 561*dfc3095cSChristophe Leroy 562*dfc3095cSChristophe Leroy mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 563*dfc3095cSChristophe Leroy rlwinm r12,r12,0,16,1 564*dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r12 565*dfc3095cSChristophe Leroy 566*dfc3095cSChristophe Leroy /* Make up the required permissions for kernel code */ 567*dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 568*dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT | _PAGE_BAP_SX 569*dfc3095cSChristophe Leroy oris r13,r13,_PAGE_ACCESSED@h 570*dfc3095cSChristophe Leroy#else 571*dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 572*dfc3095cSChristophe Leroy#endif 573*dfc3095cSChristophe Leroy b 4f 574*dfc3095cSChristophe Leroy 575*dfc3095cSChristophe Leroy /* Get the PGD for the current thread */ 576*dfc3095cSChristophe Leroy3: 577*dfc3095cSChristophe Leroy mfspr r11,SPRN_SPRG_THREAD 578*dfc3095cSChristophe Leroy lwz r11,PGDIR(r11) 579*dfc3095cSChristophe Leroy 580*dfc3095cSChristophe Leroy#ifdef CONFIG_PPC_KUAP 581*dfc3095cSChristophe Leroy mfspr r12, SPRN_MAS1 582*dfc3095cSChristophe Leroy rlwinm. r12,r12,0,0x3fff0000 583*dfc3095cSChristophe Leroy beq 2f /* KUAP fault */ 584*dfc3095cSChristophe Leroy#endif 585*dfc3095cSChristophe Leroy 586*dfc3095cSChristophe Leroy /* Make up the required permissions for user code */ 587*dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 588*dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT | _PAGE_BAP_UX 589*dfc3095cSChristophe Leroy oris r13,r13,_PAGE_ACCESSED@h 590*dfc3095cSChristophe Leroy#else 591*dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 592*dfc3095cSChristophe Leroy#endif 593*dfc3095cSChristophe Leroy 594*dfc3095cSChristophe Leroy4: 595*dfc3095cSChristophe Leroy FIND_PTE 596*dfc3095cSChristophe Leroy andc. r13,r13,r11 /* Check permission */ 597*dfc3095cSChristophe Leroy 598*dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 599*dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 600*dfc3095cSChristophe Leroy subf r13,r11,r12 /* create false data dep */ 601*dfc3095cSChristophe Leroy lwzx r13,r11,r13 /* Get upper pte bits */ 602*dfc3095cSChristophe Leroy#else 603*dfc3095cSChristophe Leroy lwz r13,0(r12) /* Get upper pte bits */ 604*dfc3095cSChristophe Leroy#endif 605*dfc3095cSChristophe Leroy#endif 606*dfc3095cSChristophe Leroy 607*dfc3095cSChristophe Leroy bne 2f /* Bail if permission mismatch */ 608*dfc3095cSChristophe Leroy 609*dfc3095cSChristophe Leroy /* Jump to common TLB load point */ 610*dfc3095cSChristophe Leroy b finish_tlb_load 611*dfc3095cSChristophe Leroy 612*dfc3095cSChristophe Leroy2: 613*dfc3095cSChristophe Leroy /* The bailout. Restore registers to pre-exception conditions 614*dfc3095cSChristophe Leroy * and call the heavyweights to help us out. 615*dfc3095cSChristophe Leroy */ 616*dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 617*dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(3)(r10) 618*dfc3095cSChristophe Leroy mtcr r11 619*dfc3095cSChristophe Leroy lwz r13, THREAD_NORMSAVE(2)(r10) 620*dfc3095cSChristophe Leroy lwz r12, THREAD_NORMSAVE(1)(r10) 621*dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(0)(r10) 622*dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_RSCRATCH0 623*dfc3095cSChristophe Leroy b InstructionStorage 624*dfc3095cSChristophe Leroy 625*dfc3095cSChristophe Leroy/* Define SPE handlers for e500v2 */ 626*dfc3095cSChristophe Leroy#ifdef CONFIG_SPE 627*dfc3095cSChristophe Leroy /* SPE Unavailable */ 628*dfc3095cSChristophe Leroy START_EXCEPTION(SPEUnavailable) 629*dfc3095cSChristophe Leroy NORMAL_EXCEPTION_PROLOG(0x2010, SPE_UNAVAIL) 630*dfc3095cSChristophe Leroy beq 1f 631*dfc3095cSChristophe Leroy bl load_up_spe 632*dfc3095cSChristophe Leroy b fast_exception_return 633*dfc3095cSChristophe Leroy1: prepare_transfer_to_handler 634*dfc3095cSChristophe Leroy bl KernelSPE 635*dfc3095cSChristophe Leroy b interrupt_return 636*dfc3095cSChristophe Leroy#elif defined(CONFIG_SPE_POSSIBLE) 637*dfc3095cSChristophe Leroy EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, unknown_exception) 638*dfc3095cSChristophe Leroy#endif /* CONFIG_SPE_POSSIBLE */ 639*dfc3095cSChristophe Leroy 640*dfc3095cSChristophe Leroy /* SPE Floating Point Data */ 641*dfc3095cSChristophe Leroy#ifdef CONFIG_SPE 642*dfc3095cSChristophe Leroy START_EXCEPTION(SPEFloatingPointData) 643*dfc3095cSChristophe Leroy NORMAL_EXCEPTION_PROLOG(0x2030, SPE_FP_DATA) 644*dfc3095cSChristophe Leroy prepare_transfer_to_handler 645*dfc3095cSChristophe Leroy bl SPEFloatingPointException 646*dfc3095cSChristophe Leroy REST_NVGPRS(r1) 647*dfc3095cSChristophe Leroy b interrupt_return 648*dfc3095cSChristophe Leroy 649*dfc3095cSChristophe Leroy /* SPE Floating Point Round */ 650*dfc3095cSChristophe Leroy START_EXCEPTION(SPEFloatingPointRound) 651*dfc3095cSChristophe Leroy NORMAL_EXCEPTION_PROLOG(0x2050, SPE_FP_ROUND) 652*dfc3095cSChristophe Leroy prepare_transfer_to_handler 653*dfc3095cSChristophe Leroy bl SPEFloatingPointRoundException 654*dfc3095cSChristophe Leroy REST_NVGPRS(r1) 655*dfc3095cSChristophe Leroy b interrupt_return 656*dfc3095cSChristophe Leroy#elif defined(CONFIG_SPE_POSSIBLE) 657*dfc3095cSChristophe Leroy EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, unknown_exception) 658*dfc3095cSChristophe Leroy EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, unknown_exception) 659*dfc3095cSChristophe Leroy#endif /* CONFIG_SPE_POSSIBLE */ 660*dfc3095cSChristophe Leroy 661*dfc3095cSChristophe Leroy 662*dfc3095cSChristophe Leroy /* Performance Monitor */ 663*dfc3095cSChristophe Leroy EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \ 664*dfc3095cSChristophe Leroy performance_monitor_exception) 665*dfc3095cSChristophe Leroy 666*dfc3095cSChristophe Leroy EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception) 667*dfc3095cSChristophe Leroy 668*dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \ 669*dfc3095cSChristophe Leroy CriticalDoorbell, unknown_exception) 670*dfc3095cSChristophe Leroy 671*dfc3095cSChristophe Leroy /* Debug Interrupt */ 672*dfc3095cSChristophe Leroy DEBUG_DEBUG_EXCEPTION 673*dfc3095cSChristophe Leroy DEBUG_CRIT_EXCEPTION 674*dfc3095cSChristophe Leroy 675*dfc3095cSChristophe Leroy GUEST_DOORBELL_EXCEPTION 676*dfc3095cSChristophe Leroy 677*dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \ 678*dfc3095cSChristophe Leroy unknown_exception) 679*dfc3095cSChristophe Leroy 680*dfc3095cSChristophe Leroy /* Hypercall */ 681*dfc3095cSChristophe Leroy EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception) 682*dfc3095cSChristophe Leroy 683*dfc3095cSChristophe Leroy /* Embedded Hypervisor Privilege */ 684*dfc3095cSChristophe Leroy EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception) 685*dfc3095cSChristophe Leroy 686*dfc3095cSChristophe Leroyinterrupt_end: 687*dfc3095cSChristophe Leroy 688*dfc3095cSChristophe Leroy/* 689*dfc3095cSChristophe Leroy * Local functions 690*dfc3095cSChristophe Leroy */ 691*dfc3095cSChristophe Leroy 692*dfc3095cSChristophe Leroy/* 693*dfc3095cSChristophe Leroy * Both the instruction and data TLB miss get to this 694*dfc3095cSChristophe Leroy * point to load the TLB. 695*dfc3095cSChristophe Leroy * r10 - tsize encoding (if HUGETLB_PAGE) or available to use 696*dfc3095cSChristophe Leroy * r11 - TLB (info from Linux PTE) 697*dfc3095cSChristophe Leroy * r12 - available to use 698*dfc3095cSChristophe Leroy * r13 - upper bits of PTE (if PTE_64BIT) or available to use 699*dfc3095cSChristophe Leroy * CR5 - results of addr >= PAGE_OFFSET 700*dfc3095cSChristophe Leroy * MAS0, MAS1 - loaded with proper value when we get here 701*dfc3095cSChristophe Leroy * MAS2, MAS3 - will need additional info from Linux PTE 702*dfc3095cSChristophe Leroy * Upon exit, we reload everything and RFI. 703*dfc3095cSChristophe Leroy */ 704*dfc3095cSChristophe Leroyfinish_tlb_load: 705*dfc3095cSChristophe Leroy#ifdef CONFIG_HUGETLB_PAGE 706*dfc3095cSChristophe Leroy cmpwi 6, r10, 0 /* check for huge page */ 707*dfc3095cSChristophe Leroy beq 6, finish_tlb_load_cont /* !huge */ 708*dfc3095cSChristophe Leroy 709*dfc3095cSChristophe Leroy /* Alas, we need more scratch registers for hugepages */ 710*dfc3095cSChristophe Leroy mfspr r12, SPRN_SPRG_THREAD 711*dfc3095cSChristophe Leroy stw r14, THREAD_NORMSAVE(4)(r12) 712*dfc3095cSChristophe Leroy stw r15, THREAD_NORMSAVE(5)(r12) 713*dfc3095cSChristophe Leroy stw r16, THREAD_NORMSAVE(6)(r12) 714*dfc3095cSChristophe Leroy stw r17, THREAD_NORMSAVE(7)(r12) 715*dfc3095cSChristophe Leroy 716*dfc3095cSChristophe Leroy /* Get the next_tlbcam_idx percpu var */ 717*dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 718*dfc3095cSChristophe Leroy lwz r15, TASK_CPU-THREAD(r12) 719*dfc3095cSChristophe Leroy lis r14, __per_cpu_offset@h 720*dfc3095cSChristophe Leroy ori r14, r14, __per_cpu_offset@l 721*dfc3095cSChristophe Leroy rlwinm r15, r15, 2, 0, 29 722*dfc3095cSChristophe Leroy lwzx r16, r14, r15 723*dfc3095cSChristophe Leroy#else 724*dfc3095cSChristophe Leroy li r16, 0 725*dfc3095cSChristophe Leroy#endif 726*dfc3095cSChristophe Leroy lis r17, next_tlbcam_idx@h 727*dfc3095cSChristophe Leroy ori r17, r17, next_tlbcam_idx@l 728*dfc3095cSChristophe Leroy add r17, r17, r16 /* r17 = *next_tlbcam_idx */ 729*dfc3095cSChristophe Leroy lwz r15, 0(r17) /* r15 = next_tlbcam_idx */ 730*dfc3095cSChristophe Leroy 731*dfc3095cSChristophe Leroy lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */ 732*dfc3095cSChristophe Leroy rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */ 733*dfc3095cSChristophe Leroy mtspr SPRN_MAS0, r14 734*dfc3095cSChristophe Leroy 735*dfc3095cSChristophe Leroy /* Extract TLB1CFG(NENTRY) */ 736*dfc3095cSChristophe Leroy mfspr r16, SPRN_TLB1CFG 737*dfc3095cSChristophe Leroy andi. r16, r16, 0xfff 738*dfc3095cSChristophe Leroy 739*dfc3095cSChristophe Leroy /* Update next_tlbcam_idx, wrapping when necessary */ 740*dfc3095cSChristophe Leroy addi r15, r15, 1 741*dfc3095cSChristophe Leroy cmpw r15, r16 742*dfc3095cSChristophe Leroy blt 100f 743*dfc3095cSChristophe Leroy lis r14, tlbcam_index@h 744*dfc3095cSChristophe Leroy ori r14, r14, tlbcam_index@l 745*dfc3095cSChristophe Leroy lwz r15, 0(r14) 746*dfc3095cSChristophe Leroy100: stw r15, 0(r17) 747*dfc3095cSChristophe Leroy 748*dfc3095cSChristophe Leroy /* 749*dfc3095cSChristophe Leroy * Calc MAS1_TSIZE from r10 (which has pshift encoded) 750*dfc3095cSChristophe Leroy * tlb_enc = (pshift - 10). 751*dfc3095cSChristophe Leroy */ 752*dfc3095cSChristophe Leroy subi r15, r10, 10 753*dfc3095cSChristophe Leroy mfspr r16, SPRN_MAS1 754*dfc3095cSChristophe Leroy rlwimi r16, r15, 7, 20, 24 755*dfc3095cSChristophe Leroy mtspr SPRN_MAS1, r16 756*dfc3095cSChristophe Leroy 757*dfc3095cSChristophe Leroy /* copy the pshift for use later */ 758*dfc3095cSChristophe Leroy mr r14, r10 759*dfc3095cSChristophe Leroy 760*dfc3095cSChristophe Leroy /* fall through */ 761*dfc3095cSChristophe Leroy 762*dfc3095cSChristophe Leroy#endif /* CONFIG_HUGETLB_PAGE */ 763*dfc3095cSChristophe Leroy 764*dfc3095cSChristophe Leroy /* 765*dfc3095cSChristophe Leroy * We set execute, because we don't have the granularity to 766*dfc3095cSChristophe Leroy * properly set this at the page level (Linux problem). 767*dfc3095cSChristophe Leroy * Many of these bits are software only. Bits we don't set 768*dfc3095cSChristophe Leroy * here we (properly should) assume have the appropriate value. 769*dfc3095cSChristophe Leroy */ 770*dfc3095cSChristophe Leroyfinish_tlb_load_cont: 771*dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 772*dfc3095cSChristophe Leroy rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ 773*dfc3095cSChristophe Leroy andi. r10, r11, _PAGE_DIRTY 774*dfc3095cSChristophe Leroy bne 1f 775*dfc3095cSChristophe Leroy li r10, MAS3_SW | MAS3_UW 776*dfc3095cSChristophe Leroy andc r12, r12, r10 777*dfc3095cSChristophe Leroy1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ 778*dfc3095cSChristophe Leroy rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ 779*dfc3095cSChristophe Leroy2: mtspr SPRN_MAS3, r12 780*dfc3095cSChristophe LeroyBEGIN_MMU_FTR_SECTION 781*dfc3095cSChristophe Leroy srwi r10, r13, 12 /* grab RPN[12:31] */ 782*dfc3095cSChristophe Leroy mtspr SPRN_MAS7, r10 783*dfc3095cSChristophe LeroyEND_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) 784*dfc3095cSChristophe Leroy#else 785*dfc3095cSChristophe Leroy li r10, (_PAGE_EXEC | _PAGE_PRESENT) 786*dfc3095cSChristophe Leroy mr r13, r11 787*dfc3095cSChristophe Leroy rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ 788*dfc3095cSChristophe Leroy and r12, r11, r10 789*dfc3095cSChristophe Leroy andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ 790*dfc3095cSChristophe Leroy slwi r10, r12, 1 791*dfc3095cSChristophe Leroy or r10, r10, r12 792*dfc3095cSChristophe Leroy rlwinm r10, r10, 0, ~_PAGE_EXEC /* Clear SX on user pages */ 793*dfc3095cSChristophe Leroy iseleq r12, r12, r10 794*dfc3095cSChristophe Leroy rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */ 795*dfc3095cSChristophe Leroy mtspr SPRN_MAS3, r13 796*dfc3095cSChristophe Leroy#endif 797*dfc3095cSChristophe Leroy 798*dfc3095cSChristophe Leroy mfspr r12, SPRN_MAS2 799*dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 800*dfc3095cSChristophe Leroy rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ 801*dfc3095cSChristophe Leroy#else 802*dfc3095cSChristophe Leroy rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ 803*dfc3095cSChristophe Leroy#endif 804*dfc3095cSChristophe Leroy#ifdef CONFIG_HUGETLB_PAGE 805*dfc3095cSChristophe Leroy beq 6, 3f /* don't mask if page isn't huge */ 806*dfc3095cSChristophe Leroy li r13, 1 807*dfc3095cSChristophe Leroy slw r13, r13, r14 808*dfc3095cSChristophe Leroy subi r13, r13, 1 809*dfc3095cSChristophe Leroy rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */ 810*dfc3095cSChristophe Leroy andc r12, r12, r13 /* mask off ea bits within the page */ 811*dfc3095cSChristophe Leroy#endif 812*dfc3095cSChristophe Leroy3: mtspr SPRN_MAS2, r12 813*dfc3095cSChristophe Leroy 814*dfc3095cSChristophe Leroytlb_write_entry: 815*dfc3095cSChristophe Leroy tlbwe 816*dfc3095cSChristophe Leroy 817*dfc3095cSChristophe Leroy /* Done...restore registers and get out of here. */ 818*dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 819*dfc3095cSChristophe Leroy#ifdef CONFIG_HUGETLB_PAGE 820*dfc3095cSChristophe Leroy beq 6, 8f /* skip restore for 4k page faults */ 821*dfc3095cSChristophe Leroy lwz r14, THREAD_NORMSAVE(4)(r10) 822*dfc3095cSChristophe Leroy lwz r15, THREAD_NORMSAVE(5)(r10) 823*dfc3095cSChristophe Leroy lwz r16, THREAD_NORMSAVE(6)(r10) 824*dfc3095cSChristophe Leroy lwz r17, THREAD_NORMSAVE(7)(r10) 825*dfc3095cSChristophe Leroy#endif 826*dfc3095cSChristophe Leroy8: lwz r11, THREAD_NORMSAVE(3)(r10) 827*dfc3095cSChristophe Leroy mtcr r11 828*dfc3095cSChristophe Leroy lwz r13, THREAD_NORMSAVE(2)(r10) 829*dfc3095cSChristophe Leroy lwz r12, THREAD_NORMSAVE(1)(r10) 830*dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(0)(r10) 831*dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_RSCRATCH0 832*dfc3095cSChristophe Leroy rfi /* Force context change */ 833*dfc3095cSChristophe Leroy 834*dfc3095cSChristophe Leroy#ifdef CONFIG_SPE 835*dfc3095cSChristophe Leroy/* Note that the SPE support is closely modeled after the AltiVec 836*dfc3095cSChristophe Leroy * support. Changes to one are likely to be applicable to the 837*dfc3095cSChristophe Leroy * other! */ 838*dfc3095cSChristophe Leroy_GLOBAL(load_up_spe) 839*dfc3095cSChristophe Leroy/* 840*dfc3095cSChristophe Leroy * Disable SPE for the task which had SPE previously, 841*dfc3095cSChristophe Leroy * and save its SPE registers in its thread_struct. 842*dfc3095cSChristophe Leroy * Enables SPE for use in the kernel on return. 843*dfc3095cSChristophe Leroy * On SMP we know the SPE units are free, since we give it up every 844*dfc3095cSChristophe Leroy * switch. -- Kumar 845*dfc3095cSChristophe Leroy */ 846*dfc3095cSChristophe Leroy mfmsr r5 847*dfc3095cSChristophe Leroy oris r5,r5,MSR_SPE@h 848*dfc3095cSChristophe Leroy mtmsr r5 /* enable use of SPE now */ 849*dfc3095cSChristophe Leroy isync 850*dfc3095cSChristophe Leroy /* enable use of SPE after return */ 851*dfc3095cSChristophe Leroy oris r9,r9,MSR_SPE@h 852*dfc3095cSChristophe Leroy mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 853*dfc3095cSChristophe Leroy li r4,1 854*dfc3095cSChristophe Leroy li r10,THREAD_ACC 855*dfc3095cSChristophe Leroy stw r4,THREAD_USED_SPE(r5) 856*dfc3095cSChristophe Leroy evlddx evr4,r10,r5 857*dfc3095cSChristophe Leroy evmra evr4,evr4 858*dfc3095cSChristophe Leroy REST_32EVRS(0,r10,r5,THREAD_EVR0) 859*dfc3095cSChristophe Leroy blr 860*dfc3095cSChristophe Leroy 861*dfc3095cSChristophe Leroy/* 862*dfc3095cSChristophe Leroy * SPE unavailable trap from kernel - print a message, but let 863*dfc3095cSChristophe Leroy * the task use SPE in the kernel until it returns to user mode. 864*dfc3095cSChristophe Leroy */ 865*dfc3095cSChristophe LeroyKernelSPE: 866*dfc3095cSChristophe Leroy lwz r3,_MSR(r1) 867*dfc3095cSChristophe Leroy oris r3,r3,MSR_SPE@h 868*dfc3095cSChristophe Leroy stw r3,_MSR(r1) /* enable use of SPE after return */ 869*dfc3095cSChristophe Leroy#ifdef CONFIG_PRINTK 870*dfc3095cSChristophe Leroy lis r3,87f@h 871*dfc3095cSChristophe Leroy ori r3,r3,87f@l 872*dfc3095cSChristophe Leroy mr r4,r2 /* current */ 873*dfc3095cSChristophe Leroy lwz r5,_NIP(r1) 874*dfc3095cSChristophe Leroy bl _printk 875*dfc3095cSChristophe Leroy#endif 876*dfc3095cSChristophe Leroy b interrupt_return 877*dfc3095cSChristophe Leroy#ifdef CONFIG_PRINTK 878*dfc3095cSChristophe Leroy87: .string "SPE used in kernel (task=%p, pc=%x) \n" 879*dfc3095cSChristophe Leroy#endif 880*dfc3095cSChristophe Leroy .align 4,0 881*dfc3095cSChristophe Leroy 882*dfc3095cSChristophe Leroy#endif /* CONFIG_SPE */ 883*dfc3095cSChristophe Leroy 884*dfc3095cSChristophe Leroy/* 885*dfc3095cSChristophe Leroy * Translate the effec addr in r3 to phys addr. The phys addr will be put 886*dfc3095cSChristophe Leroy * into r3(higher 32bit) and r4(lower 32bit) 887*dfc3095cSChristophe Leroy */ 888*dfc3095cSChristophe Leroyget_phys_addr: 889*dfc3095cSChristophe Leroy mfmsr r8 890*dfc3095cSChristophe Leroy mfspr r9,SPRN_PID 891*dfc3095cSChristophe Leroy rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 892*dfc3095cSChristophe Leroy rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */ 893*dfc3095cSChristophe Leroy mtspr SPRN_MAS6,r9 894*dfc3095cSChristophe Leroy 895*dfc3095cSChristophe Leroy tlbsx 0,r3 /* must succeed */ 896*dfc3095cSChristophe Leroy 897*dfc3095cSChristophe Leroy mfspr r8,SPRN_MAS1 898*dfc3095cSChristophe Leroy mfspr r12,SPRN_MAS3 899*dfc3095cSChristophe Leroy rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */ 900*dfc3095cSChristophe Leroy li r10,1024 901*dfc3095cSChristophe Leroy slw r10,r10,r9 /* r10 = page size */ 902*dfc3095cSChristophe Leroy addi r10,r10,-1 903*dfc3095cSChristophe Leroy and r11,r3,r10 /* r11 = page offset */ 904*dfc3095cSChristophe Leroy andc r4,r12,r10 /* r4 = page base */ 905*dfc3095cSChristophe Leroy or r4,r4,r11 /* r4 = devtree phys addr */ 906*dfc3095cSChristophe Leroy#ifdef CONFIG_PHYS_64BIT 907*dfc3095cSChristophe Leroy mfspr r3,SPRN_MAS7 908*dfc3095cSChristophe Leroy#endif 909*dfc3095cSChristophe Leroy blr 910*dfc3095cSChristophe Leroy 911*dfc3095cSChristophe Leroy/* 912*dfc3095cSChristophe Leroy * Global functions 913*dfc3095cSChristophe Leroy */ 914*dfc3095cSChristophe Leroy 915*dfc3095cSChristophe Leroy#ifdef CONFIG_E500 916*dfc3095cSChristophe Leroy#ifndef CONFIG_PPC_E500MC 917*dfc3095cSChristophe Leroy/* Adjust or setup IVORs for e500v1/v2 */ 918*dfc3095cSChristophe Leroy_GLOBAL(__setup_e500_ivors) 919*dfc3095cSChristophe Leroy li r3,DebugCrit@l 920*dfc3095cSChristophe Leroy mtspr SPRN_IVOR15,r3 921*dfc3095cSChristophe Leroy li r3,SPEUnavailable@l 922*dfc3095cSChristophe Leroy mtspr SPRN_IVOR32,r3 923*dfc3095cSChristophe Leroy li r3,SPEFloatingPointData@l 924*dfc3095cSChristophe Leroy mtspr SPRN_IVOR33,r3 925*dfc3095cSChristophe Leroy li r3,SPEFloatingPointRound@l 926*dfc3095cSChristophe Leroy mtspr SPRN_IVOR34,r3 927*dfc3095cSChristophe Leroy li r3,PerformanceMonitor@l 928*dfc3095cSChristophe Leroy mtspr SPRN_IVOR35,r3 929*dfc3095cSChristophe Leroy sync 930*dfc3095cSChristophe Leroy blr 931*dfc3095cSChristophe Leroy#else 932*dfc3095cSChristophe Leroy/* Adjust or setup IVORs for e500mc */ 933*dfc3095cSChristophe Leroy_GLOBAL(__setup_e500mc_ivors) 934*dfc3095cSChristophe Leroy li r3,DebugDebug@l 935*dfc3095cSChristophe Leroy mtspr SPRN_IVOR15,r3 936*dfc3095cSChristophe Leroy li r3,PerformanceMonitor@l 937*dfc3095cSChristophe Leroy mtspr SPRN_IVOR35,r3 938*dfc3095cSChristophe Leroy li r3,Doorbell@l 939*dfc3095cSChristophe Leroy mtspr SPRN_IVOR36,r3 940*dfc3095cSChristophe Leroy li r3,CriticalDoorbell@l 941*dfc3095cSChristophe Leroy mtspr SPRN_IVOR37,r3 942*dfc3095cSChristophe Leroy sync 943*dfc3095cSChristophe Leroy blr 944*dfc3095cSChristophe Leroy 945*dfc3095cSChristophe Leroy/* setup ehv ivors for */ 946*dfc3095cSChristophe Leroy_GLOBAL(__setup_ehv_ivors) 947*dfc3095cSChristophe Leroy li r3,GuestDoorbell@l 948*dfc3095cSChristophe Leroy mtspr SPRN_IVOR38,r3 949*dfc3095cSChristophe Leroy li r3,CriticalGuestDoorbell@l 950*dfc3095cSChristophe Leroy mtspr SPRN_IVOR39,r3 951*dfc3095cSChristophe Leroy li r3,Hypercall@l 952*dfc3095cSChristophe Leroy mtspr SPRN_IVOR40,r3 953*dfc3095cSChristophe Leroy li r3,Ehvpriv@l 954*dfc3095cSChristophe Leroy mtspr SPRN_IVOR41,r3 955*dfc3095cSChristophe Leroy sync 956*dfc3095cSChristophe Leroy blr 957*dfc3095cSChristophe Leroy#endif /* CONFIG_PPC_E500MC */ 958*dfc3095cSChristophe Leroy#endif /* CONFIG_E500 */ 959*dfc3095cSChristophe Leroy 960*dfc3095cSChristophe Leroy#ifdef CONFIG_SPE 961*dfc3095cSChristophe Leroy/* 962*dfc3095cSChristophe Leroy * extern void __giveup_spe(struct task_struct *prev) 963*dfc3095cSChristophe Leroy * 964*dfc3095cSChristophe Leroy */ 965*dfc3095cSChristophe Leroy_GLOBAL(__giveup_spe) 966*dfc3095cSChristophe Leroy addi r3,r3,THREAD /* want THREAD of task */ 967*dfc3095cSChristophe Leroy lwz r5,PT_REGS(r3) 968*dfc3095cSChristophe Leroy cmpi 0,r5,0 969*dfc3095cSChristophe Leroy SAVE_32EVRS(0, r4, r3, THREAD_EVR0) 970*dfc3095cSChristophe Leroy evxor evr6, evr6, evr6 /* clear out evr6 */ 971*dfc3095cSChristophe Leroy evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ 972*dfc3095cSChristophe Leroy li r4,THREAD_ACC 973*dfc3095cSChristophe Leroy evstddx evr6, r4, r3 /* save off accumulator */ 974*dfc3095cSChristophe Leroy beq 1f 975*dfc3095cSChristophe Leroy lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) 976*dfc3095cSChristophe Leroy lis r3,MSR_SPE@h 977*dfc3095cSChristophe Leroy andc r4,r4,r3 /* disable SPE for previous task */ 978*dfc3095cSChristophe Leroy stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) 979*dfc3095cSChristophe Leroy1: 980*dfc3095cSChristophe Leroy blr 981*dfc3095cSChristophe Leroy#endif /* CONFIG_SPE */ 982*dfc3095cSChristophe Leroy 983*dfc3095cSChristophe Leroy/* 984*dfc3095cSChristophe Leroy * extern void abort(void) 985*dfc3095cSChristophe Leroy * 986*dfc3095cSChristophe Leroy * At present, this routine just applies a system reset. 987*dfc3095cSChristophe Leroy */ 988*dfc3095cSChristophe Leroy_GLOBAL(abort) 989*dfc3095cSChristophe Leroy li r13,0 990*dfc3095cSChristophe Leroy mtspr SPRN_DBCR0,r13 /* disable all debug events */ 991*dfc3095cSChristophe Leroy isync 992*dfc3095cSChristophe Leroy mfmsr r13 993*dfc3095cSChristophe Leroy ori r13,r13,MSR_DE@l /* Enable Debug Events */ 994*dfc3095cSChristophe Leroy mtmsr r13 995*dfc3095cSChristophe Leroy isync 996*dfc3095cSChristophe Leroy mfspr r13,SPRN_DBCR0 997*dfc3095cSChristophe Leroy lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h 998*dfc3095cSChristophe Leroy mtspr SPRN_DBCR0,r13 999*dfc3095cSChristophe Leroy isync 1000*dfc3095cSChristophe Leroy 1001*dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 1002*dfc3095cSChristophe Leroy/* When we get here, r24 needs to hold the CPU # */ 1003*dfc3095cSChristophe Leroy .globl __secondary_start 1004*dfc3095cSChristophe Leroy__secondary_start: 1005*dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r3, tlbcam_index) 1006*dfc3095cSChristophe Leroy lwz r3,0(r3) 1007*dfc3095cSChristophe Leroy mtctr r3 1008*dfc3095cSChristophe Leroy li r26,0 /* r26 safe? */ 1009*dfc3095cSChristophe Leroy 1010*dfc3095cSChristophe Leroy bl switch_to_as1 1011*dfc3095cSChristophe Leroy mr r27,r3 /* tlb entry */ 1012*dfc3095cSChristophe Leroy /* Load each CAM entry */ 1013*dfc3095cSChristophe Leroy1: mr r3,r26 1014*dfc3095cSChristophe Leroy bl loadcam_entry 1015*dfc3095cSChristophe Leroy addi r26,r26,1 1016*dfc3095cSChristophe Leroy bdnz 1b 1017*dfc3095cSChristophe Leroy mr r3,r27 /* tlb entry */ 1018*dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r4, memstart_addr) 1019*dfc3095cSChristophe Leroy lwz r4,0(r4) 1020*dfc3095cSChristophe Leroy mr r5,r25 /* phys kernel start */ 1021*dfc3095cSChristophe Leroy rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */ 1022*dfc3095cSChristophe Leroy subf r4,r5,r4 /* memstart_addr - phys kernel start */ 1023*dfc3095cSChristophe Leroy lis r7,KERNELBASE@h 1024*dfc3095cSChristophe Leroy ori r7,r7,KERNELBASE@l 1025*dfc3095cSChristophe Leroy cmpw r20,r7 /* if kernstart_virt_addr != KERNELBASE, randomized */ 1026*dfc3095cSChristophe Leroy beq 2f 1027*dfc3095cSChristophe Leroy li r4,0 1028*dfc3095cSChristophe Leroy2: li r5,0 /* no device tree */ 1029*dfc3095cSChristophe Leroy li r6,0 /* not boot cpu */ 1030*dfc3095cSChristophe Leroy bl restore_to_as0 1031*dfc3095cSChristophe Leroy 1032*dfc3095cSChristophe Leroy 1033*dfc3095cSChristophe Leroy lis r3,__secondary_hold_acknowledge@h 1034*dfc3095cSChristophe Leroy ori r3,r3,__secondary_hold_acknowledge@l 1035*dfc3095cSChristophe Leroy stw r24,0(r3) 1036*dfc3095cSChristophe Leroy 1037*dfc3095cSChristophe Leroy li r3,0 1038*dfc3095cSChristophe Leroy mr r4,r24 /* Why? */ 1039*dfc3095cSChristophe Leroy bl call_setup_cpu 1040*dfc3095cSChristophe Leroy 1041*dfc3095cSChristophe Leroy /* get current's stack and current */ 1042*dfc3095cSChristophe Leroy lis r2,secondary_current@ha 1043*dfc3095cSChristophe Leroy lwz r2,secondary_current@l(r2) 1044*dfc3095cSChristophe Leroy lwz r1,TASK_STACK(r2) 1045*dfc3095cSChristophe Leroy 1046*dfc3095cSChristophe Leroy /* stack */ 1047*dfc3095cSChristophe Leroy addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1048*dfc3095cSChristophe Leroy li r0,0 1049*dfc3095cSChristophe Leroy stw r0,0(r1) 1050*dfc3095cSChristophe Leroy 1051*dfc3095cSChristophe Leroy /* ptr to current thread */ 1052*dfc3095cSChristophe Leroy addi r4,r2,THREAD /* address of our thread_struct */ 1053*dfc3095cSChristophe Leroy mtspr SPRN_SPRG_THREAD,r4 1054*dfc3095cSChristophe Leroy 1055*dfc3095cSChristophe Leroy /* Setup the defaults for TLB entries */ 1056*dfc3095cSChristophe Leroy li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 1057*dfc3095cSChristophe Leroy mtspr SPRN_MAS4,r4 1058*dfc3095cSChristophe Leroy 1059*dfc3095cSChristophe Leroy /* Jump to start_secondary */ 1060*dfc3095cSChristophe Leroy lis r4,MSR_KERNEL@h 1061*dfc3095cSChristophe Leroy ori r4,r4,MSR_KERNEL@l 1062*dfc3095cSChristophe Leroy lis r3,start_secondary@h 1063*dfc3095cSChristophe Leroy ori r3,r3,start_secondary@l 1064*dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r3 1065*dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r4 1066*dfc3095cSChristophe Leroy sync 1067*dfc3095cSChristophe Leroy rfi 1068*dfc3095cSChristophe Leroy sync 1069*dfc3095cSChristophe Leroy 1070*dfc3095cSChristophe Leroy .globl __secondary_hold_acknowledge 1071*dfc3095cSChristophe Leroy__secondary_hold_acknowledge: 1072*dfc3095cSChristophe Leroy .long -1 1073*dfc3095cSChristophe Leroy#endif 1074*dfc3095cSChristophe Leroy 1075*dfc3095cSChristophe Leroy/* 1076*dfc3095cSChristophe Leroy * Create a 64M tlb by address and entry 1077*dfc3095cSChristophe Leroy * r3 - entry 1078*dfc3095cSChristophe Leroy * r4 - virtual address 1079*dfc3095cSChristophe Leroy * r5/r6 - physical address 1080*dfc3095cSChristophe Leroy */ 1081*dfc3095cSChristophe Leroy_GLOBAL(create_kaslr_tlb_entry) 1082*dfc3095cSChristophe Leroy lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1083*dfc3095cSChristophe Leroy rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 1084*dfc3095cSChristophe Leroy mtspr SPRN_MAS0,r7 /* Write MAS0 */ 1085*dfc3095cSChristophe Leroy 1086*dfc3095cSChristophe Leroy lis r3,(MAS1_VALID|MAS1_IPROT)@h 1087*dfc3095cSChristophe Leroy ori r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l 1088*dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r3 /* Write MAS1 */ 1089*dfc3095cSChristophe Leroy 1090*dfc3095cSChristophe Leroy lis r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h 1091*dfc3095cSChristophe Leroy ori r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l 1092*dfc3095cSChristophe Leroy and r3,r3,r4 1093*dfc3095cSChristophe Leroy ori r3,r3,MAS2_M_IF_NEEDED@l 1094*dfc3095cSChristophe Leroy mtspr SPRN_MAS2,r3 /* Write MAS2(EPN) */ 1095*dfc3095cSChristophe Leroy 1096*dfc3095cSChristophe Leroy#ifdef CONFIG_PHYS_64BIT 1097*dfc3095cSChristophe Leroy ori r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX) 1098*dfc3095cSChristophe Leroy mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ 1099*dfc3095cSChristophe Leroy mtspr SPRN_MAS7,r5 1100*dfc3095cSChristophe Leroy#else 1101*dfc3095cSChristophe Leroy ori r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX) 1102*dfc3095cSChristophe Leroy mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ 1103*dfc3095cSChristophe Leroy#endif 1104*dfc3095cSChristophe Leroy 1105*dfc3095cSChristophe Leroy tlbwe /* Write TLB */ 1106*dfc3095cSChristophe Leroy isync 1107*dfc3095cSChristophe Leroy sync 1108*dfc3095cSChristophe Leroy blr 1109*dfc3095cSChristophe Leroy 1110*dfc3095cSChristophe Leroy/* 1111*dfc3095cSChristophe Leroy * Return to the start of the relocated kernel and run again 1112*dfc3095cSChristophe Leroy * r3 - virtual address of fdt 1113*dfc3095cSChristophe Leroy * r4 - entry of the kernel 1114*dfc3095cSChristophe Leroy */ 1115*dfc3095cSChristophe Leroy_GLOBAL(reloc_kernel_entry) 1116*dfc3095cSChristophe Leroy mfmsr r7 1117*dfc3095cSChristophe Leroy rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS) 1118*dfc3095cSChristophe Leroy 1119*dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r4 1120*dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r7 1121*dfc3095cSChristophe Leroy rfi 1122*dfc3095cSChristophe Leroy 1123*dfc3095cSChristophe Leroy/* 1124*dfc3095cSChristophe Leroy * Create a tlb entry with the same effective and physical address as 1125*dfc3095cSChristophe Leroy * the tlb entry used by the current running code. But set the TS to 1. 1126*dfc3095cSChristophe Leroy * Then switch to the address space 1. It will return with the r3 set to 1127*dfc3095cSChristophe Leroy * the ESEL of the new created tlb. 1128*dfc3095cSChristophe Leroy */ 1129*dfc3095cSChristophe Leroy_GLOBAL(switch_to_as1) 1130*dfc3095cSChristophe Leroy mflr r5 1131*dfc3095cSChristophe Leroy 1132*dfc3095cSChristophe Leroy /* Find a entry not used */ 1133*dfc3095cSChristophe Leroy mfspr r3,SPRN_TLB1CFG 1134*dfc3095cSChristophe Leroy andi. r3,r3,0xfff 1135*dfc3095cSChristophe Leroy mfspr r4,SPRN_PID 1136*dfc3095cSChristophe Leroy rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 1137*dfc3095cSChristophe Leroy mtspr SPRN_MAS6,r4 1138*dfc3095cSChristophe Leroy1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1139*dfc3095cSChristophe Leroy addi r3,r3,-1 1140*dfc3095cSChristophe Leroy rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1141*dfc3095cSChristophe Leroy mtspr SPRN_MAS0,r4 1142*dfc3095cSChristophe Leroy tlbre 1143*dfc3095cSChristophe Leroy mfspr r4,SPRN_MAS1 1144*dfc3095cSChristophe Leroy andis. r4,r4,MAS1_VALID@h 1145*dfc3095cSChristophe Leroy bne 1b 1146*dfc3095cSChristophe Leroy 1147*dfc3095cSChristophe Leroy /* Get the tlb entry used by the current running code */ 1148*dfc3095cSChristophe Leroy bcl 20,31,$+4 1149*dfc3095cSChristophe Leroy0: mflr r4 1150*dfc3095cSChristophe Leroy tlbsx 0,r4 1151*dfc3095cSChristophe Leroy 1152*dfc3095cSChristophe Leroy mfspr r4,SPRN_MAS1 1153*dfc3095cSChristophe Leroy ori r4,r4,MAS1_TS /* Set the TS = 1 */ 1154*dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r4 1155*dfc3095cSChristophe Leroy 1156*dfc3095cSChristophe Leroy mfspr r4,SPRN_MAS0 1157*dfc3095cSChristophe Leroy rlwinm r4,r4,0,~MAS0_ESEL_MASK 1158*dfc3095cSChristophe Leroy rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1159*dfc3095cSChristophe Leroy mtspr SPRN_MAS0,r4 1160*dfc3095cSChristophe Leroy tlbwe 1161*dfc3095cSChristophe Leroy isync 1162*dfc3095cSChristophe Leroy sync 1163*dfc3095cSChristophe Leroy 1164*dfc3095cSChristophe Leroy mfmsr r4 1165*dfc3095cSChristophe Leroy ori r4,r4,MSR_IS | MSR_DS 1166*dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r5 1167*dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r4 1168*dfc3095cSChristophe Leroy sync 1169*dfc3095cSChristophe Leroy rfi 1170*dfc3095cSChristophe Leroy 1171*dfc3095cSChristophe Leroy/* 1172*dfc3095cSChristophe Leroy * Restore to the address space 0 and also invalidate the tlb entry created 1173*dfc3095cSChristophe Leroy * by switch_to_as1. 1174*dfc3095cSChristophe Leroy * r3 - the tlb entry which should be invalidated 1175*dfc3095cSChristophe Leroy * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0) 1176*dfc3095cSChristophe Leroy * r5 - device tree virtual address. If r4 is 0, r5 is ignored. 1177*dfc3095cSChristophe Leroy * r6 - boot cpu 1178*dfc3095cSChristophe Leroy*/ 1179*dfc3095cSChristophe Leroy_GLOBAL(restore_to_as0) 1180*dfc3095cSChristophe Leroy mflr r0 1181*dfc3095cSChristophe Leroy 1182*dfc3095cSChristophe Leroy bcl 20,31,$+4 1183*dfc3095cSChristophe Leroy0: mflr r9 1184*dfc3095cSChristophe Leroy addi r9,r9,1f - 0b 1185*dfc3095cSChristophe Leroy 1186*dfc3095cSChristophe Leroy /* 1187*dfc3095cSChristophe Leroy * We may map the PAGE_OFFSET in AS0 to a different physical address, 1188*dfc3095cSChristophe Leroy * so we need calculate the right jump and device tree address based 1189*dfc3095cSChristophe Leroy * on the offset passed by r4. 1190*dfc3095cSChristophe Leroy */ 1191*dfc3095cSChristophe Leroy add r9,r9,r4 1192*dfc3095cSChristophe Leroy add r5,r5,r4 1193*dfc3095cSChristophe Leroy add r0,r0,r4 1194*dfc3095cSChristophe Leroy 1195*dfc3095cSChristophe Leroy2: mfmsr r7 1196*dfc3095cSChristophe Leroy li r8,(MSR_IS | MSR_DS) 1197*dfc3095cSChristophe Leroy andc r7,r7,r8 1198*dfc3095cSChristophe Leroy 1199*dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r9 1200*dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r7 1201*dfc3095cSChristophe Leroy sync 1202*dfc3095cSChristophe Leroy rfi 1203*dfc3095cSChristophe Leroy 1204*dfc3095cSChristophe Leroy /* Invalidate the temporary tlb entry for AS1 */ 1205*dfc3095cSChristophe Leroy1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1206*dfc3095cSChristophe Leroy rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1207*dfc3095cSChristophe Leroy mtspr SPRN_MAS0,r9 1208*dfc3095cSChristophe Leroy tlbre 1209*dfc3095cSChristophe Leroy mfspr r9,SPRN_MAS1 1210*dfc3095cSChristophe Leroy rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */ 1211*dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r9 1212*dfc3095cSChristophe Leroy tlbwe 1213*dfc3095cSChristophe Leroy isync 1214*dfc3095cSChristophe Leroy 1215*dfc3095cSChristophe Leroy cmpwi r4,0 1216*dfc3095cSChristophe Leroy cmpwi cr1,r6,0 1217*dfc3095cSChristophe Leroy cror eq,4*cr1+eq,eq 1218*dfc3095cSChristophe Leroy bne 3f /* offset != 0 && is_boot_cpu */ 1219*dfc3095cSChristophe Leroy mtlr r0 1220*dfc3095cSChristophe Leroy blr 1221*dfc3095cSChristophe Leroy 1222*dfc3095cSChristophe Leroy /* 1223*dfc3095cSChristophe Leroy * The PAGE_OFFSET will map to a different physical address, 1224*dfc3095cSChristophe Leroy * jump to _start to do another relocation again. 1225*dfc3095cSChristophe Leroy */ 1226*dfc3095cSChristophe Leroy3: mr r3,r5 1227*dfc3095cSChristophe Leroy bl _start 1228