1dfc3095cSChristophe Leroy/* SPDX-License-Identifier: GPL-2.0-or-later */ 2dfc3095cSChristophe Leroy/* 3dfc3095cSChristophe Leroy * Kernel execution entry point code. 4dfc3095cSChristophe Leroy * 5dfc3095cSChristophe Leroy * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 6dfc3095cSChristophe Leroy * Initial PowerPC version. 7dfc3095cSChristophe Leroy * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 8dfc3095cSChristophe Leroy * Rewritten for PReP 9dfc3095cSChristophe Leroy * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 10dfc3095cSChristophe Leroy * Low-level exception handers, MMU support, and rewrite. 11dfc3095cSChristophe Leroy * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 12dfc3095cSChristophe Leroy * PowerPC 8xx modifications. 13dfc3095cSChristophe Leroy * Copyright (c) 1998-1999 TiVo, Inc. 14dfc3095cSChristophe Leroy * PowerPC 403GCX modifications. 15dfc3095cSChristophe Leroy * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 16dfc3095cSChristophe Leroy * PowerPC 403GCX/405GP modifications. 17dfc3095cSChristophe Leroy * Copyright 2000 MontaVista Software Inc. 18dfc3095cSChristophe Leroy * PPC405 modifications 19dfc3095cSChristophe Leroy * PowerPC 403GCX/405GP modifications. 20dfc3095cSChristophe Leroy * Author: MontaVista Software, Inc. 21dfc3095cSChristophe Leroy * frank_rowand@mvista.com or source@mvista.com 22dfc3095cSChristophe Leroy * debbie_chu@mvista.com 23dfc3095cSChristophe Leroy * Copyright 2002-2004 MontaVista Software, Inc. 24dfc3095cSChristophe Leroy * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> 25dfc3095cSChristophe Leroy * Copyright 2004 Freescale Semiconductor, Inc 26dfc3095cSChristophe Leroy * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> 27dfc3095cSChristophe Leroy */ 28dfc3095cSChristophe Leroy 29dfc3095cSChristophe Leroy#include <linux/init.h> 30dfc3095cSChristophe Leroy#include <linux/threads.h> 31dfc3095cSChristophe Leroy#include <linux/pgtable.h> 322da37761SChristophe Leroy#include <linux/linkage.h> 332da37761SChristophe Leroy 34dfc3095cSChristophe Leroy#include <asm/processor.h> 35dfc3095cSChristophe Leroy#include <asm/page.h> 36dfc3095cSChristophe Leroy#include <asm/mmu.h> 37dfc3095cSChristophe Leroy#include <asm/cputable.h> 38dfc3095cSChristophe Leroy#include <asm/thread_info.h> 39dfc3095cSChristophe Leroy#include <asm/ppc_asm.h> 40dfc3095cSChristophe Leroy#include <asm/asm-offsets.h> 41dfc3095cSChristophe Leroy#include <asm/cache.h> 42dfc3095cSChristophe Leroy#include <asm/ptrace.h> 43dfc3095cSChristophe Leroy#include <asm/feature-fixups.h> 44dfc3095cSChristophe Leroy#include "head_booke.h" 45dfc3095cSChristophe Leroy 46dfc3095cSChristophe Leroy/* As with the other PowerPC ports, it is expected that when code 47dfc3095cSChristophe Leroy * execution begins here, the following registers contain valid, yet 48dfc3095cSChristophe Leroy * optional, information: 49dfc3095cSChristophe Leroy * 50dfc3095cSChristophe Leroy * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 51dfc3095cSChristophe Leroy * r4 - Starting address of the init RAM disk 52dfc3095cSChristophe Leroy * r5 - Ending address of the init RAM disk 53dfc3095cSChristophe Leroy * r6 - Start of kernel command line string (e.g. "mem=128") 54dfc3095cSChristophe Leroy * r7 - End of kernel command line string 55dfc3095cSChristophe Leroy * 56dfc3095cSChristophe Leroy */ 57dfc3095cSChristophe Leroy __HEAD 58dfc3095cSChristophe Leroy_GLOBAL(_stext); 59dfc3095cSChristophe Leroy_GLOBAL(_start); 60dfc3095cSChristophe Leroy /* 61dfc3095cSChristophe Leroy * Reserve a word at a fixed location to store the address 62dfc3095cSChristophe Leroy * of abatron_pteptrs 63dfc3095cSChristophe Leroy */ 64dfc3095cSChristophe Leroy nop 65dfc3095cSChristophe Leroy 66dfc3095cSChristophe Leroy /* Translate device tree address to physical, save in r30/r31 */ 67dfc3095cSChristophe Leroy bl get_phys_addr 68dfc3095cSChristophe Leroy mr r30,r3 69dfc3095cSChristophe Leroy mr r31,r4 70dfc3095cSChristophe Leroy 71dfc3095cSChristophe Leroy li r25,0 /* phys kernel start (low) */ 72dfc3095cSChristophe Leroy li r24,0 /* CPU number */ 73dfc3095cSChristophe Leroy li r23,0 /* phys kernel start (high) */ 74dfc3095cSChristophe Leroy 75dfc3095cSChristophe Leroy#ifdef CONFIG_RELOCATABLE 76dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */ 77dfc3095cSChristophe Leroy 78dfc3095cSChristophe Leroy /* Translate _stext address to physical, save in r23/r25 */ 79dfc3095cSChristophe Leroy bl get_phys_addr 80dfc3095cSChristophe Leroy mr r23,r3 81dfc3095cSChristophe Leroy mr r25,r4 82dfc3095cSChristophe Leroy 83dfc3095cSChristophe Leroy bcl 20,31,$+4 84dfc3095cSChristophe Leroy0: mflr r8 85dfc3095cSChristophe Leroy addis r3,r8,(is_second_reloc - 0b)@ha 86dfc3095cSChristophe Leroy lwz r19,(is_second_reloc - 0b)@l(r3) 87dfc3095cSChristophe Leroy 88dfc3095cSChristophe Leroy /* Check if this is the second relocation. */ 89dfc3095cSChristophe Leroy cmpwi r19,1 90dfc3095cSChristophe Leroy bne 1f 91dfc3095cSChristophe Leroy 92dfc3095cSChristophe Leroy /* 93dfc3095cSChristophe Leroy * For the second relocation, we already get the real memstart_addr 94dfc3095cSChristophe Leroy * from device tree. So we will map PAGE_OFFSET to memstart_addr, 95dfc3095cSChristophe Leroy * then the virtual address of start kernel should be: 96dfc3095cSChristophe Leroy * PAGE_OFFSET + (kernstart_addr - memstart_addr) 97dfc3095cSChristophe Leroy * Since the offset between kernstart_addr and memstart_addr should 98dfc3095cSChristophe Leroy * never be beyond 1G, so we can just use the lower 32bit of them 99dfc3095cSChristophe Leroy * for the calculation. 100dfc3095cSChristophe Leroy */ 101dfc3095cSChristophe Leroy lis r3,PAGE_OFFSET@h 102dfc3095cSChristophe Leroy 103dfc3095cSChristophe Leroy addis r4,r8,(kernstart_addr - 0b)@ha 104dfc3095cSChristophe Leroy addi r4,r4,(kernstart_addr - 0b)@l 105dfc3095cSChristophe Leroy lwz r5,4(r4) 106dfc3095cSChristophe Leroy 107dfc3095cSChristophe Leroy addis r6,r8,(memstart_addr - 0b)@ha 108dfc3095cSChristophe Leroy addi r6,r6,(memstart_addr - 0b)@l 109dfc3095cSChristophe Leroy lwz r7,4(r6) 110dfc3095cSChristophe Leroy 111dfc3095cSChristophe Leroy subf r5,r7,r5 112dfc3095cSChristophe Leroy add r3,r3,r5 113dfc3095cSChristophe Leroy b 2f 114dfc3095cSChristophe Leroy 115dfc3095cSChristophe Leroy1: 116dfc3095cSChristophe Leroy /* 117dfc3095cSChristophe Leroy * We have the runtime (virtual) address of our base. 118dfc3095cSChristophe Leroy * We calculate our shift of offset from a 64M page. 119dfc3095cSChristophe Leroy * We could map the 64M page we belong to at PAGE_OFFSET and 120dfc3095cSChristophe Leroy * get going from there. 121dfc3095cSChristophe Leroy */ 122dfc3095cSChristophe Leroy lis r4,KERNELBASE@h 123dfc3095cSChristophe Leroy ori r4,r4,KERNELBASE@l 124dfc3095cSChristophe Leroy rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */ 125dfc3095cSChristophe Leroy rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */ 126dfc3095cSChristophe Leroy subf r3,r5,r6 /* r3 = r6 - r5 */ 127dfc3095cSChristophe Leroy add r3,r4,r3 /* Required Virtual Address */ 128dfc3095cSChristophe Leroy 129dfc3095cSChristophe Leroy2: bl relocate 130dfc3095cSChristophe Leroy 131dfc3095cSChristophe Leroy /* 132dfc3095cSChristophe Leroy * For the second relocation, we already set the right tlb entries 133dfc3095cSChristophe Leroy * for the kernel space, so skip the code in 85xx_entry_mapping.S 134dfc3095cSChristophe Leroy */ 135dfc3095cSChristophe Leroy cmpwi r19,1 136dfc3095cSChristophe Leroy beq set_ivor 137dfc3095cSChristophe Leroy#endif 138dfc3095cSChristophe Leroy 139dfc3095cSChristophe Leroy/* We try to not make any assumptions about how the boot loader 140dfc3095cSChristophe Leroy * setup or used the TLBs. We invalidate all mappings from the 141dfc3095cSChristophe Leroy * boot loader and load a single entry in TLB1[0] to map the 142dfc3095cSChristophe Leroy * first 64M of kernel memory. Any boot info passed from the 143dfc3095cSChristophe Leroy * bootloader needs to live in this first 64M. 144dfc3095cSChristophe Leroy * 145dfc3095cSChristophe Leroy * Requirement on bootloader: 146dfc3095cSChristophe Leroy * - The page we're executing in needs to reside in TLB1 and 147dfc3095cSChristophe Leroy * have IPROT=1. If not an invalidate broadcast could 148dfc3095cSChristophe Leroy * evict the entry we're currently executing in. 149dfc3095cSChristophe Leroy * 150dfc3095cSChristophe Leroy * r3 = Index of TLB1 were executing in 151dfc3095cSChristophe Leroy * r4 = Current MSR[IS] 152dfc3095cSChristophe Leroy * r5 = Index of TLB1 temp mapping 153dfc3095cSChristophe Leroy * 154dfc3095cSChristophe Leroy * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] 155dfc3095cSChristophe Leroy * if needed 156dfc3095cSChristophe Leroy */ 157dfc3095cSChristophe Leroy 158dfc3095cSChristophe Leroy_GLOBAL(__early_start) 159dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr) 160dfc3095cSChristophe Leroy lwz r20,0(r20) 161dfc3095cSChristophe Leroy 162dfc3095cSChristophe Leroy#define ENTRY_MAPPING_BOOT_SETUP 163dfc3095cSChristophe Leroy#include "85xx_entry_mapping.S" 164dfc3095cSChristophe Leroy#undef ENTRY_MAPPING_BOOT_SETUP 165dfc3095cSChristophe Leroy 166dfc3095cSChristophe Leroyset_ivor: 167dfc3095cSChristophe Leroy /* Establish the interrupt vector offsets */ 168dfc3095cSChristophe Leroy SET_IVOR(0, CriticalInput); 169dfc3095cSChristophe Leroy SET_IVOR(1, MachineCheck); 170dfc3095cSChristophe Leroy SET_IVOR(2, DataStorage); 171dfc3095cSChristophe Leroy SET_IVOR(3, InstructionStorage); 172dfc3095cSChristophe Leroy SET_IVOR(4, ExternalInput); 173dfc3095cSChristophe Leroy SET_IVOR(5, Alignment); 174dfc3095cSChristophe Leroy SET_IVOR(6, Program); 175dfc3095cSChristophe Leroy SET_IVOR(7, FloatingPointUnavailable); 176dfc3095cSChristophe Leroy SET_IVOR(8, SystemCall); 177dfc3095cSChristophe Leroy SET_IVOR(9, AuxillaryProcessorUnavailable); 178dfc3095cSChristophe Leroy SET_IVOR(10, Decrementer); 179dfc3095cSChristophe Leroy SET_IVOR(11, FixedIntervalTimer); 180dfc3095cSChristophe Leroy SET_IVOR(12, WatchdogTimer); 181dfc3095cSChristophe Leroy SET_IVOR(13, DataTLBError); 182dfc3095cSChristophe Leroy SET_IVOR(14, InstructionTLBError); 183dfc3095cSChristophe Leroy SET_IVOR(15, DebugCrit); 184dfc3095cSChristophe Leroy 185dfc3095cSChristophe Leroy /* Establish the interrupt vector base */ 186dfc3095cSChristophe Leroy lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 187dfc3095cSChristophe Leroy mtspr SPRN_IVPR,r4 188dfc3095cSChristophe Leroy 189dfc3095cSChristophe Leroy /* Setup the defaults for TLB entries */ 190dfc3095cSChristophe Leroy li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 191dfc3095cSChristophe Leroy mtspr SPRN_MAS4, r2 192dfc3095cSChristophe Leroy 193dfc3095cSChristophe Leroy#if !defined(CONFIG_BDI_SWITCH) 194dfc3095cSChristophe Leroy /* 195dfc3095cSChristophe Leroy * The Abatron BDI JTAG debugger does not tolerate others 196dfc3095cSChristophe Leroy * mucking with the debug registers. 197dfc3095cSChristophe Leroy */ 198dfc3095cSChristophe Leroy lis r2,DBCR0_IDM@h 199dfc3095cSChristophe Leroy mtspr SPRN_DBCR0,r2 200dfc3095cSChristophe Leroy isync 201dfc3095cSChristophe Leroy /* clear any residual debug events */ 202dfc3095cSChristophe Leroy li r2,-1 203dfc3095cSChristophe Leroy mtspr SPRN_DBSR,r2 204dfc3095cSChristophe Leroy#endif 205dfc3095cSChristophe Leroy 206dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 207dfc3095cSChristophe Leroy /* Check to see if we're the second processor, and jump 208dfc3095cSChristophe Leroy * to the secondary_start code if so 209dfc3095cSChristophe Leroy */ 210dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r24, boot_cpuid) 211dfc3095cSChristophe Leroy lwz r24, 0(r24) 212dfc3095cSChristophe Leroy cmpwi r24, -1 213dfc3095cSChristophe Leroy mfspr r24,SPRN_PIR 214dfc3095cSChristophe Leroy bne __secondary_start 215dfc3095cSChristophe Leroy#endif 216dfc3095cSChristophe Leroy 217dfc3095cSChristophe Leroy /* 218dfc3095cSChristophe Leroy * This is where the main kernel code starts. 219dfc3095cSChristophe Leroy */ 220dfc3095cSChristophe Leroy 221dfc3095cSChristophe Leroy /* ptr to current */ 222dfc3095cSChristophe Leroy lis r2,init_task@h 223dfc3095cSChristophe Leroy ori r2,r2,init_task@l 224dfc3095cSChristophe Leroy 225dfc3095cSChristophe Leroy /* ptr to current thread */ 226dfc3095cSChristophe Leroy addi r4,r2,THREAD /* init task's THREAD */ 227dfc3095cSChristophe Leroy mtspr SPRN_SPRG_THREAD,r4 228dfc3095cSChristophe Leroy 229dfc3095cSChristophe Leroy /* stack */ 230dfc3095cSChristophe Leroy lis r1,init_thread_union@h 231dfc3095cSChristophe Leroy ori r1,r1,init_thread_union@l 232dfc3095cSChristophe Leroy li r0,0 23390f1b431SNicholas Piggin stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1) 234dfc3095cSChristophe Leroy 235dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 236dfc3095cSChristophe Leroy stw r24, TASK_CPU(r2) 237dfc3095cSChristophe Leroy#endif 238dfc3095cSChristophe Leroy 239dfc3095cSChristophe Leroy bl early_init 240dfc3095cSChristophe Leroy 241dfc3095cSChristophe Leroy#ifdef CONFIG_KASAN 242dfc3095cSChristophe Leroy bl kasan_early_init 243dfc3095cSChristophe Leroy#endif 244dfc3095cSChristophe Leroy#ifdef CONFIG_RELOCATABLE 245dfc3095cSChristophe Leroy mr r3,r30 246dfc3095cSChristophe Leroy mr r4,r31 247dfc3095cSChristophe Leroy#ifdef CONFIG_PHYS_64BIT 248dfc3095cSChristophe Leroy mr r5,r23 249dfc3095cSChristophe Leroy mr r6,r25 250dfc3095cSChristophe Leroy#else 251dfc3095cSChristophe Leroy mr r5,r25 252dfc3095cSChristophe Leroy#endif 253dfc3095cSChristophe Leroy bl relocate_init 254dfc3095cSChristophe Leroy#endif 255dfc3095cSChristophe Leroy 256dfc3095cSChristophe Leroy#ifdef CONFIG_DYNAMIC_MEMSTART 257dfc3095cSChristophe Leroy lis r3,kernstart_addr@ha 258dfc3095cSChristophe Leroy la r3,kernstart_addr@l(r3) 259dfc3095cSChristophe Leroy#ifdef CONFIG_PHYS_64BIT 260dfc3095cSChristophe Leroy stw r23,0(r3) 261dfc3095cSChristophe Leroy stw r25,4(r3) 262dfc3095cSChristophe Leroy#else 263dfc3095cSChristophe Leroy stw r25,0(r3) 264dfc3095cSChristophe Leroy#endif 265dfc3095cSChristophe Leroy#endif 266dfc3095cSChristophe Leroy 267dfc3095cSChristophe Leroy/* 268dfc3095cSChristophe Leroy * Decide what sort of machine this is and initialize the MMU. 269dfc3095cSChristophe Leroy */ 270dfc3095cSChristophe Leroy mr r3,r30 271dfc3095cSChristophe Leroy mr r4,r31 272dfc3095cSChristophe Leroy bl machine_init 273dfc3095cSChristophe Leroy bl MMU_init 274dfc3095cSChristophe Leroy 275dfc3095cSChristophe Leroy /* Setup PTE pointers for the Abatron bdiGDB */ 276dfc3095cSChristophe Leroy lis r6, swapper_pg_dir@h 277dfc3095cSChristophe Leroy ori r6, r6, swapper_pg_dir@l 278dfc3095cSChristophe Leroy lis r5, abatron_pteptrs@h 279dfc3095cSChristophe Leroy ori r5, r5, abatron_pteptrs@l 280dfc3095cSChristophe Leroy lis r3, kernstart_virt_addr@ha 281dfc3095cSChristophe Leroy lwz r4, kernstart_virt_addr@l(r3) 282dfc3095cSChristophe Leroy stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ 283dfc3095cSChristophe Leroy stw r6, 0(r5) 284dfc3095cSChristophe Leroy 285dfc3095cSChristophe Leroy /* Let's move on */ 286dfc3095cSChristophe Leroy lis r4,start_kernel@h 287dfc3095cSChristophe Leroy ori r4,r4,start_kernel@l 288dfc3095cSChristophe Leroy lis r3,MSR_KERNEL@h 289dfc3095cSChristophe Leroy ori r3,r3,MSR_KERNEL@l 290dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r4 291dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r3 292dfc3095cSChristophe Leroy rfi /* change context and jump to start_kernel */ 293dfc3095cSChristophe Leroy 294dfc3095cSChristophe Leroy/* Macros to hide the PTE size differences 295dfc3095cSChristophe Leroy * 296dfc3095cSChristophe Leroy * FIND_PTE -- walks the page tables given EA & pgdir pointer 297dfc3095cSChristophe Leroy * r10 -- EA of fault 298dfc3095cSChristophe Leroy * r11 -- PGDIR pointer 299dfc3095cSChristophe Leroy * r12 -- free 300dfc3095cSChristophe Leroy * label 2: is the bailout case 301dfc3095cSChristophe Leroy * 302dfc3095cSChristophe Leroy * if we find the pte (fall through): 303dfc3095cSChristophe Leroy * r11 is low pte word 304dfc3095cSChristophe Leroy * r12 is pointer to the pte 305dfc3095cSChristophe Leroy * r10 is the pshift from the PGD, if we're a hugepage 306dfc3095cSChristophe Leroy */ 307dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 308dfc3095cSChristophe Leroy#ifdef CONFIG_HUGETLB_PAGE 309dfc3095cSChristophe Leroy#define FIND_PTE \ 310dfc3095cSChristophe Leroy rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ 311dfc3095cSChristophe Leroy lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ 312dfc3095cSChristophe Leroy rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 313dfc3095cSChristophe Leroy blt 1000f; /* Normal non-huge page */ \ 314dfc3095cSChristophe Leroy beq 2f; /* Bail if no table */ \ 315dfc3095cSChristophe Leroy oris r11, r11, PD_HUGE@h; /* Put back address bit */ \ 316dfc3095cSChristophe Leroy andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \ 317dfc3095cSChristophe Leroy xor r12, r10, r11; /* drop size bits from pointer */ \ 318dfc3095cSChristophe Leroy b 1001f; \ 319dfc3095cSChristophe Leroy1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ 320dfc3095cSChristophe Leroy li r10, 0; /* clear r10 */ \ 321dfc3095cSChristophe Leroy1001: lwz r11, 4(r12); /* Get pte entry */ 322dfc3095cSChristophe Leroy#else 323dfc3095cSChristophe Leroy#define FIND_PTE \ 324dfc3095cSChristophe Leroy rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ 325dfc3095cSChristophe Leroy lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ 326dfc3095cSChristophe Leroy rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 327dfc3095cSChristophe Leroy beq 2f; /* Bail if no table */ \ 328dfc3095cSChristophe Leroy rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ 329dfc3095cSChristophe Leroy lwz r11, 4(r12); /* Get pte entry */ 330dfc3095cSChristophe Leroy#endif /* HUGEPAGE */ 331dfc3095cSChristophe Leroy#else /* !PTE_64BIT */ 332dfc3095cSChristophe Leroy#define FIND_PTE \ 333dfc3095cSChristophe Leroy rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ 334dfc3095cSChristophe Leroy lwz r11, 0(r11); /* Get L1 entry */ \ 335dfc3095cSChristophe Leroy rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ 336dfc3095cSChristophe Leroy beq 2f; /* Bail if no table */ \ 337dfc3095cSChristophe Leroy rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ 338dfc3095cSChristophe Leroy lwz r11, 0(r12); /* Get Linux PTE */ 339dfc3095cSChristophe Leroy#endif 340dfc3095cSChristophe Leroy 341dfc3095cSChristophe Leroy/* 342dfc3095cSChristophe Leroy * Interrupt vector entry code 343dfc3095cSChristophe Leroy * 344dfc3095cSChristophe Leroy * The Book E MMUs are always on so we don't need to handle 345dfc3095cSChristophe Leroy * interrupts in real mode as with previous PPC processors. In 346dfc3095cSChristophe Leroy * this case we handle interrupts in the kernel virtual address 347dfc3095cSChristophe Leroy * space. 348dfc3095cSChristophe Leroy * 349dfc3095cSChristophe Leroy * Interrupt vectors are dynamically placed relative to the 350dfc3095cSChristophe Leroy * interrupt prefix as determined by the address of interrupt_base. 351dfc3095cSChristophe Leroy * The interrupt vectors offsets are programmed using the labels 352dfc3095cSChristophe Leroy * for each interrupt vector entry. 353dfc3095cSChristophe Leroy * 354dfc3095cSChristophe Leroy * Interrupt vectors must be aligned on a 16 byte boundary. 355dfc3095cSChristophe Leroy * We align on a 32 byte cache line boundary for good measure. 356dfc3095cSChristophe Leroy */ 357dfc3095cSChristophe Leroy 358dfc3095cSChristophe Leroyinterrupt_base: 359dfc3095cSChristophe Leroy /* Critical Input Interrupt */ 360dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) 361dfc3095cSChristophe Leroy 362dfc3095cSChristophe Leroy /* Machine Check Interrupt */ 363dfc3095cSChristophe Leroy MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 364dfc3095cSChristophe Leroy 365dfc3095cSChristophe Leroy /* Data Storage Interrupt */ 366dfc3095cSChristophe Leroy START_EXCEPTION(DataStorage) 367dfc3095cSChristophe Leroy NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE) 368dfc3095cSChristophe Leroy mfspr r5,SPRN_ESR /* Grab the ESR, save it */ 369dfc3095cSChristophe Leroy stw r5,_ESR(r11) 370dfc3095cSChristophe Leroy mfspr r4,SPRN_DEAR /* Grab the DEAR, save it */ 371dfc3095cSChristophe Leroy stw r4, _DEAR(r11) 372dfc3095cSChristophe Leroy andis. r10,r5,(ESR_ILK|ESR_DLK)@h 373dfc3095cSChristophe Leroy bne 1f 374dfc3095cSChristophe Leroy prepare_transfer_to_handler 375dfc3095cSChristophe Leroy bl do_page_fault 376dfc3095cSChristophe Leroy b interrupt_return 377dfc3095cSChristophe Leroy1: 378dfc3095cSChristophe Leroy prepare_transfer_to_handler 379dfc3095cSChristophe Leroy bl CacheLockingException 380dfc3095cSChristophe Leroy b interrupt_return 381dfc3095cSChristophe Leroy 382dfc3095cSChristophe Leroy /* Instruction Storage Interrupt */ 383dfc3095cSChristophe Leroy INSTRUCTION_STORAGE_EXCEPTION 384dfc3095cSChristophe Leroy 385dfc3095cSChristophe Leroy /* External Input Interrupt */ 386dfc3095cSChristophe Leroy EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ) 387dfc3095cSChristophe Leroy 388dfc3095cSChristophe Leroy /* Alignment Interrupt */ 389dfc3095cSChristophe Leroy ALIGNMENT_EXCEPTION 390dfc3095cSChristophe Leroy 391dfc3095cSChristophe Leroy /* Program Interrupt */ 392dfc3095cSChristophe Leroy PROGRAM_EXCEPTION 393dfc3095cSChristophe Leroy 394dfc3095cSChristophe Leroy /* Floating Point Unavailable Interrupt */ 395dfc3095cSChristophe Leroy#ifdef CONFIG_PPC_FPU 396dfc3095cSChristophe Leroy FP_UNAVAILABLE_EXCEPTION 397dfc3095cSChristophe Leroy#else 398*8e8a12ecSChristophe Leroy EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, emulation_assist_interrupt) 399dfc3095cSChristophe Leroy#endif 400dfc3095cSChristophe Leroy 401dfc3095cSChristophe Leroy /* System Call Interrupt */ 402dfc3095cSChristophe Leroy START_EXCEPTION(SystemCall) 403dfc3095cSChristophe Leroy SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1 404dfc3095cSChristophe Leroy 405dfc3095cSChristophe Leroy /* Auxiliary Processor Unavailable Interrupt */ 406dfc3095cSChristophe Leroy EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, unknown_exception) 407dfc3095cSChristophe Leroy 408dfc3095cSChristophe Leroy /* Decrementer Interrupt */ 409dfc3095cSChristophe Leroy DECREMENTER_EXCEPTION 410dfc3095cSChristophe Leroy 411dfc3095cSChristophe Leroy /* Fixed Internal Timer Interrupt */ 412dfc3095cSChristophe Leroy /* TODO: Add FIT support */ 413dfc3095cSChristophe Leroy EXCEPTION(0x3100, FIT, FixedIntervalTimer, unknown_exception) 414dfc3095cSChristophe Leroy 415dfc3095cSChristophe Leroy /* Watchdog Timer Interrupt */ 416dfc3095cSChristophe Leroy#ifdef CONFIG_BOOKE_WDT 417dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException) 418dfc3095cSChristophe Leroy#else 419dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception) 420dfc3095cSChristophe Leroy#endif 421dfc3095cSChristophe Leroy 422dfc3095cSChristophe Leroy /* Data TLB Error Interrupt */ 423dfc3095cSChristophe Leroy START_EXCEPTION(DataTLBError) 424dfc3095cSChristophe Leroy mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 425dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 426dfc3095cSChristophe Leroy stw r11, THREAD_NORMSAVE(0)(r10) 427dfc3095cSChristophe Leroy#ifdef CONFIG_KVM_BOOKE_HV 428dfc3095cSChristophe LeroyBEGIN_FTR_SECTION 429dfc3095cSChristophe Leroy mfspr r11, SPRN_SRR1 430dfc3095cSChristophe LeroyEND_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 431dfc3095cSChristophe Leroy#endif 432dfc3095cSChristophe Leroy stw r12, THREAD_NORMSAVE(1)(r10) 433dfc3095cSChristophe Leroy stw r13, THREAD_NORMSAVE(2)(r10) 434dfc3095cSChristophe Leroy mfcr r13 435dfc3095cSChristophe Leroy stw r13, THREAD_NORMSAVE(3)(r10) 436dfc3095cSChristophe Leroy DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 437dfc3095cSChristophe LeroySTART_BTB_FLUSH_SECTION 438dfc3095cSChristophe Leroy mfspr r11, SPRN_SRR1 439dfc3095cSChristophe Leroy andi. r10,r11,MSR_PR 440dfc3095cSChristophe Leroy beq 1f 441dfc3095cSChristophe Leroy BTB_FLUSH(r10) 442dfc3095cSChristophe Leroy1: 443dfc3095cSChristophe LeroyEND_BTB_FLUSH_SECTION 444dfc3095cSChristophe Leroy mfspr r10, SPRN_DEAR /* Get faulting address */ 445dfc3095cSChristophe Leroy 446dfc3095cSChristophe Leroy /* If we are faulting a kernel address, we have to use the 447dfc3095cSChristophe Leroy * kernel page tables. 448dfc3095cSChristophe Leroy */ 449dfc3095cSChristophe Leroy lis r11, PAGE_OFFSET@h 450dfc3095cSChristophe Leroy cmplw 5, r10, r11 451dfc3095cSChristophe Leroy blt 5, 3f 452dfc3095cSChristophe Leroy lis r11, swapper_pg_dir@h 453dfc3095cSChristophe Leroy ori r11, r11, swapper_pg_dir@l 454dfc3095cSChristophe Leroy 455dfc3095cSChristophe Leroy mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 456dfc3095cSChristophe Leroy rlwinm r12,r12,0,16,1 457dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r12 458dfc3095cSChristophe Leroy 459dfc3095cSChristophe Leroy b 4f 460dfc3095cSChristophe Leroy 461dfc3095cSChristophe Leroy /* Get the PGD for the current thread */ 462dfc3095cSChristophe Leroy3: 463dfc3095cSChristophe Leroy mfspr r11,SPRN_SPRG_THREAD 464dfc3095cSChristophe Leroy lwz r11,PGDIR(r11) 465dfc3095cSChristophe Leroy 466dfc3095cSChristophe Leroy#ifdef CONFIG_PPC_KUAP 467dfc3095cSChristophe Leroy mfspr r12, SPRN_MAS1 468dfc3095cSChristophe Leroy rlwinm. r12,r12,0,0x3fff0000 469dfc3095cSChristophe Leroy beq 2f /* KUAP fault */ 470dfc3095cSChristophe Leroy#endif 471dfc3095cSChristophe Leroy 472dfc3095cSChristophe Leroy4: 473dfc3095cSChristophe Leroy /* Mask of required permission bits. Note that while we 474dfc3095cSChristophe Leroy * do copy ESR:ST to _PAGE_RW position as trying to write 475dfc3095cSChristophe Leroy * to an RO page is pretty common, we don't do it with 476dfc3095cSChristophe Leroy * _PAGE_DIRTY. We could do it, but it's a fairly rare 477dfc3095cSChristophe Leroy * event so I'd rather take the overhead when it happens 478dfc3095cSChristophe Leroy * rather than adding an instruction here. We should measure 479dfc3095cSChristophe Leroy * whether the whole thing is worth it in the first place 480dfc3095cSChristophe Leroy * as we could avoid loading SPRN_ESR completely in the first 481dfc3095cSChristophe Leroy * place... 482dfc3095cSChristophe Leroy * 483dfc3095cSChristophe Leroy * TODO: Is it worth doing that mfspr & rlwimi in the first 484dfc3095cSChristophe Leroy * place or can we save a couple of instructions here ? 485dfc3095cSChristophe Leroy */ 486dfc3095cSChristophe Leroy mfspr r12,SPRN_ESR 487dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 488dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT 489dfc3095cSChristophe Leroy oris r13,r13,_PAGE_ACCESSED@h 490dfc3095cSChristophe Leroy#else 491dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT|_PAGE_ACCESSED 492dfc3095cSChristophe Leroy#endif 493dfc3095cSChristophe Leroy rlwimi r13,r12,11,29,29 494dfc3095cSChristophe Leroy 495dfc3095cSChristophe Leroy FIND_PTE 496dfc3095cSChristophe Leroy andc. r13,r13,r11 /* Check permission */ 497dfc3095cSChristophe Leroy 498dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 499dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 500dfc3095cSChristophe Leroy subf r13,r11,r12 /* create false data dep */ 501dfc3095cSChristophe Leroy lwzx r13,r11,r13 /* Get upper pte bits */ 502dfc3095cSChristophe Leroy#else 503dfc3095cSChristophe Leroy lwz r13,0(r12) /* Get upper pte bits */ 504dfc3095cSChristophe Leroy#endif 505dfc3095cSChristophe Leroy#endif 506dfc3095cSChristophe Leroy 507dfc3095cSChristophe Leroy bne 2f /* Bail if permission/valid mismatch */ 508dfc3095cSChristophe Leroy 509dfc3095cSChristophe Leroy /* Jump to common tlb load */ 510dfc3095cSChristophe Leroy b finish_tlb_load 511dfc3095cSChristophe Leroy2: 512dfc3095cSChristophe Leroy /* The bailout. Restore registers to pre-exception conditions 513dfc3095cSChristophe Leroy * and call the heavyweights to help us out. 514dfc3095cSChristophe Leroy */ 515dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 516dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(3)(r10) 517dfc3095cSChristophe Leroy mtcr r11 518dfc3095cSChristophe Leroy lwz r13, THREAD_NORMSAVE(2)(r10) 519dfc3095cSChristophe Leroy lwz r12, THREAD_NORMSAVE(1)(r10) 520dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(0)(r10) 521dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_RSCRATCH0 522dfc3095cSChristophe Leroy b DataStorage 523dfc3095cSChristophe Leroy 524dfc3095cSChristophe Leroy /* Instruction TLB Error Interrupt */ 525dfc3095cSChristophe Leroy /* 526dfc3095cSChristophe Leroy * Nearly the same as above, except we get our 527dfc3095cSChristophe Leroy * information from different registers and bailout 528dfc3095cSChristophe Leroy * to a different point. 529dfc3095cSChristophe Leroy */ 530dfc3095cSChristophe Leroy START_EXCEPTION(InstructionTLBError) 531dfc3095cSChristophe Leroy mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 532dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 533dfc3095cSChristophe Leroy stw r11, THREAD_NORMSAVE(0)(r10) 534dfc3095cSChristophe Leroy#ifdef CONFIG_KVM_BOOKE_HV 535dfc3095cSChristophe LeroyBEGIN_FTR_SECTION 536dfc3095cSChristophe Leroy mfspr r11, SPRN_SRR1 537dfc3095cSChristophe LeroyEND_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 538dfc3095cSChristophe Leroy#endif 539dfc3095cSChristophe Leroy stw r12, THREAD_NORMSAVE(1)(r10) 540dfc3095cSChristophe Leroy stw r13, THREAD_NORMSAVE(2)(r10) 541dfc3095cSChristophe Leroy mfcr r13 542dfc3095cSChristophe Leroy stw r13, THREAD_NORMSAVE(3)(r10) 543dfc3095cSChristophe Leroy DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 544dfc3095cSChristophe LeroySTART_BTB_FLUSH_SECTION 545dfc3095cSChristophe Leroy mfspr r11, SPRN_SRR1 546dfc3095cSChristophe Leroy andi. r10,r11,MSR_PR 547dfc3095cSChristophe Leroy beq 1f 548dfc3095cSChristophe Leroy BTB_FLUSH(r10) 549dfc3095cSChristophe Leroy1: 550dfc3095cSChristophe LeroyEND_BTB_FLUSH_SECTION 551dfc3095cSChristophe Leroy 552dfc3095cSChristophe Leroy mfspr r10, SPRN_SRR0 /* Get faulting address */ 553dfc3095cSChristophe Leroy 554dfc3095cSChristophe Leroy /* If we are faulting a kernel address, we have to use the 555dfc3095cSChristophe Leroy * kernel page tables. 556dfc3095cSChristophe Leroy */ 557dfc3095cSChristophe Leroy lis r11, PAGE_OFFSET@h 558dfc3095cSChristophe Leroy cmplw 5, r10, r11 559dfc3095cSChristophe Leroy blt 5, 3f 560dfc3095cSChristophe Leroy lis r11, swapper_pg_dir@h 561dfc3095cSChristophe Leroy ori r11, r11, swapper_pg_dir@l 562dfc3095cSChristophe Leroy 563dfc3095cSChristophe Leroy mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 564dfc3095cSChristophe Leroy rlwinm r12,r12,0,16,1 565dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r12 566dfc3095cSChristophe Leroy 567dfc3095cSChristophe Leroy /* Make up the required permissions for kernel code */ 568dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 569dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT | _PAGE_BAP_SX 570dfc3095cSChristophe Leroy oris r13,r13,_PAGE_ACCESSED@h 571dfc3095cSChristophe Leroy#else 572dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 573dfc3095cSChristophe Leroy#endif 574dfc3095cSChristophe Leroy b 4f 575dfc3095cSChristophe Leroy 576dfc3095cSChristophe Leroy /* Get the PGD for the current thread */ 577dfc3095cSChristophe Leroy3: 578dfc3095cSChristophe Leroy mfspr r11,SPRN_SPRG_THREAD 579dfc3095cSChristophe Leroy lwz r11,PGDIR(r11) 580dfc3095cSChristophe Leroy 581dfc3095cSChristophe Leroy#ifdef CONFIG_PPC_KUAP 582dfc3095cSChristophe Leroy mfspr r12, SPRN_MAS1 583dfc3095cSChristophe Leroy rlwinm. r12,r12,0,0x3fff0000 584dfc3095cSChristophe Leroy beq 2f /* KUAP fault */ 585dfc3095cSChristophe Leroy#endif 586dfc3095cSChristophe Leroy 587dfc3095cSChristophe Leroy /* Make up the required permissions for user code */ 588dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 589dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT | _PAGE_BAP_UX 590dfc3095cSChristophe Leroy oris r13,r13,_PAGE_ACCESSED@h 591dfc3095cSChristophe Leroy#else 592dfc3095cSChristophe Leroy li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 593dfc3095cSChristophe Leroy#endif 594dfc3095cSChristophe Leroy 595dfc3095cSChristophe Leroy4: 596dfc3095cSChristophe Leroy FIND_PTE 597dfc3095cSChristophe Leroy andc. r13,r13,r11 /* Check permission */ 598dfc3095cSChristophe Leroy 599dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 600dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 601dfc3095cSChristophe Leroy subf r13,r11,r12 /* create false data dep */ 602dfc3095cSChristophe Leroy lwzx r13,r11,r13 /* Get upper pte bits */ 603dfc3095cSChristophe Leroy#else 604dfc3095cSChristophe Leroy lwz r13,0(r12) /* Get upper pte bits */ 605dfc3095cSChristophe Leroy#endif 606dfc3095cSChristophe Leroy#endif 607dfc3095cSChristophe Leroy 608dfc3095cSChristophe Leroy bne 2f /* Bail if permission mismatch */ 609dfc3095cSChristophe Leroy 610dfc3095cSChristophe Leroy /* Jump to common TLB load point */ 611dfc3095cSChristophe Leroy b finish_tlb_load 612dfc3095cSChristophe Leroy 613dfc3095cSChristophe Leroy2: 614dfc3095cSChristophe Leroy /* The bailout. Restore registers to pre-exception conditions 615dfc3095cSChristophe Leroy * and call the heavyweights to help us out. 616dfc3095cSChristophe Leroy */ 617dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 618dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(3)(r10) 619dfc3095cSChristophe Leroy mtcr r11 620dfc3095cSChristophe Leroy lwz r13, THREAD_NORMSAVE(2)(r10) 621dfc3095cSChristophe Leroy lwz r12, THREAD_NORMSAVE(1)(r10) 622dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(0)(r10) 623dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_RSCRATCH0 624dfc3095cSChristophe Leroy b InstructionStorage 625dfc3095cSChristophe Leroy 626dfc3095cSChristophe Leroy/* Define SPE handlers for e500v2 */ 627dfc3095cSChristophe Leroy#ifdef CONFIG_SPE 628dfc3095cSChristophe Leroy /* SPE Unavailable */ 629dfc3095cSChristophe Leroy START_EXCEPTION(SPEUnavailable) 630dfc3095cSChristophe Leroy NORMAL_EXCEPTION_PROLOG(0x2010, SPE_UNAVAIL) 631dfc3095cSChristophe Leroy beq 1f 632dfc3095cSChristophe Leroy bl load_up_spe 633dfc3095cSChristophe Leroy b fast_exception_return 634dfc3095cSChristophe Leroy1: prepare_transfer_to_handler 635dfc3095cSChristophe Leroy bl KernelSPE 636dfc3095cSChristophe Leroy b interrupt_return 637dfc3095cSChristophe Leroy#elif defined(CONFIG_SPE_POSSIBLE) 638dfc3095cSChristophe Leroy EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, unknown_exception) 639dfc3095cSChristophe Leroy#endif /* CONFIG_SPE_POSSIBLE */ 640dfc3095cSChristophe Leroy 641dfc3095cSChristophe Leroy /* SPE Floating Point Data */ 642dfc3095cSChristophe Leroy#ifdef CONFIG_SPE 643dfc3095cSChristophe Leroy START_EXCEPTION(SPEFloatingPointData) 644dfc3095cSChristophe Leroy NORMAL_EXCEPTION_PROLOG(0x2030, SPE_FP_DATA) 645dfc3095cSChristophe Leroy prepare_transfer_to_handler 646dfc3095cSChristophe Leroy bl SPEFloatingPointException 647dfc3095cSChristophe Leroy REST_NVGPRS(r1) 648dfc3095cSChristophe Leroy b interrupt_return 649dfc3095cSChristophe Leroy 650dfc3095cSChristophe Leroy /* SPE Floating Point Round */ 651dfc3095cSChristophe Leroy START_EXCEPTION(SPEFloatingPointRound) 652dfc3095cSChristophe Leroy NORMAL_EXCEPTION_PROLOG(0x2050, SPE_FP_ROUND) 653dfc3095cSChristophe Leroy prepare_transfer_to_handler 654dfc3095cSChristophe Leroy bl SPEFloatingPointRoundException 655dfc3095cSChristophe Leroy REST_NVGPRS(r1) 656dfc3095cSChristophe Leroy b interrupt_return 657dfc3095cSChristophe Leroy#elif defined(CONFIG_SPE_POSSIBLE) 658dfc3095cSChristophe Leroy EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, unknown_exception) 659dfc3095cSChristophe Leroy EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, unknown_exception) 660dfc3095cSChristophe Leroy#endif /* CONFIG_SPE_POSSIBLE */ 661dfc3095cSChristophe Leroy 662dfc3095cSChristophe Leroy 663dfc3095cSChristophe Leroy /* Performance Monitor */ 664dfc3095cSChristophe Leroy EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \ 665dfc3095cSChristophe Leroy performance_monitor_exception) 666dfc3095cSChristophe Leroy 667dfc3095cSChristophe Leroy EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception) 668dfc3095cSChristophe Leroy 669dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \ 670dfc3095cSChristophe Leroy CriticalDoorbell, unknown_exception) 671dfc3095cSChristophe Leroy 672dfc3095cSChristophe Leroy /* Debug Interrupt */ 673dfc3095cSChristophe Leroy DEBUG_DEBUG_EXCEPTION 674dfc3095cSChristophe Leroy DEBUG_CRIT_EXCEPTION 675dfc3095cSChristophe Leroy 676dfc3095cSChristophe Leroy GUEST_DOORBELL_EXCEPTION 677dfc3095cSChristophe Leroy 678dfc3095cSChristophe Leroy CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \ 679dfc3095cSChristophe Leroy unknown_exception) 680dfc3095cSChristophe Leroy 681dfc3095cSChristophe Leroy /* Hypercall */ 682dfc3095cSChristophe Leroy EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception) 683dfc3095cSChristophe Leroy 684dfc3095cSChristophe Leroy /* Embedded Hypervisor Privilege */ 685dfc3095cSChristophe Leroy EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception) 686dfc3095cSChristophe Leroy 687dfc3095cSChristophe Leroyinterrupt_end: 688dfc3095cSChristophe Leroy 689dfc3095cSChristophe Leroy/* 690dfc3095cSChristophe Leroy * Local functions 691dfc3095cSChristophe Leroy */ 692dfc3095cSChristophe Leroy 693dfc3095cSChristophe Leroy/* 694dfc3095cSChristophe Leroy * Both the instruction and data TLB miss get to this 695dfc3095cSChristophe Leroy * point to load the TLB. 696dfc3095cSChristophe Leroy * r10 - tsize encoding (if HUGETLB_PAGE) or available to use 697dfc3095cSChristophe Leroy * r11 - TLB (info from Linux PTE) 698dfc3095cSChristophe Leroy * r12 - available to use 699dfc3095cSChristophe Leroy * r13 - upper bits of PTE (if PTE_64BIT) or available to use 700dfc3095cSChristophe Leroy * CR5 - results of addr >= PAGE_OFFSET 701dfc3095cSChristophe Leroy * MAS0, MAS1 - loaded with proper value when we get here 702dfc3095cSChristophe Leroy * MAS2, MAS3 - will need additional info from Linux PTE 703dfc3095cSChristophe Leroy * Upon exit, we reload everything and RFI. 704dfc3095cSChristophe Leroy */ 705dfc3095cSChristophe Leroyfinish_tlb_load: 706dfc3095cSChristophe Leroy#ifdef CONFIG_HUGETLB_PAGE 707dfc3095cSChristophe Leroy cmpwi 6, r10, 0 /* check for huge page */ 708dfc3095cSChristophe Leroy beq 6, finish_tlb_load_cont /* !huge */ 709dfc3095cSChristophe Leroy 710dfc3095cSChristophe Leroy /* Alas, we need more scratch registers for hugepages */ 711dfc3095cSChristophe Leroy mfspr r12, SPRN_SPRG_THREAD 712dfc3095cSChristophe Leroy stw r14, THREAD_NORMSAVE(4)(r12) 713dfc3095cSChristophe Leroy stw r15, THREAD_NORMSAVE(5)(r12) 714dfc3095cSChristophe Leroy stw r16, THREAD_NORMSAVE(6)(r12) 715dfc3095cSChristophe Leroy stw r17, THREAD_NORMSAVE(7)(r12) 716dfc3095cSChristophe Leroy 717dfc3095cSChristophe Leroy /* Get the next_tlbcam_idx percpu var */ 718dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 719dfc3095cSChristophe Leroy lwz r15, TASK_CPU-THREAD(r12) 720dfc3095cSChristophe Leroy lis r14, __per_cpu_offset@h 721dfc3095cSChristophe Leroy ori r14, r14, __per_cpu_offset@l 722dfc3095cSChristophe Leroy rlwinm r15, r15, 2, 0, 29 723dfc3095cSChristophe Leroy lwzx r16, r14, r15 724dfc3095cSChristophe Leroy#else 725dfc3095cSChristophe Leroy li r16, 0 726dfc3095cSChristophe Leroy#endif 727dfc3095cSChristophe Leroy lis r17, next_tlbcam_idx@h 728dfc3095cSChristophe Leroy ori r17, r17, next_tlbcam_idx@l 729dfc3095cSChristophe Leroy add r17, r17, r16 /* r17 = *next_tlbcam_idx */ 730dfc3095cSChristophe Leroy lwz r15, 0(r17) /* r15 = next_tlbcam_idx */ 731dfc3095cSChristophe Leroy 732dfc3095cSChristophe Leroy lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */ 733dfc3095cSChristophe Leroy rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */ 734dfc3095cSChristophe Leroy mtspr SPRN_MAS0, r14 735dfc3095cSChristophe Leroy 736dfc3095cSChristophe Leroy /* Extract TLB1CFG(NENTRY) */ 737dfc3095cSChristophe Leroy mfspr r16, SPRN_TLB1CFG 738dfc3095cSChristophe Leroy andi. r16, r16, 0xfff 739dfc3095cSChristophe Leroy 740dfc3095cSChristophe Leroy /* Update next_tlbcam_idx, wrapping when necessary */ 741dfc3095cSChristophe Leroy addi r15, r15, 1 742dfc3095cSChristophe Leroy cmpw r15, r16 743dfc3095cSChristophe Leroy blt 100f 744dfc3095cSChristophe Leroy lis r14, tlbcam_index@h 745dfc3095cSChristophe Leroy ori r14, r14, tlbcam_index@l 746dfc3095cSChristophe Leroy lwz r15, 0(r14) 747dfc3095cSChristophe Leroy100: stw r15, 0(r17) 748dfc3095cSChristophe Leroy 749dfc3095cSChristophe Leroy /* 750dfc3095cSChristophe Leroy * Calc MAS1_TSIZE from r10 (which has pshift encoded) 751dfc3095cSChristophe Leroy * tlb_enc = (pshift - 10). 752dfc3095cSChristophe Leroy */ 753dfc3095cSChristophe Leroy subi r15, r10, 10 754dfc3095cSChristophe Leroy mfspr r16, SPRN_MAS1 755dfc3095cSChristophe Leroy rlwimi r16, r15, 7, 20, 24 756dfc3095cSChristophe Leroy mtspr SPRN_MAS1, r16 757dfc3095cSChristophe Leroy 758dfc3095cSChristophe Leroy /* copy the pshift for use later */ 759dfc3095cSChristophe Leroy mr r14, r10 760dfc3095cSChristophe Leroy 761dfc3095cSChristophe Leroy /* fall through */ 762dfc3095cSChristophe Leroy 763dfc3095cSChristophe Leroy#endif /* CONFIG_HUGETLB_PAGE */ 764dfc3095cSChristophe Leroy 765dfc3095cSChristophe Leroy /* 766dfc3095cSChristophe Leroy * We set execute, because we don't have the granularity to 767dfc3095cSChristophe Leroy * properly set this at the page level (Linux problem). 768dfc3095cSChristophe Leroy * Many of these bits are software only. Bits we don't set 769dfc3095cSChristophe Leroy * here we (properly should) assume have the appropriate value. 770dfc3095cSChristophe Leroy */ 771dfc3095cSChristophe Leroyfinish_tlb_load_cont: 772dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 773dfc3095cSChristophe Leroy rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ 774dfc3095cSChristophe Leroy andi. r10, r11, _PAGE_DIRTY 775dfc3095cSChristophe Leroy bne 1f 776dfc3095cSChristophe Leroy li r10, MAS3_SW | MAS3_UW 777dfc3095cSChristophe Leroy andc r12, r12, r10 778dfc3095cSChristophe Leroy1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ 779dfc3095cSChristophe Leroy rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ 780dfc3095cSChristophe Leroy2: mtspr SPRN_MAS3, r12 781dfc3095cSChristophe LeroyBEGIN_MMU_FTR_SECTION 782dfc3095cSChristophe Leroy srwi r10, r13, 12 /* grab RPN[12:31] */ 783dfc3095cSChristophe Leroy mtspr SPRN_MAS7, r10 784dfc3095cSChristophe LeroyEND_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) 785dfc3095cSChristophe Leroy#else 786dfc3095cSChristophe Leroy li r10, (_PAGE_EXEC | _PAGE_PRESENT) 787dfc3095cSChristophe Leroy mr r13, r11 788dfc3095cSChristophe Leroy rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ 789dfc3095cSChristophe Leroy and r12, r11, r10 790dfc3095cSChristophe Leroy andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ 791dfc3095cSChristophe Leroy slwi r10, r12, 1 792dfc3095cSChristophe Leroy or r10, r10, r12 793dfc3095cSChristophe Leroy rlwinm r10, r10, 0, ~_PAGE_EXEC /* Clear SX on user pages */ 794dfc3095cSChristophe Leroy iseleq r12, r12, r10 795dfc3095cSChristophe Leroy rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */ 796dfc3095cSChristophe Leroy mtspr SPRN_MAS3, r13 797dfc3095cSChristophe Leroy#endif 798dfc3095cSChristophe Leroy 799dfc3095cSChristophe Leroy mfspr r12, SPRN_MAS2 800dfc3095cSChristophe Leroy#ifdef CONFIG_PTE_64BIT 801dfc3095cSChristophe Leroy rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ 802dfc3095cSChristophe Leroy#else 803dfc3095cSChristophe Leroy rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ 804dfc3095cSChristophe Leroy#endif 805dfc3095cSChristophe Leroy#ifdef CONFIG_HUGETLB_PAGE 806dfc3095cSChristophe Leroy beq 6, 3f /* don't mask if page isn't huge */ 807dfc3095cSChristophe Leroy li r13, 1 808dfc3095cSChristophe Leroy slw r13, r13, r14 809dfc3095cSChristophe Leroy subi r13, r13, 1 810dfc3095cSChristophe Leroy rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */ 811dfc3095cSChristophe Leroy andc r12, r12, r13 /* mask off ea bits within the page */ 812dfc3095cSChristophe Leroy#endif 813dfc3095cSChristophe Leroy3: mtspr SPRN_MAS2, r12 814dfc3095cSChristophe Leroy 815dfc3095cSChristophe Leroytlb_write_entry: 816dfc3095cSChristophe Leroy tlbwe 817dfc3095cSChristophe Leroy 818dfc3095cSChristophe Leroy /* Done...restore registers and get out of here. */ 819dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_THREAD 820dfc3095cSChristophe Leroy#ifdef CONFIG_HUGETLB_PAGE 821dfc3095cSChristophe Leroy beq 6, 8f /* skip restore for 4k page faults */ 822dfc3095cSChristophe Leroy lwz r14, THREAD_NORMSAVE(4)(r10) 823dfc3095cSChristophe Leroy lwz r15, THREAD_NORMSAVE(5)(r10) 824dfc3095cSChristophe Leroy lwz r16, THREAD_NORMSAVE(6)(r10) 825dfc3095cSChristophe Leroy lwz r17, THREAD_NORMSAVE(7)(r10) 826dfc3095cSChristophe Leroy#endif 827dfc3095cSChristophe Leroy8: lwz r11, THREAD_NORMSAVE(3)(r10) 828dfc3095cSChristophe Leroy mtcr r11 829dfc3095cSChristophe Leroy lwz r13, THREAD_NORMSAVE(2)(r10) 830dfc3095cSChristophe Leroy lwz r12, THREAD_NORMSAVE(1)(r10) 831dfc3095cSChristophe Leroy lwz r11, THREAD_NORMSAVE(0)(r10) 832dfc3095cSChristophe Leroy mfspr r10, SPRN_SPRG_RSCRATCH0 833dfc3095cSChristophe Leroy rfi /* Force context change */ 834dfc3095cSChristophe Leroy 835dfc3095cSChristophe Leroy#ifdef CONFIG_SPE 836dfc3095cSChristophe Leroy/* Note that the SPE support is closely modeled after the AltiVec 837dfc3095cSChristophe Leroy * support. Changes to one are likely to be applicable to the 838dfc3095cSChristophe Leroy * other! */ 839dfc3095cSChristophe Leroy_GLOBAL(load_up_spe) 840dfc3095cSChristophe Leroy/* 841dfc3095cSChristophe Leroy * Disable SPE for the task which had SPE previously, 842dfc3095cSChristophe Leroy * and save its SPE registers in its thread_struct. 843dfc3095cSChristophe Leroy * Enables SPE for use in the kernel on return. 844dfc3095cSChristophe Leroy * On SMP we know the SPE units are free, since we give it up every 845dfc3095cSChristophe Leroy * switch. -- Kumar 846dfc3095cSChristophe Leroy */ 847dfc3095cSChristophe Leroy mfmsr r5 848dfc3095cSChristophe Leroy oris r5,r5,MSR_SPE@h 849dfc3095cSChristophe Leroy mtmsr r5 /* enable use of SPE now */ 850dfc3095cSChristophe Leroy isync 851dfc3095cSChristophe Leroy /* enable use of SPE after return */ 852dfc3095cSChristophe Leroy oris r9,r9,MSR_SPE@h 853dfc3095cSChristophe Leroy mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 854dfc3095cSChristophe Leroy li r4,1 855dfc3095cSChristophe Leroy li r10,THREAD_ACC 856dfc3095cSChristophe Leroy stw r4,THREAD_USED_SPE(r5) 857dfc3095cSChristophe Leroy evlddx evr4,r10,r5 858dfc3095cSChristophe Leroy evmra evr4,evr4 859dfc3095cSChristophe Leroy REST_32EVRS(0,r10,r5,THREAD_EVR0) 860dfc3095cSChristophe Leroy blr 861dfc3095cSChristophe Leroy 862dfc3095cSChristophe Leroy/* 863dfc3095cSChristophe Leroy * SPE unavailable trap from kernel - print a message, but let 864dfc3095cSChristophe Leroy * the task use SPE in the kernel until it returns to user mode. 865dfc3095cSChristophe Leroy */ 8668afffce6SSathvika VasireddySYM_FUNC_START_LOCAL(KernelSPE) 867dfc3095cSChristophe Leroy lwz r3,_MSR(r1) 868dfc3095cSChristophe Leroy oris r3,r3,MSR_SPE@h 869dfc3095cSChristophe Leroy stw r3,_MSR(r1) /* enable use of SPE after return */ 870dfc3095cSChristophe Leroy#ifdef CONFIG_PRINTK 871dfc3095cSChristophe Leroy lis r3,87f@h 872dfc3095cSChristophe Leroy ori r3,r3,87f@l 873dfc3095cSChristophe Leroy mr r4,r2 /* current */ 874dfc3095cSChristophe Leroy lwz r5,_NIP(r1) 875dfc3095cSChristophe Leroy bl _printk 876dfc3095cSChristophe Leroy#endif 877dfc3095cSChristophe Leroy b interrupt_return 878dfc3095cSChristophe Leroy#ifdef CONFIG_PRINTK 879dfc3095cSChristophe Leroy87: .string "SPE used in kernel (task=%p, pc=%x) \n" 880dfc3095cSChristophe Leroy#endif 881dfc3095cSChristophe Leroy .align 4,0 882dfc3095cSChristophe Leroy 8838afffce6SSathvika VasireddySYM_FUNC_END(KernelSPE) 884dfc3095cSChristophe Leroy#endif /* CONFIG_SPE */ 885dfc3095cSChristophe Leroy 886dfc3095cSChristophe Leroy/* 887dfc3095cSChristophe Leroy * Translate the effec addr in r3 to phys addr. The phys addr will be put 888dfc3095cSChristophe Leroy * into r3(higher 32bit) and r4(lower 32bit) 889dfc3095cSChristophe Leroy */ 8902da37761SChristophe LeroySYM_FUNC_START_LOCAL(get_phys_addr) 891dfc3095cSChristophe Leroy mfmsr r8 892dfc3095cSChristophe Leroy mfspr r9,SPRN_PID 893dfc3095cSChristophe Leroy rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 894dfc3095cSChristophe Leroy rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */ 895dfc3095cSChristophe Leroy mtspr SPRN_MAS6,r9 896dfc3095cSChristophe Leroy 897dfc3095cSChristophe Leroy tlbsx 0,r3 /* must succeed */ 898dfc3095cSChristophe Leroy 899dfc3095cSChristophe Leroy mfspr r8,SPRN_MAS1 900dfc3095cSChristophe Leroy mfspr r12,SPRN_MAS3 901dfc3095cSChristophe Leroy rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */ 902dfc3095cSChristophe Leroy li r10,1024 903dfc3095cSChristophe Leroy slw r10,r10,r9 /* r10 = page size */ 904dfc3095cSChristophe Leroy addi r10,r10,-1 905dfc3095cSChristophe Leroy and r11,r3,r10 /* r11 = page offset */ 906dfc3095cSChristophe Leroy andc r4,r12,r10 /* r4 = page base */ 907dfc3095cSChristophe Leroy or r4,r4,r11 /* r4 = devtree phys addr */ 908dfc3095cSChristophe Leroy#ifdef CONFIG_PHYS_64BIT 909dfc3095cSChristophe Leroy mfspr r3,SPRN_MAS7 910dfc3095cSChristophe Leroy#endif 911dfc3095cSChristophe Leroy blr 9122da37761SChristophe LeroySYM_FUNC_END(get_phys_addr) 913dfc3095cSChristophe Leroy 914dfc3095cSChristophe Leroy/* 915dfc3095cSChristophe Leroy * Global functions 916dfc3095cSChristophe Leroy */ 917dfc3095cSChristophe Leroy 918688de017SChristophe Leroy#ifdef CONFIG_PPC_E500 919dfc3095cSChristophe Leroy#ifndef CONFIG_PPC_E500MC 920dfc3095cSChristophe Leroy/* Adjust or setup IVORs for e500v1/v2 */ 921dfc3095cSChristophe Leroy_GLOBAL(__setup_e500_ivors) 922dfc3095cSChristophe Leroy li r3,DebugCrit@l 923dfc3095cSChristophe Leroy mtspr SPRN_IVOR15,r3 924dfc3095cSChristophe Leroy li r3,SPEUnavailable@l 925dfc3095cSChristophe Leroy mtspr SPRN_IVOR32,r3 926dfc3095cSChristophe Leroy li r3,SPEFloatingPointData@l 927dfc3095cSChristophe Leroy mtspr SPRN_IVOR33,r3 928dfc3095cSChristophe Leroy li r3,SPEFloatingPointRound@l 929dfc3095cSChristophe Leroy mtspr SPRN_IVOR34,r3 930dfc3095cSChristophe Leroy li r3,PerformanceMonitor@l 931dfc3095cSChristophe Leroy mtspr SPRN_IVOR35,r3 932dfc3095cSChristophe Leroy sync 933dfc3095cSChristophe Leroy blr 934dfc3095cSChristophe Leroy#else 935dfc3095cSChristophe Leroy/* Adjust or setup IVORs for e500mc */ 936dfc3095cSChristophe Leroy_GLOBAL(__setup_e500mc_ivors) 937dfc3095cSChristophe Leroy li r3,DebugDebug@l 938dfc3095cSChristophe Leroy mtspr SPRN_IVOR15,r3 939dfc3095cSChristophe Leroy li r3,PerformanceMonitor@l 940dfc3095cSChristophe Leroy mtspr SPRN_IVOR35,r3 941dfc3095cSChristophe Leroy li r3,Doorbell@l 942dfc3095cSChristophe Leroy mtspr SPRN_IVOR36,r3 943dfc3095cSChristophe Leroy li r3,CriticalDoorbell@l 944dfc3095cSChristophe Leroy mtspr SPRN_IVOR37,r3 945dfc3095cSChristophe Leroy sync 946dfc3095cSChristophe Leroy blr 947dfc3095cSChristophe Leroy 948dfc3095cSChristophe Leroy/* setup ehv ivors for */ 949dfc3095cSChristophe Leroy_GLOBAL(__setup_ehv_ivors) 950dfc3095cSChristophe Leroy li r3,GuestDoorbell@l 951dfc3095cSChristophe Leroy mtspr SPRN_IVOR38,r3 952dfc3095cSChristophe Leroy li r3,CriticalGuestDoorbell@l 953dfc3095cSChristophe Leroy mtspr SPRN_IVOR39,r3 954dfc3095cSChristophe Leroy li r3,Hypercall@l 955dfc3095cSChristophe Leroy mtspr SPRN_IVOR40,r3 956dfc3095cSChristophe Leroy li r3,Ehvpriv@l 957dfc3095cSChristophe Leroy mtspr SPRN_IVOR41,r3 958dfc3095cSChristophe Leroy sync 959dfc3095cSChristophe Leroy blr 960dfc3095cSChristophe Leroy#endif /* CONFIG_PPC_E500MC */ 961688de017SChristophe Leroy#endif /* CONFIG_PPC_E500 */ 962dfc3095cSChristophe Leroy 963dfc3095cSChristophe Leroy#ifdef CONFIG_SPE 964dfc3095cSChristophe Leroy/* 965dfc3095cSChristophe Leroy * extern void __giveup_spe(struct task_struct *prev) 966dfc3095cSChristophe Leroy * 967dfc3095cSChristophe Leroy */ 968dfc3095cSChristophe Leroy_GLOBAL(__giveup_spe) 969dfc3095cSChristophe Leroy addi r3,r3,THREAD /* want THREAD of task */ 970dfc3095cSChristophe Leroy lwz r5,PT_REGS(r3) 971dfc3095cSChristophe Leroy cmpi 0,r5,0 972dfc3095cSChristophe Leroy SAVE_32EVRS(0, r4, r3, THREAD_EVR0) 973dfc3095cSChristophe Leroy evxor evr6, evr6, evr6 /* clear out evr6 */ 974dfc3095cSChristophe Leroy evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ 975dfc3095cSChristophe Leroy li r4,THREAD_ACC 976dfc3095cSChristophe Leroy evstddx evr6, r4, r3 /* save off accumulator */ 977dfc3095cSChristophe Leroy beq 1f 978c03be0a3SNicholas Piggin lwz r4,_MSR-STACK_INT_FRAME_REGS(r5) 979dfc3095cSChristophe Leroy lis r3,MSR_SPE@h 980dfc3095cSChristophe Leroy andc r4,r4,r3 /* disable SPE for previous task */ 981c03be0a3SNicholas Piggin stw r4,_MSR-STACK_INT_FRAME_REGS(r5) 982dfc3095cSChristophe Leroy1: 983dfc3095cSChristophe Leroy blr 984dfc3095cSChristophe Leroy#endif /* CONFIG_SPE */ 985dfc3095cSChristophe Leroy 986dfc3095cSChristophe Leroy/* 987dfc3095cSChristophe Leroy * extern void abort(void) 988dfc3095cSChristophe Leroy * 989dfc3095cSChristophe Leroy * At present, this routine just applies a system reset. 990dfc3095cSChristophe Leroy */ 991dfc3095cSChristophe Leroy_GLOBAL(abort) 992dfc3095cSChristophe Leroy li r13,0 993dfc3095cSChristophe Leroy mtspr SPRN_DBCR0,r13 /* disable all debug events */ 994dfc3095cSChristophe Leroy isync 995dfc3095cSChristophe Leroy mfmsr r13 996dfc3095cSChristophe Leroy ori r13,r13,MSR_DE@l /* Enable Debug Events */ 997dfc3095cSChristophe Leroy mtmsr r13 998dfc3095cSChristophe Leroy isync 999dfc3095cSChristophe Leroy mfspr r13,SPRN_DBCR0 1000dfc3095cSChristophe Leroy lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h 1001dfc3095cSChristophe Leroy mtspr SPRN_DBCR0,r13 1002dfc3095cSChristophe Leroy isync 1003dfc3095cSChristophe Leroy 1004dfc3095cSChristophe Leroy#ifdef CONFIG_SMP 1005dfc3095cSChristophe Leroy/* When we get here, r24 needs to hold the CPU # */ 1006dfc3095cSChristophe Leroy .globl __secondary_start 1007dfc3095cSChristophe Leroy__secondary_start: 1008dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r3, tlbcam_index) 1009dfc3095cSChristophe Leroy lwz r3,0(r3) 1010dfc3095cSChristophe Leroy mtctr r3 1011dfc3095cSChristophe Leroy li r26,0 /* r26 safe? */ 1012dfc3095cSChristophe Leroy 1013dfc3095cSChristophe Leroy bl switch_to_as1 1014dfc3095cSChristophe Leroy mr r27,r3 /* tlb entry */ 1015dfc3095cSChristophe Leroy /* Load each CAM entry */ 1016dfc3095cSChristophe Leroy1: mr r3,r26 1017dfc3095cSChristophe Leroy bl loadcam_entry 1018dfc3095cSChristophe Leroy addi r26,r26,1 1019dfc3095cSChristophe Leroy bdnz 1b 1020dfc3095cSChristophe Leroy mr r3,r27 /* tlb entry */ 1021dfc3095cSChristophe Leroy LOAD_REG_ADDR_PIC(r4, memstart_addr) 1022dfc3095cSChristophe Leroy lwz r4,0(r4) 1023dfc3095cSChristophe Leroy mr r5,r25 /* phys kernel start */ 1024dfc3095cSChristophe Leroy rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */ 1025dfc3095cSChristophe Leroy subf r4,r5,r4 /* memstart_addr - phys kernel start */ 1026dfc3095cSChristophe Leroy lis r7,KERNELBASE@h 1027dfc3095cSChristophe Leroy ori r7,r7,KERNELBASE@l 1028dfc3095cSChristophe Leroy cmpw r20,r7 /* if kernstart_virt_addr != KERNELBASE, randomized */ 1029dfc3095cSChristophe Leroy beq 2f 1030dfc3095cSChristophe Leroy li r4,0 1031dfc3095cSChristophe Leroy2: li r5,0 /* no device tree */ 1032dfc3095cSChristophe Leroy li r6,0 /* not boot cpu */ 1033dfc3095cSChristophe Leroy bl restore_to_as0 1034dfc3095cSChristophe Leroy 1035dfc3095cSChristophe Leroy 1036dfc3095cSChristophe Leroy lis r3,__secondary_hold_acknowledge@h 1037dfc3095cSChristophe Leroy ori r3,r3,__secondary_hold_acknowledge@l 1038dfc3095cSChristophe Leroy stw r24,0(r3) 1039dfc3095cSChristophe Leroy 1040dfc3095cSChristophe Leroy li r3,0 1041dfc3095cSChristophe Leroy mr r4,r24 /* Why? */ 1042dfc3095cSChristophe Leroy bl call_setup_cpu 1043dfc3095cSChristophe Leroy 1044dfc3095cSChristophe Leroy /* get current's stack and current */ 1045dfc3095cSChristophe Leroy lis r2,secondary_current@ha 1046dfc3095cSChristophe Leroy lwz r2,secondary_current@l(r2) 1047dfc3095cSChristophe Leroy lwz r1,TASK_STACK(r2) 1048dfc3095cSChristophe Leroy 1049dfc3095cSChristophe Leroy /* stack */ 105090f1b431SNicholas Piggin addi r1,r1,THREAD_SIZE-STACK_FRAME_MIN_SIZE 1051dfc3095cSChristophe Leroy li r0,0 1052dfc3095cSChristophe Leroy stw r0,0(r1) 1053dfc3095cSChristophe Leroy 1054dfc3095cSChristophe Leroy /* ptr to current thread */ 1055dfc3095cSChristophe Leroy addi r4,r2,THREAD /* address of our thread_struct */ 1056dfc3095cSChristophe Leroy mtspr SPRN_SPRG_THREAD,r4 1057dfc3095cSChristophe Leroy 1058dfc3095cSChristophe Leroy /* Setup the defaults for TLB entries */ 1059dfc3095cSChristophe Leroy li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 1060dfc3095cSChristophe Leroy mtspr SPRN_MAS4,r4 1061dfc3095cSChristophe Leroy 1062dfc3095cSChristophe Leroy /* Jump to start_secondary */ 1063dfc3095cSChristophe Leroy lis r4,MSR_KERNEL@h 1064dfc3095cSChristophe Leroy ori r4,r4,MSR_KERNEL@l 1065dfc3095cSChristophe Leroy lis r3,start_secondary@h 1066dfc3095cSChristophe Leroy ori r3,r3,start_secondary@l 1067dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r3 1068dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r4 1069dfc3095cSChristophe Leroy sync 1070dfc3095cSChristophe Leroy rfi 1071dfc3095cSChristophe Leroy sync 1072dfc3095cSChristophe Leroy 1073dfc3095cSChristophe Leroy .globl __secondary_hold_acknowledge 1074dfc3095cSChristophe Leroy__secondary_hold_acknowledge: 1075dfc3095cSChristophe Leroy .long -1 1076dfc3095cSChristophe Leroy#endif 1077dfc3095cSChristophe Leroy 1078dfc3095cSChristophe Leroy/* 1079dfc3095cSChristophe Leroy * Create a 64M tlb by address and entry 1080dfc3095cSChristophe Leroy * r3 - entry 1081dfc3095cSChristophe Leroy * r4 - virtual address 1082dfc3095cSChristophe Leroy * r5/r6 - physical address 1083dfc3095cSChristophe Leroy */ 1084dfc3095cSChristophe Leroy_GLOBAL(create_kaslr_tlb_entry) 1085dfc3095cSChristophe Leroy lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1086dfc3095cSChristophe Leroy rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 1087dfc3095cSChristophe Leroy mtspr SPRN_MAS0,r7 /* Write MAS0 */ 1088dfc3095cSChristophe Leroy 1089dfc3095cSChristophe Leroy lis r3,(MAS1_VALID|MAS1_IPROT)@h 1090dfc3095cSChristophe Leroy ori r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l 1091dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r3 /* Write MAS1 */ 1092dfc3095cSChristophe Leroy 1093dfc3095cSChristophe Leroy lis r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h 1094dfc3095cSChristophe Leroy ori r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l 1095dfc3095cSChristophe Leroy and r3,r3,r4 1096dfc3095cSChristophe Leroy ori r3,r3,MAS2_M_IF_NEEDED@l 1097dfc3095cSChristophe Leroy mtspr SPRN_MAS2,r3 /* Write MAS2(EPN) */ 1098dfc3095cSChristophe Leroy 1099dfc3095cSChristophe Leroy#ifdef CONFIG_PHYS_64BIT 1100dfc3095cSChristophe Leroy ori r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX) 1101dfc3095cSChristophe Leroy mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ 1102dfc3095cSChristophe Leroy mtspr SPRN_MAS7,r5 1103dfc3095cSChristophe Leroy#else 1104dfc3095cSChristophe Leroy ori r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX) 1105dfc3095cSChristophe Leroy mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ 1106dfc3095cSChristophe Leroy#endif 1107dfc3095cSChristophe Leroy 1108dfc3095cSChristophe Leroy tlbwe /* Write TLB */ 1109dfc3095cSChristophe Leroy isync 1110dfc3095cSChristophe Leroy sync 1111dfc3095cSChristophe Leroy blr 1112dfc3095cSChristophe Leroy 1113dfc3095cSChristophe Leroy/* 1114dfc3095cSChristophe Leroy * Return to the start of the relocated kernel and run again 1115dfc3095cSChristophe Leroy * r3 - virtual address of fdt 1116dfc3095cSChristophe Leroy * r4 - entry of the kernel 1117dfc3095cSChristophe Leroy */ 1118dfc3095cSChristophe Leroy_GLOBAL(reloc_kernel_entry) 1119dfc3095cSChristophe Leroy mfmsr r7 1120dfc3095cSChristophe Leroy rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS) 1121dfc3095cSChristophe Leroy 1122dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r4 1123dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r7 1124dfc3095cSChristophe Leroy rfi 1125dfc3095cSChristophe Leroy 1126dfc3095cSChristophe Leroy/* 1127dfc3095cSChristophe Leroy * Create a tlb entry with the same effective and physical address as 1128dfc3095cSChristophe Leroy * the tlb entry used by the current running code. But set the TS to 1. 1129dfc3095cSChristophe Leroy * Then switch to the address space 1. It will return with the r3 set to 1130dfc3095cSChristophe Leroy * the ESEL of the new created tlb. 1131dfc3095cSChristophe Leroy */ 1132dfc3095cSChristophe Leroy_GLOBAL(switch_to_as1) 1133dfc3095cSChristophe Leroy mflr r5 1134dfc3095cSChristophe Leroy 1135dfc3095cSChristophe Leroy /* Find a entry not used */ 1136dfc3095cSChristophe Leroy mfspr r3,SPRN_TLB1CFG 1137dfc3095cSChristophe Leroy andi. r3,r3,0xfff 1138dfc3095cSChristophe Leroy mfspr r4,SPRN_PID 1139dfc3095cSChristophe Leroy rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 1140dfc3095cSChristophe Leroy mtspr SPRN_MAS6,r4 1141dfc3095cSChristophe Leroy1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1142dfc3095cSChristophe Leroy addi r3,r3,-1 1143dfc3095cSChristophe Leroy rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1144dfc3095cSChristophe Leroy mtspr SPRN_MAS0,r4 1145dfc3095cSChristophe Leroy tlbre 1146dfc3095cSChristophe Leroy mfspr r4,SPRN_MAS1 1147dfc3095cSChristophe Leroy andis. r4,r4,MAS1_VALID@h 1148dfc3095cSChristophe Leroy bne 1b 1149dfc3095cSChristophe Leroy 1150dfc3095cSChristophe Leroy /* Get the tlb entry used by the current running code */ 1151dfc3095cSChristophe Leroy bcl 20,31,$+4 1152dfc3095cSChristophe Leroy0: mflr r4 1153dfc3095cSChristophe Leroy tlbsx 0,r4 1154dfc3095cSChristophe Leroy 1155dfc3095cSChristophe Leroy mfspr r4,SPRN_MAS1 1156dfc3095cSChristophe Leroy ori r4,r4,MAS1_TS /* Set the TS = 1 */ 1157dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r4 1158dfc3095cSChristophe Leroy 1159dfc3095cSChristophe Leroy mfspr r4,SPRN_MAS0 1160dfc3095cSChristophe Leroy rlwinm r4,r4,0,~MAS0_ESEL_MASK 1161dfc3095cSChristophe Leroy rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1162dfc3095cSChristophe Leroy mtspr SPRN_MAS0,r4 1163dfc3095cSChristophe Leroy tlbwe 1164dfc3095cSChristophe Leroy isync 1165dfc3095cSChristophe Leroy sync 1166dfc3095cSChristophe Leroy 1167dfc3095cSChristophe Leroy mfmsr r4 1168dfc3095cSChristophe Leroy ori r4,r4,MSR_IS | MSR_DS 1169dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r5 1170dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r4 1171dfc3095cSChristophe Leroy sync 1172dfc3095cSChristophe Leroy rfi 1173dfc3095cSChristophe Leroy 1174dfc3095cSChristophe Leroy/* 1175dfc3095cSChristophe Leroy * Restore to the address space 0 and also invalidate the tlb entry created 1176dfc3095cSChristophe Leroy * by switch_to_as1. 1177dfc3095cSChristophe Leroy * r3 - the tlb entry which should be invalidated 1178dfc3095cSChristophe Leroy * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0) 1179dfc3095cSChristophe Leroy * r5 - device tree virtual address. If r4 is 0, r5 is ignored. 1180dfc3095cSChristophe Leroy * r6 - boot cpu 1181dfc3095cSChristophe Leroy*/ 1182dfc3095cSChristophe Leroy_GLOBAL(restore_to_as0) 1183dfc3095cSChristophe Leroy mflr r0 1184dfc3095cSChristophe Leroy 1185dfc3095cSChristophe Leroy bcl 20,31,$+4 1186dfc3095cSChristophe Leroy0: mflr r9 1187dfc3095cSChristophe Leroy addi r9,r9,1f - 0b 1188dfc3095cSChristophe Leroy 1189dfc3095cSChristophe Leroy /* 1190dfc3095cSChristophe Leroy * We may map the PAGE_OFFSET in AS0 to a different physical address, 1191dfc3095cSChristophe Leroy * so we need calculate the right jump and device tree address based 1192dfc3095cSChristophe Leroy * on the offset passed by r4. 1193dfc3095cSChristophe Leroy */ 1194dfc3095cSChristophe Leroy add r9,r9,r4 1195dfc3095cSChristophe Leroy add r5,r5,r4 1196dfc3095cSChristophe Leroy add r0,r0,r4 1197dfc3095cSChristophe Leroy 1198dfc3095cSChristophe Leroy2: mfmsr r7 1199dfc3095cSChristophe Leroy li r8,(MSR_IS | MSR_DS) 1200dfc3095cSChristophe Leroy andc r7,r7,r8 1201dfc3095cSChristophe Leroy 1202dfc3095cSChristophe Leroy mtspr SPRN_SRR0,r9 1203dfc3095cSChristophe Leroy mtspr SPRN_SRR1,r7 1204dfc3095cSChristophe Leroy sync 1205dfc3095cSChristophe Leroy rfi 1206dfc3095cSChristophe Leroy 1207dfc3095cSChristophe Leroy /* Invalidate the temporary tlb entry for AS1 */ 1208dfc3095cSChristophe Leroy1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1209dfc3095cSChristophe Leroy rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1210dfc3095cSChristophe Leroy mtspr SPRN_MAS0,r9 1211dfc3095cSChristophe Leroy tlbre 1212dfc3095cSChristophe Leroy mfspr r9,SPRN_MAS1 1213dfc3095cSChristophe Leroy rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */ 1214dfc3095cSChristophe Leroy mtspr SPRN_MAS1,r9 1215dfc3095cSChristophe Leroy tlbwe 1216dfc3095cSChristophe Leroy isync 1217dfc3095cSChristophe Leroy 1218dfc3095cSChristophe Leroy cmpwi r4,0 1219dfc3095cSChristophe Leroy cmpwi cr1,r6,0 1220dfc3095cSChristophe Leroy cror eq,4*cr1+eq,eq 1221dfc3095cSChristophe Leroy bne 3f /* offset != 0 && is_boot_cpu */ 1222dfc3095cSChristophe Leroy mtlr r0 1223dfc3095cSChristophe Leroy blr 1224dfc3095cSChristophe Leroy 1225dfc3095cSChristophe Leroy /* 1226dfc3095cSChristophe Leroy * The PAGE_OFFSET will map to a different physical address, 1227dfc3095cSChristophe Leroy * jump to _start to do another relocation again. 1228dfc3095cSChristophe Leroy */ 1229dfc3095cSChristophe Leroy3: mr r3,r5 1230dfc3095cSChristophe Leroy bl _start 1231