1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the entry point for the 64-bit kernel along 16 * with some early initialization code common to all 64-bit powerpc 17 * variants. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 25#include <linux/threads.h> 26#include <linux/init.h> 27#include <asm/reg.h> 28#include <asm/page.h> 29#include <asm/mmu.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/bug.h> 33#include <asm/cputable.h> 34#include <asm/setup.h> 35#include <asm/hvcall.h> 36#include <asm/thread_info.h> 37#include <asm/firmware.h> 38#include <asm/page_64.h> 39#include <asm/irqflags.h> 40#include <asm/kvm_book3s_asm.h> 41#include <asm/ptrace.h> 42#include <asm/hw_irq.h> 43 44/* The physical memory is laid out such that the secondary processor 45 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 46 * using the layout described in exceptions-64s.S 47 */ 48 49/* 50 * Entering into this code we make the following assumptions: 51 * 52 * For pSeries or server processors: 53 * 1. The MMU is off & open firmware is running in real mode. 54 * 2. The kernel is entered at __start 55 * -or- For OPAL entry: 56 * 1. The MMU is off, processor in HV mode, primary CPU enters at 0 57 * with device-tree in gpr3. We also get OPAL base in r8 and 58 * entry in r9 for debugging purposes 59 * 2. Secondary processors enter at 0x60 with PIR in gpr3 60 * 61 * For Book3E processors: 62 * 1. The MMU is on running in AS0 in a state defined in ePAPR 63 * 2. The kernel is entered at __start 64 */ 65 66 .text 67 .globl _stext 68_stext: 69_GLOBAL(__start) 70 /* NOP this out unconditionally */ 71BEGIN_FTR_SECTION 72 FIXUP_ENDIAN 73 b __start_initialization_multiplatform 74END_FTR_SECTION(0, 1) 75 76 /* Catch branch to 0 in real mode */ 77 trap 78 79 /* Secondary processors spin on this value until it becomes non-zero. 80 * When non-zero, it contains the real address of the function the cpu 81 * should jump to. 82 */ 83 .balign 8 84 .globl __secondary_hold_spinloop 85__secondary_hold_spinloop: 86 .llong 0x0 87 88 /* Secondary processors write this value with their cpu # */ 89 /* after they enter the spin loop immediately below. */ 90 .globl __secondary_hold_acknowledge 91__secondary_hold_acknowledge: 92 .llong 0x0 93 94#ifdef CONFIG_RELOCATABLE 95 /* This flag is set to 1 by a loader if the kernel should run 96 * at the loaded address instead of the linked address. This 97 * is used by kexec-tools to keep the the kdump kernel in the 98 * crash_kernel region. The loader is responsible for 99 * observing the alignment requirement. 100 */ 101 /* Do not move this variable as kexec-tools knows about it. */ 102 . = 0x5c 103 .globl __run_at_load 104__run_at_load: 105 .long 0x72756e30 /* "run0" -- relocate to 0 by default */ 106#endif 107 108 . = 0x60 109/* 110 * The following code is used to hold secondary processors 111 * in a spin loop after they have entered the kernel, but 112 * before the bulk of the kernel has been relocated. This code 113 * is relocated to physical address 0x60 before prom_init is run. 114 * All of it must fit below the first exception vector at 0x100. 115 * Use .globl here not _GLOBAL because we want __secondary_hold 116 * to be the actual text address, not a descriptor. 117 */ 118 .globl __secondary_hold 119__secondary_hold: 120 FIXUP_ENDIAN 121#ifndef CONFIG_PPC_BOOK3E 122 mfmsr r24 123 ori r24,r24,MSR_RI 124 mtmsrd r24 /* RI on */ 125#endif 126 /* Grab our physical cpu number */ 127 mr r24,r3 128 /* stash r4 for book3e */ 129 mr r25,r4 130 131 /* Tell the master cpu we're here */ 132 /* Relocation is off & we are located at an address less */ 133 /* than 0x100, so only need to grab low order offset. */ 134 std r24,__secondary_hold_acknowledge-_stext(0) 135 sync 136 137 li r26,0 138#ifdef CONFIG_PPC_BOOK3E 139 tovirt(r26,r26) 140#endif 141 /* All secondary cpus wait here until told to start. */ 142100: ld r12,__secondary_hold_spinloop-_stext(r26) 143 cmpdi 0,r12,0 144 beq 100b 145 146#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 147#ifdef CONFIG_PPC_BOOK3E 148 tovirt(r12,r12) 149#endif 150 mtctr r12 151 mr r3,r24 152 /* 153 * it may be the case that other platforms have r4 right to 154 * begin with, this gives us some safety in case it is not 155 */ 156#ifdef CONFIG_PPC_BOOK3E 157 mr r4,r25 158#else 159 li r4,0 160#endif 161 /* Make sure that patched code is visible */ 162 isync 163 bctr 164#else 165 BUG_OPCODE 166#endif 167 168/* This value is used to mark exception frames on the stack. */ 169 .section ".toc","aw" 170exception_marker: 171 .tc ID_72656773_68657265[TC],0x7265677368657265 172 .text 173 174/* 175 * On server, we include the exception vectors code here as it 176 * relies on absolute addressing which is only possible within 177 * this compilation unit 178 */ 179#ifdef CONFIG_PPC_BOOK3S 180#include "exceptions-64s.S" 181#endif 182 183#ifdef CONFIG_PPC_BOOK3E 184_GLOBAL(fsl_secondary_thread_init) 185 mfspr r4,SPRN_BUCSR 186 187 /* Enable branch prediction */ 188 lis r3,BUCSR_INIT@h 189 ori r3,r3,BUCSR_INIT@l 190 mtspr SPRN_BUCSR,r3 191 isync 192 193 /* 194 * Fix PIR to match the linear numbering in the device tree. 195 * 196 * On e6500, the reset value of PIR uses the low three bits for 197 * the thread within a core, and the upper bits for the core 198 * number. There are two threads per core, so shift everything 199 * but the low bit right by two bits so that the cpu numbering is 200 * continuous. 201 * 202 * If the old value of BUCSR is non-zero, this thread has run 203 * before. Thus, we assume we are coming from kexec or a similar 204 * scenario, and PIR is already set to the correct value. This 205 * is a bit of a hack, but there are limited opportunities for 206 * getting information into the thread and the alternatives 207 * seemed like they'd be overkill. We can't tell just by looking 208 * at the old PIR value which state it's in, since the same value 209 * could be valid for one thread out of reset and for a different 210 * thread in Linux. 211 */ 212 213 mfspr r3, SPRN_PIR 214 cmpwi r4,0 215 bne 1f 216 rlwimi r3, r3, 30, 2, 30 217 mtspr SPRN_PIR, r3 2181: 219#endif 220 221_GLOBAL(generic_secondary_thread_init) 222 mr r24,r3 223 224 /* turn on 64-bit mode */ 225 bl enable_64b_mode 226 227 /* get a valid TOC pointer, wherever we're mapped at */ 228 bl relative_toc 229 tovirt(r2,r2) 230 231#ifdef CONFIG_PPC_BOOK3E 232 /* Book3E initialization */ 233 mr r3,r24 234 bl book3e_secondary_thread_init 235#endif 236 b generic_secondary_common_init 237 238/* 239 * On pSeries and most other platforms, secondary processors spin 240 * in the following code. 241 * At entry, r3 = this processor's number (physical cpu id) 242 * 243 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 244 * this core already exists (setup via some other mechanism such 245 * as SCOM before entry). 246 */ 247_GLOBAL(generic_secondary_smp_init) 248 FIXUP_ENDIAN 249 mr r24,r3 250 mr r25,r4 251 252 /* turn on 64-bit mode */ 253 bl enable_64b_mode 254 255 /* get a valid TOC pointer, wherever we're mapped at */ 256 bl relative_toc 257 tovirt(r2,r2) 258 259#ifdef CONFIG_PPC_BOOK3E 260 /* Book3E initialization */ 261 mr r3,r24 262 mr r4,r25 263 bl book3e_secondary_core_init 264#endif 265 266generic_secondary_common_init: 267 /* Set up a paca value for this processor. Since we have the 268 * physical cpu id in r24, we need to search the pacas to find 269 * which logical id maps to our physical one. 270 */ 271 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ 272 ld r13,0(r13) /* Get base vaddr of paca array */ 273#ifndef CONFIG_SMP 274 addi r13,r13,PACA_SIZE /* know r13 if used accidentally */ 275 b kexec_wait /* wait for next kernel if !SMP */ 276#else 277 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 278 lwz r7,0(r7) /* also the max paca allocated */ 279 li r5,0 /* logical cpu id */ 2801: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 281 cmpw r6,r24 /* Compare to our id */ 282 beq 2f 283 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 284 addi r5,r5,1 285 cmpw r5,r7 /* Check if more pacas exist */ 286 blt 1b 287 288 mr r3,r24 /* not found, copy phys to r3 */ 289 b kexec_wait /* next kernel might do better */ 290 2912: SET_PACA(r13) 292#ifdef CONFIG_PPC_BOOK3E 293 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 294 mtspr SPRN_SPRG_TLB_EXFRAME,r12 295#endif 296 297 /* From now on, r24 is expected to be logical cpuid */ 298 mr r24,r5 299 300 /* See if we need to call a cpu state restore handler */ 301 LOAD_REG_ADDR(r23, cur_cpu_spec) 302 ld r23,0(r23) 303 ld r12,CPU_SPEC_RESTORE(r23) 304 cmpdi 0,r12,0 305 beq 3f 306#if !defined(_CALL_ELF) || _CALL_ELF != 2 307 ld r12,0(r12) 308#endif 309 mtctr r12 310 bctrl 311 3123: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 313 lwarx r4,0,r3 314 subi r4,r4,1 315 stwcx. r4,0,r3 316 bne 3b 317 isync 318 3194: HMT_LOW 320 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 321 /* start. */ 322 cmpwi 0,r23,0 323 beq 4b /* Loop until told to go */ 324 325 sync /* order paca.run and cur_cpu_spec */ 326 isync /* In case code patching happened */ 327 328 /* Create a temp kernel stack for use before relocation is on. */ 329 ld r1,PACAEMERGSP(r13) 330 subi r1,r1,STACK_FRAME_OVERHEAD 331 332 b __secondary_start 333#endif /* SMP */ 334 335/* 336 * Turn the MMU off. 337 * Assumes we're mapped EA == RA if the MMU is on. 338 */ 339#ifdef CONFIG_PPC_BOOK3S 340__mmu_off: 341 mfmsr r3 342 andi. r0,r3,MSR_IR|MSR_DR 343 beqlr 344 mflr r4 345 andc r3,r3,r0 346 mtspr SPRN_SRR0,r4 347 mtspr SPRN_SRR1,r3 348 sync 349 rfid 350 b . /* prevent speculative execution */ 351#endif 352 353 354/* 355 * Here is our main kernel entry point. We support currently 2 kind of entries 356 * depending on the value of r5. 357 * 358 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 359 * in r3...r7 360 * 361 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 362 * DT block, r4 is a physical pointer to the kernel itself 363 * 364 */ 365__start_initialization_multiplatform: 366 /* Make sure we are running in 64 bits mode */ 367 bl enable_64b_mode 368 369 /* Get TOC pointer (current runtime address) */ 370 bl relative_toc 371 372 /* find out where we are now */ 373 bcl 20,31,$+4 3740: mflr r26 /* r26 = runtime addr here */ 375 addis r26,r26,(_stext - 0b)@ha 376 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 377 378 /* 379 * Are we booted from a PROM Of-type client-interface ? 380 */ 381 cmpldi cr0,r5,0 382 beq 1f 383 b __boot_from_prom /* yes -> prom */ 3841: 385 /* Save parameters */ 386 mr r31,r3 387 mr r30,r4 388#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 389 /* Save OPAL entry */ 390 mr r28,r8 391 mr r29,r9 392#endif 393 394#ifdef CONFIG_PPC_BOOK3E 395 bl start_initialization_book3e 396 b __after_prom_start 397#else 398 /* Setup some critical 970 SPRs before switching MMU off */ 399 mfspr r0,SPRN_PVR 400 srwi r0,r0,16 401 cmpwi r0,0x39 /* 970 */ 402 beq 1f 403 cmpwi r0,0x3c /* 970FX */ 404 beq 1f 405 cmpwi r0,0x44 /* 970MP */ 406 beq 1f 407 cmpwi r0,0x45 /* 970GX */ 408 bne 2f 4091: bl __cpu_preinit_ppc970 4102: 411 412 /* Switch off MMU if not already off */ 413 bl __mmu_off 414 b __after_prom_start 415#endif /* CONFIG_PPC_BOOK3E */ 416 417__boot_from_prom: 418#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 419 /* Save parameters */ 420 mr r31,r3 421 mr r30,r4 422 mr r29,r5 423 mr r28,r6 424 mr r27,r7 425 426 /* 427 * Align the stack to 16-byte boundary 428 * Depending on the size and layout of the ELF sections in the initial 429 * boot binary, the stack pointer may be unaligned on PowerMac 430 */ 431 rldicr r1,r1,0,59 432 433#ifdef CONFIG_RELOCATABLE 434 /* Relocate code for where we are now */ 435 mr r3,r26 436 bl relocate 437#endif 438 439 /* Restore parameters */ 440 mr r3,r31 441 mr r4,r30 442 mr r5,r29 443 mr r6,r28 444 mr r7,r27 445 446 /* Do all of the interaction with OF client interface */ 447 mr r8,r26 448 bl prom_init 449#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 450 451 /* We never return. We also hit that trap if trying to boot 452 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 453 trap 454 455__after_prom_start: 456#ifdef CONFIG_RELOCATABLE 457 /* process relocations for the final address of the kernel */ 458 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 459 sldi r25,r25,32 460#if defined(CONFIG_PPC_BOOK3E) 461 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 462#endif 463 lwz r7,__run_at_load-_stext(r26) 464#if defined(CONFIG_PPC_BOOK3E) 465 tophys(r26,r26) 466#endif 467 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 468 bne 1f 469 add r25,r25,r26 4701: mr r3,r25 471 bl relocate 472#if defined(CONFIG_PPC_BOOK3E) 473 /* IVPR needs to be set after relocation. */ 474 bl init_core_book3e 475#endif 476#endif 477 478/* 479 * We need to run with _stext at physical address PHYSICAL_START. 480 * This will leave some code in the first 256B of 481 * real memory, which are reserved for software use. 482 * 483 * Note: This process overwrites the OF exception vectors. 484 */ 485 li r3,0 /* target addr */ 486#ifdef CONFIG_PPC_BOOK3E 487 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 488#endif 489 mr. r4,r26 /* In some cases the loader may */ 490#if defined(CONFIG_PPC_BOOK3E) 491 tovirt(r4,r4) 492#endif 493 beq 9f /* have already put us at zero */ 494 li r6,0x100 /* Start offset, the first 0x100 */ 495 /* bytes were copied earlier. */ 496 497#ifdef CONFIG_RELOCATABLE 498/* 499 * Check if the kernel has to be running as relocatable kernel based on the 500 * variable __run_at_load, if it is set the kernel is treated as relocatable 501 * kernel, otherwise it will be moved to PHYSICAL_START 502 */ 503#if defined(CONFIG_PPC_BOOK3E) 504 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 505#endif 506 lwz r7,__run_at_load-_stext(r26) 507 cmplwi cr0,r7,1 508 bne 3f 509 510#ifdef CONFIG_PPC_BOOK3E 511 LOAD_REG_ADDR(r5, __end_interrupts) 512 LOAD_REG_ADDR(r11, _stext) 513 sub r5,r5,r11 514#else 515 /* just copy interrupts */ 516 LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext) 517#endif 518 b 5f 5193: 520#endif 521 lis r5,(copy_to_here - _stext)@ha 522 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ 523 524 bl copy_and_flush /* copy the first n bytes */ 525 /* this includes the code being */ 526 /* executed here. */ 527 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ 528 addi r12,r8,(4f - _stext)@l /* that we just made */ 529 mtctr r12 530 bctr 531 532.balign 8 533p_end: .llong _end - _stext 534 5354: /* Now copy the rest of the kernel up to _end */ 536 addis r5,r26,(p_end - _stext)@ha 537 ld r5,(p_end - _stext)@l(r5) /* get _end */ 5385: bl copy_and_flush /* copy the rest */ 539 5409: b start_here_multiplatform 541 542/* 543 * Copy routine used to copy the kernel to start at physical address 0 544 * and flush and invalidate the caches as needed. 545 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 546 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 547 * 548 * Note: this routine *only* clobbers r0, r6 and lr 549 */ 550_GLOBAL(copy_and_flush) 551 addi r5,r5,-8 552 addi r6,r6,-8 5534: li r0,8 /* Use the smallest common */ 554 /* denominator cache line */ 555 /* size. This results in */ 556 /* extra cache line flushes */ 557 /* but operation is correct. */ 558 /* Can't get cache line size */ 559 /* from NACA as it is being */ 560 /* moved too. */ 561 562 mtctr r0 /* put # words/line in ctr */ 5633: addi r6,r6,8 /* copy a cache line */ 564 ldx r0,r6,r4 565 stdx r0,r6,r3 566 bdnz 3b 567 dcbst r6,r3 /* write it to memory */ 568 sync 569 icbi r6,r3 /* flush the icache line */ 570 cmpld 0,r6,r5 571 blt 4b 572 sync 573 addi r5,r5,8 574 addi r6,r6,8 575 isync 576 blr 577 578.align 8 579copy_to_here: 580 581#ifdef CONFIG_SMP 582#ifdef CONFIG_PPC_PMAC 583/* 584 * On PowerMac, secondary processors starts from the reset vector, which 585 * is temporarily turned into a call to one of the functions below. 586 */ 587 .section ".text"; 588 .align 2 ; 589 590 .globl __secondary_start_pmac_0 591__secondary_start_pmac_0: 592 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 593 li r24,0 594 b 1f 595 li r24,1 596 b 1f 597 li r24,2 598 b 1f 599 li r24,3 6001: 601 602_GLOBAL(pmac_secondary_start) 603 /* turn on 64-bit mode */ 604 bl enable_64b_mode 605 606 li r0,0 607 mfspr r3,SPRN_HID4 608 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 609 sync 610 mtspr SPRN_HID4,r3 611 isync 612 sync 613 slbia 614 615 /* get TOC pointer (real address) */ 616 bl relative_toc 617 tovirt(r2,r2) 618 619 /* Copy some CPU settings from CPU 0 */ 620 bl __restore_cpu_ppc970 621 622 /* pSeries do that early though I don't think we really need it */ 623 mfmsr r3 624 ori r3,r3,MSR_RI 625 mtmsrd r3 /* RI on */ 626 627 /* Set up a paca value for this processor. */ 628 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ 629 ld r4,0(r4) /* Get base vaddr of paca array */ 630 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 631 add r13,r13,r4 /* for this processor. */ 632 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 633 634 /* Mark interrupts soft and hard disabled (they might be enabled 635 * in the PACA when doing hotplug) 636 */ 637 li r0,0 638 stb r0,PACASOFTIRQEN(r13) 639 li r0,PACA_IRQ_HARD_DIS 640 stb r0,PACAIRQHAPPENED(r13) 641 642 /* Create a temp kernel stack for use before relocation is on. */ 643 ld r1,PACAEMERGSP(r13) 644 subi r1,r1,STACK_FRAME_OVERHEAD 645 646 b __secondary_start 647 648#endif /* CONFIG_PPC_PMAC */ 649 650/* 651 * This function is called after the master CPU has released the 652 * secondary processors. The execution environment is relocation off. 653 * The paca for this processor has the following fields initialized at 654 * this point: 655 * 1. Processor number 656 * 2. Segment table pointer (virtual address) 657 * On entry the following are set: 658 * r1 = stack pointer (real addr of temp stack) 659 * r24 = cpu# (in Linux terms) 660 * r13 = paca virtual address 661 * SPRG_PACA = paca virtual address 662 */ 663 .section ".text"; 664 .align 2 ; 665 666 .globl __secondary_start 667__secondary_start: 668 /* Set thread priority to MEDIUM */ 669 HMT_MEDIUM 670 671 /* Initialize the kernel stack */ 672 LOAD_REG_ADDR(r3, current_set) 673 sldi r28,r24,3 /* get current_set[cpu#] */ 674 ldx r14,r3,r28 675 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD 676 std r14,PACAKSAVE(r13) 677 678 /* Do early setup for that CPU (SLB and hash table pointer) */ 679 bl early_setup_secondary 680 681 /* 682 * setup the new stack pointer, but *don't* use this until 683 * translation is on. 684 */ 685 mr r1, r14 686 687 /* Clear backchain so we get nice backtraces */ 688 li r7,0 689 mtlr r7 690 691 /* Mark interrupts soft and hard disabled (they might be enabled 692 * in the PACA when doing hotplug) 693 */ 694 stb r7,PACASOFTIRQEN(r13) 695 li r0,PACA_IRQ_HARD_DIS 696 stb r0,PACAIRQHAPPENED(r13) 697 698 /* enable MMU and jump to start_secondary */ 699 LOAD_REG_ADDR(r3, start_secondary_prolog) 700 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 701 702 mtspr SPRN_SRR0,r3 703 mtspr SPRN_SRR1,r4 704 RFI 705 b . /* prevent speculative execution */ 706 707/* 708 * Running with relocation on at this point. All we want to do is 709 * zero the stack back-chain pointer and get the TOC virtual address 710 * before going into C code. 711 */ 712start_secondary_prolog: 713 ld r2,PACATOC(r13) 714 li r3,0 715 std r3,0(r1) /* Zero the stack frame pointer */ 716 bl start_secondary 717 b . 718/* 719 * Reset stack pointer and call start_secondary 720 * to continue with online operation when woken up 721 * from cede in cpu offline. 722 */ 723_GLOBAL(start_secondary_resume) 724 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 725 li r3,0 726 std r3,0(r1) /* Zero the stack frame pointer */ 727 bl start_secondary 728 b . 729#endif 730 731/* 732 * This subroutine clobbers r11 and r12 733 */ 734enable_64b_mode: 735 mfmsr r11 /* grab the current MSR */ 736#ifdef CONFIG_PPC_BOOK3E 737 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 738 mtmsr r11 739#else /* CONFIG_PPC_BOOK3E */ 740 li r12,(MSR_64BIT | MSR_ISF)@highest 741 sldi r12,r12,48 742 or r11,r11,r12 743 mtmsrd r11 744 isync 745#endif 746 blr 747 748/* 749 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 750 * by the toolchain). It computes the correct value for wherever we 751 * are running at the moment, using position-independent code. 752 * 753 * Note: The compiler constructs pointers using offsets from the 754 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 755 * the MMU is on we need our TOC to be a virtual address otherwise 756 * these pointers will be real addresses which may get stored and 757 * accessed later with the MMU on. We use tovirt() at the call 758 * sites to handle this. 759 */ 760_GLOBAL(relative_toc) 761 mflr r0 762 bcl 20,31,$+4 7630: mflr r11 764 ld r2,(p_toc - 0b)(r11) 765 add r2,r2,r11 766 mtlr r0 767 blr 768 769.balign 8 770p_toc: .llong __toc_start + 0x8000 - 0b 771 772/* 773 * This is where the main kernel code starts. 774 */ 775start_here_multiplatform: 776 /* set up the TOC */ 777 bl relative_toc 778 tovirt(r2,r2) 779 780 /* Clear out the BSS. It may have been done in prom_init, 781 * already but that's irrelevant since prom_init will soon 782 * be detached from the kernel completely. Besides, we need 783 * to clear it now for kexec-style entry. 784 */ 785 LOAD_REG_ADDR(r11,__bss_stop) 786 LOAD_REG_ADDR(r8,__bss_start) 787 sub r11,r11,r8 /* bss size */ 788 addi r11,r11,7 /* round up to an even double word */ 789 srdi. r11,r11,3 /* shift right by 3 */ 790 beq 4f 791 addi r8,r8,-8 792 li r0,0 793 mtctr r11 /* zero this many doublewords */ 7943: stdu r0,8(r8) 795 bdnz 3b 7964: 797 798#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 799 /* Setup OPAL entry */ 800 LOAD_REG_ADDR(r11, opal) 801 std r28,0(r11); 802 std r29,8(r11); 803#endif 804 805#ifndef CONFIG_PPC_BOOK3E 806 mfmsr r6 807 ori r6,r6,MSR_RI 808 mtmsrd r6 /* RI on */ 809#endif 810 811#ifdef CONFIG_RELOCATABLE 812 /* Save the physical address we're running at in kernstart_addr */ 813 LOAD_REG_ADDR(r4, kernstart_addr) 814 clrldi r0,r25,2 815 std r0,0(r4) 816#endif 817 818 /* The following gets the stack set up with the regs */ 819 /* pointing to the real addr of the kernel stack. This is */ 820 /* all done to support the C function call below which sets */ 821 /* up the htab. This is done because we have relocated the */ 822 /* kernel but are still running in real mode. */ 823 824 LOAD_REG_ADDR(r3,init_thread_union) 825 826 /* set up a stack pointer */ 827 addi r1,r3,THREAD_SIZE 828 li r0,0 829 stdu r0,-STACK_FRAME_OVERHEAD(r1) 830 831 /* 832 * Do very early kernel initializations, including initial hash table 833 * and SLB setup before we turn on relocation. 834 */ 835 836 /* Restore parameters passed from prom_init/kexec */ 837 mr r3,r31 838 bl early_setup /* also sets r13 and SPRG_PACA */ 839 840 LOAD_REG_ADDR(r3, start_here_common) 841 ld r4,PACAKMSR(r13) 842 mtspr SPRN_SRR0,r3 843 mtspr SPRN_SRR1,r4 844 RFI 845 b . /* prevent speculative execution */ 846 847 /* This is where all platforms converge execution */ 848 849start_here_common: 850 /* relocation is on at this point */ 851 std r1,PACAKSAVE(r13) 852 853 /* Load the TOC (virtual address) */ 854 ld r2,PACATOC(r13) 855 856 /* Do more system initializations in virtual mode */ 857 bl setup_system 858 859 /* Mark interrupts soft and hard disabled (they might be enabled 860 * in the PACA when doing hotplug) 861 */ 862 li r0,0 863 stb r0,PACASOFTIRQEN(r13) 864 li r0,PACA_IRQ_HARD_DIS 865 stb r0,PACAIRQHAPPENED(r13) 866 867 /* Generic kernel entry */ 868 bl start_kernel 869 870 /* Not reached */ 871 BUG_OPCODE 872 873/* 874 * We put a few things here that have to be page-aligned. 875 * This stuff goes at the beginning of the bss, which is page-aligned. 876 */ 877 .section ".bss" 878 879 .align PAGE_SHIFT 880 881 .globl empty_zero_page 882empty_zero_page: 883 .space PAGE_SIZE 884 885 .globl swapper_pg_dir 886swapper_pg_dir: 887 .space PGD_TABLE_SIZE 888