1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the low-level support and setup for the 16 * PowerPC-64 platform, including trap and interrupt dispatch. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License 20 * as published by the Free Software Foundation; either version 21 * 2 of the License, or (at your option) any later version. 22 */ 23 24#include <linux/threads.h> 25#include <asm/reg.h> 26#include <asm/page.h> 27#include <asm/mmu.h> 28#include <asm/ppc_asm.h> 29#include <asm/asm-offsets.h> 30#include <asm/bug.h> 31#include <asm/cputable.h> 32#include <asm/setup.h> 33#include <asm/hvcall.h> 34#include <asm/iseries/lpar_map.h> 35#include <asm/thread_info.h> 36#include <asm/firmware.h> 37 38#define DO_SOFT_DISABLE 39 40/* 41 * We layout physical memory as follows: 42 * 0x0000 - 0x00ff : Secondary processor spin code 43 * 0x0100 - 0x2fff : pSeries Interrupt prologs 44 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs 45 * 0x6000 - 0x6fff : Initial (CPU0) segment table 46 * 0x7000 - 0x7fff : FWNMI data area 47 * 0x8000 - : Early init and support code 48 */ 49 50/* 51 * SPRG Usage 52 * 53 * Register Definition 54 * 55 * SPRG0 reserved for hypervisor 56 * SPRG1 temp - used to save gpr 57 * SPRG2 temp - used to save gpr 58 * SPRG3 virt addr of paca 59 */ 60 61/* 62 * Entering into this code we make the following assumptions: 63 * For pSeries: 64 * 1. The MMU is off & open firmware is running in real mode. 65 * 2. The kernel is entered at __start 66 * 67 * For iSeries: 68 * 1. The MMU is on (as it always is for iSeries) 69 * 2. The kernel is entered at system_reset_iSeries 70 */ 71 72 .text 73 .globl _stext 74_stext: 75_GLOBAL(__start) 76 /* NOP this out unconditionally */ 77BEGIN_FTR_SECTION 78 b .__start_initialization_multiplatform 79END_FTR_SECTION(0, 1) 80 81 /* Catch branch to 0 in real mode */ 82 trap 83 84 /* Secondary processors spin on this value until it goes to 1. */ 85 .globl __secondary_hold_spinloop 86__secondary_hold_spinloop: 87 .llong 0x0 88 89 /* Secondary processors write this value with their cpu # */ 90 /* after they enter the spin loop immediately below. */ 91 .globl __secondary_hold_acknowledge 92__secondary_hold_acknowledge: 93 .llong 0x0 94 95#ifdef CONFIG_PPC_ISERIES 96 /* 97 * At offset 0x20, there is a pointer to iSeries LPAR data. 98 * This is required by the hypervisor 99 */ 100 . = 0x20 101 .llong hvReleaseData-KERNELBASE 102#endif /* CONFIG_PPC_ISERIES */ 103 104 . = 0x60 105/* 106 * The following code is used to hold secondary processors 107 * in a spin loop after they have entered the kernel, but 108 * before the bulk of the kernel has been relocated. This code 109 * is relocated to physical address 0x60 before prom_init is run. 110 * All of it must fit below the first exception vector at 0x100. 111 */ 112_GLOBAL(__secondary_hold) 113 mfmsr r24 114 ori r24,r24,MSR_RI 115 mtmsrd r24 /* RI on */ 116 117 /* Grab our physical cpu number */ 118 mr r24,r3 119 120 /* Tell the master cpu we're here */ 121 /* Relocation is off & we are located at an address less */ 122 /* than 0x100, so only need to grab low order offset. */ 123 std r24,__secondary_hold_acknowledge@l(0) 124 sync 125 126 /* All secondary cpus wait here until told to start. */ 127100: ld r4,__secondary_hold_spinloop@l(0) 128 cmpdi 0,r4,1 129 bne 100b 130 131#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 132 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init) 133 mtctr r4 134 mr r3,r24 135 bctr 136#else 137 BUG_OPCODE 138#endif 139 140/* This value is used to mark exception frames on the stack. */ 141 .section ".toc","aw" 142exception_marker: 143 .tc ID_72656773_68657265[TC],0x7265677368657265 144 .text 145 146/* 147 * The following macros define the code that appears as 148 * the prologue to each of the exception handlers. They 149 * are split into two parts to allow a single kernel binary 150 * to be used for pSeries and iSeries. 151 * LOL. One day... - paulus 152 */ 153 154/* 155 * We make as much of the exception code common between native 156 * exception handlers (including pSeries LPAR) and iSeries LPAR 157 * implementations as possible. 158 */ 159 160/* 161 * This is the start of the interrupt handlers for pSeries 162 * This code runs with relocation off. 163 */ 164#define EX_R9 0 165#define EX_R10 8 166#define EX_R11 16 167#define EX_R12 24 168#define EX_R13 32 169#define EX_SRR0 40 170#define EX_DAR 48 171#define EX_DSISR 56 172#define EX_CCR 60 173#define EX_R3 64 174#define EX_LR 72 175 176/* 177 * We're short on space and time in the exception prolog, so we can't 178 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the 179 * low halfword of the address, but for Kdump we need the whole low 180 * word. 181 */ 182#ifdef CONFIG_CRASH_DUMP 183#define LOAD_HANDLER(reg, label) \ 184 oris reg,reg,(label)@h; /* virt addr of handler ... */ \ 185 ori reg,reg,(label)@l; /* .. and the rest */ 186#else 187#define LOAD_HANDLER(reg, label) \ 188 ori reg,reg,(label)@l; /* virt addr of handler ... */ 189#endif 190 191/* 192 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode. 193 * The firmware calls the registered system_reset_fwnmi and 194 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run 195 * a 32bit application at the time of the event. 196 * This firmware bug is present on POWER4 and JS20. 197 */ 198#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \ 199 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 200 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 201 std r10,area+EX_R10(r13); \ 202 std r11,area+EX_R11(r13); \ 203 std r12,area+EX_R12(r13); \ 204 mfspr r9,SPRN_SPRG1; \ 205 std r9,area+EX_R13(r13); \ 206 mfcr r9; \ 207 clrrdi r12,r13,32; /* get high part of &label */ \ 208 mfmsr r10; \ 209 /* force 64bit mode */ \ 210 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \ 211 rldimi r10,r11,61,0; /* insert into top 3 bits */ \ 212 /* done 64bit mode */ \ 213 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 214 LOAD_HANDLER(r12,label) \ 215 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 216 mtspr SPRN_SRR0,r12; \ 217 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 218 mtspr SPRN_SRR1,r10; \ 219 rfid; \ 220 b . /* prevent speculative execution */ 221 222#define EXCEPTION_PROLOG_PSERIES(area, label) \ 223 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 224 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 225 std r10,area+EX_R10(r13); \ 226 std r11,area+EX_R11(r13); \ 227 std r12,area+EX_R12(r13); \ 228 mfspr r9,SPRN_SPRG1; \ 229 std r9,area+EX_R13(r13); \ 230 mfcr r9; \ 231 clrrdi r12,r13,32; /* get high part of &label */ \ 232 mfmsr r10; \ 233 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 234 LOAD_HANDLER(r12,label) \ 235 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 236 mtspr SPRN_SRR0,r12; \ 237 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 238 mtspr SPRN_SRR1,r10; \ 239 rfid; \ 240 b . /* prevent speculative execution */ 241 242/* 243 * This is the start of the interrupt handlers for iSeries 244 * This code runs with relocation on. 245 */ 246#define EXCEPTION_PROLOG_ISERIES_1(area) \ 247 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 248 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 249 std r10,area+EX_R10(r13); \ 250 std r11,area+EX_R11(r13); \ 251 std r12,area+EX_R12(r13); \ 252 mfspr r9,SPRN_SPRG1; \ 253 std r9,area+EX_R13(r13); \ 254 mfcr r9 255 256#define EXCEPTION_PROLOG_ISERIES_2 \ 257 mfmsr r10; \ 258 ld r12,PACALPPACAPTR(r13); \ 259 ld r11,LPPACASRR0(r12); \ 260 ld r12,LPPACASRR1(r12); \ 261 ori r10,r10,MSR_RI; \ 262 mtmsrd r10,1 263 264/* 265 * The common exception prolog is used for all except a few exceptions 266 * such as a segment miss on a kernel address. We have to be prepared 267 * to take another exception from the point where we first touch the 268 * kernel stack onwards. 269 * 270 * On entry r13 points to the paca, r9-r13 are saved in the paca, 271 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 272 * SRR1, and relocation is on. 273 */ 274#define EXCEPTION_PROLOG_COMMON(n, area) \ 275 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 276 mr r10,r1; /* Save r1 */ \ 277 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 278 beq- 1f; \ 279 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 2801: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 281 bge- cr1,2f; /* abort if it is */ \ 282 b 3f; \ 2832: li r1,(n); /* will be reloaded later */ \ 284 sth r1,PACA_TRAP_SAVE(r13); \ 285 b bad_stack; \ 2863: std r9,_CCR(r1); /* save CR in stackframe */ \ 287 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 288 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 289 std r10,0(r1); /* make stack chain pointer */ \ 290 std r0,GPR0(r1); /* save r0 in stackframe */ \ 291 std r10,GPR1(r1); /* save r1 in stackframe */ \ 292 ACCOUNT_CPU_USER_ENTRY(r9, r10); \ 293 std r2,GPR2(r1); /* save r2 in stackframe */ \ 294 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 295 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 296 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 297 ld r10,area+EX_R10(r13); \ 298 std r9,GPR9(r1); \ 299 std r10,GPR10(r1); \ 300 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 301 ld r10,area+EX_R12(r13); \ 302 ld r11,area+EX_R13(r13); \ 303 std r9,GPR11(r1); \ 304 std r10,GPR12(r1); \ 305 std r11,GPR13(r1); \ 306 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 307 mflr r9; /* save LR in stackframe */ \ 308 std r9,_LINK(r1); \ 309 mfctr r10; /* save CTR in stackframe */ \ 310 std r10,_CTR(r1); \ 311 lbz r10,PACASOFTIRQEN(r13); \ 312 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 313 std r10,SOFTE(r1); \ 314 std r11,_XER(r1); \ 315 li r9,(n)+1; \ 316 std r9,_TRAP(r1); /* set trap number */ \ 317 li r10,0; \ 318 ld r11,exception_marker@toc(r2); \ 319 std r10,RESULT(r1); /* clear regs->result */ \ 320 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 321 322/* 323 * Exception vectors. 324 */ 325#define STD_EXCEPTION_PSERIES(n, label) \ 326 . = n; \ 327 .globl label##_pSeries; \ 328label##_pSeries: \ 329 HMT_MEDIUM; \ 330 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 331 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 332 333#define HSTD_EXCEPTION_PSERIES(n, label) \ 334 . = n; \ 335 .globl label##_pSeries; \ 336label##_pSeries: \ 337 HMT_MEDIUM; \ 338 mtspr SPRN_SPRG1,r20; /* save r20 */ \ 339 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ 340 mtspr SPRN_SRR0,r20; \ 341 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \ 342 mtspr SPRN_SRR1,r20; \ 343 mfspr r20,SPRN_SPRG1; /* restore r20 */ \ 344 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 345 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 346 347 348#define MASKABLE_EXCEPTION_PSERIES(n, label) \ 349 . = n; \ 350 .globl label##_pSeries; \ 351label##_pSeries: \ 352 HMT_MEDIUM; \ 353 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 354 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 355 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ 356 std r10,PACA_EXGEN+EX_R10(r13); \ 357 lbz r10,PACASOFTIRQEN(r13); \ 358 mfcr r9; \ 359 cmpwi r10,0; \ 360 beq masked_interrupt; \ 361 mfspr r10,SPRN_SPRG1; \ 362 std r10,PACA_EXGEN+EX_R13(r13); \ 363 std r11,PACA_EXGEN+EX_R11(r13); \ 364 std r12,PACA_EXGEN+EX_R12(r13); \ 365 clrrdi r12,r13,32; /* get high part of &label */ \ 366 mfmsr r10; \ 367 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 368 LOAD_HANDLER(r12,label##_common) \ 369 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 370 mtspr SPRN_SRR0,r12; \ 371 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 372 mtspr SPRN_SRR1,r10; \ 373 rfid; \ 374 b . /* prevent speculative execution */ 375 376#define STD_EXCEPTION_ISERIES(n, label, area) \ 377 .globl label##_iSeries; \ 378label##_iSeries: \ 379 HMT_MEDIUM; \ 380 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 381 EXCEPTION_PROLOG_ISERIES_1(area); \ 382 EXCEPTION_PROLOG_ISERIES_2; \ 383 b label##_common 384 385#define MASKABLE_EXCEPTION_ISERIES(n, label) \ 386 .globl label##_iSeries; \ 387label##_iSeries: \ 388 HMT_MEDIUM; \ 389 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 390 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ 391 lbz r10,PACASOFTIRQEN(r13); \ 392 cmpwi 0,r10,0; \ 393 beq- label##_iSeries_masked; \ 394 EXCEPTION_PROLOG_ISERIES_2; \ 395 b label##_common; \ 396 397#ifdef CONFIG_PPC_ISERIES 398#define DISABLE_INTS \ 399 li r11,0; \ 400 stb r11,PACASOFTIRQEN(r13); \ 401BEGIN_FW_FTR_SECTION; \ 402 stb r11,PACAHARDIRQEN(r13); \ 403END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ 404BEGIN_FW_FTR_SECTION; \ 405 mfmsr r10; \ 406 ori r10,r10,MSR_EE; \ 407 mtmsrd r10,1; \ 408END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 409 410#else 411#define DISABLE_INTS \ 412 li r11,0; \ 413 stb r11,PACASOFTIRQEN(r13); \ 414 stb r11,PACAHARDIRQEN(r13) 415 416#endif /* CONFIG_PPC_ISERIES */ 417 418#define ENABLE_INTS \ 419 ld r12,_MSR(r1); \ 420 mfmsr r11; \ 421 rlwimi r11,r12,0,MSR_EE; \ 422 mtmsrd r11,1 423 424#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 425 .align 7; \ 426 .globl label##_common; \ 427label##_common: \ 428 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 429 DISABLE_INTS; \ 430 bl .save_nvgprs; \ 431 addi r3,r1,STACK_FRAME_OVERHEAD; \ 432 bl hdlr; \ 433 b .ret_from_except 434 435/* 436 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 437 * in the idle task and therefore need the special idle handling. 438 */ 439#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \ 440 .align 7; \ 441 .globl label##_common; \ 442label##_common: \ 443 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 444 FINISH_NAP; \ 445 DISABLE_INTS; \ 446 bl .save_nvgprs; \ 447 addi r3,r1,STACK_FRAME_OVERHEAD; \ 448 bl hdlr; \ 449 b .ret_from_except 450 451#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ 452 .align 7; \ 453 .globl label##_common; \ 454label##_common: \ 455 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 456 FINISH_NAP; \ 457 DISABLE_INTS; \ 458 bl .ppc64_runlatch_on; \ 459 addi r3,r1,STACK_FRAME_OVERHEAD; \ 460 bl hdlr; \ 461 b .ret_from_except_lite 462 463/* 464 * When the idle code in power4_idle puts the CPU into NAP mode, 465 * it has to do so in a loop, and relies on the external interrupt 466 * and decrementer interrupt entry code to get it out of the loop. 467 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 468 * to signal that it is in the loop and needs help to get out. 469 */ 470#ifdef CONFIG_PPC_970_NAP 471#define FINISH_NAP \ 472BEGIN_FTR_SECTION \ 473 clrrdi r11,r1,THREAD_SHIFT; \ 474 ld r9,TI_LOCAL_FLAGS(r11); \ 475 andi. r10,r9,_TLF_NAPPING; \ 476 bnel power4_fixup_nap; \ 477END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 478#else 479#define FINISH_NAP 480#endif 481 482/* 483 * Start of pSeries system interrupt routines 484 */ 485 . = 0x100 486 .globl __start_interrupts 487__start_interrupts: 488 489 STD_EXCEPTION_PSERIES(0x100, system_reset) 490 491 . = 0x200 492_machine_check_pSeries: 493 HMT_MEDIUM 494 mtspr SPRN_SPRG1,r13 /* save r13 */ 495 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 496 497 . = 0x300 498 .globl data_access_pSeries 499data_access_pSeries: 500 HMT_MEDIUM 501 mtspr SPRN_SPRG1,r13 502BEGIN_FTR_SECTION 503 mtspr SPRN_SPRG2,r12 504 mfspr r13,SPRN_DAR 505 mfspr r12,SPRN_DSISR 506 srdi r13,r13,60 507 rlwimi r13,r12,16,0x20 508 mfcr r12 509 cmpwi r13,0x2c 510 beq do_stab_bolted_pSeries 511 mtcrf 0x80,r12 512 mfspr r12,SPRN_SPRG2 513END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 514 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 515 516 . = 0x380 517 .globl data_access_slb_pSeries 518data_access_slb_pSeries: 519 HMT_MEDIUM 520 mtspr SPRN_SPRG1,r13 521 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 522 std r3,PACA_EXSLB+EX_R3(r13) 523 mfspr r3,SPRN_DAR 524 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 525 mfcr r9 526#ifdef __DISABLED__ 527 /* Keep that around for when we re-implement dynamic VSIDs */ 528 cmpdi r3,0 529 bge slb_miss_user_pseries 530#endif /* __DISABLED__ */ 531 std r10,PACA_EXSLB+EX_R10(r13) 532 std r11,PACA_EXSLB+EX_R11(r13) 533 std r12,PACA_EXSLB+EX_R12(r13) 534 mfspr r10,SPRN_SPRG1 535 std r10,PACA_EXSLB+EX_R13(r13) 536 mfspr r12,SPRN_SRR1 /* and SRR1 */ 537 b .slb_miss_realmode /* Rel. branch works in real mode */ 538 539 STD_EXCEPTION_PSERIES(0x400, instruction_access) 540 541 . = 0x480 542 .globl instruction_access_slb_pSeries 543instruction_access_slb_pSeries: 544 HMT_MEDIUM 545 mtspr SPRN_SPRG1,r13 546 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 547 std r3,PACA_EXSLB+EX_R3(r13) 548 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 549 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 550 mfcr r9 551#ifdef __DISABLED__ 552 /* Keep that around for when we re-implement dynamic VSIDs */ 553 cmpdi r3,0 554 bge slb_miss_user_pseries 555#endif /* __DISABLED__ */ 556 std r10,PACA_EXSLB+EX_R10(r13) 557 std r11,PACA_EXSLB+EX_R11(r13) 558 std r12,PACA_EXSLB+EX_R12(r13) 559 mfspr r10,SPRN_SPRG1 560 std r10,PACA_EXSLB+EX_R13(r13) 561 mfspr r12,SPRN_SRR1 /* and SRR1 */ 562 b .slb_miss_realmode /* Rel. branch works in real mode */ 563 564 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) 565 STD_EXCEPTION_PSERIES(0x600, alignment) 566 STD_EXCEPTION_PSERIES(0x700, program_check) 567 STD_EXCEPTION_PSERIES(0x800, fp_unavailable) 568 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) 569 STD_EXCEPTION_PSERIES(0xa00, trap_0a) 570 STD_EXCEPTION_PSERIES(0xb00, trap_0b) 571 572 . = 0xc00 573 .globl system_call_pSeries 574system_call_pSeries: 575 HMT_MEDIUM 576 mr r9,r13 577 mfmsr r10 578 mfspr r13,SPRN_SPRG3 579 mfspr r11,SPRN_SRR0 580 clrrdi r12,r13,32 581 oris r12,r12,system_call_common@h 582 ori r12,r12,system_call_common@l 583 mtspr SPRN_SRR0,r12 584 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 585 mfspr r12,SPRN_SRR1 586 mtspr SPRN_SRR1,r10 587 rfid 588 b . /* prevent speculative execution */ 589 590 STD_EXCEPTION_PSERIES(0xd00, single_step) 591 STD_EXCEPTION_PSERIES(0xe00, trap_0e) 592 593 /* We need to deal with the Altivec unavailable exception 594 * here which is at 0xf20, thus in the middle of the 595 * prolog code of the PerformanceMonitor one. A little 596 * trickery is thus necessary 597 */ 598 . = 0xf00 599 b performance_monitor_pSeries 600 601 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) 602 603#ifdef CONFIG_CBE_RAS 604 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) 605#endif /* CONFIG_CBE_RAS */ 606 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) 607#ifdef CONFIG_CBE_RAS 608 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) 609#endif /* CONFIG_CBE_RAS */ 610 STD_EXCEPTION_PSERIES(0x1700, altivec_assist) 611#ifdef CONFIG_CBE_RAS 612 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) 613#endif /* CONFIG_CBE_RAS */ 614 615 . = 0x3000 616 617/*** pSeries interrupt support ***/ 618 619 /* moved from 0xf00 */ 620 STD_EXCEPTION_PSERIES(., performance_monitor) 621 622/* 623 * An interrupt came in while soft-disabled; clear EE in SRR1, 624 * clear paca->hard_enabled and return. 625 */ 626masked_interrupt: 627 stb r10,PACAHARDIRQEN(r13) 628 mtcrf 0x80,r9 629 ld r9,PACA_EXGEN+EX_R9(r13) 630 mfspr r10,SPRN_SRR1 631 rldicl r10,r10,48,1 /* clear MSR_EE */ 632 rotldi r10,r10,16 633 mtspr SPRN_SRR1,r10 634 ld r10,PACA_EXGEN+EX_R10(r13) 635 mfspr r13,SPRN_SPRG1 636 rfid 637 b . 638 639 .align 7 640do_stab_bolted_pSeries: 641 mtcrf 0x80,r12 642 mfspr r12,SPRN_SPRG2 643 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 644 645/* 646 * We have some room here we use that to put 647 * the peries slb miss user trampoline code so it's reasonably 648 * away from slb_miss_user_common to avoid problems with rfid 649 * 650 * This is used for when the SLB miss handler has to go virtual, 651 * which doesn't happen for now anymore but will once we re-implement 652 * dynamic VSIDs for shared page tables 653 */ 654#ifdef __DISABLED__ 655slb_miss_user_pseries: 656 std r10,PACA_EXGEN+EX_R10(r13) 657 std r11,PACA_EXGEN+EX_R11(r13) 658 std r12,PACA_EXGEN+EX_R12(r13) 659 mfspr r10,SPRG1 660 ld r11,PACA_EXSLB+EX_R9(r13) 661 ld r12,PACA_EXSLB+EX_R3(r13) 662 std r10,PACA_EXGEN+EX_R13(r13) 663 std r11,PACA_EXGEN+EX_R9(r13) 664 std r12,PACA_EXGEN+EX_R3(r13) 665 clrrdi r12,r13,32 666 mfmsr r10 667 mfspr r11,SRR0 /* save SRR0 */ 668 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ 669 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 670 mtspr SRR0,r12 671 mfspr r12,SRR1 /* and SRR1 */ 672 mtspr SRR1,r10 673 rfid 674 b . /* prevent spec. execution */ 675#endif /* __DISABLED__ */ 676 677/* 678 * Vectors for the FWNMI option. Share common code. 679 */ 680 .globl system_reset_fwnmi 681 .align 7 682system_reset_fwnmi: 683 HMT_MEDIUM 684 mtspr SPRN_SPRG1,r13 /* save r13 */ 685 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common) 686 687 .globl machine_check_fwnmi 688 .align 7 689machine_check_fwnmi: 690 HMT_MEDIUM 691 mtspr SPRN_SPRG1,r13 /* save r13 */ 692 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common) 693 694#ifdef CONFIG_PPC_ISERIES 695/*** ISeries-LPAR interrupt handlers ***/ 696 697 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) 698 699 .globl data_access_iSeries 700data_access_iSeries: 701 mtspr SPRN_SPRG1,r13 702BEGIN_FTR_SECTION 703 mtspr SPRN_SPRG2,r12 704 mfspr r13,SPRN_DAR 705 mfspr r12,SPRN_DSISR 706 srdi r13,r13,60 707 rlwimi r13,r12,16,0x20 708 mfcr r12 709 cmpwi r13,0x2c 710 beq .do_stab_bolted_iSeries 711 mtcrf 0x80,r12 712 mfspr r12,SPRN_SPRG2 713END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 714 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) 715 EXCEPTION_PROLOG_ISERIES_2 716 b data_access_common 717 718.do_stab_bolted_iSeries: 719 mtcrf 0x80,r12 720 mfspr r12,SPRN_SPRG2 721 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) 722 EXCEPTION_PROLOG_ISERIES_2 723 b .do_stab_bolted 724 725 .globl data_access_slb_iSeries 726data_access_slb_iSeries: 727 mtspr SPRN_SPRG1,r13 /* save r13 */ 728 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 729 std r3,PACA_EXSLB+EX_R3(r13) 730 mfspr r3,SPRN_DAR 731 std r9,PACA_EXSLB+EX_R9(r13) 732 mfcr r9 733#ifdef __DISABLED__ 734 cmpdi r3,0 735 bge slb_miss_user_iseries 736#endif 737 std r10,PACA_EXSLB+EX_R10(r13) 738 std r11,PACA_EXSLB+EX_R11(r13) 739 std r12,PACA_EXSLB+EX_R12(r13) 740 mfspr r10,SPRN_SPRG1 741 std r10,PACA_EXSLB+EX_R13(r13) 742 ld r12,PACALPPACAPTR(r13) 743 ld r12,LPPACASRR1(r12) 744 b .slb_miss_realmode 745 746 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) 747 748 .globl instruction_access_slb_iSeries 749instruction_access_slb_iSeries: 750 mtspr SPRN_SPRG1,r13 /* save r13 */ 751 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 752 std r3,PACA_EXSLB+EX_R3(r13) 753 ld r3,PACALPPACAPTR(r13) 754 ld r3,LPPACASRR0(r3) /* get SRR0 value */ 755 std r9,PACA_EXSLB+EX_R9(r13) 756 mfcr r9 757#ifdef __DISABLED__ 758 cmpdi r3,0 759 bge .slb_miss_user_iseries 760#endif 761 std r10,PACA_EXSLB+EX_R10(r13) 762 std r11,PACA_EXSLB+EX_R11(r13) 763 std r12,PACA_EXSLB+EX_R12(r13) 764 mfspr r10,SPRN_SPRG1 765 std r10,PACA_EXSLB+EX_R13(r13) 766 ld r12,PACALPPACAPTR(r13) 767 ld r12,LPPACASRR1(r12) 768 b .slb_miss_realmode 769 770#ifdef __DISABLED__ 771slb_miss_user_iseries: 772 std r10,PACA_EXGEN+EX_R10(r13) 773 std r11,PACA_EXGEN+EX_R11(r13) 774 std r12,PACA_EXGEN+EX_R12(r13) 775 mfspr r10,SPRG1 776 ld r11,PACA_EXSLB+EX_R9(r13) 777 ld r12,PACA_EXSLB+EX_R3(r13) 778 std r10,PACA_EXGEN+EX_R13(r13) 779 std r11,PACA_EXGEN+EX_R9(r13) 780 std r12,PACA_EXGEN+EX_R3(r13) 781 EXCEPTION_PROLOG_ISERIES_2 782 b slb_miss_user_common 783#endif 784 785 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) 786 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) 787 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) 788 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) 789 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) 790 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) 791 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) 792 793 .globl system_call_iSeries 794system_call_iSeries: 795 mr r9,r13 796 mfspr r13,SPRN_SPRG3 797 EXCEPTION_PROLOG_ISERIES_2 798 b system_call_common 799 800 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) 801 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) 802 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) 803 804 .globl system_reset_iSeries 805system_reset_iSeries: 806 mfspr r13,SPRN_SPRG3 /* Get paca address */ 807 mfmsr r24 808 ori r24,r24,MSR_RI 809 mtmsrd r24 /* RI on */ 810 lhz r24,PACAPACAINDEX(r13) /* Get processor # */ 811 cmpwi 0,r24,0 /* Are we processor 0? */ 812 bne 1f 813 b .__start_initialization_iSeries /* Start up the first processor */ 8141: mfspr r4,SPRN_CTRLF 815 li r5,CTRL_RUNLATCH /* Turn off the run light */ 816 andc r4,r4,r5 817 mtspr SPRN_CTRLT,r4 818 8191: 820 HMT_LOW 821#ifdef CONFIG_SMP 822 lbz r23,PACAPROCSTART(r13) /* Test if this processor 823 * should start */ 824 sync 825 LOAD_REG_IMMEDIATE(r3,current_set) 826 sldi r28,r24,3 /* get current_set[cpu#] */ 827 ldx r3,r3,r28 828 addi r1,r3,THREAD_SIZE 829 subi r1,r1,STACK_FRAME_OVERHEAD 830 831 cmpwi 0,r23,0 832 beq iSeries_secondary_smp_loop /* Loop until told to go */ 833 bne __secondary_start /* Loop until told to go */ 834iSeries_secondary_smp_loop: 835 /* Let the Hypervisor know we are alive */ 836 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ 837 lis r3,0x8002 838 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ 839#else /* CONFIG_SMP */ 840 /* Yield the processor. This is required for non-SMP kernels 841 which are running on multi-threaded machines. */ 842 lis r3,0x8000 843 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ 844 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ 845 li r4,0 /* "yield timed" */ 846 li r5,-1 /* "yield forever" */ 847#endif /* CONFIG_SMP */ 848 li r0,-1 /* r0=-1 indicates a Hypervisor call */ 849 sc /* Invoke the hypervisor via a system call */ 850 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ 851 b 1b /* If SMP not configured, secondaries 852 * loop forever */ 853 854decrementer_iSeries_masked: 855 /* We may not have a valid TOC pointer in here. */ 856 li r11,1 857 ld r12,PACALPPACAPTR(r13) 858 stb r11,LPPACADECRINT(r12) 859 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy) 860 lwz r12,0(r12) 861 mtspr SPRN_DEC,r12 862 /* fall through */ 863 864hardware_interrupt_iSeries_masked: 865 mtcrf 0x80,r9 /* Restore regs */ 866 ld r12,PACALPPACAPTR(r13) 867 ld r11,LPPACASRR0(r12) 868 ld r12,LPPACASRR1(r12) 869 mtspr SPRN_SRR0,r11 870 mtspr SPRN_SRR1,r12 871 ld r9,PACA_EXGEN+EX_R9(r13) 872 ld r10,PACA_EXGEN+EX_R10(r13) 873 ld r11,PACA_EXGEN+EX_R11(r13) 874 ld r12,PACA_EXGEN+EX_R12(r13) 875 ld r13,PACA_EXGEN+EX_R13(r13) 876 rfid 877 b . /* prevent speculative execution */ 878#endif /* CONFIG_PPC_ISERIES */ 879 880/*** Common interrupt handlers ***/ 881 882 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) 883 884 /* 885 * Machine check is different because we use a different 886 * save area: PACA_EXMC instead of PACA_EXGEN. 887 */ 888 .align 7 889 .globl machine_check_common 890machine_check_common: 891 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 892 FINISH_NAP 893 DISABLE_INTS 894 bl .save_nvgprs 895 addi r3,r1,STACK_FRAME_OVERHEAD 896 bl .machine_check_exception 897 b .ret_from_except 898 899 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) 900 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) 901 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) 902 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) 903 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) 904 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) 905 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) 906#ifdef CONFIG_ALTIVEC 907 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) 908#else 909 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) 910#endif 911#ifdef CONFIG_CBE_RAS 912 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) 913 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) 914 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) 915#endif /* CONFIG_CBE_RAS */ 916 917/* 918 * Here we have detected that the kernel stack pointer is bad. 919 * R9 contains the saved CR, r13 points to the paca, 920 * r10 contains the (bad) kernel stack pointer, 921 * r11 and r12 contain the saved SRR0 and SRR1. 922 * We switch to using an emergency stack, save the registers there, 923 * and call kernel_bad_stack(), which panics. 924 */ 925bad_stack: 926 ld r1,PACAEMERGSP(r13) 927 subi r1,r1,64+INT_FRAME_SIZE 928 std r9,_CCR(r1) 929 std r10,GPR1(r1) 930 std r11,_NIP(r1) 931 std r12,_MSR(r1) 932 mfspr r11,SPRN_DAR 933 mfspr r12,SPRN_DSISR 934 std r11,_DAR(r1) 935 std r12,_DSISR(r1) 936 mflr r10 937 mfctr r11 938 mfxer r12 939 std r10,_LINK(r1) 940 std r11,_CTR(r1) 941 std r12,_XER(r1) 942 SAVE_GPR(0,r1) 943 SAVE_GPR(2,r1) 944 SAVE_4GPRS(3,r1) 945 SAVE_2GPRS(7,r1) 946 SAVE_10GPRS(12,r1) 947 SAVE_10GPRS(22,r1) 948 lhz r12,PACA_TRAP_SAVE(r13) 949 std r12,_TRAP(r1) 950 addi r11,r1,INT_FRAME_SIZE 951 std r11,0(r1) 952 li r12,0 953 std r12,0(r11) 954 ld r2,PACATOC(r13) 9551: addi r3,r1,STACK_FRAME_OVERHEAD 956 bl .kernel_bad_stack 957 b 1b 958 959/* 960 * Return from an exception with minimal checks. 961 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. 962 * If interrupts have been enabled, or anything has been 963 * done that might have changed the scheduling status of 964 * any task or sent any task a signal, you should use 965 * ret_from_except or ret_from_except_lite instead of this. 966 */ 967fast_exc_return_irq: /* restores irq state too */ 968 ld r3,SOFTE(r1) 969 ld r12,_MSR(r1) 970 stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */ 971 rldicl r4,r12,49,63 /* get MSR_EE to LSB */ 972 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ 973 b 1f 974 975 .globl fast_exception_return 976fast_exception_return: 977 ld r12,_MSR(r1) 9781: ld r11,_NIP(r1) 979 andi. r3,r12,MSR_RI /* check if RI is set */ 980 beq- unrecov_fer 981 982#ifdef CONFIG_VIRT_CPU_ACCOUNTING 983 andi. r3,r12,MSR_PR 984 beq 2f 985 ACCOUNT_CPU_USER_EXIT(r3, r4) 9862: 987#endif 988 989 ld r3,_CCR(r1) 990 ld r4,_LINK(r1) 991 ld r5,_CTR(r1) 992 ld r6,_XER(r1) 993 mtcr r3 994 mtlr r4 995 mtctr r5 996 mtxer r6 997 REST_GPR(0, r1) 998 REST_8GPRS(2, r1) 999 1000 mfmsr r10 1001 rldicl r10,r10,48,1 /* clear EE */ 1002 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ 1003 mtmsrd r10,1 1004 1005 mtspr SPRN_SRR1,r12 1006 mtspr SPRN_SRR0,r11 1007 REST_4GPRS(10, r1) 1008 ld r1,GPR1(r1) 1009 rfid 1010 b . /* prevent speculative execution */ 1011 1012unrecov_fer: 1013 bl .save_nvgprs 10141: addi r3,r1,STACK_FRAME_OVERHEAD 1015 bl .unrecoverable_exception 1016 b 1b 1017 1018/* 1019 * Here r13 points to the paca, r9 contains the saved CR, 1020 * SRR0 and SRR1 are saved in r11 and r12, 1021 * r9 - r13 are saved in paca->exgen. 1022 */ 1023 .align 7 1024 .globl data_access_common 1025data_access_common: 1026 mfspr r10,SPRN_DAR 1027 std r10,PACA_EXGEN+EX_DAR(r13) 1028 mfspr r10,SPRN_DSISR 1029 stw r10,PACA_EXGEN+EX_DSISR(r13) 1030 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 1031 ld r3,PACA_EXGEN+EX_DAR(r13) 1032 lwz r4,PACA_EXGEN+EX_DSISR(r13) 1033 li r5,0x300 1034 b .do_hash_page /* Try to handle as hpte fault */ 1035 1036 .align 7 1037 .globl instruction_access_common 1038instruction_access_common: 1039 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 1040 ld r3,_NIP(r1) 1041 andis. r4,r12,0x5820 1042 li r5,0x400 1043 b .do_hash_page /* Try to handle as hpte fault */ 1044 1045/* 1046 * Here is the common SLB miss user that is used when going to virtual 1047 * mode for SLB misses, that is currently not used 1048 */ 1049#ifdef __DISABLED__ 1050 .align 7 1051 .globl slb_miss_user_common 1052slb_miss_user_common: 1053 mflr r10 1054 std r3,PACA_EXGEN+EX_DAR(r13) 1055 stw r9,PACA_EXGEN+EX_CCR(r13) 1056 std r10,PACA_EXGEN+EX_LR(r13) 1057 std r11,PACA_EXGEN+EX_SRR0(r13) 1058 bl .slb_allocate_user 1059 1060 ld r10,PACA_EXGEN+EX_LR(r13) 1061 ld r3,PACA_EXGEN+EX_R3(r13) 1062 lwz r9,PACA_EXGEN+EX_CCR(r13) 1063 ld r11,PACA_EXGEN+EX_SRR0(r13) 1064 mtlr r10 1065 beq- slb_miss_fault 1066 1067 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 1068 beq- unrecov_user_slb 1069 mfmsr r10 1070 1071.machine push 1072.machine "power4" 1073 mtcrf 0x80,r9 1074.machine pop 1075 1076 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ 1077 mtmsrd r10,1 1078 1079 mtspr SRR0,r11 1080 mtspr SRR1,r12 1081 1082 ld r9,PACA_EXGEN+EX_R9(r13) 1083 ld r10,PACA_EXGEN+EX_R10(r13) 1084 ld r11,PACA_EXGEN+EX_R11(r13) 1085 ld r12,PACA_EXGEN+EX_R12(r13) 1086 ld r13,PACA_EXGEN+EX_R13(r13) 1087 rfid 1088 b . 1089 1090slb_miss_fault: 1091 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) 1092 ld r4,PACA_EXGEN+EX_DAR(r13) 1093 li r5,0 1094 std r4,_DAR(r1) 1095 std r5,_DSISR(r1) 1096 b handle_page_fault 1097 1098unrecov_user_slb: 1099 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) 1100 DISABLE_INTS 1101 bl .save_nvgprs 11021: addi r3,r1,STACK_FRAME_OVERHEAD 1103 bl .unrecoverable_exception 1104 b 1b 1105 1106#endif /* __DISABLED__ */ 1107 1108 1109/* 1110 * r13 points to the PACA, r9 contains the saved CR, 1111 * r12 contain the saved SRR1, SRR0 is still ready for return 1112 * r3 has the faulting address 1113 * r9 - r13 are saved in paca->exslb. 1114 * r3 is saved in paca->slb_r3 1115 * We assume we aren't going to take any exceptions during this procedure. 1116 */ 1117_GLOBAL(slb_miss_realmode) 1118 mflr r10 1119 1120 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 1121 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 1122 1123 bl .slb_allocate_realmode 1124 1125 /* All done -- return from exception. */ 1126 1127 ld r10,PACA_EXSLB+EX_LR(r13) 1128 ld r3,PACA_EXSLB+EX_R3(r13) 1129 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 1130#ifdef CONFIG_PPC_ISERIES 1131BEGIN_FW_FTR_SECTION 1132 ld r11,PACALPPACAPTR(r13) 1133 ld r11,LPPACASRR0(r11) /* get SRR0 value */ 1134END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1135#endif /* CONFIG_PPC_ISERIES */ 1136 1137 mtlr r10 1138 1139 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 1140 beq- unrecov_slb 1141 1142.machine push 1143.machine "power4" 1144 mtcrf 0x80,r9 1145 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 1146.machine pop 1147 1148#ifdef CONFIG_PPC_ISERIES 1149BEGIN_FW_FTR_SECTION 1150 mtspr SPRN_SRR0,r11 1151 mtspr SPRN_SRR1,r12 1152END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1153#endif /* CONFIG_PPC_ISERIES */ 1154 ld r9,PACA_EXSLB+EX_R9(r13) 1155 ld r10,PACA_EXSLB+EX_R10(r13) 1156 ld r11,PACA_EXSLB+EX_R11(r13) 1157 ld r12,PACA_EXSLB+EX_R12(r13) 1158 ld r13,PACA_EXSLB+EX_R13(r13) 1159 rfid 1160 b . /* prevent speculative execution */ 1161 1162unrecov_slb: 1163 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 1164 DISABLE_INTS 1165 bl .save_nvgprs 11661: addi r3,r1,STACK_FRAME_OVERHEAD 1167 bl .unrecoverable_exception 1168 b 1b 1169 1170 .align 7 1171 .globl hardware_interrupt_common 1172 .globl hardware_interrupt_entry 1173hardware_interrupt_common: 1174 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) 1175 FINISH_NAP 1176hardware_interrupt_entry: 1177 DISABLE_INTS 1178 bl .ppc64_runlatch_on 1179 addi r3,r1,STACK_FRAME_OVERHEAD 1180 bl .do_IRQ 1181 b .ret_from_except_lite 1182 1183#ifdef CONFIG_PPC_970_NAP 1184power4_fixup_nap: 1185 andc r9,r9,r10 1186 std r9,TI_LOCAL_FLAGS(r11) 1187 ld r10,_LINK(r1) /* make idle task do the */ 1188 std r10,_NIP(r1) /* equivalent of a blr */ 1189 blr 1190#endif 1191 1192 .align 7 1193 .globl alignment_common 1194alignment_common: 1195 mfspr r10,SPRN_DAR 1196 std r10,PACA_EXGEN+EX_DAR(r13) 1197 mfspr r10,SPRN_DSISR 1198 stw r10,PACA_EXGEN+EX_DSISR(r13) 1199 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 1200 ld r3,PACA_EXGEN+EX_DAR(r13) 1201 lwz r4,PACA_EXGEN+EX_DSISR(r13) 1202 std r3,_DAR(r1) 1203 std r4,_DSISR(r1) 1204 bl .save_nvgprs 1205 addi r3,r1,STACK_FRAME_OVERHEAD 1206 ENABLE_INTS 1207 bl .alignment_exception 1208 b .ret_from_except 1209 1210 .align 7 1211 .globl program_check_common 1212program_check_common: 1213 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 1214 bl .save_nvgprs 1215 addi r3,r1,STACK_FRAME_OVERHEAD 1216 ENABLE_INTS 1217 bl .program_check_exception 1218 b .ret_from_except 1219 1220 .align 7 1221 .globl fp_unavailable_common 1222fp_unavailable_common: 1223 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 1224 bne 1f /* if from user, just load it up */ 1225 bl .save_nvgprs 1226 addi r3,r1,STACK_FRAME_OVERHEAD 1227 ENABLE_INTS 1228 bl .kernel_fp_unavailable_exception 1229 BUG_OPCODE 12301: b .load_up_fpu 1231 1232 .align 7 1233 .globl altivec_unavailable_common 1234altivec_unavailable_common: 1235 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1236#ifdef CONFIG_ALTIVEC 1237BEGIN_FTR_SECTION 1238 bne .load_up_altivec /* if from user, just load it up */ 1239END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1240#endif 1241 bl .save_nvgprs 1242 addi r3,r1,STACK_FRAME_OVERHEAD 1243 ENABLE_INTS 1244 bl .altivec_unavailable_exception 1245 b .ret_from_except 1246 1247#ifdef CONFIG_ALTIVEC 1248/* 1249 * load_up_altivec(unused, unused, tsk) 1250 * Disable VMX for the task which had it previously, 1251 * and save its vector registers in its thread_struct. 1252 * Enables the VMX for use in the kernel on return. 1253 * On SMP we know the VMX is free, since we give it up every 1254 * switch (ie, no lazy save of the vector registers). 1255 * On entry: r13 == 'current' && last_task_used_altivec != 'current' 1256 */ 1257_STATIC(load_up_altivec) 1258 mfmsr r5 /* grab the current MSR */ 1259 oris r5,r5,MSR_VEC@h 1260 mtmsrd r5 /* enable use of VMX now */ 1261 isync 1262 1263/* 1264 * For SMP, we don't do lazy VMX switching because it just gets too 1265 * horrendously complex, especially when a task switches from one CPU 1266 * to another. Instead we call giveup_altvec in switch_to. 1267 * VRSAVE isn't dealt with here, that is done in the normal context 1268 * switch code. Note that we could rely on vrsave value to eventually 1269 * avoid saving all of the VREGs here... 1270 */ 1271#ifndef CONFIG_SMP 1272 ld r3,last_task_used_altivec@got(r2) 1273 ld r4,0(r3) 1274 cmpdi 0,r4,0 1275 beq 1f 1276 /* Save VMX state to last_task_used_altivec's THREAD struct */ 1277 addi r4,r4,THREAD 1278 SAVE_32VRS(0,r5,r4) 1279 mfvscr vr0 1280 li r10,THREAD_VSCR 1281 stvx vr0,r10,r4 1282 /* Disable VMX for last_task_used_altivec */ 1283 ld r5,PT_REGS(r4) 1284 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1285 lis r6,MSR_VEC@h 1286 andc r4,r4,r6 1287 std r4,_MSR-STACK_FRAME_OVERHEAD(r5) 12881: 1289#endif /* CONFIG_SMP */ 1290 /* Hack: if we get an altivec unavailable trap with VRSAVE 1291 * set to all zeros, we assume this is a broken application 1292 * that fails to set it properly, and thus we switch it to 1293 * all 1's 1294 */ 1295 mfspr r4,SPRN_VRSAVE 1296 cmpdi 0,r4,0 1297 bne+ 1f 1298 li r4,-1 1299 mtspr SPRN_VRSAVE,r4 13001: 1301 /* enable use of VMX after return */ 1302 ld r4,PACACURRENT(r13) 1303 addi r5,r4,THREAD /* Get THREAD */ 1304 oris r12,r12,MSR_VEC@h 1305 std r12,_MSR(r1) 1306 li r4,1 1307 li r10,THREAD_VSCR 1308 stw r4,THREAD_USED_VR(r5) 1309 lvx vr0,r10,r5 1310 mtvscr vr0 1311 REST_32VRS(0,r4,r5) 1312#ifndef CONFIG_SMP 1313 /* Update last_task_used_math to 'current' */ 1314 subi r4,r5,THREAD /* Back to 'current' */ 1315 std r4,0(r3) 1316#endif /* CONFIG_SMP */ 1317 /* restore registers and return */ 1318 b fast_exception_return 1319#endif /* CONFIG_ALTIVEC */ 1320 1321/* 1322 * Hash table stuff 1323 */ 1324 .align 7 1325_GLOBAL(do_hash_page) 1326 std r3,_DAR(r1) 1327 std r4,_DSISR(r1) 1328 1329 andis. r0,r4,0xa450 /* weird error? */ 1330 bne- handle_page_fault /* if not, try to insert a HPTE */ 1331BEGIN_FTR_SECTION 1332 andis. r0,r4,0x0020 /* Is it a segment table fault? */ 1333 bne- do_ste_alloc /* If so handle it */ 1334END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 1335 1336 /* 1337 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are 1338 * accessing a userspace segment (even from the kernel). We assume 1339 * kernel addresses always have the high bit set. 1340 */ 1341 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ 1342 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ 1343 orc r0,r12,r0 /* MSR_PR | ~high_bit */ 1344 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ 1345 ori r4,r4,1 /* add _PAGE_PRESENT */ 1346 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ 1347 1348 /* 1349 * On iSeries, we soft-disable interrupts here, then 1350 * hard-enable interrupts so that the hash_page code can spin on 1351 * the hash_table_lock without problems on a shared processor. 1352 */ 1353 DISABLE_INTS 1354 1355 /* 1356 * r3 contains the faulting address 1357 * r4 contains the required access permissions 1358 * r5 contains the trap number 1359 * 1360 * at return r3 = 0 for success 1361 */ 1362 bl .hash_page /* build HPTE if possible */ 1363 cmpdi r3,0 /* see if hash_page succeeded */ 1364 1365#ifdef DO_SOFT_DISABLE 1366BEGIN_FW_FTR_SECTION 1367 /* 1368 * If we had interrupts soft-enabled at the point where the 1369 * DSI/ISI occurred, and an interrupt came in during hash_page, 1370 * handle it now. 1371 * We jump to ret_from_except_lite rather than fast_exception_return 1372 * because ret_from_except_lite will check for and handle pending 1373 * interrupts if necessary. 1374 */ 1375 beq 13f 1376END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1377#endif 1378BEGIN_FW_FTR_SECTION 1379 /* 1380 * Here we have interrupts hard-disabled, so it is sufficient 1381 * to restore paca->{soft,hard}_enable and get out. 1382 */ 1383 beq fast_exc_return_irq /* Return from exception on success */ 1384END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1385 1386 /* For a hash failure, we don't bother re-enabling interrupts */ 1387 ble- 12f 1388 1389 /* 1390 * hash_page couldn't handle it, set soft interrupt enable back 1391 * to what it was before the trap. Note that .local_irq_restore 1392 * handles any interrupts pending at this point. 1393 */ 1394 ld r3,SOFTE(r1) 1395 bl .local_irq_restore 1396 b 11f 1397 1398/* Here we have a page fault that hash_page can't handle. */ 1399handle_page_fault: 1400 ENABLE_INTS 140111: ld r4,_DAR(r1) 1402 ld r5,_DSISR(r1) 1403 addi r3,r1,STACK_FRAME_OVERHEAD 1404 bl .do_page_fault 1405 cmpdi r3,0 1406 beq+ 13f 1407 bl .save_nvgprs 1408 mr r5,r3 1409 addi r3,r1,STACK_FRAME_OVERHEAD 1410 lwz r4,_DAR(r1) 1411 bl .bad_page_fault 1412 b .ret_from_except 1413 141413: b .ret_from_except_lite 1415 1416/* We have a page fault that hash_page could handle but HV refused 1417 * the PTE insertion 1418 */ 141912: bl .save_nvgprs 1420 addi r3,r1,STACK_FRAME_OVERHEAD 1421 lwz r4,_DAR(r1) 1422 bl .low_hash_fault 1423 b .ret_from_except 1424 1425 /* here we have a segment miss */ 1426do_ste_alloc: 1427 bl .ste_allocate /* try to insert stab entry */ 1428 cmpdi r3,0 1429 bne- handle_page_fault 1430 b fast_exception_return 1431 1432/* 1433 * r13 points to the PACA, r9 contains the saved CR, 1434 * r11 and r12 contain the saved SRR0 and SRR1. 1435 * r9 - r13 are saved in paca->exslb. 1436 * We assume we aren't going to take any exceptions during this procedure. 1437 * We assume (DAR >> 60) == 0xc. 1438 */ 1439 .align 7 1440_GLOBAL(do_stab_bolted) 1441 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 1442 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ 1443 1444 /* Hash to the primary group */ 1445 ld r10,PACASTABVIRT(r13) 1446 mfspr r11,SPRN_DAR 1447 srdi r11,r11,28 1448 rldimi r10,r11,7,52 /* r10 = first ste of the group */ 1449 1450 /* Calculate VSID */ 1451 /* This is a kernel address, so protovsid = ESID */ 1452 ASM_VSID_SCRAMBLE(r11, r9) 1453 rldic r9,r11,12,16 /* r9 = vsid << 12 */ 1454 1455 /* Search the primary group for a free entry */ 14561: ld r11,0(r10) /* Test valid bit of the current ste */ 1457 andi. r11,r11,0x80 1458 beq 2f 1459 addi r10,r10,16 1460 andi. r11,r10,0x70 1461 bne 1b 1462 1463 /* Stick for only searching the primary group for now. */ 1464 /* At least for now, we use a very simple random castout scheme */ 1465 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ 1466 mftb r11 1467 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ 1468 ori r11,r11,0x10 1469 1470 /* r10 currently points to an ste one past the group of interest */ 1471 /* make it point to the randomly selected entry */ 1472 subi r10,r10,128 1473 or r10,r10,r11 /* r10 is the entry to invalidate */ 1474 1475 isync /* mark the entry invalid */ 1476 ld r11,0(r10) 1477 rldicl r11,r11,56,1 /* clear the valid bit */ 1478 rotldi r11,r11,8 1479 std r11,0(r10) 1480 sync 1481 1482 clrrdi r11,r11,28 /* Get the esid part of the ste */ 1483 slbie r11 1484 14852: std r9,8(r10) /* Store the vsid part of the ste */ 1486 eieio 1487 1488 mfspr r11,SPRN_DAR /* Get the new esid */ 1489 clrrdi r11,r11,28 /* Permits a full 32b of ESID */ 1490 ori r11,r11,0x90 /* Turn on valid and kp */ 1491 std r11,0(r10) /* Put new entry back into the stab */ 1492 1493 sync 1494 1495 /* All done -- return from exception. */ 1496 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 1497 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ 1498 1499 andi. r10,r12,MSR_RI 1500 beq- unrecov_slb 1501 1502 mtcrf 0x80,r9 /* restore CR */ 1503 1504 mfmsr r10 1505 clrrdi r10,r10,2 1506 mtmsrd r10,1 1507 1508 mtspr SPRN_SRR0,r11 1509 mtspr SPRN_SRR1,r12 1510 ld r9,PACA_EXSLB+EX_R9(r13) 1511 ld r10,PACA_EXSLB+EX_R10(r13) 1512 ld r11,PACA_EXSLB+EX_R11(r13) 1513 ld r12,PACA_EXSLB+EX_R12(r13) 1514 ld r13,PACA_EXSLB+EX_R13(r13) 1515 rfid 1516 b . /* prevent speculative execution */ 1517 1518/* 1519 * Space for CPU0's segment table. 1520 * 1521 * On iSeries, the hypervisor must fill in at least one entry before 1522 * we get control (with relocate on). The address is give to the hv 1523 * as a page number (see xLparMap in lpardata.c), so this must be at a 1524 * fixed address (the linker can't compute (u64)&initial_stab >> 1525 * PAGE_SHIFT). 1526 */ 1527 . = STAB0_OFFSET /* 0x6000 */ 1528 .globl initial_stab 1529initial_stab: 1530 .space 4096 1531 1532/* 1533 * Data area reserved for FWNMI option. 1534 * This address (0x7000) is fixed by the RPA. 1535 */ 1536 .= 0x7000 1537 .globl fwnmi_data_area 1538fwnmi_data_area: 1539 1540 /* iSeries does not use the FWNMI stuff, so it is safe to put 1541 * this here, even if we later allow kernels that will boot on 1542 * both pSeries and iSeries */ 1543#ifdef CONFIG_PPC_ISERIES 1544 . = LPARMAP_PHYS 1545#include "lparmap.s" 1546/* 1547 * This ".text" is here for old compilers that generate a trailing 1548 * .note section when compiling .c files to .s 1549 */ 1550 .text 1551#endif /* CONFIG_PPC_ISERIES */ 1552 1553 . = 0x8000 1554 1555/* 1556 * On pSeries and most other platforms, secondary processors spin 1557 * in the following code. 1558 * At entry, r3 = this processor's number (physical cpu id) 1559 */ 1560_GLOBAL(generic_secondary_smp_init) 1561 mr r24,r3 1562 1563 /* turn on 64-bit mode */ 1564 bl .enable_64b_mode 1565 1566 /* Set up a paca value for this processor. Since we have the 1567 * physical cpu id in r24, we need to search the pacas to find 1568 * which logical id maps to our physical one. 1569 */ 1570 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */ 1571 li r5,0 /* logical cpu id */ 15721: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 1573 cmpw r6,r24 /* Compare to our id */ 1574 beq 2f 1575 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 1576 addi r5,r5,1 1577 cmpwi r5,NR_CPUS 1578 blt 1b 1579 1580 mr r3,r24 /* not found, copy phys to r3 */ 1581 b .kexec_wait /* next kernel might do better */ 1582 15832: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1584 /* From now on, r24 is expected to be logical cpuid */ 1585 mr r24,r5 15863: HMT_LOW 1587 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 1588 /* start. */ 1589 sync 1590 1591#ifndef CONFIG_SMP 1592 b 3b /* Never go on non-SMP */ 1593#else 1594 cmpwi 0,r23,0 1595 beq 3b /* Loop until told to go */ 1596 1597 /* See if we need to call a cpu state restore handler */ 1598 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec) 1599 ld r23,0(r23) 1600 ld r23,CPU_SPEC_RESTORE(r23) 1601 cmpdi 0,r23,0 1602 beq 4f 1603 ld r23,0(r23) 1604 mtctr r23 1605 bctrl 1606 16074: /* Create a temp kernel stack for use before relocation is on. */ 1608 ld r1,PACAEMERGSP(r13) 1609 subi r1,r1,STACK_FRAME_OVERHEAD 1610 1611 b __secondary_start 1612#endif 1613 1614#ifdef CONFIG_PPC_ISERIES 1615_INIT_STATIC(__start_initialization_iSeries) 1616 /* Clear out the BSS */ 1617 LOAD_REG_IMMEDIATE(r11,__bss_stop) 1618 LOAD_REG_IMMEDIATE(r8,__bss_start) 1619 sub r11,r11,r8 /* bss size */ 1620 addi r11,r11,7 /* round up to an even double word */ 1621 rldicl. r11,r11,61,3 /* shift right by 3 */ 1622 beq 4f 1623 addi r8,r8,-8 1624 li r0,0 1625 mtctr r11 /* zero this many doublewords */ 16263: stdu r0,8(r8) 1627 bdnz 3b 16284: 1629 LOAD_REG_IMMEDIATE(r1,init_thread_union) 1630 addi r1,r1,THREAD_SIZE 1631 li r0,0 1632 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1633 1634 LOAD_REG_IMMEDIATE(r2,__toc_start) 1635 addi r2,r2,0x4000 1636 addi r2,r2,0x4000 1637 1638 bl .iSeries_early_setup 1639 bl .early_setup 1640 1641 /* relocation is on at this point */ 1642 1643 b .start_here_common 1644#endif /* CONFIG_PPC_ISERIES */ 1645 1646 1647_STATIC(__mmu_off) 1648 mfmsr r3 1649 andi. r0,r3,MSR_IR|MSR_DR 1650 beqlr 1651 andc r3,r3,r0 1652 mtspr SPRN_SRR0,r4 1653 mtspr SPRN_SRR1,r3 1654 sync 1655 rfid 1656 b . /* prevent speculative execution */ 1657 1658 1659/* 1660 * Here is our main kernel entry point. We support currently 2 kind of entries 1661 * depending on the value of r5. 1662 * 1663 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 1664 * in r3...r7 1665 * 1666 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 1667 * DT block, r4 is a physical pointer to the kernel itself 1668 * 1669 */ 1670_GLOBAL(__start_initialization_multiplatform) 1671 /* 1672 * Are we booted from a PROM Of-type client-interface ? 1673 */ 1674 cmpldi cr0,r5,0 1675 bne .__boot_from_prom /* yes -> prom */ 1676 1677 /* Save parameters */ 1678 mr r31,r3 1679 mr r30,r4 1680 1681 /* Make sure we are running in 64 bits mode */ 1682 bl .enable_64b_mode 1683 1684 /* Setup some critical 970 SPRs before switching MMU off */ 1685 mfspr r0,SPRN_PVR 1686 srwi r0,r0,16 1687 cmpwi r0,0x39 /* 970 */ 1688 beq 1f 1689 cmpwi r0,0x3c /* 970FX */ 1690 beq 1f 1691 cmpwi r0,0x44 /* 970MP */ 1692 beq 1f 1693 cmpwi r0,0x45 /* 970GX */ 1694 bne 2f 16951: bl .__cpu_preinit_ppc970 16962: 1697 1698 /* Switch off MMU if not already */ 1699 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE) 1700 add r4,r4,r30 1701 bl .__mmu_off 1702 b .__after_prom_start 1703 1704_STATIC(__boot_from_prom) 1705 /* Save parameters */ 1706 mr r31,r3 1707 mr r30,r4 1708 mr r29,r5 1709 mr r28,r6 1710 mr r27,r7 1711 1712 /* 1713 * Align the stack to 16-byte boundary 1714 * Depending on the size and layout of the ELF sections in the initial 1715 * boot binary, the stack pointer will be unalignet on PowerMac 1716 */ 1717 rldicr r1,r1,0,59 1718 1719 /* Make sure we are running in 64 bits mode */ 1720 bl .enable_64b_mode 1721 1722 /* put a relocation offset into r3 */ 1723 bl .reloc_offset 1724 1725 LOAD_REG_IMMEDIATE(r2,__toc_start) 1726 addi r2,r2,0x4000 1727 addi r2,r2,0x4000 1728 1729 /* Relocate the TOC from a virt addr to a real addr */ 1730 add r2,r2,r3 1731 1732 /* Restore parameters */ 1733 mr r3,r31 1734 mr r4,r30 1735 mr r5,r29 1736 mr r6,r28 1737 mr r7,r27 1738 1739 /* Do all of the interaction with OF client interface */ 1740 bl .prom_init 1741 /* We never return */ 1742 trap 1743 1744_STATIC(__after_prom_start) 1745 1746/* 1747 * We need to run with __start at physical address PHYSICAL_START. 1748 * This will leave some code in the first 256B of 1749 * real memory, which are reserved for software use. 1750 * The remainder of the first page is loaded with the fixed 1751 * interrupt vectors. The next two pages are filled with 1752 * unknown exception placeholders. 1753 * 1754 * Note: This process overwrites the OF exception vectors. 1755 * r26 == relocation offset 1756 * r27 == KERNELBASE 1757 */ 1758 bl .reloc_offset 1759 mr r26,r3 1760 LOAD_REG_IMMEDIATE(r27, KERNELBASE) 1761 1762 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */ 1763 1764 // XXX FIXME: Use phys returned by OF (r30) 1765 add r4,r27,r26 /* source addr */ 1766 /* current address of _start */ 1767 /* i.e. where we are running */ 1768 /* the source addr */ 1769 1770 cmpdi r4,0 /* In some cases the loader may */ 1771 beq .start_here_multiplatform /* have already put us at zero */ 1772 /* so we can skip the copy. */ 1773 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */ 1774 sub r5,r5,r27 1775 1776 li r6,0x100 /* Start offset, the first 0x100 */ 1777 /* bytes were copied earlier. */ 1778 1779 bl .copy_and_flush /* copy the first n bytes */ 1780 /* this includes the code being */ 1781 /* executed here. */ 1782 1783 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */ 1784 mtctr r0 /* that we just made/relocated */ 1785 bctr 1786 17874: LOAD_REG_IMMEDIATE(r5,klimit) 1788 add r5,r5,r26 1789 ld r5,0(r5) /* get the value of klimit */ 1790 sub r5,r5,r27 1791 bl .copy_and_flush /* copy the rest */ 1792 b .start_here_multiplatform 1793 1794/* 1795 * Copy routine used to copy the kernel to start at physical address 0 1796 * and flush and invalidate the caches as needed. 1797 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 1798 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 1799 * 1800 * Note: this routine *only* clobbers r0, r6 and lr 1801 */ 1802_GLOBAL(copy_and_flush) 1803 addi r5,r5,-8 1804 addi r6,r6,-8 18054: li r0,8 /* Use the smallest common */ 1806 /* denominator cache line */ 1807 /* size. This results in */ 1808 /* extra cache line flushes */ 1809 /* but operation is correct. */ 1810 /* Can't get cache line size */ 1811 /* from NACA as it is being */ 1812 /* moved too. */ 1813 1814 mtctr r0 /* put # words/line in ctr */ 18153: addi r6,r6,8 /* copy a cache line */ 1816 ldx r0,r6,r4 1817 stdx r0,r6,r3 1818 bdnz 3b 1819 dcbst r6,r3 /* write it to memory */ 1820 sync 1821 icbi r6,r3 /* flush the icache line */ 1822 cmpld 0,r6,r5 1823 blt 4b 1824 sync 1825 addi r5,r5,8 1826 addi r6,r6,8 1827 blr 1828 1829.align 8 1830copy_to_here: 1831 1832#ifdef CONFIG_SMP 1833#ifdef CONFIG_PPC_PMAC 1834/* 1835 * On PowerMac, secondary processors starts from the reset vector, which 1836 * is temporarily turned into a call to one of the functions below. 1837 */ 1838 .section ".text"; 1839 .align 2 ; 1840 1841 .globl __secondary_start_pmac_0 1842__secondary_start_pmac_0: 1843 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 1844 li r24,0 1845 b 1f 1846 li r24,1 1847 b 1f 1848 li r24,2 1849 b 1f 1850 li r24,3 18511: 1852 1853_GLOBAL(pmac_secondary_start) 1854 /* turn on 64-bit mode */ 1855 bl .enable_64b_mode 1856 1857 /* Copy some CPU settings from CPU 0 */ 1858 bl .__restore_cpu_ppc970 1859 1860 /* pSeries do that early though I don't think we really need it */ 1861 mfmsr r3 1862 ori r3,r3,MSR_RI 1863 mtmsrd r3 /* RI on */ 1864 1865 /* Set up a paca value for this processor. */ 1866 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ 1867 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 1868 add r13,r13,r4 /* for this processor. */ 1869 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1870 1871 /* Create a temp kernel stack for use before relocation is on. */ 1872 ld r1,PACAEMERGSP(r13) 1873 subi r1,r1,STACK_FRAME_OVERHEAD 1874 1875 b __secondary_start 1876 1877#endif /* CONFIG_PPC_PMAC */ 1878 1879/* 1880 * This function is called after the master CPU has released the 1881 * secondary processors. The execution environment is relocation off. 1882 * The paca for this processor has the following fields initialized at 1883 * this point: 1884 * 1. Processor number 1885 * 2. Segment table pointer (virtual address) 1886 * On entry the following are set: 1887 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 1888 * r24 = cpu# (in Linux terms) 1889 * r13 = paca virtual address 1890 * SPRG3 = paca virtual address 1891 */ 1892__secondary_start: 1893 /* Set thread priority to MEDIUM */ 1894 HMT_MEDIUM 1895 1896 /* Load TOC */ 1897 ld r2,PACATOC(r13) 1898 1899 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 1900 bl .early_setup_secondary 1901 1902 /* Initialize the kernel stack. Just a repeat for iSeries. */ 1903 LOAD_REG_ADDR(r3, current_set) 1904 sldi r28,r24,3 /* get current_set[cpu#] */ 1905 ldx r1,r3,r28 1906 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1907 std r1,PACAKSAVE(r13) 1908 1909 /* Clear backchain so we get nice backtraces */ 1910 li r7,0 1911 mtlr r7 1912 1913 /* enable MMU and jump to start_secondary */ 1914 LOAD_REG_ADDR(r3, .start_secondary_prolog) 1915 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 1916#ifdef CONFIG_PPC_ISERIES 1917BEGIN_FW_FTR_SECTION 1918 ori r4,r4,MSR_EE 1919END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1920#endif 1921BEGIN_FW_FTR_SECTION 1922 stb r7,PACASOFTIRQEN(r13) 1923 stb r7,PACAHARDIRQEN(r13) 1924END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1925 1926 mtspr SPRN_SRR0,r3 1927 mtspr SPRN_SRR1,r4 1928 rfid 1929 b . /* prevent speculative execution */ 1930 1931/* 1932 * Running with relocation on at this point. All we want to do is 1933 * zero the stack back-chain pointer before going into C code. 1934 */ 1935_GLOBAL(start_secondary_prolog) 1936 li r3,0 1937 std r3,0(r1) /* Zero the stack frame pointer */ 1938 bl .start_secondary 1939 b . 1940#endif 1941 1942/* 1943 * This subroutine clobbers r11 and r12 1944 */ 1945_GLOBAL(enable_64b_mode) 1946 mfmsr r11 /* grab the current MSR */ 1947 li r12,1 1948 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) 1949 or r11,r11,r12 1950 li r12,1 1951 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) 1952 or r11,r11,r12 1953 mtmsrd r11 1954 isync 1955 blr 1956 1957/* 1958 * This is where the main kernel code starts. 1959 */ 1960_STATIC(start_here_multiplatform) 1961 /* get a new offset, now that the kernel has moved. */ 1962 bl .reloc_offset 1963 mr r26,r3 1964 1965 /* Clear out the BSS. It may have been done in prom_init, 1966 * already but that's irrelevant since prom_init will soon 1967 * be detached from the kernel completely. Besides, we need 1968 * to clear it now for kexec-style entry. 1969 */ 1970 LOAD_REG_IMMEDIATE(r11,__bss_stop) 1971 LOAD_REG_IMMEDIATE(r8,__bss_start) 1972 sub r11,r11,r8 /* bss size */ 1973 addi r11,r11,7 /* round up to an even double word */ 1974 rldicl. r11,r11,61,3 /* shift right by 3 */ 1975 beq 4f 1976 addi r8,r8,-8 1977 li r0,0 1978 mtctr r11 /* zero this many doublewords */ 19793: stdu r0,8(r8) 1980 bdnz 3b 19814: 1982 1983 mfmsr r6 1984 ori r6,r6,MSR_RI 1985 mtmsrd r6 /* RI on */ 1986 1987 /* The following gets the stack and TOC set up with the regs */ 1988 /* pointing to the real addr of the kernel stack. This is */ 1989 /* all done to support the C function call below which sets */ 1990 /* up the htab. This is done because we have relocated the */ 1991 /* kernel but are still running in real mode. */ 1992 1993 LOAD_REG_IMMEDIATE(r3,init_thread_union) 1994 add r3,r3,r26 1995 1996 /* set up a stack pointer (physical address) */ 1997 addi r1,r3,THREAD_SIZE 1998 li r0,0 1999 stdu r0,-STACK_FRAME_OVERHEAD(r1) 2000 2001 /* set up the TOC (physical address) */ 2002 LOAD_REG_IMMEDIATE(r2,__toc_start) 2003 addi r2,r2,0x4000 2004 addi r2,r2,0x4000 2005 add r2,r2,r26 2006 2007 /* Do very early kernel initializations, including initial hash table, 2008 * stab and slb setup before we turn on relocation. */ 2009 2010 /* Restore parameters passed from prom_init/kexec */ 2011 mr r3,r31 2012 bl .early_setup 2013 2014 LOAD_REG_IMMEDIATE(r3, .start_here_common) 2015 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 2016 mtspr SPRN_SRR0,r3 2017 mtspr SPRN_SRR1,r4 2018 rfid 2019 b . /* prevent speculative execution */ 2020 2021 /* This is where all platforms converge execution */ 2022_STATIC(start_here_common) 2023 /* relocation is on at this point */ 2024 2025 /* The following code sets up the SP and TOC now that we are */ 2026 /* running with translation enabled. */ 2027 2028 LOAD_REG_IMMEDIATE(r3,init_thread_union) 2029 2030 /* set up the stack */ 2031 addi r1,r3,THREAD_SIZE 2032 li r0,0 2033 stdu r0,-STACK_FRAME_OVERHEAD(r1) 2034 2035 /* ptr to current */ 2036 LOAD_REG_IMMEDIATE(r4, init_task) 2037 std r4,PACACURRENT(r13) 2038 2039 /* Load the TOC */ 2040 ld r2,PACATOC(r13) 2041 std r1,PACAKSAVE(r13) 2042 2043 bl .setup_system 2044 2045 /* Load up the kernel context */ 20465: 2047 li r5,0 2048 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ 2049#ifdef CONFIG_PPC_ISERIES 2050BEGIN_FW_FTR_SECTION 2051 mfmsr r5 2052 ori r5,r5,MSR_EE /* Hard Enabled */ 2053 mtmsrd r5 2054END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 2055#endif 2056BEGIN_FW_FTR_SECTION 2057 stb r5,PACAHARDIRQEN(r13) 2058END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 2059 2060 bl .start_kernel 2061 2062 /* Not reached */ 2063 BUG_OPCODE 2064 2065/* 2066 * We put a few things here that have to be page-aligned. 2067 * This stuff goes at the beginning of the bss, which is page-aligned. 2068 */ 2069 .section ".bss" 2070 2071 .align PAGE_SHIFT 2072 2073 .globl empty_zero_page 2074empty_zero_page: 2075 .space PAGE_SIZE 2076 2077 .globl swapper_pg_dir 2078swapper_pg_dir: 2079 .space PAGE_SIZE 2080 2081/* 2082 * This space gets a copy of optional info passed to us by the bootstrap 2083 * Used to pass parameters into the kernel like root=/dev/sda1, etc. 2084 */ 2085 .globl cmd_line 2086cmd_line: 2087 .space COMMAND_LINE_SIZE 2088