1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the entry point for the 64-bit kernel along 16 * with some early initialization code common to all 64-bit powerpc 17 * variants. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 25#include <linux/threads.h> 26#include <linux/init.h> 27#include <asm/reg.h> 28#include <asm/page.h> 29#include <asm/mmu.h> 30#include <asm/ppc_asm.h> 31#include <asm/head-64.h> 32#include <asm/asm-offsets.h> 33#include <asm/bug.h> 34#include <asm/cputable.h> 35#include <asm/setup.h> 36#include <asm/hvcall.h> 37#include <asm/thread_info.h> 38#include <asm/firmware.h> 39#include <asm/page_64.h> 40#include <asm/irqflags.h> 41#include <asm/kvm_book3s_asm.h> 42#include <asm/ptrace.h> 43#include <asm/hw_irq.h> 44#include <asm/cputhreads.h> 45#include <asm/ppc-opcode.h> 46#include <asm/export.h> 47#include <asm/feature-fixups.h> 48 49/* The physical memory is laid out such that the secondary processor 50 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 51 * using the layout described in exceptions-64s.S 52 */ 53 54/* 55 * Entering into this code we make the following assumptions: 56 * 57 * For pSeries or server processors: 58 * 1. The MMU is off & open firmware is running in real mode. 59 * 2. The primary CPU enters at __start. 60 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary 61 * CPUs will enter as directed by "start-cpu" RTAS call, which is 62 * generic_secondary_smp_init, with PIR in r3. 63 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as 64 * directed by the "start-cpu" RTS call, with PIR in r3. 65 * -or- For OPAL entry: 66 * 1. The MMU is off, processor in HV mode. 67 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base 68 * in r8, and entry in r9 for debugging purposes. 69 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which 70 * is at generic_secondary_smp_init, with PIR in r3. 71 * 72 * For Book3E processors: 73 * 1. The MMU is on running in AS0 in a state defined in ePAPR 74 * 2. The kernel is entered at __start 75 */ 76 77OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) 78USE_FIXED_SECTION(first_256B) 79 /* 80 * Offsets are relative from the start of fixed section, and 81 * first_256B starts at 0. Offsets are a bit easier to use here 82 * than the fixed section entry macros. 83 */ 84 . = 0x0 85_GLOBAL(__start) 86 /* NOP this out unconditionally */ 87BEGIN_FTR_SECTION 88 FIXUP_ENDIAN 89 b __start_initialization_multiplatform 90END_FTR_SECTION(0, 1) 91 92 /* Catch branch to 0 in real mode */ 93 trap 94 95 /* Secondary processors spin on this value until it becomes non-zero. 96 * When non-zero, it contains the real address of the function the cpu 97 * should jump to. 98 */ 99 .balign 8 100 .globl __secondary_hold_spinloop 101__secondary_hold_spinloop: 102 .8byte 0x0 103 104 /* Secondary processors write this value with their cpu # */ 105 /* after they enter the spin loop immediately below. */ 106 .globl __secondary_hold_acknowledge 107__secondary_hold_acknowledge: 108 .8byte 0x0 109 110#ifdef CONFIG_RELOCATABLE 111 /* This flag is set to 1 by a loader if the kernel should run 112 * at the loaded address instead of the linked address. This 113 * is used by kexec-tools to keep the the kdump kernel in the 114 * crash_kernel region. The loader is responsible for 115 * observing the alignment requirement. 116 */ 117 118#ifdef CONFIG_RELOCATABLE_TEST 119#define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ 120#else 121#define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ 122#endif 123 124 /* Do not move this variable as kexec-tools knows about it. */ 125 . = 0x5c 126 .globl __run_at_load 127__run_at_load: 128DEFINE_FIXED_SYMBOL(__run_at_load) 129 .long RUN_AT_LOAD_DEFAULT 130#endif 131 132 . = 0x60 133/* 134 * The following code is used to hold secondary processors 135 * in a spin loop after they have entered the kernel, but 136 * before the bulk of the kernel has been relocated. This code 137 * is relocated to physical address 0x60 before prom_init is run. 138 * All of it must fit below the first exception vector at 0x100. 139 * Use .globl here not _GLOBAL because we want __secondary_hold 140 * to be the actual text address, not a descriptor. 141 */ 142 .globl __secondary_hold 143__secondary_hold: 144 FIXUP_ENDIAN 145#ifndef CONFIG_PPC_BOOK3E 146 mfmsr r24 147 ori r24,r24,MSR_RI 148 mtmsrd r24 /* RI on */ 149#endif 150 /* Grab our physical cpu number */ 151 mr r24,r3 152 /* stash r4 for book3e */ 153 mr r25,r4 154 155 /* Tell the master cpu we're here */ 156 /* Relocation is off & we are located at an address less */ 157 /* than 0x100, so only need to grab low order offset. */ 158 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0) 159 sync 160 161 li r26,0 162#ifdef CONFIG_PPC_BOOK3E 163 tovirt(r26,r26) 164#endif 165 /* All secondary cpus wait here until told to start. */ 166100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26) 167 cmpdi 0,r12,0 168 beq 100b 169 170#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 171#ifdef CONFIG_PPC_BOOK3E 172 tovirt(r12,r12) 173#endif 174 mtctr r12 175 mr r3,r24 176 /* 177 * it may be the case that other platforms have r4 right to 178 * begin with, this gives us some safety in case it is not 179 */ 180#ifdef CONFIG_PPC_BOOK3E 181 mr r4,r25 182#else 183 li r4,0 184#endif 185 /* Make sure that patched code is visible */ 186 isync 187 bctr 188#else 189 BUG_OPCODE 190#endif 191CLOSE_FIXED_SECTION(first_256B) 192 193/* This value is used to mark exception frames on the stack. */ 194 .section ".toc","aw" 195exception_marker: 196 .tc ID_72656773_68657265[TC],0x7265677368657265 197 .previous 198 199/* 200 * On server, we include the exception vectors code here as it 201 * relies on absolute addressing which is only possible within 202 * this compilation unit 203 */ 204#ifdef CONFIG_PPC_BOOK3S 205#include "exceptions-64s.S" 206#else 207OPEN_TEXT_SECTION(0x100) 208#endif 209 210USE_TEXT_SECTION() 211 212#ifdef CONFIG_PPC_BOOK3E 213/* 214 * The booting_thread_hwid holds the thread id we want to boot in cpu 215 * hotplug case. It is set by cpu hotplug code, and is invalid by default. 216 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] 217 * bit field. 218 */ 219 .globl booting_thread_hwid 220booting_thread_hwid: 221 .long INVALID_THREAD_HWID 222 .align 3 223/* 224 * start a thread in the same core 225 * input parameters: 226 * r3 = the thread physical id 227 * r4 = the entry point where thread starts 228 */ 229_GLOBAL(book3e_start_thread) 230 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) 231 cmpwi r3, 0 232 beq 10f 233 cmpwi r3, 1 234 beq 11f 235 /* If the thread id is invalid, just exit. */ 236 b 13f 23710: 238 MTTMR(TMRN_IMSR0, 5) 239 MTTMR(TMRN_INIA0, 4) 240 b 12f 24111: 242 MTTMR(TMRN_IMSR1, 5) 243 MTTMR(TMRN_INIA1, 4) 24412: 245 isync 246 li r6, 1 247 sld r6, r6, r3 248 mtspr SPRN_TENS, r6 24913: 250 blr 251 252/* 253 * stop a thread in the same core 254 * input parameter: 255 * r3 = the thread physical id 256 */ 257_GLOBAL(book3e_stop_thread) 258 cmpwi r3, 0 259 beq 10f 260 cmpwi r3, 1 261 beq 10f 262 /* If the thread id is invalid, just exit. */ 263 b 13f 26410: 265 li r4, 1 266 sld r4, r4, r3 267 mtspr SPRN_TENC, r4 26813: 269 blr 270 271_GLOBAL(fsl_secondary_thread_init) 272 mfspr r4,SPRN_BUCSR 273 274 /* Enable branch prediction */ 275 lis r3,BUCSR_INIT@h 276 ori r3,r3,BUCSR_INIT@l 277 mtspr SPRN_BUCSR,r3 278 isync 279 280 /* 281 * Fix PIR to match the linear numbering in the device tree. 282 * 283 * On e6500, the reset value of PIR uses the low three bits for 284 * the thread within a core, and the upper bits for the core 285 * number. There are two threads per core, so shift everything 286 * but the low bit right by two bits so that the cpu numbering is 287 * continuous. 288 * 289 * If the old value of BUCSR is non-zero, this thread has run 290 * before. Thus, we assume we are coming from kexec or a similar 291 * scenario, and PIR is already set to the correct value. This 292 * is a bit of a hack, but there are limited opportunities for 293 * getting information into the thread and the alternatives 294 * seemed like they'd be overkill. We can't tell just by looking 295 * at the old PIR value which state it's in, since the same value 296 * could be valid for one thread out of reset and for a different 297 * thread in Linux. 298 */ 299 300 mfspr r3, SPRN_PIR 301 cmpwi r4,0 302 bne 1f 303 rlwimi r3, r3, 30, 2, 30 304 mtspr SPRN_PIR, r3 3051: 306#endif 307 308_GLOBAL(generic_secondary_thread_init) 309 mr r24,r3 310 311 /* turn on 64-bit mode */ 312 bl enable_64b_mode 313 314 /* get a valid TOC pointer, wherever we're mapped at */ 315 bl relative_toc 316 tovirt(r2,r2) 317 318#ifdef CONFIG_PPC_BOOK3E 319 /* Book3E initialization */ 320 mr r3,r24 321 bl book3e_secondary_thread_init 322#endif 323 b generic_secondary_common_init 324 325/* 326 * On pSeries and most other platforms, secondary processors spin 327 * in the following code. 328 * At entry, r3 = this processor's number (physical cpu id) 329 * 330 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 331 * this core already exists (setup via some other mechanism such 332 * as SCOM before entry). 333 */ 334_GLOBAL(generic_secondary_smp_init) 335 FIXUP_ENDIAN 336 mr r24,r3 337 mr r25,r4 338 339 /* turn on 64-bit mode */ 340 bl enable_64b_mode 341 342 /* get a valid TOC pointer, wherever we're mapped at */ 343 bl relative_toc 344 tovirt(r2,r2) 345 346#ifdef CONFIG_PPC_BOOK3E 347 /* Book3E initialization */ 348 mr r3,r24 349 mr r4,r25 350 bl book3e_secondary_core_init 351 352/* 353 * After common core init has finished, check if the current thread is the 354 * one we wanted to boot. If not, start the specified thread and stop the 355 * current thread. 356 */ 357 LOAD_REG_ADDR(r4, booting_thread_hwid) 358 lwz r3, 0(r4) 359 li r5, INVALID_THREAD_HWID 360 cmpw r3, r5 361 beq 20f 362 363 /* 364 * The value of booting_thread_hwid has been stored in r3, 365 * so make it invalid. 366 */ 367 stw r5, 0(r4) 368 369 /* 370 * Get the current thread id and check if it is the one we wanted. 371 * If not, start the one specified in booting_thread_hwid and stop 372 * the current thread. 373 */ 374 mfspr r8, SPRN_TIR 375 cmpw r3, r8 376 beq 20f 377 378 /* start the specified thread */ 379 LOAD_REG_ADDR(r5, fsl_secondary_thread_init) 380 ld r4, 0(r5) 381 bl book3e_start_thread 382 383 /* stop the current thread */ 384 mr r3, r8 385 bl book3e_stop_thread 38610: 387 b 10b 38820: 389#endif 390 391generic_secondary_common_init: 392 /* Set up a paca value for this processor. Since we have the 393 * physical cpu id in r24, we need to search the pacas to find 394 * which logical id maps to our physical one. 395 */ 396#ifndef CONFIG_SMP 397 b kexec_wait /* wait for next kernel if !SMP */ 398#else 399 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ 400 ld r8,0(r8) /* Get base vaddr of array */ 401 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 402 lwz r7,0(r7) /* also the max paca allocated */ 403 li r5,0 /* logical cpu id */ 4041: 405 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ 406 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ 407 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 408 cmpw r6,r24 /* Compare to our id */ 409 beq 2f 410 addi r5,r5,1 411 cmpw r5,r7 /* Check if more pacas exist */ 412 blt 1b 413 414 mr r3,r24 /* not found, copy phys to r3 */ 415 b kexec_wait /* next kernel might do better */ 416 4172: SET_PACA(r13) 418#ifdef CONFIG_PPC_BOOK3E 419 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 420 mtspr SPRN_SPRG_TLB_EXFRAME,r12 421#endif 422 423 /* From now on, r24 is expected to be logical cpuid */ 424 mr r24,r5 425 426 /* See if we need to call a cpu state restore handler */ 427 LOAD_REG_ADDR(r23, cur_cpu_spec) 428 ld r23,0(r23) 429 ld r12,CPU_SPEC_RESTORE(r23) 430 cmpdi 0,r12,0 431 beq 3f 432#ifdef PPC64_ELF_ABI_v1 433 ld r12,0(r12) 434#endif 435 mtctr r12 436 bctrl 437 4383: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 439 lwarx r4,0,r3 440 subi r4,r4,1 441 stwcx. r4,0,r3 442 bne 3b 443 isync 444 4454: HMT_LOW 446 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 447 /* start. */ 448 cmpwi 0,r23,0 449 beq 4b /* Loop until told to go */ 450 451 sync /* order paca.run and cur_cpu_spec */ 452 isync /* In case code patching happened */ 453 454 /* Create a temp kernel stack for use before relocation is on. */ 455 ld r1,PACAEMERGSP(r13) 456 subi r1,r1,STACK_FRAME_OVERHEAD 457 458 b __secondary_start 459#endif /* SMP */ 460 461/* 462 * Turn the MMU off. 463 * Assumes we're mapped EA == RA if the MMU is on. 464 */ 465#ifdef CONFIG_PPC_BOOK3S 466__mmu_off: 467 mfmsr r3 468 andi. r0,r3,MSR_IR|MSR_DR 469 beqlr 470 mflr r4 471 andc r3,r3,r0 472 mtspr SPRN_SRR0,r4 473 mtspr SPRN_SRR1,r3 474 sync 475 rfid 476 b . /* prevent speculative execution */ 477#endif 478 479 480/* 481 * Here is our main kernel entry point. We support currently 2 kind of entries 482 * depending on the value of r5. 483 * 484 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 485 * in r3...r7 486 * 487 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 488 * DT block, r4 is a physical pointer to the kernel itself 489 * 490 */ 491__start_initialization_multiplatform: 492 /* Make sure we are running in 64 bits mode */ 493 bl enable_64b_mode 494 495 /* Get TOC pointer (current runtime address) */ 496 bl relative_toc 497 498 /* find out where we are now */ 499 bcl 20,31,$+4 5000: mflr r26 /* r26 = runtime addr here */ 501 addis r26,r26,(_stext - 0b)@ha 502 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 503 504 /* 505 * Are we booted from a PROM Of-type client-interface ? 506 */ 507 cmpldi cr0,r5,0 508 beq 1f 509 b __boot_from_prom /* yes -> prom */ 5101: 511 /* Save parameters */ 512 mr r31,r3 513 mr r30,r4 514#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 515 /* Save OPAL entry */ 516 mr r28,r8 517 mr r29,r9 518#endif 519 520#ifdef CONFIG_PPC_BOOK3E 521 bl start_initialization_book3e 522 b __after_prom_start 523#else 524 /* Setup some critical 970 SPRs before switching MMU off */ 525 mfspr r0,SPRN_PVR 526 srwi r0,r0,16 527 cmpwi r0,0x39 /* 970 */ 528 beq 1f 529 cmpwi r0,0x3c /* 970FX */ 530 beq 1f 531 cmpwi r0,0x44 /* 970MP */ 532 beq 1f 533 cmpwi r0,0x45 /* 970GX */ 534 bne 2f 5351: bl __cpu_preinit_ppc970 5362: 537 538 /* Switch off MMU if not already off */ 539 bl __mmu_off 540 b __after_prom_start 541#endif /* CONFIG_PPC_BOOK3E */ 542 543__boot_from_prom: 544#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 545 /* Save parameters */ 546 mr r31,r3 547 mr r30,r4 548 mr r29,r5 549 mr r28,r6 550 mr r27,r7 551 552 /* 553 * Align the stack to 16-byte boundary 554 * Depending on the size and layout of the ELF sections in the initial 555 * boot binary, the stack pointer may be unaligned on PowerMac 556 */ 557 rldicr r1,r1,0,59 558 559#ifdef CONFIG_RELOCATABLE 560 /* Relocate code for where we are now */ 561 mr r3,r26 562 bl relocate 563#endif 564 565 /* Restore parameters */ 566 mr r3,r31 567 mr r4,r30 568 mr r5,r29 569 mr r6,r28 570 mr r7,r27 571 572 /* Do all of the interaction with OF client interface */ 573 mr r8,r26 574 bl prom_init 575#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 576 577 /* We never return. We also hit that trap if trying to boot 578 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 579 trap 580 581__after_prom_start: 582#ifdef CONFIG_RELOCATABLE 583 /* process relocations for the final address of the kernel */ 584 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 585 sldi r25,r25,32 586#if defined(CONFIG_PPC_BOOK3E) 587 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 588#endif 589 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 590#if defined(CONFIG_PPC_BOOK3E) 591 tophys(r26,r26) 592#endif 593 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 594 bne 1f 595 add r25,r25,r26 5961: mr r3,r25 597 bl relocate 598#if defined(CONFIG_PPC_BOOK3E) 599 /* IVPR needs to be set after relocation. */ 600 bl init_core_book3e 601#endif 602#endif 603 604/* 605 * We need to run with _stext at physical address PHYSICAL_START. 606 * This will leave some code in the first 256B of 607 * real memory, which are reserved for software use. 608 * 609 * Note: This process overwrites the OF exception vectors. 610 */ 611 li r3,0 /* target addr */ 612#ifdef CONFIG_PPC_BOOK3E 613 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 614#endif 615 mr. r4,r26 /* In some cases the loader may */ 616#if defined(CONFIG_PPC_BOOK3E) 617 tovirt(r4,r4) 618#endif 619 beq 9f /* have already put us at zero */ 620 li r6,0x100 /* Start offset, the first 0x100 */ 621 /* bytes were copied earlier. */ 622 623#ifdef CONFIG_RELOCATABLE 624/* 625 * Check if the kernel has to be running as relocatable kernel based on the 626 * variable __run_at_load, if it is set the kernel is treated as relocatable 627 * kernel, otherwise it will be moved to PHYSICAL_START 628 */ 629#if defined(CONFIG_PPC_BOOK3E) 630 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 631#endif 632 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 633 cmplwi cr0,r7,1 634 bne 3f 635 636#ifdef CONFIG_PPC_BOOK3E 637 LOAD_REG_ADDR(r5, __end_interrupts) 638 LOAD_REG_ADDR(r11, _stext) 639 sub r5,r5,r11 640#else 641 /* just copy interrupts */ 642 LOAD_REG_IMMEDIATE(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) 643#endif 644 b 5f 6453: 646#endif 647 /* # bytes of memory to copy */ 648 lis r5,(ABS_ADDR(copy_to_here))@ha 649 addi r5,r5,(ABS_ADDR(copy_to_here))@l 650 651 bl copy_and_flush /* copy the first n bytes */ 652 /* this includes the code being */ 653 /* executed here. */ 654 /* Jump to the copy of this code that we just made */ 655 addis r8,r3,(ABS_ADDR(4f))@ha 656 addi r12,r8,(ABS_ADDR(4f))@l 657 mtctr r12 658 bctr 659 660.balign 8 661p_end: .8byte _end - copy_to_here 662 6634: 664 /* 665 * Now copy the rest of the kernel up to _end, add 666 * _end - copy_to_here to the copy limit and run again. 667 */ 668 addis r8,r26,(ABS_ADDR(p_end))@ha 669 ld r8,(ABS_ADDR(p_end))@l(r8) 670 add r5,r5,r8 6715: bl copy_and_flush /* copy the rest */ 672 6739: b start_here_multiplatform 674 675/* 676 * Copy routine used to copy the kernel to start at physical address 0 677 * and flush and invalidate the caches as needed. 678 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 679 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 680 * 681 * Note: this routine *only* clobbers r0, r6 and lr 682 */ 683_GLOBAL(copy_and_flush) 684 addi r5,r5,-8 685 addi r6,r6,-8 6864: li r0,8 /* Use the smallest common */ 687 /* denominator cache line */ 688 /* size. This results in */ 689 /* extra cache line flushes */ 690 /* but operation is correct. */ 691 /* Can't get cache line size */ 692 /* from NACA as it is being */ 693 /* moved too. */ 694 695 mtctr r0 /* put # words/line in ctr */ 6963: addi r6,r6,8 /* copy a cache line */ 697 ldx r0,r6,r4 698 stdx r0,r6,r3 699 bdnz 3b 700 dcbst r6,r3 /* write it to memory */ 701 sync 702 icbi r6,r3 /* flush the icache line */ 703 cmpld 0,r6,r5 704 blt 4b 705 sync 706 addi r5,r5,8 707 addi r6,r6,8 708 isync 709 blr 710 711.align 8 712copy_to_here: 713 714#ifdef CONFIG_SMP 715#ifdef CONFIG_PPC_PMAC 716/* 717 * On PowerMac, secondary processors starts from the reset vector, which 718 * is temporarily turned into a call to one of the functions below. 719 */ 720 .section ".text"; 721 .align 2 ; 722 723 .globl __secondary_start_pmac_0 724__secondary_start_pmac_0: 725 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 726 li r24,0 727 b 1f 728 li r24,1 729 b 1f 730 li r24,2 731 b 1f 732 li r24,3 7331: 734 735_GLOBAL(pmac_secondary_start) 736 /* turn on 64-bit mode */ 737 bl enable_64b_mode 738 739 li r0,0 740 mfspr r3,SPRN_HID4 741 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 742 sync 743 mtspr SPRN_HID4,r3 744 isync 745 sync 746 slbia 747 748 /* get TOC pointer (real address) */ 749 bl relative_toc 750 tovirt(r2,r2) 751 752 /* Copy some CPU settings from CPU 0 */ 753 bl __restore_cpu_ppc970 754 755 /* pSeries do that early though I don't think we really need it */ 756 mfmsr r3 757 ori r3,r3,MSR_RI 758 mtmsrd r3 /* RI on */ 759 760 /* Set up a paca value for this processor. */ 761 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ 762 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ 763 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ 764 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ 765 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 766 767 /* Mark interrupts soft and hard disabled (they might be enabled 768 * in the PACA when doing hotplug) 769 */ 770 li r0,IRQS_DISABLED 771 stb r0,PACAIRQSOFTMASK(r13) 772 li r0,PACA_IRQ_HARD_DIS 773 stb r0,PACAIRQHAPPENED(r13) 774 775 /* Create a temp kernel stack for use before relocation is on. */ 776 ld r1,PACAEMERGSP(r13) 777 subi r1,r1,STACK_FRAME_OVERHEAD 778 779 b __secondary_start 780 781#endif /* CONFIG_PPC_PMAC */ 782 783/* 784 * This function is called after the master CPU has released the 785 * secondary processors. The execution environment is relocation off. 786 * The paca for this processor has the following fields initialized at 787 * this point: 788 * 1. Processor number 789 * 2. Segment table pointer (virtual address) 790 * On entry the following are set: 791 * r1 = stack pointer (real addr of temp stack) 792 * r24 = cpu# (in Linux terms) 793 * r13 = paca virtual address 794 * SPRG_PACA = paca virtual address 795 */ 796 .section ".text"; 797 .align 2 ; 798 799 .globl __secondary_start 800__secondary_start: 801 /* Set thread priority to MEDIUM */ 802 HMT_MEDIUM 803 804 /* Initialize the kernel stack */ 805 LOAD_REG_ADDR(r3, current_set) 806 sldi r28,r24,3 /* get current_set[cpu#] */ 807 ldx r14,r3,r28 808 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD 809 std r14,PACAKSAVE(r13) 810 811 /* Do early setup for that CPU (SLB and hash table pointer) */ 812 bl early_setup_secondary 813 814 /* 815 * setup the new stack pointer, but *don't* use this until 816 * translation is on. 817 */ 818 mr r1, r14 819 820 /* Clear backchain so we get nice backtraces */ 821 li r7,0 822 mtlr r7 823 824 /* Mark interrupts soft and hard disabled (they might be enabled 825 * in the PACA when doing hotplug) 826 */ 827 li r7,IRQS_DISABLED 828 stb r7,PACAIRQSOFTMASK(r13) 829 li r0,PACA_IRQ_HARD_DIS 830 stb r0,PACAIRQHAPPENED(r13) 831 832 /* enable MMU and jump to start_secondary */ 833 LOAD_REG_ADDR(r3, start_secondary_prolog) 834 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 835 836 mtspr SPRN_SRR0,r3 837 mtspr SPRN_SRR1,r4 838 RFI 839 b . /* prevent speculative execution */ 840 841/* 842 * Running with relocation on at this point. All we want to do is 843 * zero the stack back-chain pointer and get the TOC virtual address 844 * before going into C code. 845 */ 846start_secondary_prolog: 847 ld r2,PACATOC(r13) 848 li r3,0 849 std r3,0(r1) /* Zero the stack frame pointer */ 850 bl start_secondary 851 b . 852/* 853 * Reset stack pointer and call start_secondary 854 * to continue with online operation when woken up 855 * from cede in cpu offline. 856 */ 857_GLOBAL(start_secondary_resume) 858 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 859 li r3,0 860 std r3,0(r1) /* Zero the stack frame pointer */ 861 bl start_secondary 862 b . 863#endif 864 865/* 866 * This subroutine clobbers r11 and r12 867 */ 868enable_64b_mode: 869 mfmsr r11 /* grab the current MSR */ 870#ifdef CONFIG_PPC_BOOK3E 871 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 872 mtmsr r11 873#else /* CONFIG_PPC_BOOK3E */ 874 li r12,(MSR_64BIT | MSR_ISF)@highest 875 sldi r12,r12,48 876 or r11,r11,r12 877 mtmsrd r11 878 isync 879#endif 880 blr 881 882/* 883 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 884 * by the toolchain). It computes the correct value for wherever we 885 * are running at the moment, using position-independent code. 886 * 887 * Note: The compiler constructs pointers using offsets from the 888 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 889 * the MMU is on we need our TOC to be a virtual address otherwise 890 * these pointers will be real addresses which may get stored and 891 * accessed later with the MMU on. We use tovirt() at the call 892 * sites to handle this. 893 */ 894_GLOBAL(relative_toc) 895 mflr r0 896 bcl 20,31,$+4 8970: mflr r11 898 ld r2,(p_toc - 0b)(r11) 899 add r2,r2,r11 900 mtlr r0 901 blr 902 903.balign 8 904p_toc: .8byte __toc_start + 0x8000 - 0b 905 906/* 907 * This is where the main kernel code starts. 908 */ 909start_here_multiplatform: 910 /* set up the TOC */ 911 bl relative_toc 912 tovirt(r2,r2) 913 914 /* Clear out the BSS. It may have been done in prom_init, 915 * already but that's irrelevant since prom_init will soon 916 * be detached from the kernel completely. Besides, we need 917 * to clear it now for kexec-style entry. 918 */ 919 LOAD_REG_ADDR(r11,__bss_stop) 920 LOAD_REG_ADDR(r8,__bss_start) 921 sub r11,r11,r8 /* bss size */ 922 addi r11,r11,7 /* round up to an even double word */ 923 srdi. r11,r11,3 /* shift right by 3 */ 924 beq 4f 925 addi r8,r8,-8 926 li r0,0 927 mtctr r11 /* zero this many doublewords */ 9283: stdu r0,8(r8) 929 bdnz 3b 9304: 931 932#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 933 /* Setup OPAL entry */ 934 LOAD_REG_ADDR(r11, opal) 935 std r28,0(r11); 936 std r29,8(r11); 937#endif 938 939#ifndef CONFIG_PPC_BOOK3E 940 mfmsr r6 941 ori r6,r6,MSR_RI 942 mtmsrd r6 /* RI on */ 943#endif 944 945#ifdef CONFIG_RELOCATABLE 946 /* Save the physical address we're running at in kernstart_addr */ 947 LOAD_REG_ADDR(r4, kernstart_addr) 948 clrldi r0,r25,2 949 std r0,0(r4) 950#endif 951 952 /* The following gets the stack set up with the regs */ 953 /* pointing to the real addr of the kernel stack. This is */ 954 /* all done to support the C function call below which sets */ 955 /* up the htab. This is done because we have relocated the */ 956 /* kernel but are still running in real mode. */ 957 958 LOAD_REG_ADDR(r3,init_thread_union) 959 960 /* set up a stack pointer */ 961 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) 962 add r1,r3,r1 963 li r0,0 964 stdu r0,-STACK_FRAME_OVERHEAD(r1) 965 966 /* 967 * Do very early kernel initializations, including initial hash table 968 * and SLB setup before we turn on relocation. 969 */ 970 971 /* Restore parameters passed from prom_init/kexec */ 972 mr r3,r31 973 bl early_setup /* also sets r13 and SPRG_PACA */ 974 975 LOAD_REG_ADDR(r3, start_here_common) 976 ld r4,PACAKMSR(r13) 977 mtspr SPRN_SRR0,r3 978 mtspr SPRN_SRR1,r4 979 RFI 980 b . /* prevent speculative execution */ 981 982 /* This is where all platforms converge execution */ 983 984start_here_common: 985 /* relocation is on at this point */ 986 std r1,PACAKSAVE(r13) 987 988 /* Load the TOC (virtual address) */ 989 ld r2,PACATOC(r13) 990 991 /* Mark interrupts soft and hard disabled (they might be enabled 992 * in the PACA when doing hotplug) 993 */ 994 li r0,IRQS_DISABLED 995 stb r0,PACAIRQSOFTMASK(r13) 996 li r0,PACA_IRQ_HARD_DIS 997 stb r0,PACAIRQHAPPENED(r13) 998 999 /* Generic kernel entry */ 1000 bl start_kernel 1001 1002 /* Not reached */ 1003 BUG_OPCODE 1004 1005/* 1006 * We put a few things here that have to be page-aligned. 1007 * This stuff goes at the beginning of the bss, which is page-aligned. 1008 */ 1009 .section ".bss" 1010/* 1011 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K. 1012 * We will need to find a better way to fix this 1013 */ 1014 .align 16 1015 1016 .globl swapper_pg_dir 1017swapper_pg_dir: 1018 .space PGD_TABLE_SIZE 1019 1020 .globl empty_zero_page 1021empty_zero_page: 1022 .space PAGE_SIZE 1023EXPORT_SYMBOL(empty_zero_page) 1024