1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * 6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Adapted for Power Macintosh by Paul Mackerras. 9 * Low-level exception handlers and MMU support 10 * rewritten by Paul Mackerras. 11 * Copyright (C) 1996 Paul Mackerras. 12 * 13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 15 * 16 * This file contains the entry point for the 64-bit kernel along 17 * with some early initialization code common to all 64-bit powerpc 18 * variants. 19 */ 20 21#include <linux/linkage.h> 22#include <linux/threads.h> 23#include <linux/init.h> 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/mmu.h> 27#include <asm/ppc_asm.h> 28#include <asm/head-64.h> 29#include <asm/asm-offsets.h> 30#include <asm/bug.h> 31#include <asm/cputable.h> 32#include <asm/setup.h> 33#include <asm/hvcall.h> 34#include <asm/thread_info.h> 35#include <asm/firmware.h> 36#include <asm/page_64.h> 37#include <asm/irqflags.h> 38#include <asm/kvm_book3s_asm.h> 39#include <asm/ptrace.h> 40#include <asm/hw_irq.h> 41#include <asm/cputhreads.h> 42#include <asm/ppc-opcode.h> 43#include <asm/export.h> 44#include <asm/feature-fixups.h> 45#ifdef CONFIG_PPC_BOOK3S 46#include <asm/exception-64s.h> 47#else 48#include <asm/exception-64e.h> 49#endif 50 51/* The physical memory is laid out such that the secondary processor 52 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 53 * using the layout described in exceptions-64s.S 54 */ 55 56/* 57 * Entering into this code we make the following assumptions: 58 * 59 * For pSeries or server processors: 60 * 1. The MMU is off & open firmware is running in real mode. 61 * 2. The primary CPU enters at __start. 62 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary 63 * CPUs will enter as directed by "start-cpu" RTAS call, which is 64 * generic_secondary_smp_init, with PIR in r3. 65 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as 66 * directed by the "start-cpu" RTS call, with PIR in r3. 67 * -or- For OPAL entry: 68 * 1. The MMU is off, processor in HV mode. 69 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base 70 * in r8, and entry in r9 for debugging purposes. 71 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which 72 * is at generic_secondary_smp_init, with PIR in r3. 73 * 74 * For Book3E processors: 75 * 1. The MMU is on running in AS0 in a state defined in ePAPR 76 * 2. The kernel is entered at __start 77 */ 78 79OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) 80USE_FIXED_SECTION(first_256B) 81 /* 82 * Offsets are relative from the start of fixed section, and 83 * first_256B starts at 0. Offsets are a bit easier to use here 84 * than the fixed section entry macros. 85 */ 86 . = 0x0 87_GLOBAL(__start) 88 /* NOP this out unconditionally */ 89BEGIN_FTR_SECTION 90 FIXUP_ENDIAN 91 b __start_initialization_multiplatform 92END_FTR_SECTION(0, 1) 93 94 /* Catch branch to 0 in real mode */ 95 trap 96 97 /* Secondary processors spin on this value until it becomes non-zero. 98 * When non-zero, it contains the real address of the function the cpu 99 * should jump to. 100 */ 101 .balign 8 102 .globl __secondary_hold_spinloop 103__secondary_hold_spinloop: 104 .8byte 0x0 105 106 /* Secondary processors write this value with their cpu # */ 107 /* after they enter the spin loop immediately below. */ 108 .globl __secondary_hold_acknowledge 109__secondary_hold_acknowledge: 110 .8byte 0x0 111 112#ifdef CONFIG_RELOCATABLE 113 /* This flag is set to 1 by a loader if the kernel should run 114 * at the loaded address instead of the linked address. This 115 * is used by kexec-tools to keep the kdump kernel in the 116 * crash_kernel region. The loader is responsible for 117 * observing the alignment requirement. 118 */ 119 120#ifdef CONFIG_RELOCATABLE_TEST 121#define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ 122#else 123#define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ 124#endif 125 126 /* Do not move this variable as kexec-tools knows about it. */ 127 . = 0x5c 128 .globl __run_at_load 129__run_at_load: 130DEFINE_FIXED_SYMBOL(__run_at_load, first_256B) 131 .long RUN_AT_LOAD_DEFAULT 132#endif 133 134 . = 0x60 135/* 136 * The following code is used to hold secondary processors 137 * in a spin loop after they have entered the kernel, but 138 * before the bulk of the kernel has been relocated. This code 139 * is relocated to physical address 0x60 before prom_init is run. 140 * All of it must fit below the first exception vector at 0x100. 141 * Use .globl here not _GLOBAL because we want __secondary_hold 142 * to be the actual text address, not a descriptor. 143 */ 144 .globl __secondary_hold 145__secondary_hold: 146 FIXUP_ENDIAN 147#ifndef CONFIG_PPC_BOOK3E_64 148 mfmsr r24 149 ori r24,r24,MSR_RI 150 mtmsrd r24 /* RI on */ 151#endif 152 /* Grab our physical cpu number */ 153 mr r24,r3 154 /* stash r4 for book3e */ 155 mr r25,r4 156 157 /* Tell the master cpu we're here */ 158 /* Relocation is off & we are located at an address less */ 159 /* than 0x100, so only need to grab low order offset. */ 160 std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0) 161 sync 162 163 /* All secondary cpus wait here until told to start. */ 164100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(0) 165 cmpdi 0,r12,0 166 beq 100b 167 168#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 169#ifdef CONFIG_PPC_BOOK3E_64 170 tovirt(r12,r12) 171#endif 172 mtctr r12 173 mr r3,r24 174 /* 175 * it may be the case that other platforms have r4 right to 176 * begin with, this gives us some safety in case it is not 177 */ 178#ifdef CONFIG_PPC_BOOK3E_64 179 mr r4,r25 180#else 181 li r4,0 182#endif 183 /* Make sure that patched code is visible */ 184 isync 185 bctr 186#else 1870: trap 188 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 189#endif 190CLOSE_FIXED_SECTION(first_256B) 191 192/* 193 * On server, we include the exception vectors code here as it 194 * relies on absolute addressing which is only possible within 195 * this compilation unit 196 */ 197#ifdef CONFIG_PPC_BOOK3S 198#include "exceptions-64s.S" 199#else 200OPEN_TEXT_SECTION(0x100) 201#endif 202 203USE_TEXT_SECTION() 204 205#include "interrupt_64.S" 206 207#ifdef CONFIG_PPC_BOOK3E_64 208/* 209 * The booting_thread_hwid holds the thread id we want to boot in cpu 210 * hotplug case. It is set by cpu hotplug code, and is invalid by default. 211 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] 212 * bit field. 213 */ 214 .globl booting_thread_hwid 215booting_thread_hwid: 216 .long INVALID_THREAD_HWID 217 .align 3 218/* 219 * start a thread in the same core 220 * input parameters: 221 * r3 = the thread physical id 222 * r4 = the entry point where thread starts 223 */ 224_GLOBAL(book3e_start_thread) 225 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) 226 cmpwi r3, 0 227 beq 10f 228 cmpwi r3, 1 229 beq 11f 230 /* If the thread id is invalid, just exit. */ 231 b 13f 23210: 233 MTTMR(TMRN_IMSR0, 5) 234 MTTMR(TMRN_INIA0, 4) 235 b 12f 23611: 237 MTTMR(TMRN_IMSR1, 5) 238 MTTMR(TMRN_INIA1, 4) 23912: 240 isync 241 li r6, 1 242 sld r6, r6, r3 243 mtspr SPRN_TENS, r6 24413: 245 blr 246 247/* 248 * stop a thread in the same core 249 * input parameter: 250 * r3 = the thread physical id 251 */ 252_GLOBAL(book3e_stop_thread) 253 cmpwi r3, 0 254 beq 10f 255 cmpwi r3, 1 256 beq 10f 257 /* If the thread id is invalid, just exit. */ 258 b 13f 25910: 260 li r4, 1 261 sld r4, r4, r3 262 mtspr SPRN_TENC, r4 26313: 264 blr 265 266_GLOBAL(fsl_secondary_thread_init) 267 mfspr r4,SPRN_BUCSR 268 269 /* Enable branch prediction */ 270 lis r3,BUCSR_INIT@h 271 ori r3,r3,BUCSR_INIT@l 272 mtspr SPRN_BUCSR,r3 273 isync 274 275 /* 276 * Fix PIR to match the linear numbering in the device tree. 277 * 278 * On e6500, the reset value of PIR uses the low three bits for 279 * the thread within a core, and the upper bits for the core 280 * number. There are two threads per core, so shift everything 281 * but the low bit right by two bits so that the cpu numbering is 282 * continuous. 283 * 284 * If the old value of BUCSR is non-zero, this thread has run 285 * before. Thus, we assume we are coming from kexec or a similar 286 * scenario, and PIR is already set to the correct value. This 287 * is a bit of a hack, but there are limited opportunities for 288 * getting information into the thread and the alternatives 289 * seemed like they'd be overkill. We can't tell just by looking 290 * at the old PIR value which state it's in, since the same value 291 * could be valid for one thread out of reset and for a different 292 * thread in Linux. 293 */ 294 295 mfspr r3, SPRN_PIR 296 cmpwi r4,0 297 bne 1f 298 rlwimi r3, r3, 30, 2, 30 299 mtspr SPRN_PIR, r3 3001: 301 mr r24,r3 302 303 /* turn on 64-bit mode */ 304 bl enable_64b_mode 305 306 /* get a valid TOC pointer, wherever we're mapped at */ 307 bl relative_toc 308 tovirt(r2,r2) 309 310 /* Book3E initialization */ 311 mr r3,r24 312 bl book3e_secondary_thread_init 313 b generic_secondary_common_init 314 315#endif /* CONFIG_PPC_BOOK3E_64 */ 316 317/* 318 * On pSeries and most other platforms, secondary processors spin 319 * in the following code. 320 * At entry, r3 = this processor's number (physical cpu id) 321 * 322 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 323 * this core already exists (setup via some other mechanism such 324 * as SCOM before entry). 325 */ 326_GLOBAL(generic_secondary_smp_init) 327 FIXUP_ENDIAN 328 mr r24,r3 329 mr r25,r4 330 331 /* turn on 64-bit mode */ 332 bl enable_64b_mode 333 334 /* get a valid TOC pointer, wherever we're mapped at */ 335 bl relative_toc 336 tovirt(r2,r2) 337 338#ifdef CONFIG_PPC_BOOK3E_64 339 /* Book3E initialization */ 340 mr r3,r24 341 mr r4,r25 342 bl book3e_secondary_core_init 343 344/* 345 * After common core init has finished, check if the current thread is the 346 * one we wanted to boot. If not, start the specified thread and stop the 347 * current thread. 348 */ 349 LOAD_REG_ADDR(r4, booting_thread_hwid) 350 lwz r3, 0(r4) 351 li r5, INVALID_THREAD_HWID 352 cmpw r3, r5 353 beq 20f 354 355 /* 356 * The value of booting_thread_hwid has been stored in r3, 357 * so make it invalid. 358 */ 359 stw r5, 0(r4) 360 361 /* 362 * Get the current thread id and check if it is the one we wanted. 363 * If not, start the one specified in booting_thread_hwid and stop 364 * the current thread. 365 */ 366 mfspr r8, SPRN_TIR 367 cmpw r3, r8 368 beq 20f 369 370 /* start the specified thread */ 371 LOAD_REG_ADDR(r5, fsl_secondary_thread_init) 372 ld r4, 0(r5) 373 bl book3e_start_thread 374 375 /* stop the current thread */ 376 mr r3, r8 377 bl book3e_stop_thread 37810: 379 b 10b 38020: 381#endif 382 383generic_secondary_common_init: 384 /* Set up a paca value for this processor. Since we have the 385 * physical cpu id in r24, we need to search the pacas to find 386 * which logical id maps to our physical one. 387 */ 388#ifndef CONFIG_SMP 389 b kexec_wait /* wait for next kernel if !SMP */ 390#else 391 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ 392 ld r8,0(r8) /* Get base vaddr of array */ 393#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS) 394 LOAD_REG_IMMEDIATE(r7, NR_CPUS) 395#else 396 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 397 lwz r7,0(r7) /* also the max paca allocated */ 398#endif 399 li r5,0 /* logical cpu id */ 4001: 401 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ 402 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ 403 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 404 cmpw r6,r24 /* Compare to our id */ 405 beq 2f 406 addi r5,r5,1 407 cmpw r5,r7 /* Check if more pacas exist */ 408 blt 1b 409 410 mr r3,r24 /* not found, copy phys to r3 */ 411 b kexec_wait /* next kernel might do better */ 412 4132: SET_PACA(r13) 414#ifdef CONFIG_PPC_BOOK3E_64 415 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 416 mtspr SPRN_SPRG_TLB_EXFRAME,r12 417#endif 418 419 /* From now on, r24 is expected to be logical cpuid */ 420 mr r24,r5 421 422 /* Create a temp kernel stack for use before relocation is on. */ 423 ld r1,PACAEMERGSP(r13) 424 subi r1,r1,STACK_FRAME_MIN_SIZE 425 426 /* See if we need to call a cpu state restore handler */ 427 LOAD_REG_ADDR(r23, cur_cpu_spec) 428 ld r23,0(r23) 429 ld r12,CPU_SPEC_RESTORE(r23) 430 cmpdi 0,r12,0 431 beq 3f 432#ifdef CONFIG_PPC64_ELF_ABI_V1 433 ld r12,0(r12) 434#endif 435 mtctr r12 436 bctrl 437 4383: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 439 lwarx r4,0,r3 440 subi r4,r4,1 441 stwcx. r4,0,r3 442 bne 3b 443 isync 444 4454: HMT_LOW 446 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 447 /* start. */ 448 cmpwi 0,r23,0 449 beq 4b /* Loop until told to go */ 450 451 sync /* order paca.run and cur_cpu_spec */ 452 isync /* In case code patching happened */ 453 454 b __secondary_start 455#endif /* SMP */ 456 457/* 458 * Turn the MMU off. 459 * Assumes we're mapped EA == RA if the MMU is on. 460 */ 461#ifdef CONFIG_PPC_BOOK3S 462SYM_FUNC_START_LOCAL(__mmu_off) 463 mfmsr r3 464 andi. r0,r3,MSR_IR|MSR_DR 465 beqlr 466 mflr r4 467 andc r3,r3,r0 468 mtspr SPRN_SRR0,r4 469 mtspr SPRN_SRR1,r3 470 sync 471 rfid 472 b . /* prevent speculative execution */ 473SYM_FUNC_END(__mmu_off) 474 475SYM_FUNC_START_LOCAL(start_initialization_book3s) 476 mflr r25 477 478 /* Setup some critical 970 SPRs before switching MMU off */ 479 mfspr r0,SPRN_PVR 480 srwi r0,r0,16 481 cmpwi r0,0x39 /* 970 */ 482 beq 1f 483 cmpwi r0,0x3c /* 970FX */ 484 beq 1f 485 cmpwi r0,0x44 /* 970MP */ 486 beq 1f 487 cmpwi r0,0x45 /* 970GX */ 488 bne 2f 4891: bl __cpu_preinit_ppc970 4902: 491 492 /* Switch off MMU if not already off */ 493 bl __mmu_off 494 495 mtlr r25 496 blr 497SYM_FUNC_END(start_initialization_book3s) 498#endif 499 500/* 501 * Here is our main kernel entry point. We support currently 2 kind of entries 502 * depending on the value of r5. 503 * 504 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 505 * in r3...r7 506 * 507 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 508 * DT block, r4 is a physical pointer to the kernel itself 509 * 510 */ 511__start_initialization_multiplatform: 512 /* Make sure we are running in 64 bits mode */ 513 bl enable_64b_mode 514 515 /* Zero r13 (paca) so early program check / mce don't use it */ 516 li r13,0 517 518 /* Get TOC pointer (current runtime address) */ 519 bl relative_toc 520 521 /* find out where we are now */ 522 bcl 20,31,$+4 5230: mflr r26 /* r26 = runtime addr here */ 524 addis r26,r26,(_stext - 0b)@ha 525 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 526 527 /* 528 * Are we booted from a PROM Of-type client-interface ? 529 */ 530 cmpldi cr0,r5,0 531 beq 1f 532 b __boot_from_prom /* yes -> prom */ 5331: 534 /* Save parameters */ 535 mr r31,r3 536 mr r30,r4 537#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 538 /* Save OPAL entry */ 539 mr r28,r8 540 mr r29,r9 541#endif 542 543#ifdef CONFIG_PPC_BOOK3E_64 544 bl start_initialization_book3e 545#else 546 bl start_initialization_book3s 547#endif /* CONFIG_PPC_BOOK3E_64 */ 548 b __after_prom_start 549 550__REF 551__boot_from_prom: 552#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 553 /* Save parameters */ 554 mr r31,r3 555 mr r30,r4 556 mr r29,r5 557 mr r28,r6 558 mr r27,r7 559 560 /* 561 * Align the stack to 16-byte boundary 562 * Depending on the size and layout of the ELF sections in the initial 563 * boot binary, the stack pointer may be unaligned on PowerMac 564 */ 565 rldicr r1,r1,0,59 566 567#ifdef CONFIG_RELOCATABLE 568 /* Relocate code for where we are now */ 569 mr r3,r26 570 bl relocate 571#endif 572 573 /* Restore parameters */ 574 mr r3,r31 575 mr r4,r30 576 mr r5,r29 577 mr r6,r28 578 mr r7,r27 579 580 /* Do all of the interaction with OF client interface */ 581 mr r8,r26 582 bl prom_init 583#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 584 585 /* We never return. We also hit that trap if trying to boot 586 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 587 trap 588 .previous 589 590__after_prom_start: 591#ifdef CONFIG_RELOCATABLE 592 /* process relocations for the final address of the kernel */ 593 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 594 sldi r25,r25,32 595#if defined(CONFIG_PPC_BOOK3E_64) 596 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 597#endif 598 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 599#if defined(CONFIG_PPC_BOOK3E_64) 600 tophys(r26,r26) 601#endif 602 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 603 bne 1f 604 add r25,r25,r26 6051: mr r3,r25 606 bl relocate 607#if defined(CONFIG_PPC_BOOK3E_64) 608 /* IVPR needs to be set after relocation. */ 609 bl init_core_book3e 610#endif 611#endif 612 613/* 614 * We need to run with _stext at physical address PHYSICAL_START. 615 * This will leave some code in the first 256B of 616 * real memory, which are reserved for software use. 617 * 618 * Note: This process overwrites the OF exception vectors. 619 */ 620 li r3,0 /* target addr */ 621#ifdef CONFIG_PPC_BOOK3E_64 622 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 623#endif 624 mr. r4,r26 /* In some cases the loader may */ 625#if defined(CONFIG_PPC_BOOK3E_64) 626 tovirt(r4,r4) 627#endif 628 beq 9f /* have already put us at zero */ 629 li r6,0x100 /* Start offset, the first 0x100 */ 630 /* bytes were copied earlier. */ 631 632#ifdef CONFIG_RELOCATABLE 633/* 634 * Check if the kernel has to be running as relocatable kernel based on the 635 * variable __run_at_load, if it is set the kernel is treated as relocatable 636 * kernel, otherwise it will be moved to PHYSICAL_START 637 */ 638#if defined(CONFIG_PPC_BOOK3E_64) 639 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 640#endif 641 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 642 cmplwi cr0,r7,1 643 bne 3f 644 645#ifdef CONFIG_PPC_BOOK3E_64 646 LOAD_REG_ADDR(r5, __end_interrupts) 647 LOAD_REG_ADDR(r11, _stext) 648 sub r5,r5,r11 649#else 650 /* just copy interrupts */ 651 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) 652#endif 653 b 5f 6543: 655#endif 656 /* # bytes of memory to copy */ 657 lis r5,(ABS_ADDR(copy_to_here, text))@ha 658 addi r5,r5,(ABS_ADDR(copy_to_here, text))@l 659 660 bl copy_and_flush /* copy the first n bytes */ 661 /* this includes the code being */ 662 /* executed here. */ 663 /* Jump to the copy of this code that we just made */ 664 addis r8,r3,(ABS_ADDR(4f, text))@ha 665 addi r12,r8,(ABS_ADDR(4f, text))@l 666 mtctr r12 667 bctr 668 669.balign 8 670p_end: .8byte _end - copy_to_here 671 6724: 673 /* 674 * Now copy the rest of the kernel up to _end, add 675 * _end - copy_to_here to the copy limit and run again. 676 */ 677 addis r8,r26,(ABS_ADDR(p_end, text))@ha 678 ld r8,(ABS_ADDR(p_end, text))@l(r8) 679 add r5,r5,r8 6805: bl copy_and_flush /* copy the rest */ 681 6829: b start_here_multiplatform 683 684/* 685 * Copy routine used to copy the kernel to start at physical address 0 686 * and flush and invalidate the caches as needed. 687 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 688 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 689 * 690 * Note: this routine *only* clobbers r0, r6 and lr 691 */ 692_GLOBAL(copy_and_flush) 693 addi r5,r5,-8 694 addi r6,r6,-8 6954: li r0,8 /* Use the smallest common */ 696 /* denominator cache line */ 697 /* size. This results in */ 698 /* extra cache line flushes */ 699 /* but operation is correct. */ 700 /* Can't get cache line size */ 701 /* from NACA as it is being */ 702 /* moved too. */ 703 704 mtctr r0 /* put # words/line in ctr */ 7053: addi r6,r6,8 /* copy a cache line */ 706 ldx r0,r6,r4 707 stdx r0,r6,r3 708 bdnz 3b 709 dcbst r6,r3 /* write it to memory */ 710 sync 711 icbi r6,r3 /* flush the icache line */ 712 cmpld 0,r6,r5 713 blt 4b 714 sync 715 addi r5,r5,8 716 addi r6,r6,8 717 isync 718 blr 719 720_ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */ 721 722.align 8 723copy_to_here: 724 725#ifdef CONFIG_SMP 726#ifdef CONFIG_PPC_PMAC 727/* 728 * On PowerMac, secondary processors starts from the reset vector, which 729 * is temporarily turned into a call to one of the functions below. 730 */ 731 .section ".text"; 732 .align 2 ; 733 734 .globl __secondary_start_pmac_0 735__secondary_start_pmac_0: 736 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 737 li r24,0 738 b 1f 739 li r24,1 740 b 1f 741 li r24,2 742 b 1f 743 li r24,3 7441: 745 746_GLOBAL(pmac_secondary_start) 747 /* turn on 64-bit mode */ 748 bl enable_64b_mode 749 750 li r0,0 751 mfspr r3,SPRN_HID4 752 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 753 sync 754 mtspr SPRN_HID4,r3 755 isync 756 sync 757 slbia 758 759 /* get TOC pointer (real address) */ 760 bl relative_toc 761 tovirt(r2,r2) 762 763 /* Copy some CPU settings from CPU 0 */ 764 bl __restore_cpu_ppc970 765 766 /* pSeries do that early though I don't think we really need it */ 767 mfmsr r3 768 ori r3,r3,MSR_RI 769 mtmsrd r3 /* RI on */ 770 771 /* Set up a paca value for this processor. */ 772 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ 773 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ 774 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ 775 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ 776 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 777 778 /* Mark interrupts soft and hard disabled (they might be enabled 779 * in the PACA when doing hotplug) 780 */ 781 li r0,IRQS_DISABLED 782 stb r0,PACAIRQSOFTMASK(r13) 783 li r0,PACA_IRQ_HARD_DIS 784 stb r0,PACAIRQHAPPENED(r13) 785 786 /* Create a temp kernel stack for use before relocation is on. */ 787 ld r1,PACAEMERGSP(r13) 788 subi r1,r1,STACK_FRAME_MIN_SIZE 789 790 b __secondary_start 791 792#endif /* CONFIG_PPC_PMAC */ 793 794/* 795 * This function is called after the master CPU has released the 796 * secondary processors. The execution environment is relocation off. 797 * The paca for this processor has the following fields initialized at 798 * this point: 799 * 1. Processor number 800 * 2. Segment table pointer (virtual address) 801 * On entry the following are set: 802 * r1 = stack pointer (real addr of temp stack) 803 * r24 = cpu# (in Linux terms) 804 * r13 = paca virtual address 805 * SPRG_PACA = paca virtual address 806 */ 807 .section ".text"; 808 .align 2 ; 809 810 .globl __secondary_start 811__secondary_start: 812 /* Set thread priority to MEDIUM */ 813 HMT_MEDIUM 814 815 /* 816 * Do early setup for this CPU, in particular initialising the MMU so we 817 * can turn it on below. This is a call to C, which is OK, we're still 818 * running on the emergency stack. 819 */ 820 bl early_setup_secondary 821 822 /* 823 * The primary has initialized our kernel stack for us in the paca, grab 824 * it and put it in r1. We must *not* use it until we turn on the MMU 825 * below, because it may not be inside the RMO. 826 */ 827 ld r1, PACAKSAVE(r13) 828 829 /* Clear backchain so we get nice backtraces */ 830 li r7,0 831 mtlr r7 832 833 /* Mark interrupts soft and hard disabled (they might be enabled 834 * in the PACA when doing hotplug) 835 */ 836 li r7,IRQS_DISABLED 837 stb r7,PACAIRQSOFTMASK(r13) 838 li r0,PACA_IRQ_HARD_DIS 839 stb r0,PACAIRQHAPPENED(r13) 840 841 /* enable MMU and jump to start_secondary */ 842 LOAD_REG_ADDR(r3, start_secondary_prolog) 843 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 844 845 mtspr SPRN_SRR0,r3 846 mtspr SPRN_SRR1,r4 847 RFI_TO_KERNEL 848 b . /* prevent speculative execution */ 849 850/* 851 * Running with relocation on at this point. All we want to do is 852 * zero the stack back-chain pointer and get the TOC virtual address 853 * before going into C code. 854 */ 855start_secondary_prolog: 856 LOAD_PACA_TOC() 857 li r3,0 858 std r3,0(r1) /* Zero the stack frame pointer */ 859 bl start_secondary 860 b . 861/* 862 * Reset stack pointer and call start_secondary 863 * to continue with online operation when woken up 864 * from cede in cpu offline. 865 */ 866_GLOBAL(start_secondary_resume) 867 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 868 li r3,0 869 std r3,0(r1) /* Zero the stack frame pointer */ 870 bl start_secondary 871 b . 872#endif 873 874/* 875 * This subroutine clobbers r11 and r12 876 */ 877SYM_FUNC_START_LOCAL(enable_64b_mode) 878 mfmsr r11 /* grab the current MSR */ 879#ifdef CONFIG_PPC_BOOK3E_64 880 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 881 mtmsr r11 882#else /* CONFIG_PPC_BOOK3E_64 */ 883 LOAD_REG_IMMEDIATE(r12, MSR_64BIT) 884 or r11,r11,r12 885 mtmsrd r11 886 isync 887#endif 888 blr 889SYM_FUNC_END(enable_64b_mode) 890 891/* 892 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 893 * by the toolchain). It computes the correct value for wherever we 894 * are running at the moment, using position-independent code. 895 * 896 * Note: The compiler constructs pointers using offsets from the 897 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 898 * the MMU is on we need our TOC to be a virtual address otherwise 899 * these pointers will be real addresses which may get stored and 900 * accessed later with the MMU on. We use tovirt() at the call 901 * sites to handle this. 902 */ 903_GLOBAL(relative_toc) 904 mflr r0 905 bcl 20,31,$+4 9060: mflr r11 907 ld r2,(p_toc - 0b)(r11) 908 add r2,r2,r11 909 mtlr r0 910 blr 911 912.balign 8 913p_toc: .8byte .TOC. - 0b 914 915/* 916 * This is where the main kernel code starts. 917 */ 918__REF 919start_here_multiplatform: 920 /* set up the TOC */ 921 bl relative_toc 922 tovirt(r2,r2) 923 924 /* Clear out the BSS. It may have been done in prom_init, 925 * already but that's irrelevant since prom_init will soon 926 * be detached from the kernel completely. Besides, we need 927 * to clear it now for kexec-style entry. 928 */ 929 LOAD_REG_ADDR(r11,__bss_stop) 930 LOAD_REG_ADDR(r8,__bss_start) 931 sub r11,r11,r8 /* bss size */ 932 addi r11,r11,7 /* round up to an even double word */ 933 srdi. r11,r11,3 /* shift right by 3 */ 934 beq 4f 935 addi r8,r8,-8 936 li r0,0 937 mtctr r11 /* zero this many doublewords */ 9383: stdu r0,8(r8) 939 bdnz 3b 9404: 941 942#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 943 /* Setup OPAL entry */ 944 LOAD_REG_ADDR(r11, opal) 945 std r28,0(r11); 946 std r29,8(r11); 947#endif 948 949#ifndef CONFIG_PPC_BOOK3E_64 950 mfmsr r6 951 ori r6,r6,MSR_RI 952 mtmsrd r6 /* RI on */ 953#endif 954 955#ifdef CONFIG_RELOCATABLE 956 /* Save the physical address we're running at in kernstart_addr */ 957 LOAD_REG_ADDR(r4, kernstart_addr) 958 clrldi r0,r25,2 959 std r0,0(r4) 960#endif 961 962 /* set up a stack pointer */ 963 LOAD_REG_ADDR(r3,init_thread_union) 964 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) 965 add r1,r3,r1 966 li r0,0 967 stdu r0,-STACK_FRAME_MIN_SIZE(r1) 968 969 /* 970 * Do very early kernel initializations, including initial hash table 971 * and SLB setup before we turn on relocation. 972 */ 973 974#ifdef CONFIG_KASAN 975 bl kasan_early_init 976#endif 977 /* Restore parameters passed from prom_init/kexec */ 978 mr r3,r31 979 LOAD_REG_ADDR(r12, DOTSYM(early_setup)) 980 mtctr r12 981 bctrl /* also sets r13 and SPRG_PACA */ 982 983 LOAD_REG_ADDR(r3, start_here_common) 984 ld r4,PACAKMSR(r13) 985 mtspr SPRN_SRR0,r3 986 mtspr SPRN_SRR1,r4 987 RFI_TO_KERNEL 988 b . /* prevent speculative execution */ 989 990 /* This is where all platforms converge execution */ 991 992start_here_common: 993 /* relocation is on at this point */ 994 std r1,PACAKSAVE(r13) 995 996 /* Load the TOC (virtual address) */ 997 LOAD_PACA_TOC() 998 999 /* Mark interrupts soft and hard disabled (they might be enabled 1000 * in the PACA when doing hotplug) 1001 */ 1002 li r0,IRQS_DISABLED 1003 stb r0,PACAIRQSOFTMASK(r13) 1004 li r0,PACA_IRQ_HARD_DIS 1005 stb r0,PACAIRQHAPPENED(r13) 1006 1007 /* Generic kernel entry */ 1008 bl start_kernel 1009 1010 /* Not reached */ 10110: trap 1012 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 1013 .previous 1014