1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * 6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Adapted for Power Macintosh by Paul Mackerras. 9 * Low-level exception handlers and MMU support 10 * rewritten by Paul Mackerras. 11 * Copyright (C) 1996 Paul Mackerras. 12 * 13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 15 * 16 * This file contains the entry point for the 64-bit kernel along 17 * with some early initialization code common to all 64-bit powerpc 18 * variants. 19 */ 20 21#include <linux/linkage.h> 22#include <linux/threads.h> 23#include <linux/init.h> 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/mmu.h> 27#include <asm/ppc_asm.h> 28#include <asm/head-64.h> 29#include <asm/asm-offsets.h> 30#include <asm/bug.h> 31#include <asm/cputable.h> 32#include <asm/setup.h> 33#include <asm/hvcall.h> 34#include <asm/thread_info.h> 35#include <asm/firmware.h> 36#include <asm/page_64.h> 37#include <asm/irqflags.h> 38#include <asm/kvm_book3s_asm.h> 39#include <asm/ptrace.h> 40#include <asm/hw_irq.h> 41#include <asm/cputhreads.h> 42#include <asm/ppc-opcode.h> 43#include <asm/export.h> 44#include <asm/feature-fixups.h> 45#ifdef CONFIG_PPC_BOOK3S 46#include <asm/exception-64s.h> 47#else 48#include <asm/exception-64e.h> 49#endif 50 51/* The physical memory is laid out such that the secondary processor 52 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 53 * using the layout described in exceptions-64s.S 54 */ 55 56/* 57 * Entering into this code we make the following assumptions: 58 * 59 * For pSeries or server processors: 60 * 1. The MMU is off & open firmware is running in real mode. 61 * 2. The primary CPU enters at __start. 62 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary 63 * CPUs will enter as directed by "start-cpu" RTAS call, which is 64 * generic_secondary_smp_init, with PIR in r3. 65 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as 66 * directed by the "start-cpu" RTS call, with PIR in r3. 67 * -or- For OPAL entry: 68 * 1. The MMU is off, processor in HV mode. 69 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base 70 * in r8, and entry in r9 for debugging purposes. 71 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which 72 * is at generic_secondary_smp_init, with PIR in r3. 73 * 74 * For Book3E processors: 75 * 1. The MMU is on running in AS0 in a state defined in ePAPR 76 * 2. The kernel is entered at __start 77 */ 78 79/* 80 * boot_from_prom and prom_init run at the physical address. Everything 81 * after prom and kexec entry run at the virtual address (PAGE_OFFSET). 82 * Secondaries run at the virtual address from generic_secondary_common_init 83 * onward. 84 */ 85 86OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) 87USE_FIXED_SECTION(first_256B) 88 /* 89 * Offsets are relative from the start of fixed section, and 90 * first_256B starts at 0. Offsets are a bit easier to use here 91 * than the fixed section entry macros. 92 */ 93 . = 0x0 94_GLOBAL(__start) 95 /* NOP this out unconditionally */ 96BEGIN_FTR_SECTION 97 FIXUP_ENDIAN 98 b __start_initialization_multiplatform 99END_FTR_SECTION(0, 1) 100 101 /* Catch branch to 0 in real mode */ 102 trap 103 104 /* Secondary processors spin on this value until it becomes non-zero. 105 * When non-zero, it contains the real address of the function the cpu 106 * should jump to. 107 */ 108 .balign 8 109 .globl __secondary_hold_spinloop 110__secondary_hold_spinloop: 111 .8byte 0x0 112 113 /* Secondary processors write this value with their cpu # */ 114 /* after they enter the spin loop immediately below. */ 115 .globl __secondary_hold_acknowledge 116__secondary_hold_acknowledge: 117 .8byte 0x0 118 119#ifdef CONFIG_RELOCATABLE 120 /* This flag is set to 1 by a loader if the kernel should run 121 * at the loaded address instead of the linked address. This 122 * is used by kexec-tools to keep the kdump kernel in the 123 * crash_kernel region. The loader is responsible for 124 * observing the alignment requirement. 125 */ 126 127#ifdef CONFIG_RELOCATABLE_TEST 128#define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ 129#else 130#define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ 131#endif 132 133 /* Do not move this variable as kexec-tools knows about it. */ 134 . = 0x5c 135 .globl __run_at_load 136__run_at_load: 137DEFINE_FIXED_SYMBOL(__run_at_load, first_256B) 138 .long RUN_AT_LOAD_DEFAULT 139#endif 140 141 . = 0x60 142/* 143 * The following code is used to hold secondary processors 144 * in a spin loop after they have entered the kernel, but 145 * before the bulk of the kernel has been relocated. This code 146 * is relocated to physical address 0x60 before prom_init is run. 147 * All of it must fit below the first exception vector at 0x100. 148 * Use .globl here not _GLOBAL because we want __secondary_hold 149 * to be the actual text address, not a descriptor. 150 */ 151 .globl __secondary_hold 152__secondary_hold: 153 FIXUP_ENDIAN 154#ifndef CONFIG_PPC_BOOK3E_64 155 mfmsr r24 156 ori r24,r24,MSR_RI 157 mtmsrd r24 /* RI on */ 158#endif 159 /* Grab our physical cpu number */ 160 mr r24,r3 161 /* stash r4 for book3e */ 162 mr r25,r4 163 164 /* Tell the master cpu we're here */ 165 /* Relocation is off & we are located at an address less */ 166 /* than 0x100, so only need to grab low order offset. */ 167 std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0) 168 sync 169 170 /* All secondary cpus wait here until told to start. */ 171100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(0) 172 cmpdi 0,r12,0 173 beq 100b 174 175#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 176#ifdef CONFIG_PPC_BOOK3E_64 177 tovirt(r12,r12) 178#endif 179 mtctr r12 180 mr r3,r24 181 /* 182 * it may be the case that other platforms have r4 right to 183 * begin with, this gives us some safety in case it is not 184 */ 185#ifdef CONFIG_PPC_BOOK3E_64 186 mr r4,r25 187#else 188 li r4,0 189#endif 190 /* Make sure that patched code is visible */ 191 isync 192 bctr 193#else 1940: trap 195 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 196#endif 197CLOSE_FIXED_SECTION(first_256B) 198 199/* 200 * On server, we include the exception vectors code here as it 201 * relies on absolute addressing which is only possible within 202 * this compilation unit 203 */ 204#ifdef CONFIG_PPC_BOOK3S 205#include "exceptions-64s.S" 206#else 207OPEN_TEXT_SECTION(0x100) 208#endif 209 210USE_TEXT_SECTION() 211 212#include "interrupt_64.S" 213 214#ifdef CONFIG_PPC_BOOK3E_64 215/* 216 * The booting_thread_hwid holds the thread id we want to boot in cpu 217 * hotplug case. It is set by cpu hotplug code, and is invalid by default. 218 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] 219 * bit field. 220 */ 221 .globl booting_thread_hwid 222booting_thread_hwid: 223 .long INVALID_THREAD_HWID 224 .align 3 225/* 226 * start a thread in the same core 227 * input parameters: 228 * r3 = the thread physical id 229 * r4 = the entry point where thread starts 230 */ 231_GLOBAL(book3e_start_thread) 232 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) 233 cmpwi r3, 0 234 beq 10f 235 cmpwi r3, 1 236 beq 11f 237 /* If the thread id is invalid, just exit. */ 238 b 13f 23910: 240 MTTMR(TMRN_IMSR0, 5) 241 MTTMR(TMRN_INIA0, 4) 242 b 12f 24311: 244 MTTMR(TMRN_IMSR1, 5) 245 MTTMR(TMRN_INIA1, 4) 24612: 247 isync 248 li r6, 1 249 sld r6, r6, r3 250 mtspr SPRN_TENS, r6 25113: 252 blr 253 254/* 255 * stop a thread in the same core 256 * input parameter: 257 * r3 = the thread physical id 258 */ 259_GLOBAL(book3e_stop_thread) 260 cmpwi r3, 0 261 beq 10f 262 cmpwi r3, 1 263 beq 10f 264 /* If the thread id is invalid, just exit. */ 265 b 13f 26610: 267 li r4, 1 268 sld r4, r4, r3 269 mtspr SPRN_TENC, r4 27013: 271 blr 272 273_GLOBAL(fsl_secondary_thread_init) 274 mfspr r4,SPRN_BUCSR 275 276 /* Enable branch prediction */ 277 lis r3,BUCSR_INIT@h 278 ori r3,r3,BUCSR_INIT@l 279 mtspr SPRN_BUCSR,r3 280 isync 281 282 /* 283 * Fix PIR to match the linear numbering in the device tree. 284 * 285 * On e6500, the reset value of PIR uses the low three bits for 286 * the thread within a core, and the upper bits for the core 287 * number. There are two threads per core, so shift everything 288 * but the low bit right by two bits so that the cpu numbering is 289 * continuous. 290 * 291 * If the old value of BUCSR is non-zero, this thread has run 292 * before. Thus, we assume we are coming from kexec or a similar 293 * scenario, and PIR is already set to the correct value. This 294 * is a bit of a hack, but there are limited opportunities for 295 * getting information into the thread and the alternatives 296 * seemed like they'd be overkill. We can't tell just by looking 297 * at the old PIR value which state it's in, since the same value 298 * could be valid for one thread out of reset and for a different 299 * thread in Linux. 300 */ 301 302 mfspr r3, SPRN_PIR 303 cmpwi r4,0 304 bne 1f 305 rlwimi r3, r3, 30, 2, 30 306 mtspr SPRN_PIR, r3 3071: 308 mr r24,r3 309 310 /* turn on 64-bit mode */ 311 bl enable_64b_mode 312 313 /* Book3E initialization */ 314 mr r3,r24 315 bl book3e_secondary_thread_init 316 bl relative_toc 317 318 b generic_secondary_common_init 319 320#endif /* CONFIG_PPC_BOOK3E_64 */ 321 322/* 323 * On pSeries and most other platforms, secondary processors spin 324 * in the following code. 325 * At entry, r3 = this processor's number (physical cpu id) 326 * 327 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 328 * this core already exists (setup via some other mechanism such 329 * as SCOM before entry). 330 */ 331_GLOBAL(generic_secondary_smp_init) 332 FIXUP_ENDIAN 333 334 li r13,0 335 336 /* Poison TOC */ 337 li r2,-1 338 339 mr r24,r3 340 mr r25,r4 341 342 /* turn on 64-bit mode */ 343 bl enable_64b_mode 344 345#ifdef CONFIG_PPC_BOOK3E_64 346 /* Book3E initialization */ 347 mr r3,r24 348 mr r4,r25 349 bl book3e_secondary_core_init 350 /* Now NIA and r2 are relocated to PAGE_OFFSET if not already */ 351/* 352 * After common core init has finished, check if the current thread is the 353 * one we wanted to boot. If not, start the specified thread and stop the 354 * current thread. 355 */ 356 LOAD_REG_ADDR(r4, booting_thread_hwid) 357 lwz r3, 0(r4) 358 li r5, INVALID_THREAD_HWID 359 cmpw r3, r5 360 beq 20f 361 362 /* 363 * The value of booting_thread_hwid has been stored in r3, 364 * so make it invalid. 365 */ 366 stw r5, 0(r4) 367 368 /* 369 * Get the current thread id and check if it is the one we wanted. 370 * If not, start the one specified in booting_thread_hwid and stop 371 * the current thread. 372 */ 373 mfspr r8, SPRN_TIR 374 cmpw r3, r8 375 beq 20f 376 377 /* start the specified thread */ 378 LOAD_REG_ADDR(r5, DOTSYM(fsl_secondary_thread_init)) 379 bl book3e_start_thread 380 381 /* stop the current thread */ 382 mr r3, r8 383 bl book3e_stop_thread 38410: 385 b 10b 38620: 387#else 388 /* Now the MMU is off, can branch to our PAGE_OFFSET address */ 389 bcl 20,31,$+4 3901: mflr r11 391 addi r11,r11,(2f - 1b) 392 tovirt(r11, r11) 393 mtctr r11 394 bctr 3952: 396 bl relative_toc 397#endif 398 399generic_secondary_common_init: 400 /* Set up a paca value for this processor. Since we have the 401 * physical cpu id in r24, we need to search the pacas to find 402 * which logical id maps to our physical one. 403 */ 404#ifndef CONFIG_SMP 405 b kexec_wait /* wait for next kernel if !SMP */ 406#else 407 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ 408 ld r8,0(r8) /* Get base vaddr of array */ 409#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS) 410 LOAD_REG_IMMEDIATE(r7, NR_CPUS) 411#else 412 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 413 lwz r7,0(r7) /* also the max paca allocated */ 414#endif 415 li r5,0 /* logical cpu id */ 4161: 417 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ 418 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ 419 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 420 cmpw r6,r24 /* Compare to our id */ 421 beq 2f 422 addi r5,r5,1 423 cmpw r5,r7 /* Check if more pacas exist */ 424 blt 1b 425 426 mr r3,r24 /* not found, copy phys to r3 */ 427 b kexec_wait /* next kernel might do better */ 428 4292: SET_PACA(r13) 430#ifdef CONFIG_PPC_BOOK3E_64 431 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 432 mtspr SPRN_SPRG_TLB_EXFRAME,r12 433#endif 434 435 /* From now on, r24 is expected to be logical cpuid */ 436 mr r24,r5 437 438 /* Create a temp kernel stack for use before relocation is on. */ 439 ld r1,PACAEMERGSP(r13) 440 subi r1,r1,STACK_FRAME_MIN_SIZE 441 442 /* See if we need to call a cpu state restore handler */ 443 LOAD_REG_ADDR(r23, cur_cpu_spec) 444 ld r23,0(r23) 445 ld r12,CPU_SPEC_RESTORE(r23) 446 cmpdi 0,r12,0 447 beq 3f 448#ifdef CONFIG_PPC64_ELF_ABI_V1 449 ld r12,0(r12) 450#endif 451 mtctr r12 452 bctrl 453 4543: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 455 lwarx r4,0,r3 456 subi r4,r4,1 457 stwcx. r4,0,r3 458 bne 3b 459 isync 460 4614: HMT_LOW 462 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 463 /* start. */ 464 cmpwi 0,r23,0 465 beq 4b /* Loop until told to go */ 466 467 sync /* order paca.run and cur_cpu_spec */ 468 isync /* In case code patching happened */ 469 470 b __secondary_start 471#endif /* SMP */ 472 473/* 474 * Turn the MMU off. 475 * Assumes we're mapped EA == RA if the MMU is on. 476 */ 477#ifdef CONFIG_PPC_BOOK3S 478SYM_FUNC_START_LOCAL(__mmu_off) 479 mfmsr r3 480 andi. r0,r3,MSR_IR|MSR_DR 481 beqlr 482 mflr r4 483 andc r3,r3,r0 484 mtspr SPRN_SRR0,r4 485 mtspr SPRN_SRR1,r3 486 sync 487 rfid 488 b . /* prevent speculative execution */ 489SYM_FUNC_END(__mmu_off) 490 491SYM_FUNC_START_LOCAL(start_initialization_book3s) 492 mflr r25 493 494 /* Setup some critical 970 SPRs before switching MMU off */ 495 mfspr r0,SPRN_PVR 496 srwi r0,r0,16 497 cmpwi r0,0x39 /* 970 */ 498 beq 1f 499 cmpwi r0,0x3c /* 970FX */ 500 beq 1f 501 cmpwi r0,0x44 /* 970MP */ 502 beq 1f 503 cmpwi r0,0x45 /* 970GX */ 504 bne 2f 5051: bl __cpu_preinit_ppc970 5062: 507 508 /* Switch off MMU if not already off */ 509 bl __mmu_off 510 511 /* Now the MMU is off, can return to our PAGE_OFFSET address */ 512 tovirt(r25,r25) 513 mtlr r25 514 blr 515SYM_FUNC_END(start_initialization_book3s) 516#endif 517 518/* 519 * Here is our main kernel entry point. We support currently 2 kind of entries 520 * depending on the value of r5. 521 * 522 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 523 * in r3...r7 524 * 525 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 526 * DT block, r4 is a physical pointer to the kernel itself 527 * 528 */ 529__start_initialization_multiplatform: 530 /* Make sure we are running in 64 bits mode */ 531 bl enable_64b_mode 532 533 /* Zero r13 (paca) so early program check / mce don't use it */ 534 li r13,0 535 536 /* Poison TOC */ 537 li r2,-1 538 539 /* 540 * Are we booted from a PROM Of-type client-interface ? 541 */ 542 cmpldi cr0,r5,0 543 beq 1f 544 b __boot_from_prom /* yes -> prom */ 5451: 546 /* Save parameters */ 547 mr r31,r3 548 mr r30,r4 549#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 550 /* Save OPAL entry */ 551 mr r28,r8 552 mr r29,r9 553#endif 554 555 /* Get TOC pointer (current runtime address) */ 556 bl relative_toc 557 558 /* These functions return to the virtual (PAGE_OFFSET) address */ 559#ifdef CONFIG_PPC_BOOK3E_64 560 bl start_initialization_book3e 561#else 562 bl start_initialization_book3s 563#endif /* CONFIG_PPC_BOOK3E_64 */ 564 565 /* Get TOC pointer, virtual */ 566 bl relative_toc 567 568 /* find out where we are now */ 569 570 /* OPAL doesn't pass base address in r4, have to derive it. */ 571 bcl 20,31,$+4 5720: mflr r26 /* r26 = runtime addr here */ 573 addis r26,r26,(_stext - 0b)@ha 574 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 575 576 b __after_prom_start 577 578__REF 579__boot_from_prom: 580#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 581 /* Get TOC pointer, non-virtual */ 582 bl relative_toc 583 584 /* find out where we are now */ 585 bcl 20,31,$+4 5860: mflr r26 /* r26 = runtime addr here */ 587 addis r26,r26,(_stext - 0b)@ha 588 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 589 590 /* Save parameters */ 591 mr r31,r3 592 mr r30,r4 593 mr r29,r5 594 mr r28,r6 595 mr r27,r7 596 597 /* 598 * Align the stack to 16-byte boundary 599 * Depending on the size and layout of the ELF sections in the initial 600 * boot binary, the stack pointer may be unaligned on PowerMac 601 */ 602 rldicr r1,r1,0,59 603 604#ifdef CONFIG_RELOCATABLE 605 /* Relocate code for where we are now */ 606 mr r3,r26 607 bl relocate 608#endif 609 610 /* Restore parameters */ 611 mr r3,r31 612 mr r4,r30 613 mr r5,r29 614 mr r6,r28 615 mr r7,r27 616 617 /* Do all of the interaction with OF client interface */ 618 mr r8,r26 619 bl CFUNC(prom_init) 620#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 621 622 /* We never return. We also hit that trap if trying to boot 623 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 624 trap 625 .previous 626 627__after_prom_start: 628#ifdef CONFIG_RELOCATABLE 629 /* process relocations for the final address of the kernel */ 630 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 631 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 632 mr r25,r26 /* then use current kernel base */ 633 beq 1f 634 LOAD_REG_IMMEDIATE(r25, PAGE_OFFSET) /* else use static kernel base */ 6351: mr r3,r25 636 bl relocate 637#if defined(CONFIG_PPC_BOOK3E_64) 638 /* IVPR needs to be set after relocation. */ 639 bl init_core_book3e 640#endif 641#endif 642 643/* 644 * We need to run with _stext at physical address PHYSICAL_START. 645 * This will leave some code in the first 256B of 646 * real memory, which are reserved for software use. 647 * 648 * Note: This process overwrites the OF exception vectors. 649 */ 650 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET) 651 mr. r4,r26 /* In some cases the loader may */ 652 beq 9f /* have already put us at zero */ 653 li r6,0x100 /* Start offset, the first 0x100 */ 654 /* bytes were copied earlier. */ 655 656#ifdef CONFIG_RELOCATABLE 657/* 658 * Check if the kernel has to be running as relocatable kernel based on the 659 * variable __run_at_load, if it is set the kernel is treated as relocatable 660 * kernel, otherwise it will be moved to PHYSICAL_START 661 */ 662 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 663 cmplwi cr0,r7,1 664 bne 3f 665 666#ifdef CONFIG_PPC_BOOK3E_64 667 LOAD_REG_ADDR(r5, __end_interrupts) 668 LOAD_REG_ADDR(r11, _stext) 669 sub r5,r5,r11 670#else 671 /* just copy interrupts */ 672 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) 673#endif 674 b 5f 6753: 676#endif 677 /* # bytes of memory to copy */ 678 lis r5,(ABS_ADDR(copy_to_here, text))@ha 679 addi r5,r5,(ABS_ADDR(copy_to_here, text))@l 680 681 bl copy_and_flush /* copy the first n bytes */ 682 /* this includes the code being */ 683 /* executed here. */ 684 /* Jump to the copy of this code that we just made */ 685 addis r8,r3,(ABS_ADDR(4f, text))@ha 686 addi r12,r8,(ABS_ADDR(4f, text))@l 687 mtctr r12 688 bctr 689 690.balign 8 691p_end: .8byte _end - copy_to_here 692 6934: 694 /* 695 * Now copy the rest of the kernel up to _end, add 696 * _end - copy_to_here to the copy limit and run again. 697 */ 698 addis r8,r26,(ABS_ADDR(p_end, text))@ha 699 ld r8,(ABS_ADDR(p_end, text))@l(r8) 700 add r5,r5,r8 7015: bl copy_and_flush /* copy the rest */ 702 7039: b start_here_multiplatform 704 705/* 706 * Copy routine used to copy the kernel to start at physical address 0 707 * and flush and invalidate the caches as needed. 708 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 709 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 710 * 711 * Note: this routine *only* clobbers r0, r6 and lr 712 */ 713_GLOBAL(copy_and_flush) 714 addi r5,r5,-8 715 addi r6,r6,-8 7164: li r0,8 /* Use the smallest common */ 717 /* denominator cache line */ 718 /* size. This results in */ 719 /* extra cache line flushes */ 720 /* but operation is correct. */ 721 /* Can't get cache line size */ 722 /* from NACA as it is being */ 723 /* moved too. */ 724 725 mtctr r0 /* put # words/line in ctr */ 7263: addi r6,r6,8 /* copy a cache line */ 727 ldx r0,r6,r4 728 stdx r0,r6,r3 729 bdnz 3b 730 dcbst r6,r3 /* write it to memory */ 731 sync 732 icbi r6,r3 /* flush the icache line */ 733 cmpld 0,r6,r5 734 blt 4b 735 sync 736 addi r5,r5,8 737 addi r6,r6,8 738 isync 739 blr 740 741_ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */ 742 743.align 8 744copy_to_here: 745 746#ifdef CONFIG_SMP 747#ifdef CONFIG_PPC_PMAC 748/* 749 * On PowerMac, secondary processors starts from the reset vector, which 750 * is temporarily turned into a call to one of the functions below. 751 */ 752 .section ".text"; 753 .align 2 ; 754 755 .globl __secondary_start_pmac_0 756__secondary_start_pmac_0: 757 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 758 li r24,0 759 b 1f 760 li r24,1 761 b 1f 762 li r24,2 763 b 1f 764 li r24,3 7651: 766 767_GLOBAL(pmac_secondary_start) 768 /* turn on 64-bit mode */ 769 bl enable_64b_mode 770 771 li r0,0 772 mfspr r3,SPRN_HID4 773 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 774 sync 775 mtspr SPRN_HID4,r3 776 isync 777 sync 778 slbia 779 780 /* Branch to our PAGE_OFFSET address */ 781 bcl 20,31,$+4 7821: mflr r11 783 addi r11,r11,(2f - 1b) 784 tovirt(r11, r11) 785 mtctr r11 786 bctr 7872: 788 bl relative_toc 789 790 /* Copy some CPU settings from CPU 0 */ 791 bl __restore_cpu_ppc970 792 793 /* pSeries do that early though I don't think we really need it */ 794 mfmsr r3 795 ori r3,r3,MSR_RI 796 mtmsrd r3 /* RI on */ 797 798 /* Set up a paca value for this processor. */ 799 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ 800 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ 801 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ 802 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ 803 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 804 805 /* Mark interrupts soft and hard disabled (they might be enabled 806 * in the PACA when doing hotplug) 807 */ 808 li r0,IRQS_DISABLED 809 stb r0,PACAIRQSOFTMASK(r13) 810 li r0,PACA_IRQ_HARD_DIS 811 stb r0,PACAIRQHAPPENED(r13) 812 813 /* Create a temp kernel stack for use before relocation is on. */ 814 ld r1,PACAEMERGSP(r13) 815 subi r1,r1,STACK_FRAME_MIN_SIZE 816 817 b __secondary_start 818 819#endif /* CONFIG_PPC_PMAC */ 820 821/* 822 * This function is called after the master CPU has released the 823 * secondary processors. The execution environment is relocation off. 824 * The paca for this processor has the following fields initialized at 825 * this point: 826 * 1. Processor number 827 * 2. Segment table pointer (virtual address) 828 * On entry the following are set: 829 * r1 = stack pointer (real addr of temp stack) 830 * r24 = cpu# (in Linux terms) 831 * r13 = paca virtual address 832 * SPRG_PACA = paca virtual address 833 */ 834 .section ".text"; 835 .align 2 ; 836 837 .globl __secondary_start 838__secondary_start: 839 /* Set thread priority to MEDIUM */ 840 HMT_MEDIUM 841 842 /* 843 * Do early setup for this CPU, in particular initialising the MMU so we 844 * can turn it on below. This is a call to C, which is OK, we're still 845 * running on the emergency stack. 846 */ 847 bl CFUNC(early_setup_secondary) 848 849 /* 850 * The primary has initialized our kernel stack for us in the paca, grab 851 * it and put it in r1. We must *not* use it until we turn on the MMU 852 * below, because it may not be inside the RMO. 853 */ 854 ld r1, PACAKSAVE(r13) 855 856 /* Clear backchain so we get nice backtraces */ 857 li r7,0 858 mtlr r7 859 860 /* Mark interrupts soft and hard disabled (they might be enabled 861 * in the PACA when doing hotplug) 862 */ 863 li r7,IRQS_DISABLED 864 stb r7,PACAIRQSOFTMASK(r13) 865 li r0,PACA_IRQ_HARD_DIS 866 stb r0,PACAIRQHAPPENED(r13) 867 868 /* enable MMU and jump to start_secondary */ 869 LOAD_REG_ADDR(r3, start_secondary_prolog) 870 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 871 872 mtspr SPRN_SRR0,r3 873 mtspr SPRN_SRR1,r4 874 RFI_TO_KERNEL 875 b . /* prevent speculative execution */ 876 877/* 878 * Running with relocation on at this point. All we want to do is 879 * zero the stack back-chain pointer and get the TOC virtual address 880 * before going into C code. 881 */ 882start_secondary_prolog: 883 LOAD_PACA_TOC() 884 li r3,0 885 std r3,0(r1) /* Zero the stack frame pointer */ 886 bl CFUNC(start_secondary) 887 b . 888/* 889 * Reset stack pointer and call start_secondary 890 * to continue with online operation when woken up 891 * from cede in cpu offline. 892 */ 893_GLOBAL(start_secondary_resume) 894 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 895 li r3,0 896 std r3,0(r1) /* Zero the stack frame pointer */ 897 bl CFUNC(start_secondary) 898 b . 899#endif 900 901/* 902 * This subroutine clobbers r11 and r12 903 */ 904SYM_FUNC_START_LOCAL(enable_64b_mode) 905 mfmsr r11 /* grab the current MSR */ 906#ifdef CONFIG_PPC_BOOK3E_64 907 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 908 mtmsr r11 909#else /* CONFIG_PPC_BOOK3E_64 */ 910 LOAD_REG_IMMEDIATE(r12, MSR_64BIT) 911 or r11,r11,r12 912 mtmsrd r11 913 isync 914#endif 915 blr 916SYM_FUNC_END(enable_64b_mode) 917 918/* 919 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 920 * by the toolchain). It computes the correct value for wherever we 921 * are running at the moment, using position-independent code. 922 * 923 * Note: The compiler constructs pointers using offsets from the 924 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 925 * the MMU is on we need our TOC to be a virtual address otherwise 926 * these pointers will be real addresses which may get stored and 927 * accessed later with the MMU on. We branch to the virtual address 928 * while still in real mode then call relative_toc again to handle 929 * this. 930 */ 931_GLOBAL(relative_toc) 932#ifdef CONFIG_PPC_KERNEL_PCREL 933 tdnei r2,-1 934 blr 935#else 936 mflr r0 937 bcl 20,31,$+4 9380: mflr r11 939 ld r2,(p_toc - 0b)(r11) 940 add r2,r2,r11 941 mtlr r0 942 blr 943 944.balign 8 945p_toc: .8byte .TOC. - 0b 946#endif 947 948/* 949 * This is where the main kernel code starts. 950 */ 951__REF 952start_here_multiplatform: 953 /* Adjust TOC for moved kernel. Could adjust when moving it instead. */ 954 bl relative_toc 955 956 /* Clear out the BSS. It may have been done in prom_init, 957 * already but that's irrelevant since prom_init will soon 958 * be detached from the kernel completely. Besides, we need 959 * to clear it now for kexec-style entry. 960 */ 961 LOAD_REG_ADDR(r11,__bss_stop) 962 LOAD_REG_ADDR(r8,__bss_start) 963 sub r11,r11,r8 /* bss size */ 964 addi r11,r11,7 /* round up to an even double word */ 965 srdi. r11,r11,3 /* shift right by 3 */ 966 beq 4f 967 addi r8,r8,-8 968 li r0,0 969 mtctr r11 /* zero this many doublewords */ 9703: stdu r0,8(r8) 971 bdnz 3b 9724: 973 974#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 975 /* Setup OPAL entry */ 976 LOAD_REG_ADDR(r11, opal) 977 std r28,0(r11); 978 std r29,8(r11); 979#endif 980 981#ifndef CONFIG_PPC_BOOK3E_64 982 mfmsr r6 983 ori r6,r6,MSR_RI 984 mtmsrd r6 /* RI on */ 985#endif 986 987#ifdef CONFIG_RELOCATABLE 988 /* Save the physical address we're running at in kernstart_addr */ 989 LOAD_REG_ADDR(r4, kernstart_addr) 990 clrldi r0,r25,2 991 std r0,0(r4) 992#endif 993 994 /* set up a stack pointer */ 995 LOAD_REG_ADDR(r3,init_thread_union) 996 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) 997 add r1,r3,r1 998 li r0,0 999 stdu r0,-STACK_FRAME_MIN_SIZE(r1) 1000 1001 /* 1002 * Do very early kernel initializations, including initial hash table 1003 * and SLB setup before we turn on relocation. 1004 */ 1005 1006#ifdef CONFIG_KASAN 1007 bl CFUNC(kasan_early_init) 1008#endif 1009 /* Restore parameters passed from prom_init/kexec */ 1010 mr r3,r31 1011 LOAD_REG_ADDR(r12, DOTSYM(early_setup)) 1012 mtctr r12 1013 bctrl /* also sets r13 and SPRG_PACA */ 1014 1015 LOAD_REG_ADDR(r3, start_here_common) 1016 ld r4,PACAKMSR(r13) 1017 mtspr SPRN_SRR0,r3 1018 mtspr SPRN_SRR1,r4 1019 RFI_TO_KERNEL 1020 b . /* prevent speculative execution */ 1021 1022 /* This is where all platforms converge execution */ 1023 1024start_here_common: 1025 /* relocation is on at this point */ 1026 std r1,PACAKSAVE(r13) 1027 1028 /* Load the TOC (virtual address) */ 1029 LOAD_PACA_TOC() 1030 1031 /* Mark interrupts soft and hard disabled (they might be enabled 1032 * in the PACA when doing hotplug) 1033 */ 1034 li r0,IRQS_DISABLED 1035 stb r0,PACAIRQSOFTMASK(r13) 1036 li r0,PACA_IRQ_HARD_DIS 1037 stb r0,PACAIRQHAPPENED(r13) 1038 1039 /* Generic kernel entry */ 1040 bl CFUNC(start_kernel) 1041 1042 /* Not reached */ 10430: trap 1044 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 1045 .previous 1046