1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the entry point for the 64-bit kernel along 16 * with some early initialization code common to all 64-bit powerpc 17 * variants. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 25#include <linux/threads.h> 26#include <linux/init.h> 27#include <asm/reg.h> 28#include <asm/page.h> 29#include <asm/mmu.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/bug.h> 33#include <asm/cputable.h> 34#include <asm/setup.h> 35#include <asm/hvcall.h> 36#include <asm/thread_info.h> 37#include <asm/firmware.h> 38#include <asm/page_64.h> 39#include <asm/irqflags.h> 40#include <asm/kvm_book3s_asm.h> 41#include <asm/ptrace.h> 42#include <asm/hw_irq.h> 43 44/* The physical memory is laid out such that the secondary processor 45 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 46 * using the layout described in exceptions-64s.S 47 */ 48 49/* 50 * Entering into this code we make the following assumptions: 51 * 52 * For pSeries or server processors: 53 * 1. The MMU is off & open firmware is running in real mode. 54 * 2. The kernel is entered at __start 55 * -or- For OPAL entry: 56 * 1. The MMU is off, processor in HV mode, primary CPU enters at 0 57 * with device-tree in gpr3. We also get OPAL base in r8 and 58 * entry in r9 for debugging purposes 59 * 2. Secondary processors enter at 0x60 with PIR in gpr3 60 * 61 * For Book3E processors: 62 * 1. The MMU is on running in AS0 in a state defined in ePAPR 63 * 2. The kernel is entered at __start 64 */ 65 66 .text 67 .globl _stext 68_stext: 69_GLOBAL(__start) 70 /* NOP this out unconditionally */ 71BEGIN_FTR_SECTION 72 FIXUP_ENDIAN 73 b __start_initialization_multiplatform 74END_FTR_SECTION(0, 1) 75 76 /* Catch branch to 0 in real mode */ 77 trap 78 79 /* Secondary processors spin on this value until it becomes non-zero. 80 * When non-zero, it contains the real address of the function the cpu 81 * should jump to. 82 */ 83 .balign 8 84 .globl __secondary_hold_spinloop 85__secondary_hold_spinloop: 86 .llong 0x0 87 88 /* Secondary processors write this value with their cpu # */ 89 /* after they enter the spin loop immediately below. */ 90 .globl __secondary_hold_acknowledge 91__secondary_hold_acknowledge: 92 .llong 0x0 93 94#ifdef CONFIG_RELOCATABLE 95 /* This flag is set to 1 by a loader if the kernel should run 96 * at the loaded address instead of the linked address. This 97 * is used by kexec-tools to keep the the kdump kernel in the 98 * crash_kernel region. The loader is responsible for 99 * observing the alignment requirement. 100 */ 101 /* Do not move this variable as kexec-tools knows about it. */ 102 . = 0x5c 103 .globl __run_at_load 104__run_at_load: 105 .long 0x72756e30 /* "run0" -- relocate to 0 by default */ 106#endif 107 108 . = 0x60 109/* 110 * The following code is used to hold secondary processors 111 * in a spin loop after they have entered the kernel, but 112 * before the bulk of the kernel has been relocated. This code 113 * is relocated to physical address 0x60 before prom_init is run. 114 * All of it must fit below the first exception vector at 0x100. 115 * Use .globl here not _GLOBAL because we want __secondary_hold 116 * to be the actual text address, not a descriptor. 117 */ 118 .globl __secondary_hold 119__secondary_hold: 120 FIXUP_ENDIAN 121#ifndef CONFIG_PPC_BOOK3E 122 mfmsr r24 123 ori r24,r24,MSR_RI 124 mtmsrd r24 /* RI on */ 125#endif 126 /* Grab our physical cpu number */ 127 mr r24,r3 128 /* stash r4 for book3e */ 129 mr r25,r4 130 131 /* Tell the master cpu we're here */ 132 /* Relocation is off & we are located at an address less */ 133 /* than 0x100, so only need to grab low order offset. */ 134 std r24,__secondary_hold_acknowledge-_stext(0) 135 sync 136 137 li r26,0 138#ifdef CONFIG_PPC_BOOK3E 139 tovirt(r26,r26) 140#endif 141 /* All secondary cpus wait here until told to start. */ 142100: ld r12,__secondary_hold_spinloop-_stext(r26) 143 cmpdi 0,r12,0 144 beq 100b 145 146#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 147#ifdef CONFIG_PPC_BOOK3E 148 tovirt(r12,r12) 149#endif 150 mtctr r12 151 mr r3,r24 152 /* 153 * it may be the case that other platforms have r4 right to 154 * begin with, this gives us some safety in case it is not 155 */ 156#ifdef CONFIG_PPC_BOOK3E 157 mr r4,r25 158#else 159 li r4,0 160#endif 161 /* Make sure that patched code is visible */ 162 isync 163 bctr 164#else 165 BUG_OPCODE 166#endif 167 168/* This value is used to mark exception frames on the stack. */ 169 .section ".toc","aw" 170exception_marker: 171 .tc ID_72656773_68657265[TC],0x7265677368657265 172 .text 173 174/* 175 * On server, we include the exception vectors code here as it 176 * relies on absolute addressing which is only possible within 177 * this compilation unit 178 */ 179#ifdef CONFIG_PPC_BOOK3S 180#include "exceptions-64s.S" 181#endif 182 183_GLOBAL(generic_secondary_thread_init) 184 mr r24,r3 185 186 /* turn on 64-bit mode */ 187 bl enable_64b_mode 188 189 /* get a valid TOC pointer, wherever we're mapped at */ 190 bl relative_toc 191 tovirt(r2,r2) 192 193#ifdef CONFIG_PPC_BOOK3E 194 /* Book3E initialization */ 195 mr r3,r24 196 bl book3e_secondary_thread_init 197#endif 198 b generic_secondary_common_init 199 200/* 201 * On pSeries and most other platforms, secondary processors spin 202 * in the following code. 203 * At entry, r3 = this processor's number (physical cpu id) 204 * 205 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 206 * this core already exists (setup via some other mechanism such 207 * as SCOM before entry). 208 */ 209_GLOBAL(generic_secondary_smp_init) 210 FIXUP_ENDIAN 211 mr r24,r3 212 mr r25,r4 213 214 /* turn on 64-bit mode */ 215 bl enable_64b_mode 216 217 /* get a valid TOC pointer, wherever we're mapped at */ 218 bl relative_toc 219 tovirt(r2,r2) 220 221#ifdef CONFIG_PPC_BOOK3E 222 /* Book3E initialization */ 223 mr r3,r24 224 mr r4,r25 225 bl book3e_secondary_core_init 226#endif 227 228generic_secondary_common_init: 229 /* Set up a paca value for this processor. Since we have the 230 * physical cpu id in r24, we need to search the pacas to find 231 * which logical id maps to our physical one. 232 */ 233 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ 234 ld r13,0(r13) /* Get base vaddr of paca array */ 235#ifndef CONFIG_SMP 236 addi r13,r13,PACA_SIZE /* know r13 if used accidentally */ 237 b kexec_wait /* wait for next kernel if !SMP */ 238#else 239 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 240 lwz r7,0(r7) /* also the max paca allocated */ 241 li r5,0 /* logical cpu id */ 2421: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 243 cmpw r6,r24 /* Compare to our id */ 244 beq 2f 245 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 246 addi r5,r5,1 247 cmpw r5,r7 /* Check if more pacas exist */ 248 blt 1b 249 250 mr r3,r24 /* not found, copy phys to r3 */ 251 b kexec_wait /* next kernel might do better */ 252 2532: SET_PACA(r13) 254#ifdef CONFIG_PPC_BOOK3E 255 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 256 mtspr SPRN_SPRG_TLB_EXFRAME,r12 257#endif 258 259 /* From now on, r24 is expected to be logical cpuid */ 260 mr r24,r5 261 262 /* See if we need to call a cpu state restore handler */ 263 LOAD_REG_ADDR(r23, cur_cpu_spec) 264 ld r23,0(r23) 265 ld r12,CPU_SPEC_RESTORE(r23) 266 cmpdi 0,r12,0 267 beq 3f 268#if !defined(_CALL_ELF) || _CALL_ELF != 2 269 ld r12,0(r12) 270#endif 271 mtctr r12 272 bctrl 273 2743: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 275 lwarx r4,0,r3 276 subi r4,r4,1 277 stwcx. r4,0,r3 278 bne 3b 279 isync 280 2814: HMT_LOW 282 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 283 /* start. */ 284 cmpwi 0,r23,0 285 beq 4b /* Loop until told to go */ 286 287 sync /* order paca.run and cur_cpu_spec */ 288 isync /* In case code patching happened */ 289 290 /* Create a temp kernel stack for use before relocation is on. */ 291 ld r1,PACAEMERGSP(r13) 292 subi r1,r1,STACK_FRAME_OVERHEAD 293 294 b __secondary_start 295#endif /* SMP */ 296 297/* 298 * Turn the MMU off. 299 * Assumes we're mapped EA == RA if the MMU is on. 300 */ 301#ifdef CONFIG_PPC_BOOK3S 302__mmu_off: 303 mfmsr r3 304 andi. r0,r3,MSR_IR|MSR_DR 305 beqlr 306 mflr r4 307 andc r3,r3,r0 308 mtspr SPRN_SRR0,r4 309 mtspr SPRN_SRR1,r3 310 sync 311 rfid 312 b . /* prevent speculative execution */ 313#endif 314 315 316/* 317 * Here is our main kernel entry point. We support currently 2 kind of entries 318 * depending on the value of r5. 319 * 320 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 321 * in r3...r7 322 * 323 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 324 * DT block, r4 is a physical pointer to the kernel itself 325 * 326 */ 327__start_initialization_multiplatform: 328 /* Make sure we are running in 64 bits mode */ 329 bl enable_64b_mode 330 331 /* Get TOC pointer (current runtime address) */ 332 bl relative_toc 333 334 /* find out where we are now */ 335 bcl 20,31,$+4 3360: mflr r26 /* r26 = runtime addr here */ 337 addis r26,r26,(_stext - 0b)@ha 338 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 339 340 /* 341 * Are we booted from a PROM Of-type client-interface ? 342 */ 343 cmpldi cr0,r5,0 344 beq 1f 345 b __boot_from_prom /* yes -> prom */ 3461: 347 /* Save parameters */ 348 mr r31,r3 349 mr r30,r4 350#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 351 /* Save OPAL entry */ 352 mr r28,r8 353 mr r29,r9 354#endif 355 356#ifdef CONFIG_PPC_BOOK3E 357 bl start_initialization_book3e 358 b __after_prom_start 359#else 360 /* Setup some critical 970 SPRs before switching MMU off */ 361 mfspr r0,SPRN_PVR 362 srwi r0,r0,16 363 cmpwi r0,0x39 /* 970 */ 364 beq 1f 365 cmpwi r0,0x3c /* 970FX */ 366 beq 1f 367 cmpwi r0,0x44 /* 970MP */ 368 beq 1f 369 cmpwi r0,0x45 /* 970GX */ 370 bne 2f 3711: bl __cpu_preinit_ppc970 3722: 373 374 /* Switch off MMU if not already off */ 375 bl __mmu_off 376 b __after_prom_start 377#endif /* CONFIG_PPC_BOOK3E */ 378 379__boot_from_prom: 380#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 381 /* Save parameters */ 382 mr r31,r3 383 mr r30,r4 384 mr r29,r5 385 mr r28,r6 386 mr r27,r7 387 388 /* 389 * Align the stack to 16-byte boundary 390 * Depending on the size and layout of the ELF sections in the initial 391 * boot binary, the stack pointer may be unaligned on PowerMac 392 */ 393 rldicr r1,r1,0,59 394 395#ifdef CONFIG_RELOCATABLE 396 /* Relocate code for where we are now */ 397 mr r3,r26 398 bl relocate 399#endif 400 401 /* Restore parameters */ 402 mr r3,r31 403 mr r4,r30 404 mr r5,r29 405 mr r6,r28 406 mr r7,r27 407 408 /* Do all of the interaction with OF client interface */ 409 mr r8,r26 410 bl prom_init 411#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 412 413 /* We never return. We also hit that trap if trying to boot 414 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 415 trap 416 417__after_prom_start: 418#ifdef CONFIG_RELOCATABLE 419 /* process relocations for the final address of the kernel */ 420 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 421 sldi r25,r25,32 422 lwz r7,__run_at_load-_stext(r26) 423 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 424 bne 1f 425 add r25,r25,r26 4261: mr r3,r25 427 bl relocate 428#endif 429 430/* 431 * We need to run with _stext at physical address PHYSICAL_START. 432 * This will leave some code in the first 256B of 433 * real memory, which are reserved for software use. 434 * 435 * Note: This process overwrites the OF exception vectors. 436 */ 437 li r3,0 /* target addr */ 438#ifdef CONFIG_PPC_BOOK3E 439 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 440#endif 441 mr. r4,r26 /* In some cases the loader may */ 442 beq 9f /* have already put us at zero */ 443 li r6,0x100 /* Start offset, the first 0x100 */ 444 /* bytes were copied earlier. */ 445#ifdef CONFIG_PPC_BOOK3E 446 tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ 447#endif 448 449#ifdef CONFIG_RELOCATABLE 450/* 451 * Check if the kernel has to be running as relocatable kernel based on the 452 * variable __run_at_load, if it is set the kernel is treated as relocatable 453 * kernel, otherwise it will be moved to PHYSICAL_START 454 */ 455 lwz r7,__run_at_load-_stext(r26) 456 cmplwi cr0,r7,1 457 bne 3f 458 459 /* just copy interrupts */ 460 LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext) 461 b 5f 4623: 463#endif 464 lis r5,(copy_to_here - _stext)@ha 465 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ 466 467 bl copy_and_flush /* copy the first n bytes */ 468 /* this includes the code being */ 469 /* executed here. */ 470 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ 471 addi r12,r8,(4f - _stext)@l /* that we just made */ 472 mtctr r12 473 bctr 474 475.balign 8 476p_end: .llong _end - _stext 477 4784: /* Now copy the rest of the kernel up to _end */ 479 addis r5,r26,(p_end - _stext)@ha 480 ld r5,(p_end - _stext)@l(r5) /* get _end */ 4815: bl copy_and_flush /* copy the rest */ 482 4839: b start_here_multiplatform 484 485/* 486 * Copy routine used to copy the kernel to start at physical address 0 487 * and flush and invalidate the caches as needed. 488 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 489 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 490 * 491 * Note: this routine *only* clobbers r0, r6 and lr 492 */ 493_GLOBAL(copy_and_flush) 494 addi r5,r5,-8 495 addi r6,r6,-8 4964: li r0,8 /* Use the smallest common */ 497 /* denominator cache line */ 498 /* size. This results in */ 499 /* extra cache line flushes */ 500 /* but operation is correct. */ 501 /* Can't get cache line size */ 502 /* from NACA as it is being */ 503 /* moved too. */ 504 505 mtctr r0 /* put # words/line in ctr */ 5063: addi r6,r6,8 /* copy a cache line */ 507 ldx r0,r6,r4 508 stdx r0,r6,r3 509 bdnz 3b 510 dcbst r6,r3 /* write it to memory */ 511 sync 512 icbi r6,r3 /* flush the icache line */ 513 cmpld 0,r6,r5 514 blt 4b 515 sync 516 addi r5,r5,8 517 addi r6,r6,8 518 isync 519 blr 520 521.align 8 522copy_to_here: 523 524#ifdef CONFIG_SMP 525#ifdef CONFIG_PPC_PMAC 526/* 527 * On PowerMac, secondary processors starts from the reset vector, which 528 * is temporarily turned into a call to one of the functions below. 529 */ 530 .section ".text"; 531 .align 2 ; 532 533 .globl __secondary_start_pmac_0 534__secondary_start_pmac_0: 535 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 536 li r24,0 537 b 1f 538 li r24,1 539 b 1f 540 li r24,2 541 b 1f 542 li r24,3 5431: 544 545_GLOBAL(pmac_secondary_start) 546 /* turn on 64-bit mode */ 547 bl enable_64b_mode 548 549 li r0,0 550 mfspr r3,SPRN_HID4 551 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 552 sync 553 mtspr SPRN_HID4,r3 554 isync 555 sync 556 slbia 557 558 /* get TOC pointer (real address) */ 559 bl relative_toc 560 tovirt(r2,r2) 561 562 /* Copy some CPU settings from CPU 0 */ 563 bl __restore_cpu_ppc970 564 565 /* pSeries do that early though I don't think we really need it */ 566 mfmsr r3 567 ori r3,r3,MSR_RI 568 mtmsrd r3 /* RI on */ 569 570 /* Set up a paca value for this processor. */ 571 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ 572 ld r4,0(r4) /* Get base vaddr of paca array */ 573 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 574 add r13,r13,r4 /* for this processor. */ 575 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 576 577 /* Mark interrupts soft and hard disabled (they might be enabled 578 * in the PACA when doing hotplug) 579 */ 580 li r0,0 581 stb r0,PACASOFTIRQEN(r13) 582 li r0,PACA_IRQ_HARD_DIS 583 stb r0,PACAIRQHAPPENED(r13) 584 585 /* Create a temp kernel stack for use before relocation is on. */ 586 ld r1,PACAEMERGSP(r13) 587 subi r1,r1,STACK_FRAME_OVERHEAD 588 589 b __secondary_start 590 591#endif /* CONFIG_PPC_PMAC */ 592 593/* 594 * This function is called after the master CPU has released the 595 * secondary processors. The execution environment is relocation off. 596 * The paca for this processor has the following fields initialized at 597 * this point: 598 * 1. Processor number 599 * 2. Segment table pointer (virtual address) 600 * On entry the following are set: 601 * r1 = stack pointer (real addr of temp stack) 602 * r24 = cpu# (in Linux terms) 603 * r13 = paca virtual address 604 * SPRG_PACA = paca virtual address 605 */ 606 .section ".text"; 607 .align 2 ; 608 609 .globl __secondary_start 610__secondary_start: 611 /* Set thread priority to MEDIUM */ 612 HMT_MEDIUM 613 614 /* Initialize the kernel stack */ 615 LOAD_REG_ADDR(r3, current_set) 616 sldi r28,r24,3 /* get current_set[cpu#] */ 617 ldx r14,r3,r28 618 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD 619 std r14,PACAKSAVE(r13) 620 621 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 622 bl early_setup_secondary 623 624 /* 625 * setup the new stack pointer, but *don't* use this until 626 * translation is on. 627 */ 628 mr r1, r14 629 630 /* Clear backchain so we get nice backtraces */ 631 li r7,0 632 mtlr r7 633 634 /* Mark interrupts soft and hard disabled (they might be enabled 635 * in the PACA when doing hotplug) 636 */ 637 stb r7,PACASOFTIRQEN(r13) 638 li r0,PACA_IRQ_HARD_DIS 639 stb r0,PACAIRQHAPPENED(r13) 640 641 /* enable MMU and jump to start_secondary */ 642 LOAD_REG_ADDR(r3, start_secondary_prolog) 643 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 644 645 mtspr SPRN_SRR0,r3 646 mtspr SPRN_SRR1,r4 647 RFI 648 b . /* prevent speculative execution */ 649 650/* 651 * Running with relocation on at this point. All we want to do is 652 * zero the stack back-chain pointer and get the TOC virtual address 653 * before going into C code. 654 */ 655start_secondary_prolog: 656 ld r2,PACATOC(r13) 657 li r3,0 658 std r3,0(r1) /* Zero the stack frame pointer */ 659 bl start_secondary 660 b . 661/* 662 * Reset stack pointer and call start_secondary 663 * to continue with online operation when woken up 664 * from cede in cpu offline. 665 */ 666_GLOBAL(start_secondary_resume) 667 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 668 li r3,0 669 std r3,0(r1) /* Zero the stack frame pointer */ 670 bl start_secondary 671 b . 672#endif 673 674/* 675 * This subroutine clobbers r11 and r12 676 */ 677enable_64b_mode: 678 mfmsr r11 /* grab the current MSR */ 679#ifdef CONFIG_PPC_BOOK3E 680 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 681 mtmsr r11 682#else /* CONFIG_PPC_BOOK3E */ 683 li r12,(MSR_64BIT | MSR_ISF)@highest 684 sldi r12,r12,48 685 or r11,r11,r12 686 mtmsrd r11 687 isync 688#endif 689 blr 690 691/* 692 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 693 * by the toolchain). It computes the correct value for wherever we 694 * are running at the moment, using position-independent code. 695 * 696 * Note: The compiler constructs pointers using offsets from the 697 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 698 * the MMU is on we need our TOC to be a virtual address otherwise 699 * these pointers will be real addresses which may get stored and 700 * accessed later with the MMU on. We use tovirt() at the call 701 * sites to handle this. 702 */ 703_GLOBAL(relative_toc) 704 mflr r0 705 bcl 20,31,$+4 7060: mflr r11 707 ld r2,(p_toc - 0b)(r11) 708 add r2,r2,r11 709 mtlr r0 710 blr 711 712.balign 8 713p_toc: .llong __toc_start + 0x8000 - 0b 714 715/* 716 * This is where the main kernel code starts. 717 */ 718start_here_multiplatform: 719 /* set up the TOC */ 720 bl relative_toc 721 tovirt(r2,r2) 722 723 /* Clear out the BSS. It may have been done in prom_init, 724 * already but that's irrelevant since prom_init will soon 725 * be detached from the kernel completely. Besides, we need 726 * to clear it now for kexec-style entry. 727 */ 728 LOAD_REG_ADDR(r11,__bss_stop) 729 LOAD_REG_ADDR(r8,__bss_start) 730 sub r11,r11,r8 /* bss size */ 731 addi r11,r11,7 /* round up to an even double word */ 732 srdi. r11,r11,3 /* shift right by 3 */ 733 beq 4f 734 addi r8,r8,-8 735 li r0,0 736 mtctr r11 /* zero this many doublewords */ 7373: stdu r0,8(r8) 738 bdnz 3b 7394: 740 741#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 742 /* Setup OPAL entry */ 743 LOAD_REG_ADDR(r11, opal) 744 std r28,0(r11); 745 std r29,8(r11); 746#endif 747 748#ifndef CONFIG_PPC_BOOK3E 749 mfmsr r6 750 ori r6,r6,MSR_RI 751 mtmsrd r6 /* RI on */ 752#endif 753 754#ifdef CONFIG_RELOCATABLE 755 /* Save the physical address we're running at in kernstart_addr */ 756 LOAD_REG_ADDR(r4, kernstart_addr) 757 clrldi r0,r25,2 758 std r0,0(r4) 759#endif 760 761 /* The following gets the stack set up with the regs */ 762 /* pointing to the real addr of the kernel stack. This is */ 763 /* all done to support the C function call below which sets */ 764 /* up the htab. This is done because we have relocated the */ 765 /* kernel but are still running in real mode. */ 766 767 LOAD_REG_ADDR(r3,init_thread_union) 768 769 /* set up a stack pointer */ 770 addi r1,r3,THREAD_SIZE 771 li r0,0 772 stdu r0,-STACK_FRAME_OVERHEAD(r1) 773 774 /* Do very early kernel initializations, including initial hash table, 775 * stab and slb setup before we turn on relocation. */ 776 777 /* Restore parameters passed from prom_init/kexec */ 778 mr r3,r31 779 bl early_setup /* also sets r13 and SPRG_PACA */ 780 781 LOAD_REG_ADDR(r3, start_here_common) 782 ld r4,PACAKMSR(r13) 783 mtspr SPRN_SRR0,r3 784 mtspr SPRN_SRR1,r4 785 RFI 786 b . /* prevent speculative execution */ 787 788 /* This is where all platforms converge execution */ 789 790start_here_common: 791 /* relocation is on at this point */ 792 std r1,PACAKSAVE(r13) 793 794 /* Load the TOC (virtual address) */ 795 ld r2,PACATOC(r13) 796 797 /* Do more system initializations in virtual mode */ 798 bl setup_system 799 800 /* Mark interrupts soft and hard disabled (they might be enabled 801 * in the PACA when doing hotplug) 802 */ 803 li r0,0 804 stb r0,PACASOFTIRQEN(r13) 805 li r0,PACA_IRQ_HARD_DIS 806 stb r0,PACAIRQHAPPENED(r13) 807 808 /* Generic kernel entry */ 809 bl start_kernel 810 811 /* Not reached */ 812 BUG_OPCODE 813 814/* 815 * We put a few things here that have to be page-aligned. 816 * This stuff goes at the beginning of the bss, which is page-aligned. 817 */ 818 .section ".bss" 819 820 .align PAGE_SHIFT 821 822 .globl empty_zero_page 823empty_zero_page: 824 .space PAGE_SIZE 825 826 .globl swapper_pg_dir 827swapper_pg_dir: 828 .space PGD_TABLE_SIZE 829