1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * 6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Adapted for Power Macintosh by Paul Mackerras. 9 * Low-level exception handlers and MMU support 10 * rewritten by Paul Mackerras. 11 * Copyright (C) 1996 Paul Mackerras. 12 * 13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 15 * 16 * This file contains the entry point for the 64-bit kernel along 17 * with some early initialization code common to all 64-bit powerpc 18 * variants. 19 */ 20 21#include <linux/linkage.h> 22#include <linux/threads.h> 23#include <linux/init.h> 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/mmu.h> 27#include <asm/ppc_asm.h> 28#include <asm/head-64.h> 29#include <asm/asm-offsets.h> 30#include <asm/bug.h> 31#include <asm/cputable.h> 32#include <asm/setup.h> 33#include <asm/hvcall.h> 34#include <asm/thread_info.h> 35#include <asm/firmware.h> 36#include <asm/page_64.h> 37#include <asm/irqflags.h> 38#include <asm/kvm_book3s_asm.h> 39#include <asm/ptrace.h> 40#include <asm/hw_irq.h> 41#include <asm/cputhreads.h> 42#include <asm/ppc-opcode.h> 43#include <asm/export.h> 44#include <asm/feature-fixups.h> 45#ifdef CONFIG_PPC_BOOK3S 46#include <asm/exception-64s.h> 47#else 48#include <asm/exception-64e.h> 49#endif 50 51/* The physical memory is laid out such that the secondary processor 52 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 53 * using the layout described in exceptions-64s.S 54 */ 55 56/* 57 * Entering into this code we make the following assumptions: 58 * 59 * For pSeries or server processors: 60 * 1. The MMU is off & open firmware is running in real mode. 61 * 2. The primary CPU enters at __start. 62 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary 63 * CPUs will enter as directed by "start-cpu" RTAS call, which is 64 * generic_secondary_smp_init, with PIR in r3. 65 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as 66 * directed by the "start-cpu" RTS call, with PIR in r3. 67 * -or- For OPAL entry: 68 * 1. The MMU is off, processor in HV mode. 69 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base 70 * in r8, and entry in r9 for debugging purposes. 71 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which 72 * is at generic_secondary_smp_init, with PIR in r3. 73 * 74 * For Book3E processors: 75 * 1. The MMU is on running in AS0 in a state defined in ePAPR 76 * 2. The kernel is entered at __start 77 */ 78 79OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) 80USE_FIXED_SECTION(first_256B) 81 /* 82 * Offsets are relative from the start of fixed section, and 83 * first_256B starts at 0. Offsets are a bit easier to use here 84 * than the fixed section entry macros. 85 */ 86 . = 0x0 87_GLOBAL(__start) 88 /* NOP this out unconditionally */ 89BEGIN_FTR_SECTION 90 FIXUP_ENDIAN 91 b __start_initialization_multiplatform 92END_FTR_SECTION(0, 1) 93 94 /* Catch branch to 0 in real mode */ 95 trap 96 97 /* Secondary processors spin on this value until it becomes non-zero. 98 * When non-zero, it contains the real address of the function the cpu 99 * should jump to. 100 */ 101 .balign 8 102 .globl __secondary_hold_spinloop 103__secondary_hold_spinloop: 104 .8byte 0x0 105 106 /* Secondary processors write this value with their cpu # */ 107 /* after they enter the spin loop immediately below. */ 108 .globl __secondary_hold_acknowledge 109__secondary_hold_acknowledge: 110 .8byte 0x0 111 112#ifdef CONFIG_RELOCATABLE 113 /* This flag is set to 1 by a loader if the kernel should run 114 * at the loaded address instead of the linked address. This 115 * is used by kexec-tools to keep the kdump kernel in the 116 * crash_kernel region. The loader is responsible for 117 * observing the alignment requirement. 118 */ 119 120#ifdef CONFIG_RELOCATABLE_TEST 121#define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ 122#else 123#define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ 124#endif 125 126 /* Do not move this variable as kexec-tools knows about it. */ 127 . = 0x5c 128 .globl __run_at_load 129__run_at_load: 130DEFINE_FIXED_SYMBOL(__run_at_load, first_256B) 131 .long RUN_AT_LOAD_DEFAULT 132#endif 133 134 . = 0x60 135/* 136 * The following code is used to hold secondary processors 137 * in a spin loop after they have entered the kernel, but 138 * before the bulk of the kernel has been relocated. This code 139 * is relocated to physical address 0x60 before prom_init is run. 140 * All of it must fit below the first exception vector at 0x100. 141 * Use .globl here not _GLOBAL because we want __secondary_hold 142 * to be the actual text address, not a descriptor. 143 */ 144 .globl __secondary_hold 145__secondary_hold: 146 FIXUP_ENDIAN 147#ifndef CONFIG_PPC_BOOK3E_64 148 mfmsr r24 149 ori r24,r24,MSR_RI 150 mtmsrd r24 /* RI on */ 151#endif 152 /* Grab our physical cpu number */ 153 mr r24,r3 154 /* stash r4 for book3e */ 155 mr r25,r4 156 157 /* Tell the master cpu we're here */ 158 /* Relocation is off & we are located at an address less */ 159 /* than 0x100, so only need to grab low order offset. */ 160 std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0) 161 sync 162 163 li r26,0 164#ifdef CONFIG_PPC_BOOK3E_64 165 tovirt(r26,r26) 166#endif 167 /* All secondary cpus wait here until told to start. */ 168100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(r26) 169 cmpdi 0,r12,0 170 beq 100b 171 172#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 173#ifdef CONFIG_PPC_BOOK3E_64 174 tovirt(r12,r12) 175#endif 176 mtctr r12 177 mr r3,r24 178 /* 179 * it may be the case that other platforms have r4 right to 180 * begin with, this gives us some safety in case it is not 181 */ 182#ifdef CONFIG_PPC_BOOK3E_64 183 mr r4,r25 184#else 185 li r4,0 186#endif 187 /* Make sure that patched code is visible */ 188 isync 189 bctr 190#else 1910: trap 192 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 193#endif 194CLOSE_FIXED_SECTION(first_256B) 195 196/* 197 * On server, we include the exception vectors code here as it 198 * relies on absolute addressing which is only possible within 199 * this compilation unit 200 */ 201#ifdef CONFIG_PPC_BOOK3S 202#include "exceptions-64s.S" 203#else 204OPEN_TEXT_SECTION(0x100) 205#endif 206 207USE_TEXT_SECTION() 208 209#include "interrupt_64.S" 210 211#ifdef CONFIG_PPC_BOOK3E_64 212/* 213 * The booting_thread_hwid holds the thread id we want to boot in cpu 214 * hotplug case. It is set by cpu hotplug code, and is invalid by default. 215 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] 216 * bit field. 217 */ 218 .globl booting_thread_hwid 219booting_thread_hwid: 220 .long INVALID_THREAD_HWID 221 .align 3 222/* 223 * start a thread in the same core 224 * input parameters: 225 * r3 = the thread physical id 226 * r4 = the entry point where thread starts 227 */ 228_GLOBAL(book3e_start_thread) 229 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) 230 cmpwi r3, 0 231 beq 10f 232 cmpwi r3, 1 233 beq 11f 234 /* If the thread id is invalid, just exit. */ 235 b 13f 23610: 237 MTTMR(TMRN_IMSR0, 5) 238 MTTMR(TMRN_INIA0, 4) 239 b 12f 24011: 241 MTTMR(TMRN_IMSR1, 5) 242 MTTMR(TMRN_INIA1, 4) 24312: 244 isync 245 li r6, 1 246 sld r6, r6, r3 247 mtspr SPRN_TENS, r6 24813: 249 blr 250 251/* 252 * stop a thread in the same core 253 * input parameter: 254 * r3 = the thread physical id 255 */ 256_GLOBAL(book3e_stop_thread) 257 cmpwi r3, 0 258 beq 10f 259 cmpwi r3, 1 260 beq 10f 261 /* If the thread id is invalid, just exit. */ 262 b 13f 26310: 264 li r4, 1 265 sld r4, r4, r3 266 mtspr SPRN_TENC, r4 26713: 268 blr 269 270_GLOBAL(fsl_secondary_thread_init) 271 mfspr r4,SPRN_BUCSR 272 273 /* Enable branch prediction */ 274 lis r3,BUCSR_INIT@h 275 ori r3,r3,BUCSR_INIT@l 276 mtspr SPRN_BUCSR,r3 277 isync 278 279 /* 280 * Fix PIR to match the linear numbering in the device tree. 281 * 282 * On e6500, the reset value of PIR uses the low three bits for 283 * the thread within a core, and the upper bits for the core 284 * number. There are two threads per core, so shift everything 285 * but the low bit right by two bits so that the cpu numbering is 286 * continuous. 287 * 288 * If the old value of BUCSR is non-zero, this thread has run 289 * before. Thus, we assume we are coming from kexec or a similar 290 * scenario, and PIR is already set to the correct value. This 291 * is a bit of a hack, but there are limited opportunities for 292 * getting information into the thread and the alternatives 293 * seemed like they'd be overkill. We can't tell just by looking 294 * at the old PIR value which state it's in, since the same value 295 * could be valid for one thread out of reset and for a different 296 * thread in Linux. 297 */ 298 299 mfspr r3, SPRN_PIR 300 cmpwi r4,0 301 bne 1f 302 rlwimi r3, r3, 30, 2, 30 303 mtspr SPRN_PIR, r3 3041: 305 mr r24,r3 306 307 /* turn on 64-bit mode */ 308 bl enable_64b_mode 309 310 /* get a valid TOC pointer, wherever we're mapped at */ 311 bl relative_toc 312 tovirt(r2,r2) 313 314 /* Book3E initialization */ 315 mr r3,r24 316 bl book3e_secondary_thread_init 317 b generic_secondary_common_init 318 319#endif /* CONFIG_PPC_BOOK3E_64 */ 320 321/* 322 * On pSeries and most other platforms, secondary processors spin 323 * in the following code. 324 * At entry, r3 = this processor's number (physical cpu id) 325 * 326 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 327 * this core already exists (setup via some other mechanism such 328 * as SCOM before entry). 329 */ 330_GLOBAL(generic_secondary_smp_init) 331 FIXUP_ENDIAN 332 mr r24,r3 333 mr r25,r4 334 335 /* turn on 64-bit mode */ 336 bl enable_64b_mode 337 338 /* get a valid TOC pointer, wherever we're mapped at */ 339 bl relative_toc 340 tovirt(r2,r2) 341 342#ifdef CONFIG_PPC_BOOK3E_64 343 /* Book3E initialization */ 344 mr r3,r24 345 mr r4,r25 346 bl book3e_secondary_core_init 347 348/* 349 * After common core init has finished, check if the current thread is the 350 * one we wanted to boot. If not, start the specified thread and stop the 351 * current thread. 352 */ 353 LOAD_REG_ADDR(r4, booting_thread_hwid) 354 lwz r3, 0(r4) 355 li r5, INVALID_THREAD_HWID 356 cmpw r3, r5 357 beq 20f 358 359 /* 360 * The value of booting_thread_hwid has been stored in r3, 361 * so make it invalid. 362 */ 363 stw r5, 0(r4) 364 365 /* 366 * Get the current thread id and check if it is the one we wanted. 367 * If not, start the one specified in booting_thread_hwid and stop 368 * the current thread. 369 */ 370 mfspr r8, SPRN_TIR 371 cmpw r3, r8 372 beq 20f 373 374 /* start the specified thread */ 375 LOAD_REG_ADDR(r5, fsl_secondary_thread_init) 376 ld r4, 0(r5) 377 bl book3e_start_thread 378 379 /* stop the current thread */ 380 mr r3, r8 381 bl book3e_stop_thread 38210: 383 b 10b 38420: 385#endif 386 387generic_secondary_common_init: 388 /* Set up a paca value for this processor. Since we have the 389 * physical cpu id in r24, we need to search the pacas to find 390 * which logical id maps to our physical one. 391 */ 392#ifndef CONFIG_SMP 393 b kexec_wait /* wait for next kernel if !SMP */ 394#else 395 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ 396 ld r8,0(r8) /* Get base vaddr of array */ 397#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS) 398 LOAD_REG_IMMEDIATE(r7, NR_CPUS) 399#else 400 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 401 lwz r7,0(r7) /* also the max paca allocated */ 402#endif 403 li r5,0 /* logical cpu id */ 4041: 405 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ 406 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ 407 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 408 cmpw r6,r24 /* Compare to our id */ 409 beq 2f 410 addi r5,r5,1 411 cmpw r5,r7 /* Check if more pacas exist */ 412 blt 1b 413 414 mr r3,r24 /* not found, copy phys to r3 */ 415 b kexec_wait /* next kernel might do better */ 416 4172: SET_PACA(r13) 418#ifdef CONFIG_PPC_BOOK3E_64 419 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 420 mtspr SPRN_SPRG_TLB_EXFRAME,r12 421#endif 422 423 /* From now on, r24 is expected to be logical cpuid */ 424 mr r24,r5 425 426 /* Create a temp kernel stack for use before relocation is on. */ 427 ld r1,PACAEMERGSP(r13) 428 subi r1,r1,STACK_FRAME_MIN_SIZE 429 430 /* See if we need to call a cpu state restore handler */ 431 LOAD_REG_ADDR(r23, cur_cpu_spec) 432 ld r23,0(r23) 433 ld r12,CPU_SPEC_RESTORE(r23) 434 cmpdi 0,r12,0 435 beq 3f 436#ifdef CONFIG_PPC64_ELF_ABI_V1 437 ld r12,0(r12) 438#endif 439 mtctr r12 440 bctrl 441 4423: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 443 lwarx r4,0,r3 444 subi r4,r4,1 445 stwcx. r4,0,r3 446 bne 3b 447 isync 448 4494: HMT_LOW 450 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 451 /* start. */ 452 cmpwi 0,r23,0 453 beq 4b /* Loop until told to go */ 454 455 sync /* order paca.run and cur_cpu_spec */ 456 isync /* In case code patching happened */ 457 458 b __secondary_start 459#endif /* SMP */ 460 461/* 462 * Turn the MMU off. 463 * Assumes we're mapped EA == RA if the MMU is on. 464 */ 465#ifdef CONFIG_PPC_BOOK3S 466SYM_FUNC_START_LOCAL(__mmu_off) 467 mfmsr r3 468 andi. r0,r3,MSR_IR|MSR_DR 469 beqlr 470 mflr r4 471 andc r3,r3,r0 472 mtspr SPRN_SRR0,r4 473 mtspr SPRN_SRR1,r3 474 sync 475 rfid 476 b . /* prevent speculative execution */ 477SYM_FUNC_END(__mmu_off) 478#endif 479 480 481/* 482 * Here is our main kernel entry point. We support currently 2 kind of entries 483 * depending on the value of r5. 484 * 485 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 486 * in r3...r7 487 * 488 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 489 * DT block, r4 is a physical pointer to the kernel itself 490 * 491 */ 492__start_initialization_multiplatform: 493 /* Make sure we are running in 64 bits mode */ 494 bl enable_64b_mode 495 496 /* Zero r13 (paca) so early program check / mce don't use it */ 497 li r13,0 498 499 /* Get TOC pointer (current runtime address) */ 500 bl relative_toc 501 502 /* find out where we are now */ 503 bcl 20,31,$+4 5040: mflr r26 /* r26 = runtime addr here */ 505 addis r26,r26,(_stext - 0b)@ha 506 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 507 508 /* 509 * Are we booted from a PROM Of-type client-interface ? 510 */ 511 cmpldi cr0,r5,0 512 beq 1f 513 b __boot_from_prom /* yes -> prom */ 5141: 515 /* Save parameters */ 516 mr r31,r3 517 mr r30,r4 518#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 519 /* Save OPAL entry */ 520 mr r28,r8 521 mr r29,r9 522#endif 523 524#ifdef CONFIG_PPC_BOOK3E_64 525 bl start_initialization_book3e 526 b __after_prom_start 527#else 528 /* Setup some critical 970 SPRs before switching MMU off */ 529 mfspr r0,SPRN_PVR 530 srwi r0,r0,16 531 cmpwi r0,0x39 /* 970 */ 532 beq 1f 533 cmpwi r0,0x3c /* 970FX */ 534 beq 1f 535 cmpwi r0,0x44 /* 970MP */ 536 beq 1f 537 cmpwi r0,0x45 /* 970GX */ 538 bne 2f 5391: bl __cpu_preinit_ppc970 5402: 541 542 /* Switch off MMU if not already off */ 543 bl __mmu_off 544 b __after_prom_start 545#endif /* CONFIG_PPC_BOOK3E_64 */ 546 547__REF 548__boot_from_prom: 549#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 550 /* Save parameters */ 551 mr r31,r3 552 mr r30,r4 553 mr r29,r5 554 mr r28,r6 555 mr r27,r7 556 557 /* 558 * Align the stack to 16-byte boundary 559 * Depending on the size and layout of the ELF sections in the initial 560 * boot binary, the stack pointer may be unaligned on PowerMac 561 */ 562 rldicr r1,r1,0,59 563 564#ifdef CONFIG_RELOCATABLE 565 /* Relocate code for where we are now */ 566 mr r3,r26 567 bl relocate 568#endif 569 570 /* Restore parameters */ 571 mr r3,r31 572 mr r4,r30 573 mr r5,r29 574 mr r6,r28 575 mr r7,r27 576 577 /* Do all of the interaction with OF client interface */ 578 mr r8,r26 579 bl prom_init 580#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 581 582 /* We never return. We also hit that trap if trying to boot 583 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 584 trap 585 .previous 586 587__after_prom_start: 588#ifdef CONFIG_RELOCATABLE 589 /* process relocations for the final address of the kernel */ 590 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 591 sldi r25,r25,32 592#if defined(CONFIG_PPC_BOOK3E_64) 593 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 594#endif 595 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 596#if defined(CONFIG_PPC_BOOK3E_64) 597 tophys(r26,r26) 598#endif 599 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 600 bne 1f 601 add r25,r25,r26 6021: mr r3,r25 603 bl relocate 604#if defined(CONFIG_PPC_BOOK3E_64) 605 /* IVPR needs to be set after relocation. */ 606 bl init_core_book3e 607#endif 608#endif 609 610/* 611 * We need to run with _stext at physical address PHYSICAL_START. 612 * This will leave some code in the first 256B of 613 * real memory, which are reserved for software use. 614 * 615 * Note: This process overwrites the OF exception vectors. 616 */ 617 li r3,0 /* target addr */ 618#ifdef CONFIG_PPC_BOOK3E_64 619 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 620#endif 621 mr. r4,r26 /* In some cases the loader may */ 622#if defined(CONFIG_PPC_BOOK3E_64) 623 tovirt(r4,r4) 624#endif 625 beq 9f /* have already put us at zero */ 626 li r6,0x100 /* Start offset, the first 0x100 */ 627 /* bytes were copied earlier. */ 628 629#ifdef CONFIG_RELOCATABLE 630/* 631 * Check if the kernel has to be running as relocatable kernel based on the 632 * variable __run_at_load, if it is set the kernel is treated as relocatable 633 * kernel, otherwise it will be moved to PHYSICAL_START 634 */ 635#if defined(CONFIG_PPC_BOOK3E_64) 636 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 637#endif 638 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 639 cmplwi cr0,r7,1 640 bne 3f 641 642#ifdef CONFIG_PPC_BOOK3E_64 643 LOAD_REG_ADDR(r5, __end_interrupts) 644 LOAD_REG_ADDR(r11, _stext) 645 sub r5,r5,r11 646#else 647 /* just copy interrupts */ 648 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) 649#endif 650 b 5f 6513: 652#endif 653 /* # bytes of memory to copy */ 654 lis r5,(ABS_ADDR(copy_to_here, text))@ha 655 addi r5,r5,(ABS_ADDR(copy_to_here, text))@l 656 657 bl copy_and_flush /* copy the first n bytes */ 658 /* this includes the code being */ 659 /* executed here. */ 660 /* Jump to the copy of this code that we just made */ 661 addis r8,r3,(ABS_ADDR(4f, text))@ha 662 addi r12,r8,(ABS_ADDR(4f, text))@l 663 mtctr r12 664 bctr 665 666.balign 8 667p_end: .8byte _end - copy_to_here 668 6694: 670 /* 671 * Now copy the rest of the kernel up to _end, add 672 * _end - copy_to_here to the copy limit and run again. 673 */ 674 addis r8,r26,(ABS_ADDR(p_end, text))@ha 675 ld r8,(ABS_ADDR(p_end, text))@l(r8) 676 add r5,r5,r8 6775: bl copy_and_flush /* copy the rest */ 678 6799: b start_here_multiplatform 680 681/* 682 * Copy routine used to copy the kernel to start at physical address 0 683 * and flush and invalidate the caches as needed. 684 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 685 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 686 * 687 * Note: this routine *only* clobbers r0, r6 and lr 688 */ 689_GLOBAL(copy_and_flush) 690 addi r5,r5,-8 691 addi r6,r6,-8 6924: li r0,8 /* Use the smallest common */ 693 /* denominator cache line */ 694 /* size. This results in */ 695 /* extra cache line flushes */ 696 /* but operation is correct. */ 697 /* Can't get cache line size */ 698 /* from NACA as it is being */ 699 /* moved too. */ 700 701 mtctr r0 /* put # words/line in ctr */ 7023: addi r6,r6,8 /* copy a cache line */ 703 ldx r0,r6,r4 704 stdx r0,r6,r3 705 bdnz 3b 706 dcbst r6,r3 /* write it to memory */ 707 sync 708 icbi r6,r3 /* flush the icache line */ 709 cmpld 0,r6,r5 710 blt 4b 711 sync 712 addi r5,r5,8 713 addi r6,r6,8 714 isync 715 blr 716 717_ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */ 718 719.align 8 720copy_to_here: 721 722#ifdef CONFIG_SMP 723#ifdef CONFIG_PPC_PMAC 724/* 725 * On PowerMac, secondary processors starts from the reset vector, which 726 * is temporarily turned into a call to one of the functions below. 727 */ 728 .section ".text"; 729 .align 2 ; 730 731 .globl __secondary_start_pmac_0 732__secondary_start_pmac_0: 733 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 734 li r24,0 735 b 1f 736 li r24,1 737 b 1f 738 li r24,2 739 b 1f 740 li r24,3 7411: 742 743_GLOBAL(pmac_secondary_start) 744 /* turn on 64-bit mode */ 745 bl enable_64b_mode 746 747 li r0,0 748 mfspr r3,SPRN_HID4 749 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 750 sync 751 mtspr SPRN_HID4,r3 752 isync 753 sync 754 slbia 755 756 /* get TOC pointer (real address) */ 757 bl relative_toc 758 tovirt(r2,r2) 759 760 /* Copy some CPU settings from CPU 0 */ 761 bl __restore_cpu_ppc970 762 763 /* pSeries do that early though I don't think we really need it */ 764 mfmsr r3 765 ori r3,r3,MSR_RI 766 mtmsrd r3 /* RI on */ 767 768 /* Set up a paca value for this processor. */ 769 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ 770 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ 771 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ 772 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ 773 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 774 775 /* Mark interrupts soft and hard disabled (they might be enabled 776 * in the PACA when doing hotplug) 777 */ 778 li r0,IRQS_DISABLED 779 stb r0,PACAIRQSOFTMASK(r13) 780 li r0,PACA_IRQ_HARD_DIS 781 stb r0,PACAIRQHAPPENED(r13) 782 783 /* Create a temp kernel stack for use before relocation is on. */ 784 ld r1,PACAEMERGSP(r13) 785 subi r1,r1,STACK_FRAME_MIN_SIZE 786 787 b __secondary_start 788 789#endif /* CONFIG_PPC_PMAC */ 790 791/* 792 * This function is called after the master CPU has released the 793 * secondary processors. The execution environment is relocation off. 794 * The paca for this processor has the following fields initialized at 795 * this point: 796 * 1. Processor number 797 * 2. Segment table pointer (virtual address) 798 * On entry the following are set: 799 * r1 = stack pointer (real addr of temp stack) 800 * r24 = cpu# (in Linux terms) 801 * r13 = paca virtual address 802 * SPRG_PACA = paca virtual address 803 */ 804 .section ".text"; 805 .align 2 ; 806 807 .globl __secondary_start 808__secondary_start: 809 /* Set thread priority to MEDIUM */ 810 HMT_MEDIUM 811 812 /* 813 * Do early setup for this CPU, in particular initialising the MMU so we 814 * can turn it on below. This is a call to C, which is OK, we're still 815 * running on the emergency stack. 816 */ 817 bl early_setup_secondary 818 819 /* 820 * The primary has initialized our kernel stack for us in the paca, grab 821 * it and put it in r1. We must *not* use it until we turn on the MMU 822 * below, because it may not be inside the RMO. 823 */ 824 ld r1, PACAKSAVE(r13) 825 826 /* Clear backchain so we get nice backtraces */ 827 li r7,0 828 mtlr r7 829 830 /* Mark interrupts soft and hard disabled (they might be enabled 831 * in the PACA when doing hotplug) 832 */ 833 li r7,IRQS_DISABLED 834 stb r7,PACAIRQSOFTMASK(r13) 835 li r0,PACA_IRQ_HARD_DIS 836 stb r0,PACAIRQHAPPENED(r13) 837 838 /* enable MMU and jump to start_secondary */ 839 LOAD_REG_ADDR(r3, start_secondary_prolog) 840 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 841 842 mtspr SPRN_SRR0,r3 843 mtspr SPRN_SRR1,r4 844 RFI_TO_KERNEL 845 b . /* prevent speculative execution */ 846 847/* 848 * Running with relocation on at this point. All we want to do is 849 * zero the stack back-chain pointer and get the TOC virtual address 850 * before going into C code. 851 */ 852start_secondary_prolog: 853 LOAD_PACA_TOC() 854 li r3,0 855 std r3,0(r1) /* Zero the stack frame pointer */ 856 bl start_secondary 857 b . 858/* 859 * Reset stack pointer and call start_secondary 860 * to continue with online operation when woken up 861 * from cede in cpu offline. 862 */ 863_GLOBAL(start_secondary_resume) 864 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 865 li r3,0 866 std r3,0(r1) /* Zero the stack frame pointer */ 867 bl start_secondary 868 b . 869#endif 870 871/* 872 * This subroutine clobbers r11 and r12 873 */ 874SYM_FUNC_START_LOCAL(enable_64b_mode) 875 mfmsr r11 /* grab the current MSR */ 876#ifdef CONFIG_PPC_BOOK3E_64 877 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 878 mtmsr r11 879#else /* CONFIG_PPC_BOOK3E_64 */ 880 LOAD_REG_IMMEDIATE(r12, MSR_64BIT) 881 or r11,r11,r12 882 mtmsrd r11 883 isync 884#endif 885 blr 886SYM_FUNC_END(enable_64b_mode) 887 888/* 889 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 890 * by the toolchain). It computes the correct value for wherever we 891 * are running at the moment, using position-independent code. 892 * 893 * Note: The compiler constructs pointers using offsets from the 894 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 895 * the MMU is on we need our TOC to be a virtual address otherwise 896 * these pointers will be real addresses which may get stored and 897 * accessed later with the MMU on. We use tovirt() at the call 898 * sites to handle this. 899 */ 900_GLOBAL(relative_toc) 901 mflr r0 902 bcl 20,31,$+4 9030: mflr r11 904 ld r2,(p_toc - 0b)(r11) 905 add r2,r2,r11 906 mtlr r0 907 blr 908 909.balign 8 910p_toc: .8byte .TOC. - 0b 911 912/* 913 * This is where the main kernel code starts. 914 */ 915__REF 916start_here_multiplatform: 917 /* set up the TOC */ 918 bl relative_toc 919 tovirt(r2,r2) 920 921 /* Clear out the BSS. It may have been done in prom_init, 922 * already but that's irrelevant since prom_init will soon 923 * be detached from the kernel completely. Besides, we need 924 * to clear it now for kexec-style entry. 925 */ 926 LOAD_REG_ADDR(r11,__bss_stop) 927 LOAD_REG_ADDR(r8,__bss_start) 928 sub r11,r11,r8 /* bss size */ 929 addi r11,r11,7 /* round up to an even double word */ 930 srdi. r11,r11,3 /* shift right by 3 */ 931 beq 4f 932 addi r8,r8,-8 933 li r0,0 934 mtctr r11 /* zero this many doublewords */ 9353: stdu r0,8(r8) 936 bdnz 3b 9374: 938 939#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 940 /* Setup OPAL entry */ 941 LOAD_REG_ADDR(r11, opal) 942 std r28,0(r11); 943 std r29,8(r11); 944#endif 945 946#ifndef CONFIG_PPC_BOOK3E_64 947 mfmsr r6 948 ori r6,r6,MSR_RI 949 mtmsrd r6 /* RI on */ 950#endif 951 952#ifdef CONFIG_RELOCATABLE 953 /* Save the physical address we're running at in kernstart_addr */ 954 LOAD_REG_ADDR(r4, kernstart_addr) 955 clrldi r0,r25,2 956 std r0,0(r4) 957#endif 958 959 /* set up a stack pointer */ 960 LOAD_REG_ADDR(r3,init_thread_union) 961 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) 962 add r1,r3,r1 963 li r0,0 964 stdu r0,-STACK_FRAME_MIN_SIZE(r1) 965 966 /* 967 * Do very early kernel initializations, including initial hash table 968 * and SLB setup before we turn on relocation. 969 */ 970 971#ifdef CONFIG_KASAN 972 bl kasan_early_init 973#endif 974 /* Restore parameters passed from prom_init/kexec */ 975 mr r3,r31 976 LOAD_REG_ADDR(r12, DOTSYM(early_setup)) 977 mtctr r12 978 bctrl /* also sets r13 and SPRG_PACA */ 979 980 LOAD_REG_ADDR(r3, start_here_common) 981 ld r4,PACAKMSR(r13) 982 mtspr SPRN_SRR0,r3 983 mtspr SPRN_SRR1,r4 984 RFI_TO_KERNEL 985 b . /* prevent speculative execution */ 986 987 /* This is where all platforms converge execution */ 988 989start_here_common: 990 /* relocation is on at this point */ 991 std r1,PACAKSAVE(r13) 992 993 /* Load the TOC (virtual address) */ 994 LOAD_PACA_TOC() 995 996 /* Mark interrupts soft and hard disabled (they might be enabled 997 * in the PACA when doing hotplug) 998 */ 999 li r0,IRQS_DISABLED 1000 stb r0,PACAIRQSOFTMASK(r13) 1001 li r0,PACA_IRQ_HARD_DIS 1002 stb r0,PACAIRQHAPPENED(r13) 1003 1004 /* Generic kernel entry */ 1005 bl start_kernel 1006 1007 /* Not reached */ 10080: trap 1009 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 1010 .previous 1011