1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the low-level support and setup for the 16 * PowerPC-64 platform, including trap and interrupt dispatch. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License 20 * as published by the Free Software Foundation; either version 21 * 2 of the License, or (at your option) any later version. 22 */ 23 24#include <linux/threads.h> 25#include <asm/reg.h> 26#include <asm/page.h> 27#include <asm/mmu.h> 28#include <asm/ppc_asm.h> 29#include <asm/asm-offsets.h> 30#include <asm/bug.h> 31#include <asm/cputable.h> 32#include <asm/setup.h> 33#include <asm/hvcall.h> 34#include <asm/iseries/lpar_map.h> 35#include <asm/thread_info.h> 36#include <asm/firmware.h> 37#include <asm/page_64.h> 38#include <asm/exception.h> 39#include <asm/irqflags.h> 40 41/* 42 * We layout physical memory as follows: 43 * 0x0000 - 0x00ff : Secondary processor spin code 44 * 0x0100 - 0x2fff : pSeries Interrupt prologs 45 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs 46 * 0x6000 - 0x6fff : Initial (CPU0) segment table 47 * 0x7000 - 0x7fff : FWNMI data area 48 * 0x8000 - : Early init and support code 49 */ 50 51/* 52 * SPRG Usage 53 * 54 * Register Definition 55 * 56 * SPRG0 reserved for hypervisor 57 * SPRG1 temp - used to save gpr 58 * SPRG2 temp - used to save gpr 59 * SPRG3 virt addr of paca 60 */ 61 62/* 63 * Entering into this code we make the following assumptions: 64 * For pSeries: 65 * 1. The MMU is off & open firmware is running in real mode. 66 * 2. The kernel is entered at __start 67 * 68 * For iSeries: 69 * 1. The MMU is on (as it always is for iSeries) 70 * 2. The kernel is entered at system_reset_iSeries 71 */ 72 73 .text 74 .globl _stext 75_stext: 76_GLOBAL(__start) 77 /* NOP this out unconditionally */ 78BEGIN_FTR_SECTION 79 b .__start_initialization_multiplatform 80END_FTR_SECTION(0, 1) 81 82 /* Catch branch to 0 in real mode */ 83 trap 84 85 /* Secondary processors spin on this value until it goes to 1. */ 86 .globl __secondary_hold_spinloop 87__secondary_hold_spinloop: 88 .llong 0x0 89 90 /* Secondary processors write this value with their cpu # */ 91 /* after they enter the spin loop immediately below. */ 92 .globl __secondary_hold_acknowledge 93__secondary_hold_acknowledge: 94 .llong 0x0 95 96#ifdef CONFIG_PPC_ISERIES 97 /* 98 * At offset 0x20, there is a pointer to iSeries LPAR data. 99 * This is required by the hypervisor 100 */ 101 . = 0x20 102 .llong hvReleaseData-KERNELBASE 103#endif /* CONFIG_PPC_ISERIES */ 104 105 . = 0x60 106/* 107 * The following code is used to hold secondary processors 108 * in a spin loop after they have entered the kernel, but 109 * before the bulk of the kernel has been relocated. This code 110 * is relocated to physical address 0x60 before prom_init is run. 111 * All of it must fit below the first exception vector at 0x100. 112 */ 113_GLOBAL(__secondary_hold) 114 mfmsr r24 115 ori r24,r24,MSR_RI 116 mtmsrd r24 /* RI on */ 117 118 /* Grab our physical cpu number */ 119 mr r24,r3 120 121 /* Tell the master cpu we're here */ 122 /* Relocation is off & we are located at an address less */ 123 /* than 0x100, so only need to grab low order offset. */ 124 std r24,__secondary_hold_acknowledge@l(0) 125 sync 126 127 /* All secondary cpus wait here until told to start. */ 128100: ld r4,__secondary_hold_spinloop@l(0) 129 cmpdi 0,r4,1 130 bne 100b 131 132#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 133 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init) 134 mtctr r4 135 mr r3,r24 136 bctr 137#else 138 BUG_OPCODE 139#endif 140 141/* This value is used to mark exception frames on the stack. */ 142 .section ".toc","aw" 143exception_marker: 144 .tc ID_72656773_68657265[TC],0x7265677368657265 145 .text 146 147/* 148 * This is the start of the interrupt handlers for pSeries 149 * This code runs with relocation off. 150 */ 151 . = 0x100 152 .globl __start_interrupts 153__start_interrupts: 154 155 STD_EXCEPTION_PSERIES(0x100, system_reset) 156 157 . = 0x200 158_machine_check_pSeries: 159 HMT_MEDIUM 160 mtspr SPRN_SPRG1,r13 /* save r13 */ 161 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 162 163 . = 0x300 164 .globl data_access_pSeries 165data_access_pSeries: 166 HMT_MEDIUM 167 mtspr SPRN_SPRG1,r13 168BEGIN_FTR_SECTION 169 mtspr SPRN_SPRG2,r12 170 mfspr r13,SPRN_DAR 171 mfspr r12,SPRN_DSISR 172 srdi r13,r13,60 173 rlwimi r13,r12,16,0x20 174 mfcr r12 175 cmpwi r13,0x2c 176 beq do_stab_bolted_pSeries 177 mtcrf 0x80,r12 178 mfspr r12,SPRN_SPRG2 179END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 180 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 181 182 . = 0x380 183 .globl data_access_slb_pSeries 184data_access_slb_pSeries: 185 HMT_MEDIUM 186 mtspr SPRN_SPRG1,r13 187 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 188 std r3,PACA_EXSLB+EX_R3(r13) 189 mfspr r3,SPRN_DAR 190 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 191 mfcr r9 192#ifdef __DISABLED__ 193 /* Keep that around for when we re-implement dynamic VSIDs */ 194 cmpdi r3,0 195 bge slb_miss_user_pseries 196#endif /* __DISABLED__ */ 197 std r10,PACA_EXSLB+EX_R10(r13) 198 std r11,PACA_EXSLB+EX_R11(r13) 199 std r12,PACA_EXSLB+EX_R12(r13) 200 mfspr r10,SPRN_SPRG1 201 std r10,PACA_EXSLB+EX_R13(r13) 202 mfspr r12,SPRN_SRR1 /* and SRR1 */ 203 b .slb_miss_realmode /* Rel. branch works in real mode */ 204 205 STD_EXCEPTION_PSERIES(0x400, instruction_access) 206 207 . = 0x480 208 .globl instruction_access_slb_pSeries 209instruction_access_slb_pSeries: 210 HMT_MEDIUM 211 mtspr SPRN_SPRG1,r13 212 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 213 std r3,PACA_EXSLB+EX_R3(r13) 214 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 215 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 216 mfcr r9 217#ifdef __DISABLED__ 218 /* Keep that around for when we re-implement dynamic VSIDs */ 219 cmpdi r3,0 220 bge slb_miss_user_pseries 221#endif /* __DISABLED__ */ 222 std r10,PACA_EXSLB+EX_R10(r13) 223 std r11,PACA_EXSLB+EX_R11(r13) 224 std r12,PACA_EXSLB+EX_R12(r13) 225 mfspr r10,SPRN_SPRG1 226 std r10,PACA_EXSLB+EX_R13(r13) 227 mfspr r12,SPRN_SRR1 /* and SRR1 */ 228 b .slb_miss_realmode /* Rel. branch works in real mode */ 229 230 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) 231 STD_EXCEPTION_PSERIES(0x600, alignment) 232 STD_EXCEPTION_PSERIES(0x700, program_check) 233 STD_EXCEPTION_PSERIES(0x800, fp_unavailable) 234 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) 235 STD_EXCEPTION_PSERIES(0xa00, trap_0a) 236 STD_EXCEPTION_PSERIES(0xb00, trap_0b) 237 238 . = 0xc00 239 .globl system_call_pSeries 240system_call_pSeries: 241 HMT_MEDIUM 242BEGIN_FTR_SECTION 243 cmpdi r0,0x1ebe 244 beq- 1f 245END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) 246 mr r9,r13 247 mfmsr r10 248 mfspr r13,SPRN_SPRG3 249 mfspr r11,SPRN_SRR0 250 clrrdi r12,r13,32 251 oris r12,r12,system_call_common@h 252 ori r12,r12,system_call_common@l 253 mtspr SPRN_SRR0,r12 254 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 255 mfspr r12,SPRN_SRR1 256 mtspr SPRN_SRR1,r10 257 rfid 258 b . /* prevent speculative execution */ 259 260/* Fast LE/BE switch system call */ 2611: mfspr r12,SPRN_SRR1 262 xori r12,r12,MSR_LE 263 mtspr SPRN_SRR1,r12 264 rfid /* return to userspace */ 265 b . 266 267 STD_EXCEPTION_PSERIES(0xd00, single_step) 268 STD_EXCEPTION_PSERIES(0xe00, trap_0e) 269 270 /* We need to deal with the Altivec unavailable exception 271 * here which is at 0xf20, thus in the middle of the 272 * prolog code of the PerformanceMonitor one. A little 273 * trickery is thus necessary 274 */ 275 . = 0xf00 276 b performance_monitor_pSeries 277 278 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) 279 280#ifdef CONFIG_CBE_RAS 281 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) 282#endif /* CONFIG_CBE_RAS */ 283 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) 284#ifdef CONFIG_CBE_RAS 285 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) 286#endif /* CONFIG_CBE_RAS */ 287 STD_EXCEPTION_PSERIES(0x1700, altivec_assist) 288#ifdef CONFIG_CBE_RAS 289 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) 290#endif /* CONFIG_CBE_RAS */ 291 292 . = 0x3000 293 294/*** pSeries interrupt support ***/ 295 296 /* moved from 0xf00 */ 297 STD_EXCEPTION_PSERIES(., performance_monitor) 298 299/* 300 * An interrupt came in while soft-disabled; clear EE in SRR1, 301 * clear paca->hard_enabled and return. 302 */ 303masked_interrupt: 304 stb r10,PACAHARDIRQEN(r13) 305 mtcrf 0x80,r9 306 ld r9,PACA_EXGEN+EX_R9(r13) 307 mfspr r10,SPRN_SRR1 308 rldicl r10,r10,48,1 /* clear MSR_EE */ 309 rotldi r10,r10,16 310 mtspr SPRN_SRR1,r10 311 ld r10,PACA_EXGEN+EX_R10(r13) 312 mfspr r13,SPRN_SPRG1 313 rfid 314 b . 315 316 .align 7 317do_stab_bolted_pSeries: 318 mtcrf 0x80,r12 319 mfspr r12,SPRN_SPRG2 320 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 321 322/* 323 * We have some room here we use that to put 324 * the peries slb miss user trampoline code so it's reasonably 325 * away from slb_miss_user_common to avoid problems with rfid 326 * 327 * This is used for when the SLB miss handler has to go virtual, 328 * which doesn't happen for now anymore but will once we re-implement 329 * dynamic VSIDs for shared page tables 330 */ 331#ifdef __DISABLED__ 332slb_miss_user_pseries: 333 std r10,PACA_EXGEN+EX_R10(r13) 334 std r11,PACA_EXGEN+EX_R11(r13) 335 std r12,PACA_EXGEN+EX_R12(r13) 336 mfspr r10,SPRG1 337 ld r11,PACA_EXSLB+EX_R9(r13) 338 ld r12,PACA_EXSLB+EX_R3(r13) 339 std r10,PACA_EXGEN+EX_R13(r13) 340 std r11,PACA_EXGEN+EX_R9(r13) 341 std r12,PACA_EXGEN+EX_R3(r13) 342 clrrdi r12,r13,32 343 mfmsr r10 344 mfspr r11,SRR0 /* save SRR0 */ 345 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ 346 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 347 mtspr SRR0,r12 348 mfspr r12,SRR1 /* and SRR1 */ 349 mtspr SRR1,r10 350 rfid 351 b . /* prevent spec. execution */ 352#endif /* __DISABLED__ */ 353 354#ifdef CONFIG_PPC_PSERIES 355/* 356 * Vectors for the FWNMI option. Share common code. 357 */ 358 .globl system_reset_fwnmi 359 .align 7 360system_reset_fwnmi: 361 HMT_MEDIUM 362 mtspr SPRN_SPRG1,r13 /* save r13 */ 363 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common) 364 365 .globl machine_check_fwnmi 366 .align 7 367machine_check_fwnmi: 368 HMT_MEDIUM 369 mtspr SPRN_SPRG1,r13 /* save r13 */ 370 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common) 371 372#endif /* CONFIG_PPC_PSERIES */ 373 374/*** Common interrupt handlers ***/ 375 376 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) 377 378 /* 379 * Machine check is different because we use a different 380 * save area: PACA_EXMC instead of PACA_EXGEN. 381 */ 382 .align 7 383 .globl machine_check_common 384machine_check_common: 385 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 386 FINISH_NAP 387 DISABLE_INTS 388 bl .save_nvgprs 389 addi r3,r1,STACK_FRAME_OVERHEAD 390 bl .machine_check_exception 391 b .ret_from_except 392 393 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) 394 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) 395 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) 396 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) 397 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) 398 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) 399 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) 400#ifdef CONFIG_ALTIVEC 401 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) 402#else 403 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) 404#endif 405#ifdef CONFIG_CBE_RAS 406 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) 407 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) 408 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) 409#endif /* CONFIG_CBE_RAS */ 410 411/* 412 * Here we have detected that the kernel stack pointer is bad. 413 * R9 contains the saved CR, r13 points to the paca, 414 * r10 contains the (bad) kernel stack pointer, 415 * r11 and r12 contain the saved SRR0 and SRR1. 416 * We switch to using an emergency stack, save the registers there, 417 * and call kernel_bad_stack(), which panics. 418 */ 419bad_stack: 420 ld r1,PACAEMERGSP(r13) 421 subi r1,r1,64+INT_FRAME_SIZE 422 std r9,_CCR(r1) 423 std r10,GPR1(r1) 424 std r11,_NIP(r1) 425 std r12,_MSR(r1) 426 mfspr r11,SPRN_DAR 427 mfspr r12,SPRN_DSISR 428 std r11,_DAR(r1) 429 std r12,_DSISR(r1) 430 mflr r10 431 mfctr r11 432 mfxer r12 433 std r10,_LINK(r1) 434 std r11,_CTR(r1) 435 std r12,_XER(r1) 436 SAVE_GPR(0,r1) 437 SAVE_GPR(2,r1) 438 SAVE_4GPRS(3,r1) 439 SAVE_2GPRS(7,r1) 440 SAVE_10GPRS(12,r1) 441 SAVE_10GPRS(22,r1) 442 lhz r12,PACA_TRAP_SAVE(r13) 443 std r12,_TRAP(r1) 444 addi r11,r1,INT_FRAME_SIZE 445 std r11,0(r1) 446 li r12,0 447 std r12,0(r11) 448 ld r2,PACATOC(r13) 4491: addi r3,r1,STACK_FRAME_OVERHEAD 450 bl .kernel_bad_stack 451 b 1b 452 453/* 454 * Return from an exception with minimal checks. 455 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. 456 * If interrupts have been enabled, or anything has been 457 * done that might have changed the scheduling status of 458 * any task or sent any task a signal, you should use 459 * ret_from_except or ret_from_except_lite instead of this. 460 */ 461fast_exc_return_irq: /* restores irq state too */ 462 ld r3,SOFTE(r1) 463 TRACE_AND_RESTORE_IRQ(r3); 464 ld r12,_MSR(r1) 465 rldicl r4,r12,49,63 /* get MSR_EE to LSB */ 466 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ 467 b 1f 468 469 .globl fast_exception_return 470fast_exception_return: 471 ld r12,_MSR(r1) 4721: ld r11,_NIP(r1) 473 andi. r3,r12,MSR_RI /* check if RI is set */ 474 beq- unrecov_fer 475 476#ifdef CONFIG_VIRT_CPU_ACCOUNTING 477 andi. r3,r12,MSR_PR 478 beq 2f 479 ACCOUNT_CPU_USER_EXIT(r3, r4) 4802: 481#endif 482 483 ld r3,_CCR(r1) 484 ld r4,_LINK(r1) 485 ld r5,_CTR(r1) 486 ld r6,_XER(r1) 487 mtcr r3 488 mtlr r4 489 mtctr r5 490 mtxer r6 491 REST_GPR(0, r1) 492 REST_8GPRS(2, r1) 493 494 mfmsr r10 495 rldicl r10,r10,48,1 /* clear EE */ 496 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ 497 mtmsrd r10,1 498 499 mtspr SPRN_SRR1,r12 500 mtspr SPRN_SRR0,r11 501 REST_4GPRS(10, r1) 502 ld r1,GPR1(r1) 503 rfid 504 b . /* prevent speculative execution */ 505 506unrecov_fer: 507 bl .save_nvgprs 5081: addi r3,r1,STACK_FRAME_OVERHEAD 509 bl .unrecoverable_exception 510 b 1b 511 512/* 513 * Here r13 points to the paca, r9 contains the saved CR, 514 * SRR0 and SRR1 are saved in r11 and r12, 515 * r9 - r13 are saved in paca->exgen. 516 */ 517 .align 7 518 .globl data_access_common 519data_access_common: 520 mfspr r10,SPRN_DAR 521 std r10,PACA_EXGEN+EX_DAR(r13) 522 mfspr r10,SPRN_DSISR 523 stw r10,PACA_EXGEN+EX_DSISR(r13) 524 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 525 ld r3,PACA_EXGEN+EX_DAR(r13) 526 lwz r4,PACA_EXGEN+EX_DSISR(r13) 527 li r5,0x300 528 b .do_hash_page /* Try to handle as hpte fault */ 529 530 .align 7 531 .globl instruction_access_common 532instruction_access_common: 533 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 534 ld r3,_NIP(r1) 535 andis. r4,r12,0x5820 536 li r5,0x400 537 b .do_hash_page /* Try to handle as hpte fault */ 538 539/* 540 * Here is the common SLB miss user that is used when going to virtual 541 * mode for SLB misses, that is currently not used 542 */ 543#ifdef __DISABLED__ 544 .align 7 545 .globl slb_miss_user_common 546slb_miss_user_common: 547 mflr r10 548 std r3,PACA_EXGEN+EX_DAR(r13) 549 stw r9,PACA_EXGEN+EX_CCR(r13) 550 std r10,PACA_EXGEN+EX_LR(r13) 551 std r11,PACA_EXGEN+EX_SRR0(r13) 552 bl .slb_allocate_user 553 554 ld r10,PACA_EXGEN+EX_LR(r13) 555 ld r3,PACA_EXGEN+EX_R3(r13) 556 lwz r9,PACA_EXGEN+EX_CCR(r13) 557 ld r11,PACA_EXGEN+EX_SRR0(r13) 558 mtlr r10 559 beq- slb_miss_fault 560 561 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 562 beq- unrecov_user_slb 563 mfmsr r10 564 565.machine push 566.machine "power4" 567 mtcrf 0x80,r9 568.machine pop 569 570 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ 571 mtmsrd r10,1 572 573 mtspr SRR0,r11 574 mtspr SRR1,r12 575 576 ld r9,PACA_EXGEN+EX_R9(r13) 577 ld r10,PACA_EXGEN+EX_R10(r13) 578 ld r11,PACA_EXGEN+EX_R11(r13) 579 ld r12,PACA_EXGEN+EX_R12(r13) 580 ld r13,PACA_EXGEN+EX_R13(r13) 581 rfid 582 b . 583 584slb_miss_fault: 585 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) 586 ld r4,PACA_EXGEN+EX_DAR(r13) 587 li r5,0 588 std r4,_DAR(r1) 589 std r5,_DSISR(r1) 590 b handle_page_fault 591 592unrecov_user_slb: 593 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) 594 DISABLE_INTS 595 bl .save_nvgprs 5961: addi r3,r1,STACK_FRAME_OVERHEAD 597 bl .unrecoverable_exception 598 b 1b 599 600#endif /* __DISABLED__ */ 601 602 603/* 604 * r13 points to the PACA, r9 contains the saved CR, 605 * r12 contain the saved SRR1, SRR0 is still ready for return 606 * r3 has the faulting address 607 * r9 - r13 are saved in paca->exslb. 608 * r3 is saved in paca->slb_r3 609 * We assume we aren't going to take any exceptions during this procedure. 610 */ 611_GLOBAL(slb_miss_realmode) 612 mflr r10 613 614 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 615 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 616 617 bl .slb_allocate_realmode 618 619 /* All done -- return from exception. */ 620 621 ld r10,PACA_EXSLB+EX_LR(r13) 622 ld r3,PACA_EXSLB+EX_R3(r13) 623 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 624#ifdef CONFIG_PPC_ISERIES 625BEGIN_FW_FTR_SECTION 626 ld r11,PACALPPACAPTR(r13) 627 ld r11,LPPACASRR0(r11) /* get SRR0 value */ 628END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 629#endif /* CONFIG_PPC_ISERIES */ 630 631 mtlr r10 632 633 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 634 beq- 2f 635 636.machine push 637.machine "power4" 638 mtcrf 0x80,r9 639 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 640.machine pop 641 642#ifdef CONFIG_PPC_ISERIES 643BEGIN_FW_FTR_SECTION 644 mtspr SPRN_SRR0,r11 645 mtspr SPRN_SRR1,r12 646END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 647#endif /* CONFIG_PPC_ISERIES */ 648 ld r9,PACA_EXSLB+EX_R9(r13) 649 ld r10,PACA_EXSLB+EX_R10(r13) 650 ld r11,PACA_EXSLB+EX_R11(r13) 651 ld r12,PACA_EXSLB+EX_R12(r13) 652 ld r13,PACA_EXSLB+EX_R13(r13) 653 rfid 654 b . /* prevent speculative execution */ 655 6562: 657#ifdef CONFIG_PPC_ISERIES 658BEGIN_FW_FTR_SECTION 659 b unrecov_slb 660END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 661#endif /* CONFIG_PPC_ISERIES */ 662 mfspr r11,SPRN_SRR0 663 clrrdi r10,r13,32 664 LOAD_HANDLER(r10,unrecov_slb) 665 mtspr SPRN_SRR0,r10 666 mfmsr r10 667 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 668 mtspr SPRN_SRR1,r10 669 rfid 670 b . 671 672unrecov_slb: 673 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 674 DISABLE_INTS 675 bl .save_nvgprs 6761: addi r3,r1,STACK_FRAME_OVERHEAD 677 bl .unrecoverable_exception 678 b 1b 679 680 .align 7 681 .globl hardware_interrupt_common 682 .globl hardware_interrupt_entry 683hardware_interrupt_common: 684 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) 685 FINISH_NAP 686hardware_interrupt_entry: 687 DISABLE_INTS 688BEGIN_FTR_SECTION 689 bl .ppc64_runlatch_on 690END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 691 addi r3,r1,STACK_FRAME_OVERHEAD 692 bl .do_IRQ 693 b .ret_from_except_lite 694 695#ifdef CONFIG_PPC_970_NAP 696power4_fixup_nap: 697 andc r9,r9,r10 698 std r9,TI_LOCAL_FLAGS(r11) 699 ld r10,_LINK(r1) /* make idle task do the */ 700 std r10,_NIP(r1) /* equivalent of a blr */ 701 blr 702#endif 703 704 .align 7 705 .globl alignment_common 706alignment_common: 707 mfspr r10,SPRN_DAR 708 std r10,PACA_EXGEN+EX_DAR(r13) 709 mfspr r10,SPRN_DSISR 710 stw r10,PACA_EXGEN+EX_DSISR(r13) 711 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 712 ld r3,PACA_EXGEN+EX_DAR(r13) 713 lwz r4,PACA_EXGEN+EX_DSISR(r13) 714 std r3,_DAR(r1) 715 std r4,_DSISR(r1) 716 bl .save_nvgprs 717 addi r3,r1,STACK_FRAME_OVERHEAD 718 ENABLE_INTS 719 bl .alignment_exception 720 b .ret_from_except 721 722 .align 7 723 .globl program_check_common 724program_check_common: 725 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 726 bl .save_nvgprs 727 addi r3,r1,STACK_FRAME_OVERHEAD 728 ENABLE_INTS 729 bl .program_check_exception 730 b .ret_from_except 731 732 .align 7 733 .globl fp_unavailable_common 734fp_unavailable_common: 735 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 736 bne 1f /* if from user, just load it up */ 737 bl .save_nvgprs 738 addi r3,r1,STACK_FRAME_OVERHEAD 739 ENABLE_INTS 740 bl .kernel_fp_unavailable_exception 741 BUG_OPCODE 7421: b .load_up_fpu 743 744 .align 7 745 .globl altivec_unavailable_common 746altivec_unavailable_common: 747 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 748#ifdef CONFIG_ALTIVEC 749BEGIN_FTR_SECTION 750 bne .load_up_altivec /* if from user, just load it up */ 751END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 752#endif 753 bl .save_nvgprs 754 addi r3,r1,STACK_FRAME_OVERHEAD 755 ENABLE_INTS 756 bl .altivec_unavailable_exception 757 b .ret_from_except 758 759#ifdef CONFIG_ALTIVEC 760/* 761 * load_up_altivec(unused, unused, tsk) 762 * Disable VMX for the task which had it previously, 763 * and save its vector registers in its thread_struct. 764 * Enables the VMX for use in the kernel on return. 765 * On SMP we know the VMX is free, since we give it up every 766 * switch (ie, no lazy save of the vector registers). 767 * On entry: r13 == 'current' && last_task_used_altivec != 'current' 768 */ 769_STATIC(load_up_altivec) 770 mfmsr r5 /* grab the current MSR */ 771 oris r5,r5,MSR_VEC@h 772 mtmsrd r5 /* enable use of VMX now */ 773 isync 774 775/* 776 * For SMP, we don't do lazy VMX switching because it just gets too 777 * horrendously complex, especially when a task switches from one CPU 778 * to another. Instead we call giveup_altvec in switch_to. 779 * VRSAVE isn't dealt with here, that is done in the normal context 780 * switch code. Note that we could rely on vrsave value to eventually 781 * avoid saving all of the VREGs here... 782 */ 783#ifndef CONFIG_SMP 784 ld r3,last_task_used_altivec@got(r2) 785 ld r4,0(r3) 786 cmpdi 0,r4,0 787 beq 1f 788 /* Save VMX state to last_task_used_altivec's THREAD struct */ 789 addi r4,r4,THREAD 790 SAVE_32VRS(0,r5,r4) 791 mfvscr vr0 792 li r10,THREAD_VSCR 793 stvx vr0,r10,r4 794 /* Disable VMX for last_task_used_altivec */ 795 ld r5,PT_REGS(r4) 796 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 797 lis r6,MSR_VEC@h 798 andc r4,r4,r6 799 std r4,_MSR-STACK_FRAME_OVERHEAD(r5) 8001: 801#endif /* CONFIG_SMP */ 802 /* Hack: if we get an altivec unavailable trap with VRSAVE 803 * set to all zeros, we assume this is a broken application 804 * that fails to set it properly, and thus we switch it to 805 * all 1's 806 */ 807 mfspr r4,SPRN_VRSAVE 808 cmpdi 0,r4,0 809 bne+ 1f 810 li r4,-1 811 mtspr SPRN_VRSAVE,r4 8121: 813 /* enable use of VMX after return */ 814 ld r4,PACACURRENT(r13) 815 addi r5,r4,THREAD /* Get THREAD */ 816 oris r12,r12,MSR_VEC@h 817 std r12,_MSR(r1) 818 li r4,1 819 li r10,THREAD_VSCR 820 stw r4,THREAD_USED_VR(r5) 821 lvx vr0,r10,r5 822 mtvscr vr0 823 REST_32VRS(0,r4,r5) 824#ifndef CONFIG_SMP 825 /* Update last_task_used_math to 'current' */ 826 subi r4,r5,THREAD /* Back to 'current' */ 827 std r4,0(r3) 828#endif /* CONFIG_SMP */ 829 /* restore registers and return */ 830 b fast_exception_return 831#endif /* CONFIG_ALTIVEC */ 832 833/* 834 * Hash table stuff 835 */ 836 .align 7 837_STATIC(do_hash_page) 838 std r3,_DAR(r1) 839 std r4,_DSISR(r1) 840 841 andis. r0,r4,0xa450 /* weird error? */ 842 bne- handle_page_fault /* if not, try to insert a HPTE */ 843BEGIN_FTR_SECTION 844 andis. r0,r4,0x0020 /* Is it a segment table fault? */ 845 bne- do_ste_alloc /* If so handle it */ 846END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 847 848 /* 849 * On iSeries, we soft-disable interrupts here, then 850 * hard-enable interrupts so that the hash_page code can spin on 851 * the hash_table_lock without problems on a shared processor. 852 */ 853 DISABLE_INTS 854 855 /* 856 * Currently, trace_hardirqs_off() will be called by DISABLE_INTS 857 * and will clobber volatile registers when irq tracing is enabled 858 * so we need to reload them. It may be possible to be smarter here 859 * and move the irq tracing elsewhere but let's keep it simple for 860 * now 861 */ 862#ifdef CONFIG_TRACE_IRQFLAGS 863 ld r3,_DAR(r1) 864 ld r4,_DSISR(r1) 865 ld r5,_TRAP(r1) 866 ld r12,_MSR(r1) 867 clrrdi r5,r5,4 868#endif /* CONFIG_TRACE_IRQFLAGS */ 869 /* 870 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are 871 * accessing a userspace segment (even from the kernel). We assume 872 * kernel addresses always have the high bit set. 873 */ 874 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ 875 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ 876 orc r0,r12,r0 /* MSR_PR | ~high_bit */ 877 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ 878 ori r4,r4,1 /* add _PAGE_PRESENT */ 879 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ 880 881 /* 882 * r3 contains the faulting address 883 * r4 contains the required access permissions 884 * r5 contains the trap number 885 * 886 * at return r3 = 0 for success 887 */ 888 bl .hash_page /* build HPTE if possible */ 889 cmpdi r3,0 /* see if hash_page succeeded */ 890 891BEGIN_FW_FTR_SECTION 892 /* 893 * If we had interrupts soft-enabled at the point where the 894 * DSI/ISI occurred, and an interrupt came in during hash_page, 895 * handle it now. 896 * We jump to ret_from_except_lite rather than fast_exception_return 897 * because ret_from_except_lite will check for and handle pending 898 * interrupts if necessary. 899 */ 900 beq 13f 901END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 902 903BEGIN_FW_FTR_SECTION 904 /* 905 * Here we have interrupts hard-disabled, so it is sufficient 906 * to restore paca->{soft,hard}_enable and get out. 907 */ 908 beq fast_exc_return_irq /* Return from exception on success */ 909END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 910 911 /* For a hash failure, we don't bother re-enabling interrupts */ 912 ble- 12f 913 914 /* 915 * hash_page couldn't handle it, set soft interrupt enable back 916 * to what it was before the trap. Note that .raw_local_irq_restore 917 * handles any interrupts pending at this point. 918 */ 919 ld r3,SOFTE(r1) 920 TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f) 921 bl .raw_local_irq_restore 922 b 11f 923 924/* Here we have a page fault that hash_page can't handle. */ 925handle_page_fault: 926 ENABLE_INTS 92711: ld r4,_DAR(r1) 928 ld r5,_DSISR(r1) 929 addi r3,r1,STACK_FRAME_OVERHEAD 930 bl .do_page_fault 931 cmpdi r3,0 932 beq+ 13f 933 bl .save_nvgprs 934 mr r5,r3 935 addi r3,r1,STACK_FRAME_OVERHEAD 936 lwz r4,_DAR(r1) 937 bl .bad_page_fault 938 b .ret_from_except 939 94013: b .ret_from_except_lite 941 942/* We have a page fault that hash_page could handle but HV refused 943 * the PTE insertion 944 */ 94512: bl .save_nvgprs 946 mr r5,r3 947 addi r3,r1,STACK_FRAME_OVERHEAD 948 ld r4,_DAR(r1) 949 bl .low_hash_fault 950 b .ret_from_except 951 952 /* here we have a segment miss */ 953do_ste_alloc: 954 bl .ste_allocate /* try to insert stab entry */ 955 cmpdi r3,0 956 bne- handle_page_fault 957 b fast_exception_return 958 959/* 960 * r13 points to the PACA, r9 contains the saved CR, 961 * r11 and r12 contain the saved SRR0 and SRR1. 962 * r9 - r13 are saved in paca->exslb. 963 * We assume we aren't going to take any exceptions during this procedure. 964 * We assume (DAR >> 60) == 0xc. 965 */ 966 .align 7 967_GLOBAL(do_stab_bolted) 968 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 969 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ 970 971 /* Hash to the primary group */ 972 ld r10,PACASTABVIRT(r13) 973 mfspr r11,SPRN_DAR 974 srdi r11,r11,28 975 rldimi r10,r11,7,52 /* r10 = first ste of the group */ 976 977 /* Calculate VSID */ 978 /* This is a kernel address, so protovsid = ESID */ 979 ASM_VSID_SCRAMBLE(r11, r9, 256M) 980 rldic r9,r11,12,16 /* r9 = vsid << 12 */ 981 982 /* Search the primary group for a free entry */ 9831: ld r11,0(r10) /* Test valid bit of the current ste */ 984 andi. r11,r11,0x80 985 beq 2f 986 addi r10,r10,16 987 andi. r11,r10,0x70 988 bne 1b 989 990 /* Stick for only searching the primary group for now. */ 991 /* At least for now, we use a very simple random castout scheme */ 992 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ 993 mftb r11 994 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ 995 ori r11,r11,0x10 996 997 /* r10 currently points to an ste one past the group of interest */ 998 /* make it point to the randomly selected entry */ 999 subi r10,r10,128 1000 or r10,r10,r11 /* r10 is the entry to invalidate */ 1001 1002 isync /* mark the entry invalid */ 1003 ld r11,0(r10) 1004 rldicl r11,r11,56,1 /* clear the valid bit */ 1005 rotldi r11,r11,8 1006 std r11,0(r10) 1007 sync 1008 1009 clrrdi r11,r11,28 /* Get the esid part of the ste */ 1010 slbie r11 1011 10122: std r9,8(r10) /* Store the vsid part of the ste */ 1013 eieio 1014 1015 mfspr r11,SPRN_DAR /* Get the new esid */ 1016 clrrdi r11,r11,28 /* Permits a full 32b of ESID */ 1017 ori r11,r11,0x90 /* Turn on valid and kp */ 1018 std r11,0(r10) /* Put new entry back into the stab */ 1019 1020 sync 1021 1022 /* All done -- return from exception. */ 1023 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 1024 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ 1025 1026 andi. r10,r12,MSR_RI 1027 beq- unrecov_slb 1028 1029 mtcrf 0x80,r9 /* restore CR */ 1030 1031 mfmsr r10 1032 clrrdi r10,r10,2 1033 mtmsrd r10,1 1034 1035 mtspr SPRN_SRR0,r11 1036 mtspr SPRN_SRR1,r12 1037 ld r9,PACA_EXSLB+EX_R9(r13) 1038 ld r10,PACA_EXSLB+EX_R10(r13) 1039 ld r11,PACA_EXSLB+EX_R11(r13) 1040 ld r12,PACA_EXSLB+EX_R12(r13) 1041 ld r13,PACA_EXSLB+EX_R13(r13) 1042 rfid 1043 b . /* prevent speculative execution */ 1044 1045/* 1046 * Space for CPU0's segment table. 1047 * 1048 * On iSeries, the hypervisor must fill in at least one entry before 1049 * we get control (with relocate on). The address is given to the hv 1050 * as a page number (see xLparMap below), so this must be at a 1051 * fixed address (the linker can't compute (u64)&initial_stab >> 1052 * PAGE_SHIFT). 1053 */ 1054 . = STAB0_OFFSET /* 0x6000 */ 1055 .globl initial_stab 1056initial_stab: 1057 .space 4096 1058 1059#ifdef CONFIG_PPC_PSERIES 1060/* 1061 * Data area reserved for FWNMI option. 1062 * This address (0x7000) is fixed by the RPA. 1063 */ 1064 .= 0x7000 1065 .globl fwnmi_data_area 1066fwnmi_data_area: 1067#endif /* CONFIG_PPC_PSERIES */ 1068 1069 /* iSeries does not use the FWNMI stuff, so it is safe to put 1070 * this here, even if we later allow kernels that will boot on 1071 * both pSeries and iSeries */ 1072#ifdef CONFIG_PPC_ISERIES 1073 . = LPARMAP_PHYS 1074 .globl xLparMap 1075xLparMap: 1076 .quad HvEsidsToMap /* xNumberEsids */ 1077 .quad HvRangesToMap /* xNumberRanges */ 1078 .quad STAB0_PAGE /* xSegmentTableOffs */ 1079 .zero 40 /* xRsvd */ 1080 /* xEsids (HvEsidsToMap entries of 2 quads) */ 1081 .quad PAGE_OFFSET_ESID /* xKernelEsid */ 1082 .quad PAGE_OFFSET_VSID /* xKernelVsid */ 1083 .quad VMALLOC_START_ESID /* xKernelEsid */ 1084 .quad VMALLOC_START_VSID /* xKernelVsid */ 1085 /* xRanges (HvRangesToMap entries of 3 quads) */ 1086 .quad HvPagesToMap /* xPages */ 1087 .quad 0 /* xOffset */ 1088 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */ 1089 1090#endif /* CONFIG_PPC_ISERIES */ 1091 1092#ifdef CONFIG_PPC_PSERIES 1093 . = 0x8000 1094#endif /* CONFIG_PPC_PSERIES */ 1095 1096/* 1097 * On pSeries and most other platforms, secondary processors spin 1098 * in the following code. 1099 * At entry, r3 = this processor's number (physical cpu id) 1100 */ 1101_GLOBAL(generic_secondary_smp_init) 1102 mr r24,r3 1103 1104 /* turn on 64-bit mode */ 1105 bl .enable_64b_mode 1106 1107 /* Set up a paca value for this processor. Since we have the 1108 * physical cpu id in r24, we need to search the pacas to find 1109 * which logical id maps to our physical one. 1110 */ 1111 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */ 1112 li r5,0 /* logical cpu id */ 11131: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 1114 cmpw r6,r24 /* Compare to our id */ 1115 beq 2f 1116 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 1117 addi r5,r5,1 1118 cmpwi r5,NR_CPUS 1119 blt 1b 1120 1121 mr r3,r24 /* not found, copy phys to r3 */ 1122 b .kexec_wait /* next kernel might do better */ 1123 11242: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1125 /* From now on, r24 is expected to be logical cpuid */ 1126 mr r24,r5 11273: HMT_LOW 1128 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 1129 /* start. */ 1130 sync 1131 1132#ifndef CONFIG_SMP 1133 b 3b /* Never go on non-SMP */ 1134#else 1135 cmpwi 0,r23,0 1136 beq 3b /* Loop until told to go */ 1137 1138 /* See if we need to call a cpu state restore handler */ 1139 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec) 1140 ld r23,0(r23) 1141 ld r23,CPU_SPEC_RESTORE(r23) 1142 cmpdi 0,r23,0 1143 beq 4f 1144 ld r23,0(r23) 1145 mtctr r23 1146 bctrl 1147 11484: /* Create a temp kernel stack for use before relocation is on. */ 1149 ld r1,PACAEMERGSP(r13) 1150 subi r1,r1,STACK_FRAME_OVERHEAD 1151 1152 b __secondary_start 1153#endif 1154 1155_STATIC(__mmu_off) 1156 mfmsr r3 1157 andi. r0,r3,MSR_IR|MSR_DR 1158 beqlr 1159 andc r3,r3,r0 1160 mtspr SPRN_SRR0,r4 1161 mtspr SPRN_SRR1,r3 1162 sync 1163 rfid 1164 b . /* prevent speculative execution */ 1165 1166 1167/* 1168 * Here is our main kernel entry point. We support currently 2 kind of entries 1169 * depending on the value of r5. 1170 * 1171 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 1172 * in r3...r7 1173 * 1174 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 1175 * DT block, r4 is a physical pointer to the kernel itself 1176 * 1177 */ 1178_GLOBAL(__start_initialization_multiplatform) 1179 /* 1180 * Are we booted from a PROM Of-type client-interface ? 1181 */ 1182 cmpldi cr0,r5,0 1183 beq 1f 1184 b .__boot_from_prom /* yes -> prom */ 11851: 1186 /* Save parameters */ 1187 mr r31,r3 1188 mr r30,r4 1189 1190 /* Make sure we are running in 64 bits mode */ 1191 bl .enable_64b_mode 1192 1193 /* Setup some critical 970 SPRs before switching MMU off */ 1194 mfspr r0,SPRN_PVR 1195 srwi r0,r0,16 1196 cmpwi r0,0x39 /* 970 */ 1197 beq 1f 1198 cmpwi r0,0x3c /* 970FX */ 1199 beq 1f 1200 cmpwi r0,0x44 /* 970MP */ 1201 beq 1f 1202 cmpwi r0,0x45 /* 970GX */ 1203 bne 2f 12041: bl .__cpu_preinit_ppc970 12052: 1206 1207 /* Switch off MMU if not already */ 1208 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE) 1209 add r4,r4,r30 1210 bl .__mmu_off 1211 b .__after_prom_start 1212 1213_INIT_STATIC(__boot_from_prom) 1214 /* Save parameters */ 1215 mr r31,r3 1216 mr r30,r4 1217 mr r29,r5 1218 mr r28,r6 1219 mr r27,r7 1220 1221 /* 1222 * Align the stack to 16-byte boundary 1223 * Depending on the size and layout of the ELF sections in the initial 1224 * boot binary, the stack pointer will be unalignet on PowerMac 1225 */ 1226 rldicr r1,r1,0,59 1227 1228 /* Make sure we are running in 64 bits mode */ 1229 bl .enable_64b_mode 1230 1231 /* put a relocation offset into r3 */ 1232 bl .reloc_offset 1233 1234 LOAD_REG_IMMEDIATE(r2,__toc_start) 1235 addi r2,r2,0x4000 1236 addi r2,r2,0x4000 1237 1238 /* Relocate the TOC from a virt addr to a real addr */ 1239 add r2,r2,r3 1240 1241 /* Restore parameters */ 1242 mr r3,r31 1243 mr r4,r30 1244 mr r5,r29 1245 mr r6,r28 1246 mr r7,r27 1247 1248 /* Do all of the interaction with OF client interface */ 1249 bl .prom_init 1250 /* We never return */ 1251 trap 1252 1253_STATIC(__after_prom_start) 1254 1255/* 1256 * We need to run with __start at physical address PHYSICAL_START. 1257 * This will leave some code in the first 256B of 1258 * real memory, which are reserved for software use. 1259 * The remainder of the first page is loaded with the fixed 1260 * interrupt vectors. The next two pages are filled with 1261 * unknown exception placeholders. 1262 * 1263 * Note: This process overwrites the OF exception vectors. 1264 * r26 == relocation offset 1265 * r27 == KERNELBASE 1266 */ 1267 bl .reloc_offset 1268 mr r26,r3 1269 LOAD_REG_IMMEDIATE(r27, KERNELBASE) 1270 1271 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */ 1272 1273 // XXX FIXME: Use phys returned by OF (r30) 1274 add r4,r27,r26 /* source addr */ 1275 /* current address of _start */ 1276 /* i.e. where we are running */ 1277 /* the source addr */ 1278 1279 cmpdi r4,0 /* In some cases the loader may */ 1280 bne 1f 1281 b .start_here_multiplatform /* have already put us at zero */ 1282 /* so we can skip the copy. */ 12831: LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */ 1284 sub r5,r5,r27 1285 1286 li r6,0x100 /* Start offset, the first 0x100 */ 1287 /* bytes were copied earlier. */ 1288 1289 bl .copy_and_flush /* copy the first n bytes */ 1290 /* this includes the code being */ 1291 /* executed here. */ 1292 1293 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */ 1294 mtctr r0 /* that we just made/relocated */ 1295 bctr 1296 12974: LOAD_REG_IMMEDIATE(r5,klimit) 1298 add r5,r5,r26 1299 ld r5,0(r5) /* get the value of klimit */ 1300 sub r5,r5,r27 1301 bl .copy_and_flush /* copy the rest */ 1302 b .start_here_multiplatform 1303 1304/* 1305 * Copy routine used to copy the kernel to start at physical address 0 1306 * and flush and invalidate the caches as needed. 1307 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 1308 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 1309 * 1310 * Note: this routine *only* clobbers r0, r6 and lr 1311 */ 1312_GLOBAL(copy_and_flush) 1313 addi r5,r5,-8 1314 addi r6,r6,-8 13154: li r0,8 /* Use the smallest common */ 1316 /* denominator cache line */ 1317 /* size. This results in */ 1318 /* extra cache line flushes */ 1319 /* but operation is correct. */ 1320 /* Can't get cache line size */ 1321 /* from NACA as it is being */ 1322 /* moved too. */ 1323 1324 mtctr r0 /* put # words/line in ctr */ 13253: addi r6,r6,8 /* copy a cache line */ 1326 ldx r0,r6,r4 1327 stdx r0,r6,r3 1328 bdnz 3b 1329 dcbst r6,r3 /* write it to memory */ 1330 sync 1331 icbi r6,r3 /* flush the icache line */ 1332 cmpld 0,r6,r5 1333 blt 4b 1334 sync 1335 addi r5,r5,8 1336 addi r6,r6,8 1337 blr 1338 1339.align 8 1340copy_to_here: 1341 1342#ifdef CONFIG_SMP 1343#ifdef CONFIG_PPC_PMAC 1344/* 1345 * On PowerMac, secondary processors starts from the reset vector, which 1346 * is temporarily turned into a call to one of the functions below. 1347 */ 1348 .section ".text"; 1349 .align 2 ; 1350 1351 .globl __secondary_start_pmac_0 1352__secondary_start_pmac_0: 1353 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 1354 li r24,0 1355 b 1f 1356 li r24,1 1357 b 1f 1358 li r24,2 1359 b 1f 1360 li r24,3 13611: 1362 1363_GLOBAL(pmac_secondary_start) 1364 /* turn on 64-bit mode */ 1365 bl .enable_64b_mode 1366 1367 /* Copy some CPU settings from CPU 0 */ 1368 bl .__restore_cpu_ppc970 1369 1370 /* pSeries do that early though I don't think we really need it */ 1371 mfmsr r3 1372 ori r3,r3,MSR_RI 1373 mtmsrd r3 /* RI on */ 1374 1375 /* Set up a paca value for this processor. */ 1376 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ 1377 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 1378 add r13,r13,r4 /* for this processor. */ 1379 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1380 1381 /* Create a temp kernel stack for use before relocation is on. */ 1382 ld r1,PACAEMERGSP(r13) 1383 subi r1,r1,STACK_FRAME_OVERHEAD 1384 1385 b __secondary_start 1386 1387#endif /* CONFIG_PPC_PMAC */ 1388 1389/* 1390 * This function is called after the master CPU has released the 1391 * secondary processors. The execution environment is relocation off. 1392 * The paca for this processor has the following fields initialized at 1393 * this point: 1394 * 1. Processor number 1395 * 2. Segment table pointer (virtual address) 1396 * On entry the following are set: 1397 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 1398 * r24 = cpu# (in Linux terms) 1399 * r13 = paca virtual address 1400 * SPRG3 = paca virtual address 1401 */ 1402 .globl __secondary_start 1403__secondary_start: 1404 /* Set thread priority to MEDIUM */ 1405 HMT_MEDIUM 1406 1407 /* Load TOC */ 1408 ld r2,PACATOC(r13) 1409 1410 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 1411 bl .early_setup_secondary 1412 1413 /* Initialize the kernel stack. Just a repeat for iSeries. */ 1414 LOAD_REG_ADDR(r3, current_set) 1415 sldi r28,r24,3 /* get current_set[cpu#] */ 1416 ldx r1,r3,r28 1417 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1418 std r1,PACAKSAVE(r13) 1419 1420 /* Clear backchain so we get nice backtraces */ 1421 li r7,0 1422 mtlr r7 1423 1424 /* enable MMU and jump to start_secondary */ 1425 LOAD_REG_ADDR(r3, .start_secondary_prolog) 1426 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 1427#ifdef CONFIG_PPC_ISERIES 1428BEGIN_FW_FTR_SECTION 1429 ori r4,r4,MSR_EE 1430 li r8,1 1431 stb r8,PACAHARDIRQEN(r13) 1432END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1433#endif 1434BEGIN_FW_FTR_SECTION 1435 stb r7,PACAHARDIRQEN(r13) 1436END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1437 stb r7,PACASOFTIRQEN(r13) 1438 1439 mtspr SPRN_SRR0,r3 1440 mtspr SPRN_SRR1,r4 1441 rfid 1442 b . /* prevent speculative execution */ 1443 1444/* 1445 * Running with relocation on at this point. All we want to do is 1446 * zero the stack back-chain pointer before going into C code. 1447 */ 1448_GLOBAL(start_secondary_prolog) 1449 li r3,0 1450 std r3,0(r1) /* Zero the stack frame pointer */ 1451 bl .start_secondary 1452 b . 1453#endif 1454 1455/* 1456 * This subroutine clobbers r11 and r12 1457 */ 1458_GLOBAL(enable_64b_mode) 1459 mfmsr r11 /* grab the current MSR */ 1460 li r12,1 1461 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) 1462 or r11,r11,r12 1463 li r12,1 1464 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) 1465 or r11,r11,r12 1466 mtmsrd r11 1467 isync 1468 blr 1469 1470/* 1471 * This is where the main kernel code starts. 1472 */ 1473_INIT_STATIC(start_here_multiplatform) 1474 /* get a new offset, now that the kernel has moved. */ 1475 bl .reloc_offset 1476 mr r26,r3 1477 1478 /* Clear out the BSS. It may have been done in prom_init, 1479 * already but that's irrelevant since prom_init will soon 1480 * be detached from the kernel completely. Besides, we need 1481 * to clear it now for kexec-style entry. 1482 */ 1483 LOAD_REG_IMMEDIATE(r11,__bss_stop) 1484 LOAD_REG_IMMEDIATE(r8,__bss_start) 1485 sub r11,r11,r8 /* bss size */ 1486 addi r11,r11,7 /* round up to an even double word */ 1487 rldicl. r11,r11,61,3 /* shift right by 3 */ 1488 beq 4f 1489 addi r8,r8,-8 1490 li r0,0 1491 mtctr r11 /* zero this many doublewords */ 14923: stdu r0,8(r8) 1493 bdnz 3b 14944: 1495 1496 mfmsr r6 1497 ori r6,r6,MSR_RI 1498 mtmsrd r6 /* RI on */ 1499 1500 /* The following gets the stack and TOC set up with the regs */ 1501 /* pointing to the real addr of the kernel stack. This is */ 1502 /* all done to support the C function call below which sets */ 1503 /* up the htab. This is done because we have relocated the */ 1504 /* kernel but are still running in real mode. */ 1505 1506 LOAD_REG_IMMEDIATE(r3,init_thread_union) 1507 add r3,r3,r26 1508 1509 /* set up a stack pointer (physical address) */ 1510 addi r1,r3,THREAD_SIZE 1511 li r0,0 1512 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1513 1514 /* set up the TOC (physical address) */ 1515 LOAD_REG_IMMEDIATE(r2,__toc_start) 1516 addi r2,r2,0x4000 1517 addi r2,r2,0x4000 1518 add r2,r2,r26 1519 1520 /* Do very early kernel initializations, including initial hash table, 1521 * stab and slb setup before we turn on relocation. */ 1522 1523 /* Restore parameters passed from prom_init/kexec */ 1524 mr r3,r31 1525 bl .early_setup 1526 1527 LOAD_REG_IMMEDIATE(r3, .start_here_common) 1528 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 1529 mtspr SPRN_SRR0,r3 1530 mtspr SPRN_SRR1,r4 1531 rfid 1532 b . /* prevent speculative execution */ 1533 1534 /* This is where all platforms converge execution */ 1535_INIT_GLOBAL(start_here_common) 1536 /* relocation is on at this point */ 1537 1538 /* The following code sets up the SP and TOC now that we are */ 1539 /* running with translation enabled. */ 1540 1541 LOAD_REG_IMMEDIATE(r3,init_thread_union) 1542 1543 /* set up the stack */ 1544 addi r1,r3,THREAD_SIZE 1545 li r0,0 1546 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1547 1548 /* Load the TOC */ 1549 ld r2,PACATOC(r13) 1550 std r1,PACAKSAVE(r13) 1551 1552 bl .setup_system 1553 1554 /* Load up the kernel context */ 15555: 1556 li r5,0 1557 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ 1558#ifdef CONFIG_PPC_ISERIES 1559BEGIN_FW_FTR_SECTION 1560 mfmsr r5 1561 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/ 1562 mtmsrd r5 1563 li r5,1 1564END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1565#endif 1566 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */ 1567 1568 bl .start_kernel 1569 1570 /* Not reached */ 1571 BUG_OPCODE 1572 1573/* 1574 * We put a few things here that have to be page-aligned. 1575 * This stuff goes at the beginning of the bss, which is page-aligned. 1576 */ 1577 .section ".bss" 1578 1579 .align PAGE_SHIFT 1580 1581 .globl empty_zero_page 1582empty_zero_page: 1583 .space PAGE_SIZE 1584 1585 .globl swapper_pg_dir 1586swapper_pg_dir: 1587 .space PGD_TABLE_SIZE 1588