1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the entry point for the 64-bit kernel along 16 * with some early initialization code common to all 64-bit powerpc 17 * variants. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 25#include <linux/threads.h> 26#include <asm/reg.h> 27#include <asm/page.h> 28#include <asm/mmu.h> 29#include <asm/ppc_asm.h> 30#include <asm/asm-offsets.h> 31#include <asm/bug.h> 32#include <asm/cputable.h> 33#include <asm/setup.h> 34#include <asm/hvcall.h> 35#include <asm/thread_info.h> 36#include <asm/firmware.h> 37#include <asm/page_64.h> 38#include <asm/irqflags.h> 39#include <asm/kvm_book3s_asm.h> 40#include <asm/ptrace.h> 41#include <asm/hw_irq.h> 42 43/* The physical memory is laid out such that the secondary processor 44 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 45 * using the layout described in exceptions-64s.S 46 */ 47 48/* 49 * Entering into this code we make the following assumptions: 50 * 51 * For pSeries or server processors: 52 * 1. The MMU is off & open firmware is running in real mode. 53 * 2. The kernel is entered at __start 54 * -or- For OPAL entry: 55 * 1. The MMU is off, processor in HV mode, primary CPU enters at 0 56 * with device-tree in gpr3. We also get OPAL base in r8 and 57 * entry in r9 for debugging purposes 58 * 2. Secondary processors enter at 0x60 with PIR in gpr3 59 * 60 * For Book3E processors: 61 * 1. The MMU is on running in AS0 in a state defined in ePAPR 62 * 2. The kernel is entered at __start 63 */ 64 65 .text 66 .globl _stext 67_stext: 68_GLOBAL(__start) 69 /* NOP this out unconditionally */ 70BEGIN_FTR_SECTION 71 FIXUP_ENDIAN 72 b .__start_initialization_multiplatform 73END_FTR_SECTION(0, 1) 74 75 /* Catch branch to 0 in real mode */ 76 trap 77 78 /* Secondary processors spin on this value until it becomes nonzero. 79 * When it does it contains the real address of the descriptor 80 * of the function that the cpu should jump to to continue 81 * initialization. 82 */ 83 .globl __secondary_hold_spinloop 84__secondary_hold_spinloop: 85 .llong 0x0 86 87 /* Secondary processors write this value with their cpu # */ 88 /* after they enter the spin loop immediately below. */ 89 .globl __secondary_hold_acknowledge 90__secondary_hold_acknowledge: 91 .llong 0x0 92 93#ifdef CONFIG_RELOCATABLE 94 /* This flag is set to 1 by a loader if the kernel should run 95 * at the loaded address instead of the linked address. This 96 * is used by kexec-tools to keep the the kdump kernel in the 97 * crash_kernel region. The loader is responsible for 98 * observing the alignment requirement. 99 */ 100 /* Do not move this variable as kexec-tools knows about it. */ 101 . = 0x5c 102 .globl __run_at_load 103__run_at_load: 104 .long 0x72756e30 /* "run0" -- relocate to 0 by default */ 105#endif 106 107 . = 0x60 108/* 109 * The following code is used to hold secondary processors 110 * in a spin loop after they have entered the kernel, but 111 * before the bulk of the kernel has been relocated. This code 112 * is relocated to physical address 0x60 before prom_init is run. 113 * All of it must fit below the first exception vector at 0x100. 114 * Use .globl here not _GLOBAL because we want __secondary_hold 115 * to be the actual text address, not a descriptor. 116 */ 117 .globl __secondary_hold 118__secondary_hold: 119 FIXUP_ENDIAN 120#ifndef CONFIG_PPC_BOOK3E 121 mfmsr r24 122 ori r24,r24,MSR_RI 123 mtmsrd r24 /* RI on */ 124#endif 125 /* Grab our physical cpu number */ 126 mr r24,r3 127 /* stash r4 for book3e */ 128 mr r25,r4 129 130 /* Tell the master cpu we're here */ 131 /* Relocation is off & we are located at an address less */ 132 /* than 0x100, so only need to grab low order offset. */ 133 std r24,__secondary_hold_acknowledge-_stext(0) 134 sync 135 136 li r26,0 137#ifdef CONFIG_PPC_BOOK3E 138 tovirt(r26,r26) 139#endif 140 /* All secondary cpus wait here until told to start. */ 141100: ld r4,__secondary_hold_spinloop-_stext(r26) 142 cmpdi 0,r4,0 143 beq 100b 144 145#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 146#ifdef CONFIG_PPC_BOOK3E 147 tovirt(r4,r4) 148#endif 149 ld r4,0(r4) /* deref function descriptor */ 150 mtctr r4 151 mr r3,r24 152 /* 153 * it may be the case that other platforms have r4 right to 154 * begin with, this gives us some safety in case it is not 155 */ 156#ifdef CONFIG_PPC_BOOK3E 157 mr r4,r25 158#else 159 li r4,0 160#endif 161 /* Make sure that patched code is visible */ 162 isync 163 bctr 164#else 165 BUG_OPCODE 166#endif 167 168/* This value is used to mark exception frames on the stack. */ 169 .section ".toc","aw" 170exception_marker: 171 .tc ID_72656773_68657265[TC],0x7265677368657265 172 .text 173 174/* 175 * On server, we include the exception vectors code here as it 176 * relies on absolute addressing which is only possible within 177 * this compilation unit 178 */ 179#ifdef CONFIG_PPC_BOOK3S 180#include "exceptions-64s.S" 181#endif 182 183_GLOBAL(generic_secondary_thread_init) 184 mr r24,r3 185 186 /* turn on 64-bit mode */ 187 bl .enable_64b_mode 188 189 /* get a valid TOC pointer, wherever we're mapped at */ 190 bl .relative_toc 191 tovirt(r2,r2) 192 193#ifdef CONFIG_PPC_BOOK3E 194 /* Book3E initialization */ 195 mr r3,r24 196 bl .book3e_secondary_thread_init 197#endif 198 b generic_secondary_common_init 199 200/* 201 * On pSeries and most other platforms, secondary processors spin 202 * in the following code. 203 * At entry, r3 = this processor's number (physical cpu id) 204 * 205 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 206 * this core already exists (setup via some other mechanism such 207 * as SCOM before entry). 208 */ 209_GLOBAL(generic_secondary_smp_init) 210 FIXUP_ENDIAN 211 mr r24,r3 212 mr r25,r4 213 214 /* turn on 64-bit mode */ 215 bl .enable_64b_mode 216 217 /* get a valid TOC pointer, wherever we're mapped at */ 218 bl .relative_toc 219 tovirt(r2,r2) 220 221#ifdef CONFIG_PPC_BOOK3E 222 /* Book3E initialization */ 223 mr r3,r24 224 mr r4,r25 225 bl .book3e_secondary_core_init 226#endif 227 228generic_secondary_common_init: 229 /* Set up a paca value for this processor. Since we have the 230 * physical cpu id in r24, we need to search the pacas to find 231 * which logical id maps to our physical one. 232 */ 233 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ 234 ld r13,0(r13) /* Get base vaddr of paca array */ 235#ifndef CONFIG_SMP 236 addi r13,r13,PACA_SIZE /* know r13 if used accidentally */ 237 b .kexec_wait /* wait for next kernel if !SMP */ 238#else 239 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 240 lwz r7,0(r7) /* also the max paca allocated */ 241 li r5,0 /* logical cpu id */ 2421: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 243 cmpw r6,r24 /* Compare to our id */ 244 beq 2f 245 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 246 addi r5,r5,1 247 cmpw r5,r7 /* Check if more pacas exist */ 248 blt 1b 249 250 mr r3,r24 /* not found, copy phys to r3 */ 251 b .kexec_wait /* next kernel might do better */ 252 2532: SET_PACA(r13) 254#ifdef CONFIG_PPC_BOOK3E 255 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 256 mtspr SPRN_SPRG_TLB_EXFRAME,r12 257#endif 258 259 /* From now on, r24 is expected to be logical cpuid */ 260 mr r24,r5 261 262 /* See if we need to call a cpu state restore handler */ 263 LOAD_REG_ADDR(r23, cur_cpu_spec) 264 ld r23,0(r23) 265 ld r23,CPU_SPEC_RESTORE(r23) 266 cmpdi 0,r23,0 267 beq 3f 268 ld r23,0(r23) 269 mtctr r23 270 bctrl 271 2723: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 273 lwarx r4,0,r3 274 subi r4,r4,1 275 stwcx. r4,0,r3 276 bne 3b 277 isync 278 2794: HMT_LOW 280 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 281 /* start. */ 282 cmpwi 0,r23,0 283 beq 4b /* Loop until told to go */ 284 285 sync /* order paca.run and cur_cpu_spec */ 286 isync /* In case code patching happened */ 287 288 /* Create a temp kernel stack for use before relocation is on. */ 289 ld r1,PACAEMERGSP(r13) 290 subi r1,r1,STACK_FRAME_OVERHEAD 291 292 b __secondary_start 293#endif /* SMP */ 294 295/* 296 * Turn the MMU off. 297 * Assumes we're mapped EA == RA if the MMU is on. 298 */ 299#ifdef CONFIG_PPC_BOOK3S 300_STATIC(__mmu_off) 301 mfmsr r3 302 andi. r0,r3,MSR_IR|MSR_DR 303 beqlr 304 mflr r4 305 andc r3,r3,r0 306 mtspr SPRN_SRR0,r4 307 mtspr SPRN_SRR1,r3 308 sync 309 rfid 310 b . /* prevent speculative execution */ 311#endif 312 313 314/* 315 * Here is our main kernel entry point. We support currently 2 kind of entries 316 * depending on the value of r5. 317 * 318 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 319 * in r3...r7 320 * 321 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 322 * DT block, r4 is a physical pointer to the kernel itself 323 * 324 */ 325_GLOBAL(__start_initialization_multiplatform) 326 /* Make sure we are running in 64 bits mode */ 327 bl .enable_64b_mode 328 329 /* Get TOC pointer (current runtime address) */ 330 bl .relative_toc 331 332 /* find out where we are now */ 333 bcl 20,31,$+4 3340: mflr r26 /* r26 = runtime addr here */ 335 addis r26,r26,(_stext - 0b)@ha 336 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 337 338 /* 339 * Are we booted from a PROM Of-type client-interface ? 340 */ 341 cmpldi cr0,r5,0 342 beq 1f 343 b .__boot_from_prom /* yes -> prom */ 3441: 345 /* Save parameters */ 346 mr r31,r3 347 mr r30,r4 348#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 349 /* Save OPAL entry */ 350 mr r28,r8 351 mr r29,r9 352#endif 353 354#ifdef CONFIG_PPC_BOOK3E 355 bl .start_initialization_book3e 356 b .__after_prom_start 357#else 358 /* Setup some critical 970 SPRs before switching MMU off */ 359 mfspr r0,SPRN_PVR 360 srwi r0,r0,16 361 cmpwi r0,0x39 /* 970 */ 362 beq 1f 363 cmpwi r0,0x3c /* 970FX */ 364 beq 1f 365 cmpwi r0,0x44 /* 970MP */ 366 beq 1f 367 cmpwi r0,0x45 /* 970GX */ 368 bne 2f 3691: bl .__cpu_preinit_ppc970 3702: 371 372 /* Switch off MMU if not already off */ 373 bl .__mmu_off 374 b .__after_prom_start 375#endif /* CONFIG_PPC_BOOK3E */ 376 377_INIT_STATIC(__boot_from_prom) 378#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 379 /* Save parameters */ 380 mr r31,r3 381 mr r30,r4 382 mr r29,r5 383 mr r28,r6 384 mr r27,r7 385 386 /* 387 * Align the stack to 16-byte boundary 388 * Depending on the size and layout of the ELF sections in the initial 389 * boot binary, the stack pointer may be unaligned on PowerMac 390 */ 391 rldicr r1,r1,0,59 392 393#ifdef CONFIG_RELOCATABLE 394 /* Relocate code for where we are now */ 395 mr r3,r26 396 bl .relocate 397#endif 398 399 /* Restore parameters */ 400 mr r3,r31 401 mr r4,r30 402 mr r5,r29 403 mr r6,r28 404 mr r7,r27 405 406 /* Do all of the interaction with OF client interface */ 407 mr r8,r26 408 bl .prom_init 409#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 410 411 /* We never return. We also hit that trap if trying to boot 412 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 413 trap 414 415_STATIC(__after_prom_start) 416#ifdef CONFIG_RELOCATABLE 417 /* process relocations for the final address of the kernel */ 418 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 419 sldi r25,r25,32 420 lwz r7,__run_at_load-_stext(r26) 421 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 422 bne 1f 423 add r25,r25,r26 4241: mr r3,r25 425 bl .relocate 426#endif 427 428/* 429 * We need to run with _stext at physical address PHYSICAL_START. 430 * This will leave some code in the first 256B of 431 * real memory, which are reserved for software use. 432 * 433 * Note: This process overwrites the OF exception vectors. 434 */ 435 li r3,0 /* target addr */ 436#ifdef CONFIG_PPC_BOOK3E 437 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 438#endif 439 mr. r4,r26 /* In some cases the loader may */ 440 beq 9f /* have already put us at zero */ 441 li r6,0x100 /* Start offset, the first 0x100 */ 442 /* bytes were copied earlier. */ 443#ifdef CONFIG_PPC_BOOK3E 444 tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ 445#endif 446 447#ifdef CONFIG_RELOCATABLE 448/* 449 * Check if the kernel has to be running as relocatable kernel based on the 450 * variable __run_at_load, if it is set the kernel is treated as relocatable 451 * kernel, otherwise it will be moved to PHYSICAL_START 452 */ 453 lwz r7,__run_at_load-_stext(r26) 454 cmplwi cr0,r7,1 455 bne 3f 456 457 /* just copy interrupts */ 458 LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext) 459 b 5f 4603: 461#endif 462 lis r5,(copy_to_here - _stext)@ha 463 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ 464 465 bl .copy_and_flush /* copy the first n bytes */ 466 /* this includes the code being */ 467 /* executed here. */ 468 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ 469 addi r8,r8,(4f - _stext)@l /* that we just made */ 470 mtctr r8 471 bctr 472 473p_end: .llong _end - _stext 474 4754: /* Now copy the rest of the kernel up to _end */ 476 addis r5,r26,(p_end - _stext)@ha 477 ld r5,(p_end - _stext)@l(r5) /* get _end */ 4785: bl .copy_and_flush /* copy the rest */ 479 4809: b .start_here_multiplatform 481 482/* 483 * Copy routine used to copy the kernel to start at physical address 0 484 * and flush and invalidate the caches as needed. 485 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 486 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 487 * 488 * Note: this routine *only* clobbers r0, r6 and lr 489 */ 490_GLOBAL(copy_and_flush) 491 addi r5,r5,-8 492 addi r6,r6,-8 4934: li r0,8 /* Use the smallest common */ 494 /* denominator cache line */ 495 /* size. This results in */ 496 /* extra cache line flushes */ 497 /* but operation is correct. */ 498 /* Can't get cache line size */ 499 /* from NACA as it is being */ 500 /* moved too. */ 501 502 mtctr r0 /* put # words/line in ctr */ 5033: addi r6,r6,8 /* copy a cache line */ 504 ldx r0,r6,r4 505 stdx r0,r6,r3 506 bdnz 3b 507 dcbst r6,r3 /* write it to memory */ 508 sync 509 icbi r6,r3 /* flush the icache line */ 510 cmpld 0,r6,r5 511 blt 4b 512 sync 513 addi r5,r5,8 514 addi r6,r6,8 515 isync 516 blr 517 518.align 8 519copy_to_here: 520 521#ifdef CONFIG_SMP 522#ifdef CONFIG_PPC_PMAC 523/* 524 * On PowerMac, secondary processors starts from the reset vector, which 525 * is temporarily turned into a call to one of the functions below. 526 */ 527 .section ".text"; 528 .align 2 ; 529 530 .globl __secondary_start_pmac_0 531__secondary_start_pmac_0: 532 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 533 li r24,0 534 b 1f 535 li r24,1 536 b 1f 537 li r24,2 538 b 1f 539 li r24,3 5401: 541 542_GLOBAL(pmac_secondary_start) 543 /* turn on 64-bit mode */ 544 bl .enable_64b_mode 545 546 li r0,0 547 mfspr r3,SPRN_HID4 548 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 549 sync 550 mtspr SPRN_HID4,r3 551 isync 552 sync 553 slbia 554 555 /* get TOC pointer (real address) */ 556 bl .relative_toc 557 tovirt(r2,r2) 558 559 /* Copy some CPU settings from CPU 0 */ 560 bl .__restore_cpu_ppc970 561 562 /* pSeries do that early though I don't think we really need it */ 563 mfmsr r3 564 ori r3,r3,MSR_RI 565 mtmsrd r3 /* RI on */ 566 567 /* Set up a paca value for this processor. */ 568 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ 569 ld r4,0(r4) /* Get base vaddr of paca array */ 570 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 571 add r13,r13,r4 /* for this processor. */ 572 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 573 574 /* Mark interrupts soft and hard disabled (they might be enabled 575 * in the PACA when doing hotplug) 576 */ 577 li r0,0 578 stb r0,PACASOFTIRQEN(r13) 579 li r0,PACA_IRQ_HARD_DIS 580 stb r0,PACAIRQHAPPENED(r13) 581 582 /* Create a temp kernel stack for use before relocation is on. */ 583 ld r1,PACAEMERGSP(r13) 584 subi r1,r1,STACK_FRAME_OVERHEAD 585 586 b __secondary_start 587 588#endif /* CONFIG_PPC_PMAC */ 589 590/* 591 * This function is called after the master CPU has released the 592 * secondary processors. The execution environment is relocation off. 593 * The paca for this processor has the following fields initialized at 594 * this point: 595 * 1. Processor number 596 * 2. Segment table pointer (virtual address) 597 * On entry the following are set: 598 * r1 = stack pointer (real addr of temp stack) 599 * r24 = cpu# (in Linux terms) 600 * r13 = paca virtual address 601 * SPRG_PACA = paca virtual address 602 */ 603 .section ".text"; 604 .align 2 ; 605 606 .globl __secondary_start 607__secondary_start: 608 /* Set thread priority to MEDIUM */ 609 HMT_MEDIUM 610 611 /* Initialize the kernel stack */ 612 LOAD_REG_ADDR(r3, current_set) 613 sldi r28,r24,3 /* get current_set[cpu#] */ 614 ldx r14,r3,r28 615 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD 616 std r14,PACAKSAVE(r13) 617 618 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 619 bl .early_setup_secondary 620 621 /* 622 * setup the new stack pointer, but *don't* use this until 623 * translation is on. 624 */ 625 mr r1, r14 626 627 /* Clear backchain so we get nice backtraces */ 628 li r7,0 629 mtlr r7 630 631 /* Mark interrupts soft and hard disabled (they might be enabled 632 * in the PACA when doing hotplug) 633 */ 634 stb r7,PACASOFTIRQEN(r13) 635 li r0,PACA_IRQ_HARD_DIS 636 stb r0,PACAIRQHAPPENED(r13) 637 638 /* enable MMU and jump to start_secondary */ 639 LOAD_REG_ADDR(r3, .start_secondary_prolog) 640 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 641 642 mtspr SPRN_SRR0,r3 643 mtspr SPRN_SRR1,r4 644 RFI 645 b . /* prevent speculative execution */ 646 647/* 648 * Running with relocation on at this point. All we want to do is 649 * zero the stack back-chain pointer and get the TOC virtual address 650 * before going into C code. 651 */ 652_GLOBAL(start_secondary_prolog) 653 ld r2,PACATOC(r13) 654 li r3,0 655 std r3,0(r1) /* Zero the stack frame pointer */ 656 bl .start_secondary 657 b . 658/* 659 * Reset stack pointer and call start_secondary 660 * to continue with online operation when woken up 661 * from cede in cpu offline. 662 */ 663_GLOBAL(start_secondary_resume) 664 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 665 li r3,0 666 std r3,0(r1) /* Zero the stack frame pointer */ 667 bl .start_secondary 668 b . 669#endif 670 671/* 672 * This subroutine clobbers r11 and r12 673 */ 674_GLOBAL(enable_64b_mode) 675 mfmsr r11 /* grab the current MSR */ 676#ifdef CONFIG_PPC_BOOK3E 677 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 678 mtmsr r11 679#else /* CONFIG_PPC_BOOK3E */ 680 li r12,(MSR_64BIT | MSR_ISF)@highest 681 sldi r12,r12,48 682 or r11,r11,r12 683 mtmsrd r11 684 isync 685#endif 686 blr 687 688/* 689 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 690 * by the toolchain). It computes the correct value for wherever we 691 * are running at the moment, using position-independent code. 692 * 693 * Note: The compiler constructs pointers using offsets from the 694 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 695 * the MMU is on we need our TOC to be a virtual address otherwise 696 * these pointers will be real addresses which may get stored and 697 * accessed later with the MMU on. We use tovirt() at the call 698 * sites to handle this. 699 */ 700_GLOBAL(relative_toc) 701 mflr r0 702 bcl 20,31,$+4 7030: mflr r11 704 ld r2,(p_toc - 0b)(r11) 705 add r2,r2,r11 706 mtlr r0 707 blr 708 709.balign 8 710p_toc: .llong __toc_start + 0x8000 - 0b 711 712/* 713 * This is where the main kernel code starts. 714 */ 715_INIT_STATIC(start_here_multiplatform) 716 /* set up the TOC */ 717 bl .relative_toc 718 tovirt(r2,r2) 719 720 /* Clear out the BSS. It may have been done in prom_init, 721 * already but that's irrelevant since prom_init will soon 722 * be detached from the kernel completely. Besides, we need 723 * to clear it now for kexec-style entry. 724 */ 725 LOAD_REG_ADDR(r11,__bss_stop) 726 LOAD_REG_ADDR(r8,__bss_start) 727 sub r11,r11,r8 /* bss size */ 728 addi r11,r11,7 /* round up to an even double word */ 729 srdi. r11,r11,3 /* shift right by 3 */ 730 beq 4f 731 addi r8,r8,-8 732 li r0,0 733 mtctr r11 /* zero this many doublewords */ 7343: stdu r0,8(r8) 735 bdnz 3b 7364: 737 738#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 739 /* Setup OPAL entry */ 740 LOAD_REG_ADDR(r11, opal) 741 std r28,0(r11); 742 std r29,8(r11); 743#endif 744 745#ifndef CONFIG_PPC_BOOK3E 746 mfmsr r6 747 ori r6,r6,MSR_RI 748 mtmsrd r6 /* RI on */ 749#endif 750 751#ifdef CONFIG_RELOCATABLE 752 /* Save the physical address we're running at in kernstart_addr */ 753 LOAD_REG_ADDR(r4, kernstart_addr) 754 clrldi r0,r25,2 755 std r0,0(r4) 756#endif 757 758 /* The following gets the stack set up with the regs */ 759 /* pointing to the real addr of the kernel stack. This is */ 760 /* all done to support the C function call below which sets */ 761 /* up the htab. This is done because we have relocated the */ 762 /* kernel but are still running in real mode. */ 763 764 LOAD_REG_ADDR(r3,init_thread_union) 765 766 /* set up a stack pointer */ 767 addi r1,r3,THREAD_SIZE 768 li r0,0 769 stdu r0,-STACK_FRAME_OVERHEAD(r1) 770 771 /* Do very early kernel initializations, including initial hash table, 772 * stab and slb setup before we turn on relocation. */ 773 774 /* Restore parameters passed from prom_init/kexec */ 775 mr r3,r31 776 bl .early_setup /* also sets r13 and SPRG_PACA */ 777 778 LOAD_REG_ADDR(r3, .start_here_common) 779 ld r4,PACAKMSR(r13) 780 mtspr SPRN_SRR0,r3 781 mtspr SPRN_SRR1,r4 782 RFI 783 b . /* prevent speculative execution */ 784 785 /* This is where all platforms converge execution */ 786_INIT_GLOBAL(start_here_common) 787 /* relocation is on at this point */ 788 std r1,PACAKSAVE(r13) 789 790 /* Load the TOC (virtual address) */ 791 ld r2,PACATOC(r13) 792 793 /* Do more system initializations in virtual mode */ 794 bl .setup_system 795 796 /* Mark interrupts soft and hard disabled (they might be enabled 797 * in the PACA when doing hotplug) 798 */ 799 li r0,0 800 stb r0,PACASOFTIRQEN(r13) 801 li r0,PACA_IRQ_HARD_DIS 802 stb r0,PACAIRQHAPPENED(r13) 803 804 /* Generic kernel entry */ 805 bl .start_kernel 806 807 /* Not reached */ 808 BUG_OPCODE 809 810/* 811 * We put a few things here that have to be page-aligned. 812 * This stuff goes at the beginning of the bss, which is page-aligned. 813 */ 814 .section ".bss" 815 816 .align PAGE_SHIFT 817 818 .globl empty_zero_page 819empty_zero_page: 820 .space PAGE_SIZE 821 822 .globl swapper_pg_dir 823swapper_pg_dir: 824 .space PGD_TABLE_SIZE 825