114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * PowerPC version 314cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 414cf11afSPaul Mackerras * 514cf11afSPaul Mackerras * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 614cf11afSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 714cf11afSPaul Mackerras * Adapted for Power Macintosh by Paul Mackerras. 814cf11afSPaul Mackerras * Low-level exception handlers and MMU support 914cf11afSPaul Mackerras * rewritten by Paul Mackerras. 1014cf11afSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 1114cf11afSPaul Mackerras * 1214cf11afSPaul Mackerras * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 1314cf11afSPaul Mackerras * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 1414cf11afSPaul Mackerras * 1514cf11afSPaul Mackerras * This file contains the low-level support and setup for the 1614cf11afSPaul Mackerras * PowerPC-64 platform, including trap and interrupt dispatch. 1714cf11afSPaul Mackerras * 1814cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1914cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 2014cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 2114cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 2214cf11afSPaul Mackerras */ 2314cf11afSPaul Mackerras 2414cf11afSPaul Mackerras#include <linux/threads.h> 25b5bbeb23SPaul Mackerras#include <asm/reg.h> 2614cf11afSPaul Mackerras#include <asm/page.h> 2714cf11afSPaul Mackerras#include <asm/mmu.h> 2814cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2914cf11afSPaul Mackerras#include <asm/asm-offsets.h> 3014cf11afSPaul Mackerras#include <asm/bug.h> 3114cf11afSPaul Mackerras#include <asm/cputable.h> 3214cf11afSPaul Mackerras#include <asm/setup.h> 3314cf11afSPaul Mackerras#include <asm/hvcall.h> 34c43a55ffSKelly Daly#include <asm/iseries/lpar_map.h> 356cb7bfebSDavid Gibson#include <asm/thread_info.h> 363f639ee8SStephen Rothwell#include <asm/firmware.h> 3714cf11afSPaul Mackerras 3814cf11afSPaul Mackerras#define DO_SOFT_DISABLE 3914cf11afSPaul Mackerras 4014cf11afSPaul Mackerras/* 4114cf11afSPaul Mackerras * We layout physical memory as follows: 4214cf11afSPaul Mackerras * 0x0000 - 0x00ff : Secondary processor spin code 4314cf11afSPaul Mackerras * 0x0100 - 0x2fff : pSeries Interrupt prologs 4414cf11afSPaul Mackerras * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs 4514cf11afSPaul Mackerras * 0x6000 - 0x6fff : Initial (CPU0) segment table 4614cf11afSPaul Mackerras * 0x7000 - 0x7fff : FWNMI data area 4714cf11afSPaul Mackerras * 0x8000 - : Early init and support code 4814cf11afSPaul Mackerras */ 4914cf11afSPaul Mackerras 5014cf11afSPaul Mackerras/* 5114cf11afSPaul Mackerras * SPRG Usage 5214cf11afSPaul Mackerras * 5314cf11afSPaul Mackerras * Register Definition 5414cf11afSPaul Mackerras * 5514cf11afSPaul Mackerras * SPRG0 reserved for hypervisor 5614cf11afSPaul Mackerras * SPRG1 temp - used to save gpr 5714cf11afSPaul Mackerras * SPRG2 temp - used to save gpr 5814cf11afSPaul Mackerras * SPRG3 virt addr of paca 5914cf11afSPaul Mackerras */ 6014cf11afSPaul Mackerras 6114cf11afSPaul Mackerras/* 6214cf11afSPaul Mackerras * Entering into this code we make the following assumptions: 6314cf11afSPaul Mackerras * For pSeries: 6414cf11afSPaul Mackerras * 1. The MMU is off & open firmware is running in real mode. 6514cf11afSPaul Mackerras * 2. The kernel is entered at __start 6614cf11afSPaul Mackerras * 6714cf11afSPaul Mackerras * For iSeries: 6814cf11afSPaul Mackerras * 1. The MMU is on (as it always is for iSeries) 6914cf11afSPaul Mackerras * 2. The kernel is entered at system_reset_iSeries 7014cf11afSPaul Mackerras */ 7114cf11afSPaul Mackerras 7214cf11afSPaul Mackerras .text 7314cf11afSPaul Mackerras .globl _stext 7414cf11afSPaul Mackerras_stext: 7514cf11afSPaul Mackerras_GLOBAL(__start) 7614cf11afSPaul Mackerras /* NOP this out unconditionally */ 7714cf11afSPaul MackerrasBEGIN_FTR_SECTION 7814cf11afSPaul Mackerras b .__start_initialization_multiplatform 7914cf11afSPaul MackerrasEND_FTR_SECTION(0, 1) 8014cf11afSPaul Mackerras 8114cf11afSPaul Mackerras /* Catch branch to 0 in real mode */ 8214cf11afSPaul Mackerras trap 8314cf11afSPaul Mackerras 8414cf11afSPaul Mackerras /* Secondary processors spin on this value until it goes to 1. */ 8514cf11afSPaul Mackerras .globl __secondary_hold_spinloop 8614cf11afSPaul Mackerras__secondary_hold_spinloop: 8714cf11afSPaul Mackerras .llong 0x0 8814cf11afSPaul Mackerras 8914cf11afSPaul Mackerras /* Secondary processors write this value with their cpu # */ 9014cf11afSPaul Mackerras /* after they enter the spin loop immediately below. */ 9114cf11afSPaul Mackerras .globl __secondary_hold_acknowledge 9214cf11afSPaul Mackerras__secondary_hold_acknowledge: 9314cf11afSPaul Mackerras .llong 0x0 9414cf11afSPaul Mackerras 951dce0e30SMichael Ellerman#ifdef CONFIG_PPC_ISERIES 961dce0e30SMichael Ellerman /* 971dce0e30SMichael Ellerman * At offset 0x20, there is a pointer to iSeries LPAR data. 981dce0e30SMichael Ellerman * This is required by the hypervisor 991dce0e30SMichael Ellerman */ 1001dce0e30SMichael Ellerman . = 0x20 1011dce0e30SMichael Ellerman .llong hvReleaseData-KERNELBASE 1021dce0e30SMichael Ellerman#endif /* CONFIG_PPC_ISERIES */ 1031dce0e30SMichael Ellerman 10414cf11afSPaul Mackerras . = 0x60 10514cf11afSPaul Mackerras/* 10614cf11afSPaul Mackerras * The following code is used on pSeries to hold secondary processors 10714cf11afSPaul Mackerras * in a spin loop after they have been freed from OpenFirmware, but 10814cf11afSPaul Mackerras * before the bulk of the kernel has been relocated. This code 10914cf11afSPaul Mackerras * is relocated to physical address 0x60 before prom_init is run. 11014cf11afSPaul Mackerras * All of it must fit below the first exception vector at 0x100. 11114cf11afSPaul Mackerras */ 11214cf11afSPaul Mackerras_GLOBAL(__secondary_hold) 11314cf11afSPaul Mackerras mfmsr r24 11414cf11afSPaul Mackerras ori r24,r24,MSR_RI 11514cf11afSPaul Mackerras mtmsrd r24 /* RI on */ 11614cf11afSPaul Mackerras 117f1870f77SAnton Blanchard /* Grab our physical cpu number */ 11814cf11afSPaul Mackerras mr r24,r3 11914cf11afSPaul Mackerras 12014cf11afSPaul Mackerras /* Tell the master cpu we're here */ 12114cf11afSPaul Mackerras /* Relocation is off & we are located at an address less */ 12214cf11afSPaul Mackerras /* than 0x100, so only need to grab low order offset. */ 12314cf11afSPaul Mackerras std r24,__secondary_hold_acknowledge@l(0) 12414cf11afSPaul Mackerras sync 12514cf11afSPaul Mackerras 12614cf11afSPaul Mackerras /* All secondary cpus wait here until told to start. */ 12714cf11afSPaul Mackerras100: ld r4,__secondary_hold_spinloop@l(0) 12814cf11afSPaul Mackerras cmpdi 0,r4,1 12914cf11afSPaul Mackerras bne 100b 13014cf11afSPaul Mackerras 131f1870f77SAnton Blanchard#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 132f39b7a55SOlof Johansson LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init) 133758438a7SMichael Ellerman mtctr r4 13414cf11afSPaul Mackerras mr r3,r24 135758438a7SMichael Ellerman bctr 13614cf11afSPaul Mackerras#else 13714cf11afSPaul Mackerras BUG_OPCODE 13814cf11afSPaul Mackerras#endif 13914cf11afSPaul Mackerras 14014cf11afSPaul Mackerras/* This value is used to mark exception frames on the stack. */ 14114cf11afSPaul Mackerras .section ".toc","aw" 14214cf11afSPaul Mackerrasexception_marker: 14314cf11afSPaul Mackerras .tc ID_72656773_68657265[TC],0x7265677368657265 14414cf11afSPaul Mackerras .text 14514cf11afSPaul Mackerras 14614cf11afSPaul Mackerras/* 14714cf11afSPaul Mackerras * The following macros define the code that appears as 14814cf11afSPaul Mackerras * the prologue to each of the exception handlers. They 14914cf11afSPaul Mackerras * are split into two parts to allow a single kernel binary 15014cf11afSPaul Mackerras * to be used for pSeries and iSeries. 15114cf11afSPaul Mackerras * LOL. One day... - paulus 15214cf11afSPaul Mackerras */ 15314cf11afSPaul Mackerras 15414cf11afSPaul Mackerras/* 15514cf11afSPaul Mackerras * We make as much of the exception code common between native 15614cf11afSPaul Mackerras * exception handlers (including pSeries LPAR) and iSeries LPAR 15714cf11afSPaul Mackerras * implementations as possible. 15814cf11afSPaul Mackerras */ 15914cf11afSPaul Mackerras 16014cf11afSPaul Mackerras/* 16114cf11afSPaul Mackerras * This is the start of the interrupt handlers for pSeries 16214cf11afSPaul Mackerras * This code runs with relocation off. 16314cf11afSPaul Mackerras */ 16414cf11afSPaul Mackerras#define EX_R9 0 16514cf11afSPaul Mackerras#define EX_R10 8 16614cf11afSPaul Mackerras#define EX_R11 16 16714cf11afSPaul Mackerras#define EX_R12 24 16814cf11afSPaul Mackerras#define EX_R13 32 16914cf11afSPaul Mackerras#define EX_SRR0 40 17014cf11afSPaul Mackerras#define EX_DAR 48 17114cf11afSPaul Mackerras#define EX_DSISR 56 17214cf11afSPaul Mackerras#define EX_CCR 60 1733c726f8dSBenjamin Herrenschmidt#define EX_R3 64 1743c726f8dSBenjamin Herrenschmidt#define EX_LR 72 17514cf11afSPaul Mackerras 176758438a7SMichael Ellerman/* 177e58c3495SDavid Gibson * We're short on space and time in the exception prolog, so we can't 178e58c3495SDavid Gibson * use the normal SET_REG_IMMEDIATE macro. Normally we just need the 179e58c3495SDavid Gibson * low halfword of the address, but for Kdump we need the whole low 180e58c3495SDavid Gibson * word. 181758438a7SMichael Ellerman */ 182758438a7SMichael Ellerman#ifdef CONFIG_CRASH_DUMP 183758438a7SMichael Ellerman#define LOAD_HANDLER(reg, label) \ 184758438a7SMichael Ellerman oris reg,reg,(label)@h; /* virt addr of handler ... */ \ 185758438a7SMichael Ellerman ori reg,reg,(label)@l; /* .. and the rest */ 186758438a7SMichael Ellerman#else 187758438a7SMichael Ellerman#define LOAD_HANDLER(reg, label) \ 188758438a7SMichael Ellerman ori reg,reg,(label)@l; /* virt addr of handler ... */ 189758438a7SMichael Ellerman#endif 190758438a7SMichael Ellerman 1919fc0a92cSOlaf Hering/* 1929fc0a92cSOlaf Hering * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode. 1939fc0a92cSOlaf Hering * The firmware calls the registered system_reset_fwnmi and 1949fc0a92cSOlaf Hering * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run 1959fc0a92cSOlaf Hering * a 32bit application at the time of the event. 1969fc0a92cSOlaf Hering * This firmware bug is present on POWER4 and JS20. 1979fc0a92cSOlaf Hering */ 1989fc0a92cSOlaf Hering#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \ 1999fc0a92cSOlaf Hering mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 2009fc0a92cSOlaf Hering std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 2019fc0a92cSOlaf Hering std r10,area+EX_R10(r13); \ 2029fc0a92cSOlaf Hering std r11,area+EX_R11(r13); \ 2039fc0a92cSOlaf Hering std r12,area+EX_R12(r13); \ 2049fc0a92cSOlaf Hering mfspr r9,SPRN_SPRG1; \ 2059fc0a92cSOlaf Hering std r9,area+EX_R13(r13); \ 2069fc0a92cSOlaf Hering mfcr r9; \ 2079fc0a92cSOlaf Hering clrrdi r12,r13,32; /* get high part of &label */ \ 2089fc0a92cSOlaf Hering mfmsr r10; \ 2099fc0a92cSOlaf Hering /* force 64bit mode */ \ 2109fc0a92cSOlaf Hering li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \ 2119fc0a92cSOlaf Hering rldimi r10,r11,61,0; /* insert into top 3 bits */ \ 2129fc0a92cSOlaf Hering /* done 64bit mode */ \ 2139fc0a92cSOlaf Hering mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 2149fc0a92cSOlaf Hering LOAD_HANDLER(r12,label) \ 2159fc0a92cSOlaf Hering ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 2169fc0a92cSOlaf Hering mtspr SPRN_SRR0,r12; \ 2179fc0a92cSOlaf Hering mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 2189fc0a92cSOlaf Hering mtspr SPRN_SRR1,r10; \ 2199fc0a92cSOlaf Hering rfid; \ 2209fc0a92cSOlaf Hering b . /* prevent speculative execution */ 2219fc0a92cSOlaf Hering 22214cf11afSPaul Mackerras#define EXCEPTION_PROLOG_PSERIES(area, label) \ 223b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 22414cf11afSPaul Mackerras std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 22514cf11afSPaul Mackerras std r10,area+EX_R10(r13); \ 22614cf11afSPaul Mackerras std r11,area+EX_R11(r13); \ 22714cf11afSPaul Mackerras std r12,area+EX_R12(r13); \ 228b5bbeb23SPaul Mackerras mfspr r9,SPRN_SPRG1; \ 22914cf11afSPaul Mackerras std r9,area+EX_R13(r13); \ 23014cf11afSPaul Mackerras mfcr r9; \ 23114cf11afSPaul Mackerras clrrdi r12,r13,32; /* get high part of &label */ \ 23214cf11afSPaul Mackerras mfmsr r10; \ 233b5bbeb23SPaul Mackerras mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 234758438a7SMichael Ellerman LOAD_HANDLER(r12,label) \ 23514cf11afSPaul Mackerras ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 236b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r12; \ 237b5bbeb23SPaul Mackerras mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 238b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r10; \ 23914cf11afSPaul Mackerras rfid; \ 24014cf11afSPaul Mackerras b . /* prevent speculative execution */ 24114cf11afSPaul Mackerras 24214cf11afSPaul Mackerras/* 24314cf11afSPaul Mackerras * This is the start of the interrupt handlers for iSeries 24414cf11afSPaul Mackerras * This code runs with relocation on. 24514cf11afSPaul Mackerras */ 24614cf11afSPaul Mackerras#define EXCEPTION_PROLOG_ISERIES_1(area) \ 247b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 24814cf11afSPaul Mackerras std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 24914cf11afSPaul Mackerras std r10,area+EX_R10(r13); \ 25014cf11afSPaul Mackerras std r11,area+EX_R11(r13); \ 25114cf11afSPaul Mackerras std r12,area+EX_R12(r13); \ 252b5bbeb23SPaul Mackerras mfspr r9,SPRN_SPRG1; \ 25314cf11afSPaul Mackerras std r9,area+EX_R13(r13); \ 25414cf11afSPaul Mackerras mfcr r9 25514cf11afSPaul Mackerras 25614cf11afSPaul Mackerras#define EXCEPTION_PROLOG_ISERIES_2 \ 25714cf11afSPaul Mackerras mfmsr r10; \ 2583356bb9fSDavid Gibson ld r12,PACALPPACAPTR(r13); \ 2593356bb9fSDavid Gibson ld r11,LPPACASRR0(r12); \ 2603356bb9fSDavid Gibson ld r12,LPPACASRR1(r12); \ 26114cf11afSPaul Mackerras ori r10,r10,MSR_RI; \ 26214cf11afSPaul Mackerras mtmsrd r10,1 26314cf11afSPaul Mackerras 26414cf11afSPaul Mackerras/* 26514cf11afSPaul Mackerras * The common exception prolog is used for all except a few exceptions 26614cf11afSPaul Mackerras * such as a segment miss on a kernel address. We have to be prepared 26714cf11afSPaul Mackerras * to take another exception from the point where we first touch the 26814cf11afSPaul Mackerras * kernel stack onwards. 26914cf11afSPaul Mackerras * 27014cf11afSPaul Mackerras * On entry r13 points to the paca, r9-r13 are saved in the paca, 27114cf11afSPaul Mackerras * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 27214cf11afSPaul Mackerras * SRR1, and relocation is on. 27314cf11afSPaul Mackerras */ 27414cf11afSPaul Mackerras#define EXCEPTION_PROLOG_COMMON(n, area) \ 27514cf11afSPaul Mackerras andi. r10,r12,MSR_PR; /* See if coming from user */ \ 27614cf11afSPaul Mackerras mr r10,r1; /* Save r1 */ \ 27714cf11afSPaul Mackerras subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 27814cf11afSPaul Mackerras beq- 1f; \ 27914cf11afSPaul Mackerras ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 28014cf11afSPaul Mackerras1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 28114cf11afSPaul Mackerras bge- cr1,bad_stack; /* abort if it is */ \ 28214cf11afSPaul Mackerras std r9,_CCR(r1); /* save CR in stackframe */ \ 28314cf11afSPaul Mackerras std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 28414cf11afSPaul Mackerras std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 28514cf11afSPaul Mackerras std r10,0(r1); /* make stack chain pointer */ \ 28614cf11afSPaul Mackerras std r0,GPR0(r1); /* save r0 in stackframe */ \ 28714cf11afSPaul Mackerras std r10,GPR1(r1); /* save r1 in stackframe */ \ 288c6622f63SPaul Mackerras ACCOUNT_CPU_USER_ENTRY(r9, r10); \ 28914cf11afSPaul Mackerras std r2,GPR2(r1); /* save r2 in stackframe */ \ 29014cf11afSPaul Mackerras SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 29114cf11afSPaul Mackerras SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 29214cf11afSPaul Mackerras ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 29314cf11afSPaul Mackerras ld r10,area+EX_R10(r13); \ 29414cf11afSPaul Mackerras std r9,GPR9(r1); \ 29514cf11afSPaul Mackerras std r10,GPR10(r1); \ 29614cf11afSPaul Mackerras ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 29714cf11afSPaul Mackerras ld r10,area+EX_R12(r13); \ 29814cf11afSPaul Mackerras ld r11,area+EX_R13(r13); \ 29914cf11afSPaul Mackerras std r9,GPR11(r1); \ 30014cf11afSPaul Mackerras std r10,GPR12(r1); \ 30114cf11afSPaul Mackerras std r11,GPR13(r1); \ 30214cf11afSPaul Mackerras ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 30314cf11afSPaul Mackerras mflr r9; /* save LR in stackframe */ \ 30414cf11afSPaul Mackerras std r9,_LINK(r1); \ 30514cf11afSPaul Mackerras mfctr r10; /* save CTR in stackframe */ \ 30614cf11afSPaul Mackerras std r10,_CTR(r1); \ 307d04c56f7SPaul Mackerras lbz r10,PACASOFTIRQEN(r13); \ 308b5bbeb23SPaul Mackerras mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 309d04c56f7SPaul Mackerras std r10,SOFTE(r1); \ 31014cf11afSPaul Mackerras std r11,_XER(r1); \ 31114cf11afSPaul Mackerras li r9,(n)+1; \ 31214cf11afSPaul Mackerras std r9,_TRAP(r1); /* set trap number */ \ 31314cf11afSPaul Mackerras li r10,0; \ 31414cf11afSPaul Mackerras ld r11,exception_marker@toc(r2); \ 31514cf11afSPaul Mackerras std r10,RESULT(r1); /* clear regs->result */ \ 31614cf11afSPaul Mackerras std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 31714cf11afSPaul Mackerras 31814cf11afSPaul Mackerras/* 31914cf11afSPaul Mackerras * Exception vectors. 32014cf11afSPaul Mackerras */ 32114cf11afSPaul Mackerras#define STD_EXCEPTION_PSERIES(n, label) \ 32214cf11afSPaul Mackerras . = n; \ 32314cf11afSPaul Mackerras .globl label##_pSeries; \ 32414cf11afSPaul Mackerraslabel##_pSeries: \ 32514cf11afSPaul Mackerras HMT_MEDIUM; \ 326b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13; /* save r13 */ \ 32714cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 32814cf11afSPaul Mackerras 329acf7d768SBenjamin Herrenschmidt#define HSTD_EXCEPTION_PSERIES(n, label) \ 330acf7d768SBenjamin Herrenschmidt . = n; \ 331acf7d768SBenjamin Herrenschmidt .globl label##_pSeries; \ 332acf7d768SBenjamin Herrenschmidtlabel##_pSeries: \ 333acf7d768SBenjamin Herrenschmidt HMT_MEDIUM; \ 334acf7d768SBenjamin Herrenschmidt mtspr SPRN_SPRG1,r20; /* save r20 */ \ 335acf7d768SBenjamin Herrenschmidt mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ 336acf7d768SBenjamin Herrenschmidt mtspr SPRN_SRR0,r20; \ 337acf7d768SBenjamin Herrenschmidt mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \ 338acf7d768SBenjamin Herrenschmidt mtspr SPRN_SRR1,r20; \ 339acf7d768SBenjamin Herrenschmidt mfspr r20,SPRN_SPRG1; /* restore r20 */ \ 340acf7d768SBenjamin Herrenschmidt mtspr SPRN_SPRG1,r13; /* save r13 */ \ 341acf7d768SBenjamin Herrenschmidt EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 342acf7d768SBenjamin Herrenschmidt 343acf7d768SBenjamin Herrenschmidt 344d04c56f7SPaul Mackerras#define MASKABLE_EXCEPTION_PSERIES(n, label) \ 345d04c56f7SPaul Mackerras . = n; \ 346d04c56f7SPaul Mackerras .globl label##_pSeries; \ 347d04c56f7SPaul Mackerraslabel##_pSeries: \ 348d04c56f7SPaul Mackerras HMT_MEDIUM; \ 349d04c56f7SPaul Mackerras mtspr SPRN_SPRG1,r13; /* save r13 */ \ 350d04c56f7SPaul Mackerras mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 351d04c56f7SPaul Mackerras std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ 352d04c56f7SPaul Mackerras std r10,PACA_EXGEN+EX_R10(r13); \ 353d04c56f7SPaul Mackerras lbz r10,PACASOFTIRQEN(r13); \ 354d04c56f7SPaul Mackerras mfcr r9; \ 355d04c56f7SPaul Mackerras cmpwi r10,0; \ 356d04c56f7SPaul Mackerras beq masked_interrupt; \ 357d04c56f7SPaul Mackerras mfspr r10,SPRN_SPRG1; \ 358d04c56f7SPaul Mackerras std r10,PACA_EXGEN+EX_R13(r13); \ 359d04c56f7SPaul Mackerras std r11,PACA_EXGEN+EX_R11(r13); \ 360d04c56f7SPaul Mackerras std r12,PACA_EXGEN+EX_R12(r13); \ 361d04c56f7SPaul Mackerras clrrdi r12,r13,32; /* get high part of &label */ \ 362d04c56f7SPaul Mackerras mfmsr r10; \ 363d04c56f7SPaul Mackerras mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 364d04c56f7SPaul Mackerras LOAD_HANDLER(r12,label##_common) \ 365d04c56f7SPaul Mackerras ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 366d04c56f7SPaul Mackerras mtspr SPRN_SRR0,r12; \ 367d04c56f7SPaul Mackerras mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 368d04c56f7SPaul Mackerras mtspr SPRN_SRR1,r10; \ 369d04c56f7SPaul Mackerras rfid; \ 370d04c56f7SPaul Mackerras b . /* prevent speculative execution */ 371d04c56f7SPaul Mackerras 37214cf11afSPaul Mackerras#define STD_EXCEPTION_ISERIES(n, label, area) \ 37314cf11afSPaul Mackerras .globl label##_iSeries; \ 37414cf11afSPaul Mackerraslabel##_iSeries: \ 37514cf11afSPaul Mackerras HMT_MEDIUM; \ 376b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13; /* save r13 */ \ 37714cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_1(area); \ 37814cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2; \ 37914cf11afSPaul Mackerras b label##_common 38014cf11afSPaul Mackerras 38114cf11afSPaul Mackerras#define MASKABLE_EXCEPTION_ISERIES(n, label) \ 38214cf11afSPaul Mackerras .globl label##_iSeries; \ 38314cf11afSPaul Mackerraslabel##_iSeries: \ 38414cf11afSPaul Mackerras HMT_MEDIUM; \ 385b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13; /* save r13 */ \ 38614cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ 387d04c56f7SPaul Mackerras lbz r10,PACASOFTIRQEN(r13); \ 38814cf11afSPaul Mackerras cmpwi 0,r10,0; \ 38914cf11afSPaul Mackerras beq- label##_iSeries_masked; \ 39014cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2; \ 39114cf11afSPaul Mackerras b label##_common; \ 39214cf11afSPaul Mackerras 393d04c56f7SPaul Mackerras#ifdef CONFIG_PPC_ISERIES 39414cf11afSPaul Mackerras#define DISABLE_INTS \ 39514cf11afSPaul Mackerras li r11,0; \ 396d04c56f7SPaul Mackerras stb r11,PACASOFTIRQEN(r13); \ 397d04c56f7SPaul MackerrasBEGIN_FW_FTR_SECTION; \ 398d04c56f7SPaul Mackerras stb r11,PACAHARDIRQEN(r13); \ 399d04c56f7SPaul MackerrasEND_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ 400d04c56f7SPaul MackerrasBEGIN_FW_FTR_SECTION; \ 40114cf11afSPaul Mackerras mfmsr r10; \ 40214cf11afSPaul Mackerras ori r10,r10,MSR_EE; \ 4033f639ee8SStephen Rothwell mtmsrd r10,1; \ 4043f639ee8SStephen RothwellEND_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 40514cf11afSPaul Mackerras 406d04c56f7SPaul Mackerras#else 407d04c56f7SPaul Mackerras#define DISABLE_INTS \ 408d04c56f7SPaul Mackerras li r11,0; \ 409d04c56f7SPaul Mackerras stb r11,PACASOFTIRQEN(r13); \ 410d04c56f7SPaul Mackerras stb r11,PACAHARDIRQEN(r13) 41114cf11afSPaul Mackerras 412d04c56f7SPaul Mackerras#endif /* CONFIG_PPC_ISERIES */ 41314cf11afSPaul Mackerras 41414cf11afSPaul Mackerras#define ENABLE_INTS \ 41514cf11afSPaul Mackerras ld r12,_MSR(r1); \ 41614cf11afSPaul Mackerras mfmsr r11; \ 41714cf11afSPaul Mackerras rlwimi r11,r12,0,MSR_EE; \ 41814cf11afSPaul Mackerras mtmsrd r11,1 41914cf11afSPaul Mackerras 42014cf11afSPaul Mackerras#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 42114cf11afSPaul Mackerras .align 7; \ 42214cf11afSPaul Mackerras .globl label##_common; \ 42314cf11afSPaul Mackerraslabel##_common: \ 42414cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 42514cf11afSPaul Mackerras DISABLE_INTS; \ 42614cf11afSPaul Mackerras bl .save_nvgprs; \ 42714cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD; \ 42814cf11afSPaul Mackerras bl hdlr; \ 42914cf11afSPaul Mackerras b .ret_from_except 43014cf11afSPaul Mackerras 431f39224a8SPaul Mackerras/* 432f39224a8SPaul Mackerras * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 433f39224a8SPaul Mackerras * in the idle task and therefore need the special idle handling. 434f39224a8SPaul Mackerras */ 435f39224a8SPaul Mackerras#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \ 436f39224a8SPaul Mackerras .align 7; \ 437f39224a8SPaul Mackerras .globl label##_common; \ 438f39224a8SPaul Mackerraslabel##_common: \ 439f39224a8SPaul Mackerras EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 440f39224a8SPaul Mackerras FINISH_NAP; \ 441f39224a8SPaul Mackerras DISABLE_INTS; \ 442f39224a8SPaul Mackerras bl .save_nvgprs; \ 443f39224a8SPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD; \ 444f39224a8SPaul Mackerras bl hdlr; \ 445f39224a8SPaul Mackerras b .ret_from_except 446f39224a8SPaul Mackerras 44714cf11afSPaul Mackerras#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ 44814cf11afSPaul Mackerras .align 7; \ 44914cf11afSPaul Mackerras .globl label##_common; \ 45014cf11afSPaul Mackerraslabel##_common: \ 45114cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 452f39224a8SPaul Mackerras FINISH_NAP; \ 45314cf11afSPaul Mackerras DISABLE_INTS; \ 454cb2c9b27SAnton Blanchard bl .ppc64_runlatch_on; \ 45514cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD; \ 45614cf11afSPaul Mackerras bl hdlr; \ 45714cf11afSPaul Mackerras b .ret_from_except_lite 45814cf11afSPaul Mackerras 45914cf11afSPaul Mackerras/* 460f39224a8SPaul Mackerras * When the idle code in power4_idle puts the CPU into NAP mode, 461f39224a8SPaul Mackerras * it has to do so in a loop, and relies on the external interrupt 462f39224a8SPaul Mackerras * and decrementer interrupt entry code to get it out of the loop. 463f39224a8SPaul Mackerras * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 464f39224a8SPaul Mackerras * to signal that it is in the loop and needs help to get out. 465f39224a8SPaul Mackerras */ 466f39224a8SPaul Mackerras#ifdef CONFIG_PPC_970_NAP 467f39224a8SPaul Mackerras#define FINISH_NAP \ 468f39224a8SPaul MackerrasBEGIN_FTR_SECTION \ 469f39224a8SPaul Mackerras clrrdi r11,r1,THREAD_SHIFT; \ 470f39224a8SPaul Mackerras ld r9,TI_LOCAL_FLAGS(r11); \ 471f39224a8SPaul Mackerras andi. r10,r9,_TLF_NAPPING; \ 472f39224a8SPaul Mackerras bnel power4_fixup_nap; \ 473f39224a8SPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 474f39224a8SPaul Mackerras#else 475f39224a8SPaul Mackerras#define FINISH_NAP 476f39224a8SPaul Mackerras#endif 477f39224a8SPaul Mackerras 478f39224a8SPaul Mackerras/* 47914cf11afSPaul Mackerras * Start of pSeries system interrupt routines 48014cf11afSPaul Mackerras */ 48114cf11afSPaul Mackerras . = 0x100 48214cf11afSPaul Mackerras .globl __start_interrupts 48314cf11afSPaul Mackerras__start_interrupts: 48414cf11afSPaul Mackerras 48514cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x100, system_reset) 48614cf11afSPaul Mackerras 48714cf11afSPaul Mackerras . = 0x200 48814cf11afSPaul Mackerras_machine_check_pSeries: 48914cf11afSPaul Mackerras HMT_MEDIUM 490b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 49114cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 49214cf11afSPaul Mackerras 49314cf11afSPaul Mackerras . = 0x300 49414cf11afSPaul Mackerras .globl data_access_pSeries 49514cf11afSPaul Mackerrasdata_access_pSeries: 49614cf11afSPaul Mackerras HMT_MEDIUM 497b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 49814cf11afSPaul MackerrasBEGIN_FTR_SECTION 499b5bbeb23SPaul Mackerras mtspr SPRN_SPRG2,r12 500b5bbeb23SPaul Mackerras mfspr r13,SPRN_DAR 501b5bbeb23SPaul Mackerras mfspr r12,SPRN_DSISR 50214cf11afSPaul Mackerras srdi r13,r13,60 50314cf11afSPaul Mackerras rlwimi r13,r12,16,0x20 50414cf11afSPaul Mackerras mfcr r12 50514cf11afSPaul Mackerras cmpwi r13,0x2c 5063ccfc65cSPaul Mackerras beq do_stab_bolted_pSeries 50714cf11afSPaul Mackerras mtcrf 0x80,r12 508b5bbeb23SPaul Mackerras mfspr r12,SPRN_SPRG2 50914cf11afSPaul MackerrasEND_FTR_SECTION_IFCLR(CPU_FTR_SLB) 51014cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 51114cf11afSPaul Mackerras 51214cf11afSPaul Mackerras . = 0x380 51314cf11afSPaul Mackerras .globl data_access_slb_pSeries 51414cf11afSPaul Mackerrasdata_access_slb_pSeries: 51514cf11afSPaul Mackerras HMT_MEDIUM 516b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 517b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 5183c726f8dSBenjamin Herrenschmidt std r3,PACA_EXSLB+EX_R3(r13) 5193c726f8dSBenjamin Herrenschmidt mfspr r3,SPRN_DAR 52014cf11afSPaul Mackerras std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 5213c726f8dSBenjamin Herrenschmidt mfcr r9 5223c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 5233c726f8dSBenjamin Herrenschmidt /* Keep that around for when we re-implement dynamic VSIDs */ 5243c726f8dSBenjamin Herrenschmidt cmpdi r3,0 5253c726f8dSBenjamin Herrenschmidt bge slb_miss_user_pseries 5263c726f8dSBenjamin Herrenschmidt#endif /* __DISABLED__ */ 52714cf11afSPaul Mackerras std r10,PACA_EXSLB+EX_R10(r13) 52814cf11afSPaul Mackerras std r11,PACA_EXSLB+EX_R11(r13) 52914cf11afSPaul Mackerras std r12,PACA_EXSLB+EX_R12(r13) 5303c726f8dSBenjamin Herrenschmidt mfspr r10,SPRN_SPRG1 5313c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R13(r13) 532b5bbeb23SPaul Mackerras mfspr r12,SPRN_SRR1 /* and SRR1 */ 5333c726f8dSBenjamin Herrenschmidt b .slb_miss_realmode /* Rel. branch works in real mode */ 53414cf11afSPaul Mackerras 53514cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x400, instruction_access) 53614cf11afSPaul Mackerras 53714cf11afSPaul Mackerras . = 0x480 53814cf11afSPaul Mackerras .globl instruction_access_slb_pSeries 53914cf11afSPaul Mackerrasinstruction_access_slb_pSeries: 54014cf11afSPaul Mackerras HMT_MEDIUM 541b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 542b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 5433c726f8dSBenjamin Herrenschmidt std r3,PACA_EXSLB+EX_R3(r13) 5443c726f8dSBenjamin Herrenschmidt mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 54514cf11afSPaul Mackerras std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 5463c726f8dSBenjamin Herrenschmidt mfcr r9 5473c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 5483c726f8dSBenjamin Herrenschmidt /* Keep that around for when we re-implement dynamic VSIDs */ 5493c726f8dSBenjamin Herrenschmidt cmpdi r3,0 5503c726f8dSBenjamin Herrenschmidt bge slb_miss_user_pseries 5513c726f8dSBenjamin Herrenschmidt#endif /* __DISABLED__ */ 55214cf11afSPaul Mackerras std r10,PACA_EXSLB+EX_R10(r13) 55314cf11afSPaul Mackerras std r11,PACA_EXSLB+EX_R11(r13) 55414cf11afSPaul Mackerras std r12,PACA_EXSLB+EX_R12(r13) 5553c726f8dSBenjamin Herrenschmidt mfspr r10,SPRN_SPRG1 5563c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R13(r13) 557b5bbeb23SPaul Mackerras mfspr r12,SPRN_SRR1 /* and SRR1 */ 5583c726f8dSBenjamin Herrenschmidt b .slb_miss_realmode /* Rel. branch works in real mode */ 55914cf11afSPaul Mackerras 560d04c56f7SPaul Mackerras MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) 56114cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x600, alignment) 56214cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x700, program_check) 56314cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x800, fp_unavailable) 564d04c56f7SPaul Mackerras MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) 56514cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xa00, trap_0a) 56614cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xb00, trap_0b) 56714cf11afSPaul Mackerras 56814cf11afSPaul Mackerras . = 0xc00 56914cf11afSPaul Mackerras .globl system_call_pSeries 57014cf11afSPaul Mackerrassystem_call_pSeries: 57114cf11afSPaul Mackerras HMT_MEDIUM 57214cf11afSPaul Mackerras mr r9,r13 57314cf11afSPaul Mackerras mfmsr r10 574b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 575b5bbeb23SPaul Mackerras mfspr r11,SPRN_SRR0 57614cf11afSPaul Mackerras clrrdi r12,r13,32 57714cf11afSPaul Mackerras oris r12,r12,system_call_common@h 57814cf11afSPaul Mackerras ori r12,r12,system_call_common@l 579b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r12 58014cf11afSPaul Mackerras ori r10,r10,MSR_IR|MSR_DR|MSR_RI 581b5bbeb23SPaul Mackerras mfspr r12,SPRN_SRR1 582b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r10 58314cf11afSPaul Mackerras rfid 58414cf11afSPaul Mackerras b . /* prevent speculative execution */ 58514cf11afSPaul Mackerras 58614cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xd00, single_step) 58714cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xe00, trap_0e) 58814cf11afSPaul Mackerras 58914cf11afSPaul Mackerras /* We need to deal with the Altivec unavailable exception 59014cf11afSPaul Mackerras * here which is at 0xf20, thus in the middle of the 59114cf11afSPaul Mackerras * prolog code of the PerformanceMonitor one. A little 59214cf11afSPaul Mackerras * trickery is thus necessary 59314cf11afSPaul Mackerras */ 59414cf11afSPaul Mackerras . = 0xf00 59514cf11afSPaul Mackerras b performance_monitor_pSeries 59614cf11afSPaul Mackerras 59714cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) 59814cf11afSPaul Mackerras 599acf7d768SBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 600acf7d768SBenjamin Herrenschmidt HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) 601acf7d768SBenjamin Herrenschmidt#endif /* CONFIG_CBE_RAS */ 60214cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) 603acf7d768SBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 604acf7d768SBenjamin Herrenschmidt HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) 605acf7d768SBenjamin Herrenschmidt#endif /* CONFIG_CBE_RAS */ 60614cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x1700, altivec_assist) 607acf7d768SBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 608acf7d768SBenjamin Herrenschmidt HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) 609acf7d768SBenjamin Herrenschmidt#endif /* CONFIG_CBE_RAS */ 61014cf11afSPaul Mackerras 61114cf11afSPaul Mackerras . = 0x3000 61214cf11afSPaul Mackerras 61314cf11afSPaul Mackerras/*** pSeries interrupt support ***/ 61414cf11afSPaul Mackerras 61514cf11afSPaul Mackerras /* moved from 0xf00 */ 616d04c56f7SPaul Mackerras MASKABLE_EXCEPTION_PSERIES(., performance_monitor) 617d04c56f7SPaul Mackerras 618d04c56f7SPaul Mackerras/* 619d04c56f7SPaul Mackerras * An interrupt came in while soft-disabled; clear EE in SRR1, 620d04c56f7SPaul Mackerras * clear paca->hard_enabled and return. 621d04c56f7SPaul Mackerras */ 622d04c56f7SPaul Mackerrasmasked_interrupt: 623d04c56f7SPaul Mackerras stb r10,PACAHARDIRQEN(r13) 624d04c56f7SPaul Mackerras mtcrf 0x80,r9 625d04c56f7SPaul Mackerras ld r9,PACA_EXGEN+EX_R9(r13) 626d04c56f7SPaul Mackerras mfspr r10,SPRN_SRR1 627d04c56f7SPaul Mackerras rldicl r10,r10,48,1 /* clear MSR_EE */ 628d04c56f7SPaul Mackerras rotldi r10,r10,16 629d04c56f7SPaul Mackerras mtspr SPRN_SRR1,r10 630d04c56f7SPaul Mackerras ld r10,PACA_EXGEN+EX_R10(r13) 631d04c56f7SPaul Mackerras mfspr r13,SPRN_SPRG1 632d04c56f7SPaul Mackerras rfid 633d04c56f7SPaul Mackerras b . 63414cf11afSPaul Mackerras 63514cf11afSPaul Mackerras .align 7 6363ccfc65cSPaul Mackerrasdo_stab_bolted_pSeries: 63714cf11afSPaul Mackerras mtcrf 0x80,r12 638b5bbeb23SPaul Mackerras mfspr r12,SPRN_SPRG2 63914cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 64014cf11afSPaul Mackerras 64114cf11afSPaul Mackerras/* 6423c726f8dSBenjamin Herrenschmidt * We have some room here we use that to put 6433c726f8dSBenjamin Herrenschmidt * the peries slb miss user trampoline code so it's reasonably 6443c726f8dSBenjamin Herrenschmidt * away from slb_miss_user_common to avoid problems with rfid 6453c726f8dSBenjamin Herrenschmidt * 6463c726f8dSBenjamin Herrenschmidt * This is used for when the SLB miss handler has to go virtual, 6473c726f8dSBenjamin Herrenschmidt * which doesn't happen for now anymore but will once we re-implement 6483c726f8dSBenjamin Herrenschmidt * dynamic VSIDs for shared page tables 6493c726f8dSBenjamin Herrenschmidt */ 6503c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 6513c726f8dSBenjamin Herrenschmidtslb_miss_user_pseries: 6523c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_R10(r13) 6533c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R11(r13) 6543c726f8dSBenjamin Herrenschmidt std r12,PACA_EXGEN+EX_R12(r13) 6553c726f8dSBenjamin Herrenschmidt mfspr r10,SPRG1 6563c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXSLB+EX_R9(r13) 6573c726f8dSBenjamin Herrenschmidt ld r12,PACA_EXSLB+EX_R3(r13) 6583c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_R13(r13) 6593c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R9(r13) 6603c726f8dSBenjamin Herrenschmidt std r12,PACA_EXGEN+EX_R3(r13) 6613c726f8dSBenjamin Herrenschmidt clrrdi r12,r13,32 6623c726f8dSBenjamin Herrenschmidt mfmsr r10 6633c726f8dSBenjamin Herrenschmidt mfspr r11,SRR0 /* save SRR0 */ 6643c726f8dSBenjamin Herrenschmidt ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ 6653c726f8dSBenjamin Herrenschmidt ori r10,r10,MSR_IR|MSR_DR|MSR_RI 6663c726f8dSBenjamin Herrenschmidt mtspr SRR0,r12 6673c726f8dSBenjamin Herrenschmidt mfspr r12,SRR1 /* and SRR1 */ 6683c726f8dSBenjamin Herrenschmidt mtspr SRR1,r10 6693c726f8dSBenjamin Herrenschmidt rfid 6703c726f8dSBenjamin Herrenschmidt b . /* prevent spec. execution */ 6713c726f8dSBenjamin Herrenschmidt#endif /* __DISABLED__ */ 6723c726f8dSBenjamin Herrenschmidt 6733c726f8dSBenjamin Herrenschmidt/* 67414cf11afSPaul Mackerras * Vectors for the FWNMI option. Share common code. 67514cf11afSPaul Mackerras */ 67614cf11afSPaul Mackerras .globl system_reset_fwnmi 6778c4f1f29SMichael Ellerman .align 7 67814cf11afSPaul Mackerrassystem_reset_fwnmi: 67914cf11afSPaul Mackerras HMT_MEDIUM 680b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 6819fc0a92cSOlaf Hering EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common) 68214cf11afSPaul Mackerras 68314cf11afSPaul Mackerras .globl machine_check_fwnmi 6848c4f1f29SMichael Ellerman .align 7 68514cf11afSPaul Mackerrasmachine_check_fwnmi: 68614cf11afSPaul Mackerras HMT_MEDIUM 687b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 6889fc0a92cSOlaf Hering EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common) 68914cf11afSPaul Mackerras 69014cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 69114cf11afSPaul Mackerras/*** ISeries-LPAR interrupt handlers ***/ 69214cf11afSPaul Mackerras 69314cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) 69414cf11afSPaul Mackerras 69514cf11afSPaul Mackerras .globl data_access_iSeries 69614cf11afSPaul Mackerrasdata_access_iSeries: 697b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 69814cf11afSPaul MackerrasBEGIN_FTR_SECTION 699b5bbeb23SPaul Mackerras mtspr SPRN_SPRG2,r12 700b5bbeb23SPaul Mackerras mfspr r13,SPRN_DAR 701b5bbeb23SPaul Mackerras mfspr r12,SPRN_DSISR 70214cf11afSPaul Mackerras srdi r13,r13,60 70314cf11afSPaul Mackerras rlwimi r13,r12,16,0x20 70414cf11afSPaul Mackerras mfcr r12 70514cf11afSPaul Mackerras cmpwi r13,0x2c 70614cf11afSPaul Mackerras beq .do_stab_bolted_iSeries 70714cf11afSPaul Mackerras mtcrf 0x80,r12 708b5bbeb23SPaul Mackerras mfspr r12,SPRN_SPRG2 70914cf11afSPaul MackerrasEND_FTR_SECTION_IFCLR(CPU_FTR_SLB) 71014cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) 71114cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2 71214cf11afSPaul Mackerras b data_access_common 71314cf11afSPaul Mackerras 71414cf11afSPaul Mackerras.do_stab_bolted_iSeries: 71514cf11afSPaul Mackerras mtcrf 0x80,r12 716b5bbeb23SPaul Mackerras mfspr r12,SPRN_SPRG2 71714cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) 71814cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2 71914cf11afSPaul Mackerras b .do_stab_bolted 72014cf11afSPaul Mackerras 72114cf11afSPaul Mackerras .globl data_access_slb_iSeries 72214cf11afSPaul Mackerrasdata_access_slb_iSeries: 723b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 7243c726f8dSBenjamin Herrenschmidt mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 72514cf11afSPaul Mackerras std r3,PACA_EXSLB+EX_R3(r13) 726b5bbeb23SPaul Mackerras mfspr r3,SPRN_DAR 7273c726f8dSBenjamin Herrenschmidt std r9,PACA_EXSLB+EX_R9(r13) 7283c726f8dSBenjamin Herrenschmidt mfcr r9 7293c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 7303c726f8dSBenjamin Herrenschmidt cmpdi r3,0 7313c726f8dSBenjamin Herrenschmidt bge slb_miss_user_iseries 7323c726f8dSBenjamin Herrenschmidt#endif 7333c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R10(r13) 7343c726f8dSBenjamin Herrenschmidt std r11,PACA_EXSLB+EX_R11(r13) 7353c726f8dSBenjamin Herrenschmidt std r12,PACA_EXSLB+EX_R12(r13) 7363c726f8dSBenjamin Herrenschmidt mfspr r10,SPRN_SPRG1 7373c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R13(r13) 7383356bb9fSDavid Gibson ld r12,PACALPPACAPTR(r13) 7393356bb9fSDavid Gibson ld r12,LPPACASRR1(r12) 7403c726f8dSBenjamin Herrenschmidt b .slb_miss_realmode 74114cf11afSPaul Mackerras 74214cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) 74314cf11afSPaul Mackerras 74414cf11afSPaul Mackerras .globl instruction_access_slb_iSeries 74514cf11afSPaul Mackerrasinstruction_access_slb_iSeries: 746b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 7473c726f8dSBenjamin Herrenschmidt mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 74814cf11afSPaul Mackerras std r3,PACA_EXSLB+EX_R3(r13) 7493356bb9fSDavid Gibson ld r3,PACALPPACAPTR(r13) 7503356bb9fSDavid Gibson ld r3,LPPACASRR0(r3) /* get SRR0 value */ 7513c726f8dSBenjamin Herrenschmidt std r9,PACA_EXSLB+EX_R9(r13) 7523c726f8dSBenjamin Herrenschmidt mfcr r9 7533c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 7543c726f8dSBenjamin Herrenschmidt cmpdi r3,0 7553c726f8dSBenjamin Herrenschmidt bge .slb_miss_user_iseries 7563c726f8dSBenjamin Herrenschmidt#endif 7573c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R10(r13) 7583c726f8dSBenjamin Herrenschmidt std r11,PACA_EXSLB+EX_R11(r13) 7593c726f8dSBenjamin Herrenschmidt std r12,PACA_EXSLB+EX_R12(r13) 7603c726f8dSBenjamin Herrenschmidt mfspr r10,SPRN_SPRG1 7613c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R13(r13) 7623356bb9fSDavid Gibson ld r12,PACALPPACAPTR(r13) 7633356bb9fSDavid Gibson ld r12,LPPACASRR1(r12) 7643c726f8dSBenjamin Herrenschmidt b .slb_miss_realmode 7653c726f8dSBenjamin Herrenschmidt 7663c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 7673c726f8dSBenjamin Herrenschmidtslb_miss_user_iseries: 7683c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_R10(r13) 7693c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R11(r13) 7703c726f8dSBenjamin Herrenschmidt std r12,PACA_EXGEN+EX_R12(r13) 7713c726f8dSBenjamin Herrenschmidt mfspr r10,SPRG1 7723c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXSLB+EX_R9(r13) 7733c726f8dSBenjamin Herrenschmidt ld r12,PACA_EXSLB+EX_R3(r13) 7743c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_R13(r13) 7753c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R9(r13) 7763c726f8dSBenjamin Herrenschmidt std r12,PACA_EXGEN+EX_R3(r13) 7773c726f8dSBenjamin Herrenschmidt EXCEPTION_PROLOG_ISERIES_2 7783c726f8dSBenjamin Herrenschmidt b slb_miss_user_common 7793c726f8dSBenjamin Herrenschmidt#endif 78014cf11afSPaul Mackerras 78114cf11afSPaul Mackerras MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) 78214cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) 78314cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) 78414cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) 78514cf11afSPaul Mackerras MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) 78614cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) 78714cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) 78814cf11afSPaul Mackerras 78914cf11afSPaul Mackerras .globl system_call_iSeries 79014cf11afSPaul Mackerrassystem_call_iSeries: 79114cf11afSPaul Mackerras mr r9,r13 792b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 79314cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2 79414cf11afSPaul Mackerras b system_call_common 79514cf11afSPaul Mackerras 79614cf11afSPaul Mackerras STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) 79714cf11afSPaul Mackerras STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) 79814cf11afSPaul Mackerras STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) 79914cf11afSPaul Mackerras 80014cf11afSPaul Mackerras .globl system_reset_iSeries 80114cf11afSPaul Mackerrassystem_reset_iSeries: 802b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 /* Get paca address */ 80314cf11afSPaul Mackerras mfmsr r24 80414cf11afSPaul Mackerras ori r24,r24,MSR_RI 80514cf11afSPaul Mackerras mtmsrd r24 /* RI on */ 80614cf11afSPaul Mackerras lhz r24,PACAPACAINDEX(r13) /* Get processor # */ 80714cf11afSPaul Mackerras cmpwi 0,r24,0 /* Are we processor 0? */ 80814cf11afSPaul Mackerras beq .__start_initialization_iSeries /* Start up the first processor */ 80914cf11afSPaul Mackerras mfspr r4,SPRN_CTRLF 81014cf11afSPaul Mackerras li r5,CTRL_RUNLATCH /* Turn off the run light */ 81114cf11afSPaul Mackerras andc r4,r4,r5 81214cf11afSPaul Mackerras mtspr SPRN_CTRLT,r4 81314cf11afSPaul Mackerras 81414cf11afSPaul Mackerras1: 81514cf11afSPaul Mackerras HMT_LOW 81614cf11afSPaul Mackerras#ifdef CONFIG_SMP 81714cf11afSPaul Mackerras lbz r23,PACAPROCSTART(r13) /* Test if this processor 81814cf11afSPaul Mackerras * should start */ 81914cf11afSPaul Mackerras sync 820e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r3,current_set) 82114cf11afSPaul Mackerras sldi r28,r24,3 /* get current_set[cpu#] */ 82214cf11afSPaul Mackerras ldx r3,r3,r28 82314cf11afSPaul Mackerras addi r1,r3,THREAD_SIZE 82414cf11afSPaul Mackerras subi r1,r1,STACK_FRAME_OVERHEAD 82514cf11afSPaul Mackerras 82614cf11afSPaul Mackerras cmpwi 0,r23,0 82714cf11afSPaul Mackerras beq iSeries_secondary_smp_loop /* Loop until told to go */ 82814cf11afSPaul Mackerras bne .__secondary_start /* Loop until told to go */ 82914cf11afSPaul MackerrasiSeries_secondary_smp_loop: 83014cf11afSPaul Mackerras /* Let the Hypervisor know we are alive */ 83114cf11afSPaul Mackerras /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ 83214cf11afSPaul Mackerras lis r3,0x8002 83314cf11afSPaul Mackerras rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ 83414cf11afSPaul Mackerras#else /* CONFIG_SMP */ 83514cf11afSPaul Mackerras /* Yield the processor. This is required for non-SMP kernels 83614cf11afSPaul Mackerras which are running on multi-threaded machines. */ 83714cf11afSPaul Mackerras lis r3,0x8000 83814cf11afSPaul Mackerras rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ 83914cf11afSPaul Mackerras addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ 84014cf11afSPaul Mackerras li r4,0 /* "yield timed" */ 84114cf11afSPaul Mackerras li r5,-1 /* "yield forever" */ 84214cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 84314cf11afSPaul Mackerras li r0,-1 /* r0=-1 indicates a Hypervisor call */ 84414cf11afSPaul Mackerras sc /* Invoke the hypervisor via a system call */ 845b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ 84614cf11afSPaul Mackerras b 1b /* If SMP not configured, secondaries 84714cf11afSPaul Mackerras * loop forever */ 84814cf11afSPaul Mackerras 84914cf11afSPaul Mackerras .globl decrementer_iSeries_masked 85014cf11afSPaul Mackerrasdecrementer_iSeries_masked: 851f9b4045dSMichael Ellerman /* We may not have a valid TOC pointer in here. */ 85214cf11afSPaul Mackerras li r11,1 8533356bb9fSDavid Gibson ld r12,PACALPPACAPTR(r13) 8543356bb9fSDavid Gibson stb r11,LPPACADECRINT(r12) 855f9b4045dSMichael Ellerman LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy) 856f9b4045dSMichael Ellerman lwz r12,0(r12) 85714cf11afSPaul Mackerras mtspr SPRN_DEC,r12 85814cf11afSPaul Mackerras /* fall through */ 85914cf11afSPaul Mackerras 86014cf11afSPaul Mackerras .globl hardware_interrupt_iSeries_masked 86114cf11afSPaul Mackerrashardware_interrupt_iSeries_masked: 86214cf11afSPaul Mackerras mtcrf 0x80,r9 /* Restore regs */ 8633356bb9fSDavid Gibson ld r12,PACALPPACAPTR(r13) 8643356bb9fSDavid Gibson ld r11,LPPACASRR0(r12) 8653356bb9fSDavid Gibson ld r12,LPPACASRR1(r12) 866b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r11 867b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r12 86814cf11afSPaul Mackerras ld r9,PACA_EXGEN+EX_R9(r13) 86914cf11afSPaul Mackerras ld r10,PACA_EXGEN+EX_R10(r13) 87014cf11afSPaul Mackerras ld r11,PACA_EXGEN+EX_R11(r13) 87114cf11afSPaul Mackerras ld r12,PACA_EXGEN+EX_R12(r13) 87214cf11afSPaul Mackerras ld r13,PACA_EXGEN+EX_R13(r13) 87314cf11afSPaul Mackerras rfid 87414cf11afSPaul Mackerras b . /* prevent speculative execution */ 87514cf11afSPaul Mackerras#endif /* CONFIG_PPC_ISERIES */ 87614cf11afSPaul Mackerras 87714cf11afSPaul Mackerras/*** Common interrupt handlers ***/ 87814cf11afSPaul Mackerras 87914cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) 88014cf11afSPaul Mackerras 88114cf11afSPaul Mackerras /* 88214cf11afSPaul Mackerras * Machine check is different because we use a different 88314cf11afSPaul Mackerras * save area: PACA_EXMC instead of PACA_EXGEN. 88414cf11afSPaul Mackerras */ 88514cf11afSPaul Mackerras .align 7 88614cf11afSPaul Mackerras .globl machine_check_common 88714cf11afSPaul Mackerrasmachine_check_common: 88814cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 889f39224a8SPaul Mackerras FINISH_NAP 89014cf11afSPaul Mackerras DISABLE_INTS 89114cf11afSPaul Mackerras bl .save_nvgprs 89214cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 89314cf11afSPaul Mackerras bl .machine_check_exception 89414cf11afSPaul Mackerras b .ret_from_except 89514cf11afSPaul Mackerras 89614cf11afSPaul Mackerras STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) 89714cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) 89814cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) 89914cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) 90014cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) 901f39224a8SPaul Mackerras STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) 90214cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) 90314cf11afSPaul Mackerras#ifdef CONFIG_ALTIVEC 90414cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) 90514cf11afSPaul Mackerras#else 90614cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) 90714cf11afSPaul Mackerras#endif 908acf7d768SBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 909acf7d768SBenjamin Herrenschmidt STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) 910acf7d768SBenjamin Herrenschmidt STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) 911acf7d768SBenjamin Herrenschmidt STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) 912acf7d768SBenjamin Herrenschmidt#endif /* CONFIG_CBE_RAS */ 91314cf11afSPaul Mackerras 91414cf11afSPaul Mackerras/* 91514cf11afSPaul Mackerras * Here we have detected that the kernel stack pointer is bad. 91614cf11afSPaul Mackerras * R9 contains the saved CR, r13 points to the paca, 91714cf11afSPaul Mackerras * r10 contains the (bad) kernel stack pointer, 91814cf11afSPaul Mackerras * r11 and r12 contain the saved SRR0 and SRR1. 91914cf11afSPaul Mackerras * We switch to using an emergency stack, save the registers there, 92014cf11afSPaul Mackerras * and call kernel_bad_stack(), which panics. 92114cf11afSPaul Mackerras */ 92214cf11afSPaul Mackerrasbad_stack: 92314cf11afSPaul Mackerras ld r1,PACAEMERGSP(r13) 92414cf11afSPaul Mackerras subi r1,r1,64+INT_FRAME_SIZE 92514cf11afSPaul Mackerras std r9,_CCR(r1) 92614cf11afSPaul Mackerras std r10,GPR1(r1) 92714cf11afSPaul Mackerras std r11,_NIP(r1) 92814cf11afSPaul Mackerras std r12,_MSR(r1) 929b5bbeb23SPaul Mackerras mfspr r11,SPRN_DAR 930b5bbeb23SPaul Mackerras mfspr r12,SPRN_DSISR 93114cf11afSPaul Mackerras std r11,_DAR(r1) 93214cf11afSPaul Mackerras std r12,_DSISR(r1) 93314cf11afSPaul Mackerras mflr r10 93414cf11afSPaul Mackerras mfctr r11 93514cf11afSPaul Mackerras mfxer r12 93614cf11afSPaul Mackerras std r10,_LINK(r1) 93714cf11afSPaul Mackerras std r11,_CTR(r1) 93814cf11afSPaul Mackerras std r12,_XER(r1) 93914cf11afSPaul Mackerras SAVE_GPR(0,r1) 94014cf11afSPaul Mackerras SAVE_GPR(2,r1) 94114cf11afSPaul Mackerras SAVE_4GPRS(3,r1) 94214cf11afSPaul Mackerras SAVE_2GPRS(7,r1) 94314cf11afSPaul Mackerras SAVE_10GPRS(12,r1) 94414cf11afSPaul Mackerras SAVE_10GPRS(22,r1) 94514cf11afSPaul Mackerras addi r11,r1,INT_FRAME_SIZE 94614cf11afSPaul Mackerras std r11,0(r1) 94714cf11afSPaul Mackerras li r12,0 94814cf11afSPaul Mackerras std r12,0(r11) 94914cf11afSPaul Mackerras ld r2,PACATOC(r13) 95014cf11afSPaul Mackerras1: addi r3,r1,STACK_FRAME_OVERHEAD 95114cf11afSPaul Mackerras bl .kernel_bad_stack 95214cf11afSPaul Mackerras b 1b 95314cf11afSPaul Mackerras 95414cf11afSPaul Mackerras/* 95514cf11afSPaul Mackerras * Return from an exception with minimal checks. 95614cf11afSPaul Mackerras * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. 95714cf11afSPaul Mackerras * If interrupts have been enabled, or anything has been 95814cf11afSPaul Mackerras * done that might have changed the scheduling status of 95914cf11afSPaul Mackerras * any task or sent any task a signal, you should use 96014cf11afSPaul Mackerras * ret_from_except or ret_from_except_lite instead of this. 96114cf11afSPaul Mackerras */ 962b0a779deSPaul Mackerrasfast_exc_return_irq: /* restores irq state too */ 963b0a779deSPaul Mackerras ld r3,SOFTE(r1) 964b0a779deSPaul Mackerras ld r12,_MSR(r1) 965b0a779deSPaul Mackerras stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */ 966b0a779deSPaul Mackerras rldicl r4,r12,49,63 /* get MSR_EE to LSB */ 967b0a779deSPaul Mackerras stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ 968b0a779deSPaul Mackerras b 1f 969b0a779deSPaul Mackerras 97040ef8cbcSPaul Mackerras .globl fast_exception_return 97114cf11afSPaul Mackerrasfast_exception_return: 97214cf11afSPaul Mackerras ld r12,_MSR(r1) 973b0a779deSPaul Mackerras1: ld r11,_NIP(r1) 97414cf11afSPaul Mackerras andi. r3,r12,MSR_RI /* check if RI is set */ 97514cf11afSPaul Mackerras beq- unrecov_fer 976c6622f63SPaul Mackerras 977c6622f63SPaul Mackerras#ifdef CONFIG_VIRT_CPU_ACCOUNTING 978c6622f63SPaul Mackerras andi. r3,r12,MSR_PR 979c6622f63SPaul Mackerras beq 2f 980c6622f63SPaul Mackerras ACCOUNT_CPU_USER_EXIT(r3, r4) 981c6622f63SPaul Mackerras2: 982c6622f63SPaul Mackerras#endif 983c6622f63SPaul Mackerras 98414cf11afSPaul Mackerras ld r3,_CCR(r1) 98514cf11afSPaul Mackerras ld r4,_LINK(r1) 98614cf11afSPaul Mackerras ld r5,_CTR(r1) 98714cf11afSPaul Mackerras ld r6,_XER(r1) 98814cf11afSPaul Mackerras mtcr r3 98914cf11afSPaul Mackerras mtlr r4 99014cf11afSPaul Mackerras mtctr r5 99114cf11afSPaul Mackerras mtxer r6 99214cf11afSPaul Mackerras REST_GPR(0, r1) 99314cf11afSPaul Mackerras REST_8GPRS(2, r1) 99414cf11afSPaul Mackerras 99514cf11afSPaul Mackerras mfmsr r10 996d04c56f7SPaul Mackerras rldicl r10,r10,48,1 /* clear EE */ 997d04c56f7SPaul Mackerras rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ 99814cf11afSPaul Mackerras mtmsrd r10,1 99914cf11afSPaul Mackerras 1000b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r12 1001b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r11 100214cf11afSPaul Mackerras REST_4GPRS(10, r1) 100314cf11afSPaul Mackerras ld r1,GPR1(r1) 100414cf11afSPaul Mackerras rfid 100514cf11afSPaul Mackerras b . /* prevent speculative execution */ 100614cf11afSPaul Mackerras 100714cf11afSPaul Mackerrasunrecov_fer: 100814cf11afSPaul Mackerras bl .save_nvgprs 100914cf11afSPaul Mackerras1: addi r3,r1,STACK_FRAME_OVERHEAD 101014cf11afSPaul Mackerras bl .unrecoverable_exception 101114cf11afSPaul Mackerras b 1b 101214cf11afSPaul Mackerras 101314cf11afSPaul Mackerras/* 101414cf11afSPaul Mackerras * Here r13 points to the paca, r9 contains the saved CR, 101514cf11afSPaul Mackerras * SRR0 and SRR1 are saved in r11 and r12, 101614cf11afSPaul Mackerras * r9 - r13 are saved in paca->exgen. 101714cf11afSPaul Mackerras */ 101814cf11afSPaul Mackerras .align 7 101914cf11afSPaul Mackerras .globl data_access_common 102014cf11afSPaul Mackerrasdata_access_common: 1021b5bbeb23SPaul Mackerras mfspr r10,SPRN_DAR 102214cf11afSPaul Mackerras std r10,PACA_EXGEN+EX_DAR(r13) 1023b5bbeb23SPaul Mackerras mfspr r10,SPRN_DSISR 102414cf11afSPaul Mackerras stw r10,PACA_EXGEN+EX_DSISR(r13) 102514cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 102614cf11afSPaul Mackerras ld r3,PACA_EXGEN+EX_DAR(r13) 102714cf11afSPaul Mackerras lwz r4,PACA_EXGEN+EX_DSISR(r13) 102814cf11afSPaul Mackerras li r5,0x300 102914cf11afSPaul Mackerras b .do_hash_page /* Try to handle as hpte fault */ 103014cf11afSPaul Mackerras 103114cf11afSPaul Mackerras .align 7 103214cf11afSPaul Mackerras .globl instruction_access_common 103314cf11afSPaul Mackerrasinstruction_access_common: 103414cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 103514cf11afSPaul Mackerras ld r3,_NIP(r1) 103614cf11afSPaul Mackerras andis. r4,r12,0x5820 103714cf11afSPaul Mackerras li r5,0x400 103814cf11afSPaul Mackerras b .do_hash_page /* Try to handle as hpte fault */ 103914cf11afSPaul Mackerras 10403c726f8dSBenjamin Herrenschmidt/* 10413c726f8dSBenjamin Herrenschmidt * Here is the common SLB miss user that is used when going to virtual 10423c726f8dSBenjamin Herrenschmidt * mode for SLB misses, that is currently not used 10433c726f8dSBenjamin Herrenschmidt */ 10443c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 10453c726f8dSBenjamin Herrenschmidt .align 7 10463c726f8dSBenjamin Herrenschmidt .globl slb_miss_user_common 10473c726f8dSBenjamin Herrenschmidtslb_miss_user_common: 10483c726f8dSBenjamin Herrenschmidt mflr r10 10493c726f8dSBenjamin Herrenschmidt std r3,PACA_EXGEN+EX_DAR(r13) 10503c726f8dSBenjamin Herrenschmidt stw r9,PACA_EXGEN+EX_CCR(r13) 10513c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_LR(r13) 10523c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_SRR0(r13) 10533c726f8dSBenjamin Herrenschmidt bl .slb_allocate_user 10543c726f8dSBenjamin Herrenschmidt 10553c726f8dSBenjamin Herrenschmidt ld r10,PACA_EXGEN+EX_LR(r13) 10563c726f8dSBenjamin Herrenschmidt ld r3,PACA_EXGEN+EX_R3(r13) 10573c726f8dSBenjamin Herrenschmidt lwz r9,PACA_EXGEN+EX_CCR(r13) 10583c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXGEN+EX_SRR0(r13) 10593c726f8dSBenjamin Herrenschmidt mtlr r10 10603c726f8dSBenjamin Herrenschmidt beq- slb_miss_fault 10613c726f8dSBenjamin Herrenschmidt 10623c726f8dSBenjamin Herrenschmidt andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 10633c726f8dSBenjamin Herrenschmidt beq- unrecov_user_slb 10643c726f8dSBenjamin Herrenschmidt mfmsr r10 10653c726f8dSBenjamin Herrenschmidt 10663c726f8dSBenjamin Herrenschmidt.machine push 10673c726f8dSBenjamin Herrenschmidt.machine "power4" 10683c726f8dSBenjamin Herrenschmidt mtcrf 0x80,r9 10693c726f8dSBenjamin Herrenschmidt.machine pop 10703c726f8dSBenjamin Herrenschmidt 10713c726f8dSBenjamin Herrenschmidt clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ 10723c726f8dSBenjamin Herrenschmidt mtmsrd r10,1 10733c726f8dSBenjamin Herrenschmidt 10743c726f8dSBenjamin Herrenschmidt mtspr SRR0,r11 10753c726f8dSBenjamin Herrenschmidt mtspr SRR1,r12 10763c726f8dSBenjamin Herrenschmidt 10773c726f8dSBenjamin Herrenschmidt ld r9,PACA_EXGEN+EX_R9(r13) 10783c726f8dSBenjamin Herrenschmidt ld r10,PACA_EXGEN+EX_R10(r13) 10793c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXGEN+EX_R11(r13) 10803c726f8dSBenjamin Herrenschmidt ld r12,PACA_EXGEN+EX_R12(r13) 10813c726f8dSBenjamin Herrenschmidt ld r13,PACA_EXGEN+EX_R13(r13) 10823c726f8dSBenjamin Herrenschmidt rfid 10833c726f8dSBenjamin Herrenschmidt b . 10843c726f8dSBenjamin Herrenschmidt 10853c726f8dSBenjamin Herrenschmidtslb_miss_fault: 10863c726f8dSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) 10873c726f8dSBenjamin Herrenschmidt ld r4,PACA_EXGEN+EX_DAR(r13) 10883c726f8dSBenjamin Herrenschmidt li r5,0 10893c726f8dSBenjamin Herrenschmidt std r4,_DAR(r1) 10903c726f8dSBenjamin Herrenschmidt std r5,_DSISR(r1) 10913ccfc65cSPaul Mackerras b handle_page_fault 10923c726f8dSBenjamin Herrenschmidt 10933c726f8dSBenjamin Herrenschmidtunrecov_user_slb: 10943c726f8dSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) 10953c726f8dSBenjamin Herrenschmidt DISABLE_INTS 10963c726f8dSBenjamin Herrenschmidt bl .save_nvgprs 10973c726f8dSBenjamin Herrenschmidt1: addi r3,r1,STACK_FRAME_OVERHEAD 10983c726f8dSBenjamin Herrenschmidt bl .unrecoverable_exception 10993c726f8dSBenjamin Herrenschmidt b 1b 11003c726f8dSBenjamin Herrenschmidt 11013c726f8dSBenjamin Herrenschmidt#endif /* __DISABLED__ */ 11023c726f8dSBenjamin Herrenschmidt 11033c726f8dSBenjamin Herrenschmidt 11043c726f8dSBenjamin Herrenschmidt/* 11053c726f8dSBenjamin Herrenschmidt * r13 points to the PACA, r9 contains the saved CR, 11063c726f8dSBenjamin Herrenschmidt * r12 contain the saved SRR1, SRR0 is still ready for return 11073c726f8dSBenjamin Herrenschmidt * r3 has the faulting address 11083c726f8dSBenjamin Herrenschmidt * r9 - r13 are saved in paca->exslb. 11093c726f8dSBenjamin Herrenschmidt * r3 is saved in paca->slb_r3 11103c726f8dSBenjamin Herrenschmidt * We assume we aren't going to take any exceptions during this procedure. 11113c726f8dSBenjamin Herrenschmidt */ 11123c726f8dSBenjamin Herrenschmidt_GLOBAL(slb_miss_realmode) 11133c726f8dSBenjamin Herrenschmidt mflr r10 11143c726f8dSBenjamin Herrenschmidt 11153c726f8dSBenjamin Herrenschmidt stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 11163c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 11173c726f8dSBenjamin Herrenschmidt 11183c726f8dSBenjamin Herrenschmidt bl .slb_allocate_realmode 11193c726f8dSBenjamin Herrenschmidt 11203c726f8dSBenjamin Herrenschmidt /* All done -- return from exception. */ 11213c726f8dSBenjamin Herrenschmidt 11223c726f8dSBenjamin Herrenschmidt ld r10,PACA_EXSLB+EX_LR(r13) 11233c726f8dSBenjamin Herrenschmidt ld r3,PACA_EXSLB+EX_R3(r13) 11243c726f8dSBenjamin Herrenschmidt lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 11253c726f8dSBenjamin Herrenschmidt#ifdef CONFIG_PPC_ISERIES 11263f639ee8SStephen RothwellBEGIN_FW_FTR_SECTION 11273356bb9fSDavid Gibson ld r11,PACALPPACAPTR(r13) 11283356bb9fSDavid Gibson ld r11,LPPACASRR0(r11) /* get SRR0 value */ 11293f639ee8SStephen RothwellEND_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 11303c726f8dSBenjamin Herrenschmidt#endif /* CONFIG_PPC_ISERIES */ 11313c726f8dSBenjamin Herrenschmidt 11323c726f8dSBenjamin Herrenschmidt mtlr r10 11333c726f8dSBenjamin Herrenschmidt 11343c726f8dSBenjamin Herrenschmidt andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 11353c726f8dSBenjamin Herrenschmidt beq- unrecov_slb 11363c726f8dSBenjamin Herrenschmidt 11373c726f8dSBenjamin Herrenschmidt.machine push 11383c726f8dSBenjamin Herrenschmidt.machine "power4" 11393c726f8dSBenjamin Herrenschmidt mtcrf 0x80,r9 11403c726f8dSBenjamin Herrenschmidt mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 11413c726f8dSBenjamin Herrenschmidt.machine pop 11423c726f8dSBenjamin Herrenschmidt 11433c726f8dSBenjamin Herrenschmidt#ifdef CONFIG_PPC_ISERIES 11443f639ee8SStephen RothwellBEGIN_FW_FTR_SECTION 11453c726f8dSBenjamin Herrenschmidt mtspr SPRN_SRR0,r11 11463c726f8dSBenjamin Herrenschmidt mtspr SPRN_SRR1,r12 11473f639ee8SStephen RothwellEND_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 11483c726f8dSBenjamin Herrenschmidt#endif /* CONFIG_PPC_ISERIES */ 11493c726f8dSBenjamin Herrenschmidt ld r9,PACA_EXSLB+EX_R9(r13) 11503c726f8dSBenjamin Herrenschmidt ld r10,PACA_EXSLB+EX_R10(r13) 11513c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXSLB+EX_R11(r13) 11523c726f8dSBenjamin Herrenschmidt ld r12,PACA_EXSLB+EX_R12(r13) 11533c726f8dSBenjamin Herrenschmidt ld r13,PACA_EXSLB+EX_R13(r13) 11543c726f8dSBenjamin Herrenschmidt rfid 11553c726f8dSBenjamin Herrenschmidt b . /* prevent speculative execution */ 11563c726f8dSBenjamin Herrenschmidt 11573c726f8dSBenjamin Herrenschmidtunrecov_slb: 11583c726f8dSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 11593c726f8dSBenjamin Herrenschmidt DISABLE_INTS 11603c726f8dSBenjamin Herrenschmidt bl .save_nvgprs 11613c726f8dSBenjamin Herrenschmidt1: addi r3,r1,STACK_FRAME_OVERHEAD 11623c726f8dSBenjamin Herrenschmidt bl .unrecoverable_exception 11633c726f8dSBenjamin Herrenschmidt b 1b 11643c726f8dSBenjamin Herrenschmidt 116514cf11afSPaul Mackerras .align 7 116614cf11afSPaul Mackerras .globl hardware_interrupt_common 116714cf11afSPaul Mackerras .globl hardware_interrupt_entry 116814cf11afSPaul Mackerrashardware_interrupt_common: 116914cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) 1170f39224a8SPaul Mackerras FINISH_NAP 117114cf11afSPaul Mackerrashardware_interrupt_entry: 117214cf11afSPaul Mackerras DISABLE_INTS 1173cb2c9b27SAnton Blanchard bl .ppc64_runlatch_on 117414cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 117514cf11afSPaul Mackerras bl .do_IRQ 117614cf11afSPaul Mackerras b .ret_from_except_lite 117714cf11afSPaul Mackerras 1178f39224a8SPaul Mackerras#ifdef CONFIG_PPC_970_NAP 1179f39224a8SPaul Mackerraspower4_fixup_nap: 1180f39224a8SPaul Mackerras andc r9,r9,r10 1181f39224a8SPaul Mackerras std r9,TI_LOCAL_FLAGS(r11) 1182f39224a8SPaul Mackerras ld r10,_LINK(r1) /* make idle task do the */ 1183f39224a8SPaul Mackerras std r10,_NIP(r1) /* equivalent of a blr */ 1184f39224a8SPaul Mackerras blr 1185f39224a8SPaul Mackerras#endif 1186f39224a8SPaul Mackerras 118714cf11afSPaul Mackerras .align 7 118814cf11afSPaul Mackerras .globl alignment_common 118914cf11afSPaul Mackerrasalignment_common: 1190b5bbeb23SPaul Mackerras mfspr r10,SPRN_DAR 119114cf11afSPaul Mackerras std r10,PACA_EXGEN+EX_DAR(r13) 1192b5bbeb23SPaul Mackerras mfspr r10,SPRN_DSISR 119314cf11afSPaul Mackerras stw r10,PACA_EXGEN+EX_DSISR(r13) 119414cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 119514cf11afSPaul Mackerras ld r3,PACA_EXGEN+EX_DAR(r13) 119614cf11afSPaul Mackerras lwz r4,PACA_EXGEN+EX_DSISR(r13) 119714cf11afSPaul Mackerras std r3,_DAR(r1) 119814cf11afSPaul Mackerras std r4,_DSISR(r1) 119914cf11afSPaul Mackerras bl .save_nvgprs 120014cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 120114cf11afSPaul Mackerras ENABLE_INTS 120214cf11afSPaul Mackerras bl .alignment_exception 120314cf11afSPaul Mackerras b .ret_from_except 120414cf11afSPaul Mackerras 120514cf11afSPaul Mackerras .align 7 120614cf11afSPaul Mackerras .globl program_check_common 120714cf11afSPaul Mackerrasprogram_check_common: 120814cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 120914cf11afSPaul Mackerras bl .save_nvgprs 121014cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 121114cf11afSPaul Mackerras ENABLE_INTS 121214cf11afSPaul Mackerras bl .program_check_exception 121314cf11afSPaul Mackerras b .ret_from_except 121414cf11afSPaul Mackerras 121514cf11afSPaul Mackerras .align 7 121614cf11afSPaul Mackerras .globl fp_unavailable_common 121714cf11afSPaul Mackerrasfp_unavailable_common: 121814cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 12193ccfc65cSPaul Mackerras bne 1f /* if from user, just load it up */ 122014cf11afSPaul Mackerras bl .save_nvgprs 122114cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 122214cf11afSPaul Mackerras ENABLE_INTS 122314cf11afSPaul Mackerras bl .kernel_fp_unavailable_exception 122414cf11afSPaul Mackerras BUG_OPCODE 12253ccfc65cSPaul Mackerras1: b .load_up_fpu 122614cf11afSPaul Mackerras 122714cf11afSPaul Mackerras .align 7 122814cf11afSPaul Mackerras .globl altivec_unavailable_common 122914cf11afSPaul Mackerrasaltivec_unavailable_common: 123014cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 123114cf11afSPaul Mackerras#ifdef CONFIG_ALTIVEC 123214cf11afSPaul MackerrasBEGIN_FTR_SECTION 123314cf11afSPaul Mackerras bne .load_up_altivec /* if from user, just load it up */ 123414cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 123514cf11afSPaul Mackerras#endif 123614cf11afSPaul Mackerras bl .save_nvgprs 123714cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 123814cf11afSPaul Mackerras ENABLE_INTS 123914cf11afSPaul Mackerras bl .altivec_unavailable_exception 124014cf11afSPaul Mackerras b .ret_from_except 124114cf11afSPaul Mackerras 124214cf11afSPaul Mackerras#ifdef CONFIG_ALTIVEC 124314cf11afSPaul Mackerras/* 124414cf11afSPaul Mackerras * load_up_altivec(unused, unused, tsk) 124514cf11afSPaul Mackerras * Disable VMX for the task which had it previously, 124614cf11afSPaul Mackerras * and save its vector registers in its thread_struct. 124714cf11afSPaul Mackerras * Enables the VMX for use in the kernel on return. 124814cf11afSPaul Mackerras * On SMP we know the VMX is free, since we give it up every 124914cf11afSPaul Mackerras * switch (ie, no lazy save of the vector registers). 125014cf11afSPaul Mackerras * On entry: r13 == 'current' && last_task_used_altivec != 'current' 125114cf11afSPaul Mackerras */ 125214cf11afSPaul Mackerras_STATIC(load_up_altivec) 125314cf11afSPaul Mackerras mfmsr r5 /* grab the current MSR */ 125414cf11afSPaul Mackerras oris r5,r5,MSR_VEC@h 125514cf11afSPaul Mackerras mtmsrd r5 /* enable use of VMX now */ 125614cf11afSPaul Mackerras isync 125714cf11afSPaul Mackerras 125814cf11afSPaul Mackerras/* 125914cf11afSPaul Mackerras * For SMP, we don't do lazy VMX switching because it just gets too 126014cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 126114cf11afSPaul Mackerras * to another. Instead we call giveup_altvec in switch_to. 126214cf11afSPaul Mackerras * VRSAVE isn't dealt with here, that is done in the normal context 126314cf11afSPaul Mackerras * switch code. Note that we could rely on vrsave value to eventually 126414cf11afSPaul Mackerras * avoid saving all of the VREGs here... 126514cf11afSPaul Mackerras */ 126614cf11afSPaul Mackerras#ifndef CONFIG_SMP 126714cf11afSPaul Mackerras ld r3,last_task_used_altivec@got(r2) 126814cf11afSPaul Mackerras ld r4,0(r3) 126914cf11afSPaul Mackerras cmpdi 0,r4,0 127014cf11afSPaul Mackerras beq 1f 127114cf11afSPaul Mackerras /* Save VMX state to last_task_used_altivec's THREAD struct */ 127214cf11afSPaul Mackerras addi r4,r4,THREAD 127314cf11afSPaul Mackerras SAVE_32VRS(0,r5,r4) 127414cf11afSPaul Mackerras mfvscr vr0 127514cf11afSPaul Mackerras li r10,THREAD_VSCR 127614cf11afSPaul Mackerras stvx vr0,r10,r4 127714cf11afSPaul Mackerras /* Disable VMX for last_task_used_altivec */ 127814cf11afSPaul Mackerras ld r5,PT_REGS(r4) 127914cf11afSPaul Mackerras ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 128014cf11afSPaul Mackerras lis r6,MSR_VEC@h 128114cf11afSPaul Mackerras andc r4,r4,r6 128214cf11afSPaul Mackerras std r4,_MSR-STACK_FRAME_OVERHEAD(r5) 128314cf11afSPaul Mackerras1: 128414cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 128514cf11afSPaul Mackerras /* Hack: if we get an altivec unavailable trap with VRSAVE 128614cf11afSPaul Mackerras * set to all zeros, we assume this is a broken application 128714cf11afSPaul Mackerras * that fails to set it properly, and thus we switch it to 128814cf11afSPaul Mackerras * all 1's 128914cf11afSPaul Mackerras */ 129014cf11afSPaul Mackerras mfspr r4,SPRN_VRSAVE 129114cf11afSPaul Mackerras cmpdi 0,r4,0 129214cf11afSPaul Mackerras bne+ 1f 129314cf11afSPaul Mackerras li r4,-1 129414cf11afSPaul Mackerras mtspr SPRN_VRSAVE,r4 129514cf11afSPaul Mackerras1: 129614cf11afSPaul Mackerras /* enable use of VMX after return */ 129714cf11afSPaul Mackerras ld r4,PACACURRENT(r13) 129814cf11afSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 129914cf11afSPaul Mackerras oris r12,r12,MSR_VEC@h 130014cf11afSPaul Mackerras std r12,_MSR(r1) 130114cf11afSPaul Mackerras li r4,1 130214cf11afSPaul Mackerras li r10,THREAD_VSCR 130314cf11afSPaul Mackerras stw r4,THREAD_USED_VR(r5) 130414cf11afSPaul Mackerras lvx vr0,r10,r5 130514cf11afSPaul Mackerras mtvscr vr0 130614cf11afSPaul Mackerras REST_32VRS(0,r4,r5) 130714cf11afSPaul Mackerras#ifndef CONFIG_SMP 130814cf11afSPaul Mackerras /* Update last_task_used_math to 'current' */ 130914cf11afSPaul Mackerras subi r4,r5,THREAD /* Back to 'current' */ 131014cf11afSPaul Mackerras std r4,0(r3) 131114cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 131214cf11afSPaul Mackerras /* restore registers and return */ 131314cf11afSPaul Mackerras b fast_exception_return 131414cf11afSPaul Mackerras#endif /* CONFIG_ALTIVEC */ 131514cf11afSPaul Mackerras 131614cf11afSPaul Mackerras/* 131714cf11afSPaul Mackerras * Hash table stuff 131814cf11afSPaul Mackerras */ 131914cf11afSPaul Mackerras .align 7 132014cf11afSPaul Mackerras_GLOBAL(do_hash_page) 132114cf11afSPaul Mackerras std r3,_DAR(r1) 132214cf11afSPaul Mackerras std r4,_DSISR(r1) 132314cf11afSPaul Mackerras 132414cf11afSPaul Mackerras andis. r0,r4,0xa450 /* weird error? */ 13253ccfc65cSPaul Mackerras bne- handle_page_fault /* if not, try to insert a HPTE */ 132614cf11afSPaul MackerrasBEGIN_FTR_SECTION 132714cf11afSPaul Mackerras andis. r0,r4,0x0020 /* Is it a segment table fault? */ 13283ccfc65cSPaul Mackerras bne- do_ste_alloc /* If so handle it */ 132914cf11afSPaul MackerrasEND_FTR_SECTION_IFCLR(CPU_FTR_SLB) 133014cf11afSPaul Mackerras 133114cf11afSPaul Mackerras /* 133214cf11afSPaul Mackerras * We need to set the _PAGE_USER bit if MSR_PR is set or if we are 133314cf11afSPaul Mackerras * accessing a userspace segment (even from the kernel). We assume 133414cf11afSPaul Mackerras * kernel addresses always have the high bit set. 133514cf11afSPaul Mackerras */ 133614cf11afSPaul Mackerras rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ 133714cf11afSPaul Mackerras rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ 133814cf11afSPaul Mackerras orc r0,r12,r0 /* MSR_PR | ~high_bit */ 133914cf11afSPaul Mackerras rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ 134014cf11afSPaul Mackerras ori r4,r4,1 /* add _PAGE_PRESENT */ 134114cf11afSPaul Mackerras rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ 134214cf11afSPaul Mackerras 134314cf11afSPaul Mackerras /* 134414cf11afSPaul Mackerras * On iSeries, we soft-disable interrupts here, then 134514cf11afSPaul Mackerras * hard-enable interrupts so that the hash_page code can spin on 134614cf11afSPaul Mackerras * the hash_table_lock without problems on a shared processor. 134714cf11afSPaul Mackerras */ 134814cf11afSPaul Mackerras DISABLE_INTS 134914cf11afSPaul Mackerras 135014cf11afSPaul Mackerras /* 135114cf11afSPaul Mackerras * r3 contains the faulting address 135214cf11afSPaul Mackerras * r4 contains the required access permissions 135314cf11afSPaul Mackerras * r5 contains the trap number 135414cf11afSPaul Mackerras * 135514cf11afSPaul Mackerras * at return r3 = 0 for success 135614cf11afSPaul Mackerras */ 135714cf11afSPaul Mackerras bl .hash_page /* build HPTE if possible */ 135814cf11afSPaul Mackerras cmpdi r3,0 /* see if hash_page succeeded */ 135914cf11afSPaul Mackerras 136014cf11afSPaul Mackerras#ifdef DO_SOFT_DISABLE 13613f639ee8SStephen RothwellBEGIN_FW_FTR_SECTION 136214cf11afSPaul Mackerras /* 136314cf11afSPaul Mackerras * If we had interrupts soft-enabled at the point where the 136414cf11afSPaul Mackerras * DSI/ISI occurred, and an interrupt came in during hash_page, 136514cf11afSPaul Mackerras * handle it now. 136614cf11afSPaul Mackerras * We jump to ret_from_except_lite rather than fast_exception_return 136714cf11afSPaul Mackerras * because ret_from_except_lite will check for and handle pending 136814cf11afSPaul Mackerras * interrupts if necessary. 136914cf11afSPaul Mackerras */ 13703ccfc65cSPaul Mackerras beq 13f 1371b0a779deSPaul MackerrasEND_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1372b0a779deSPaul Mackerras#endif 1373b0a779deSPaul MackerrasBEGIN_FW_FTR_SECTION 1374b0a779deSPaul Mackerras /* 1375b0a779deSPaul Mackerras * Here we have interrupts hard-disabled, so it is sufficient 1376b0a779deSPaul Mackerras * to restore paca->{soft,hard}_enable and get out. 1377b0a779deSPaul Mackerras */ 1378b0a779deSPaul Mackerras beq fast_exc_return_irq /* Return from exception on success */ 1379b0a779deSPaul MackerrasEND_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1380b0a779deSPaul Mackerras 138114cf11afSPaul Mackerras /* For a hash failure, we don't bother re-enabling interrupts */ 138214cf11afSPaul Mackerras ble- 12f 138314cf11afSPaul Mackerras 138414cf11afSPaul Mackerras /* 138514cf11afSPaul Mackerras * hash_page couldn't handle it, set soft interrupt enable back 138614cf11afSPaul Mackerras * to what it was before the trap. Note that .local_irq_restore 138714cf11afSPaul Mackerras * handles any interrupts pending at this point. 138814cf11afSPaul Mackerras */ 138914cf11afSPaul Mackerras ld r3,SOFTE(r1) 139014cf11afSPaul Mackerras bl .local_irq_restore 139114cf11afSPaul Mackerras b 11f 139214cf11afSPaul Mackerras 139314cf11afSPaul Mackerras/* Here we have a page fault that hash_page can't handle. */ 13943ccfc65cSPaul Mackerrashandle_page_fault: 139514cf11afSPaul Mackerras ENABLE_INTS 139614cf11afSPaul Mackerras11: ld r4,_DAR(r1) 139714cf11afSPaul Mackerras ld r5,_DSISR(r1) 139814cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 139914cf11afSPaul Mackerras bl .do_page_fault 140014cf11afSPaul Mackerras cmpdi r3,0 14013ccfc65cSPaul Mackerras beq+ 13f 140214cf11afSPaul Mackerras bl .save_nvgprs 140314cf11afSPaul Mackerras mr r5,r3 140414cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 140514cf11afSPaul Mackerras lwz r4,_DAR(r1) 140614cf11afSPaul Mackerras bl .bad_page_fault 140714cf11afSPaul Mackerras b .ret_from_except 140814cf11afSPaul Mackerras 140979acbb3fSPaul Mackerras13: b .ret_from_except_lite 141079acbb3fSPaul Mackerras 141114cf11afSPaul Mackerras/* We have a page fault that hash_page could handle but HV refused 141214cf11afSPaul Mackerras * the PTE insertion 141314cf11afSPaul Mackerras */ 141414cf11afSPaul Mackerras12: bl .save_nvgprs 141514cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 141614cf11afSPaul Mackerras lwz r4,_DAR(r1) 141714cf11afSPaul Mackerras bl .low_hash_fault 141814cf11afSPaul Mackerras b .ret_from_except 141914cf11afSPaul Mackerras 142014cf11afSPaul Mackerras /* here we have a segment miss */ 14213ccfc65cSPaul Mackerrasdo_ste_alloc: 142214cf11afSPaul Mackerras bl .ste_allocate /* try to insert stab entry */ 142314cf11afSPaul Mackerras cmpdi r3,0 14243ccfc65cSPaul Mackerras bne- handle_page_fault 14253ccfc65cSPaul Mackerras b fast_exception_return 142614cf11afSPaul Mackerras 142714cf11afSPaul Mackerras/* 142814cf11afSPaul Mackerras * r13 points to the PACA, r9 contains the saved CR, 142914cf11afSPaul Mackerras * r11 and r12 contain the saved SRR0 and SRR1. 143014cf11afSPaul Mackerras * r9 - r13 are saved in paca->exslb. 143114cf11afSPaul Mackerras * We assume we aren't going to take any exceptions during this procedure. 143214cf11afSPaul Mackerras * We assume (DAR >> 60) == 0xc. 143314cf11afSPaul Mackerras */ 143414cf11afSPaul Mackerras .align 7 143514cf11afSPaul Mackerras_GLOBAL(do_stab_bolted) 143614cf11afSPaul Mackerras stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 143714cf11afSPaul Mackerras std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ 143814cf11afSPaul Mackerras 143914cf11afSPaul Mackerras /* Hash to the primary group */ 144014cf11afSPaul Mackerras ld r10,PACASTABVIRT(r13) 1441b5bbeb23SPaul Mackerras mfspr r11,SPRN_DAR 144214cf11afSPaul Mackerras srdi r11,r11,28 144314cf11afSPaul Mackerras rldimi r10,r11,7,52 /* r10 = first ste of the group */ 144414cf11afSPaul Mackerras 144514cf11afSPaul Mackerras /* Calculate VSID */ 144614cf11afSPaul Mackerras /* This is a kernel address, so protovsid = ESID */ 144714cf11afSPaul Mackerras ASM_VSID_SCRAMBLE(r11, r9) 144814cf11afSPaul Mackerras rldic r9,r11,12,16 /* r9 = vsid << 12 */ 144914cf11afSPaul Mackerras 145014cf11afSPaul Mackerras /* Search the primary group for a free entry */ 145114cf11afSPaul Mackerras1: ld r11,0(r10) /* Test valid bit of the current ste */ 145214cf11afSPaul Mackerras andi. r11,r11,0x80 145314cf11afSPaul Mackerras beq 2f 145414cf11afSPaul Mackerras addi r10,r10,16 145514cf11afSPaul Mackerras andi. r11,r10,0x70 145614cf11afSPaul Mackerras bne 1b 145714cf11afSPaul Mackerras 145814cf11afSPaul Mackerras /* Stick for only searching the primary group for now. */ 145914cf11afSPaul Mackerras /* At least for now, we use a very simple random castout scheme */ 146014cf11afSPaul Mackerras /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ 146114cf11afSPaul Mackerras mftb r11 146214cf11afSPaul Mackerras rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ 146314cf11afSPaul Mackerras ori r11,r11,0x10 146414cf11afSPaul Mackerras 146514cf11afSPaul Mackerras /* r10 currently points to an ste one past the group of interest */ 146614cf11afSPaul Mackerras /* make it point to the randomly selected entry */ 146714cf11afSPaul Mackerras subi r10,r10,128 146814cf11afSPaul Mackerras or r10,r10,r11 /* r10 is the entry to invalidate */ 146914cf11afSPaul Mackerras 147014cf11afSPaul Mackerras isync /* mark the entry invalid */ 147114cf11afSPaul Mackerras ld r11,0(r10) 147214cf11afSPaul Mackerras rldicl r11,r11,56,1 /* clear the valid bit */ 147314cf11afSPaul Mackerras rotldi r11,r11,8 147414cf11afSPaul Mackerras std r11,0(r10) 147514cf11afSPaul Mackerras sync 147614cf11afSPaul Mackerras 147714cf11afSPaul Mackerras clrrdi r11,r11,28 /* Get the esid part of the ste */ 147814cf11afSPaul Mackerras slbie r11 147914cf11afSPaul Mackerras 148014cf11afSPaul Mackerras2: std r9,8(r10) /* Store the vsid part of the ste */ 148114cf11afSPaul Mackerras eieio 148214cf11afSPaul Mackerras 1483b5bbeb23SPaul Mackerras mfspr r11,SPRN_DAR /* Get the new esid */ 148414cf11afSPaul Mackerras clrrdi r11,r11,28 /* Permits a full 32b of ESID */ 148514cf11afSPaul Mackerras ori r11,r11,0x90 /* Turn on valid and kp */ 148614cf11afSPaul Mackerras std r11,0(r10) /* Put new entry back into the stab */ 148714cf11afSPaul Mackerras 148814cf11afSPaul Mackerras sync 148914cf11afSPaul Mackerras 149014cf11afSPaul Mackerras /* All done -- return from exception. */ 149114cf11afSPaul Mackerras lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 149214cf11afSPaul Mackerras ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ 149314cf11afSPaul Mackerras 149414cf11afSPaul Mackerras andi. r10,r12,MSR_RI 149514cf11afSPaul Mackerras beq- unrecov_slb 149614cf11afSPaul Mackerras 149714cf11afSPaul Mackerras mtcrf 0x80,r9 /* restore CR */ 149814cf11afSPaul Mackerras 149914cf11afSPaul Mackerras mfmsr r10 150014cf11afSPaul Mackerras clrrdi r10,r10,2 150114cf11afSPaul Mackerras mtmsrd r10,1 150214cf11afSPaul Mackerras 1503b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r11 1504b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r12 150514cf11afSPaul Mackerras ld r9,PACA_EXSLB+EX_R9(r13) 150614cf11afSPaul Mackerras ld r10,PACA_EXSLB+EX_R10(r13) 150714cf11afSPaul Mackerras ld r11,PACA_EXSLB+EX_R11(r13) 150814cf11afSPaul Mackerras ld r12,PACA_EXSLB+EX_R12(r13) 150914cf11afSPaul Mackerras ld r13,PACA_EXSLB+EX_R13(r13) 151014cf11afSPaul Mackerras rfid 151114cf11afSPaul Mackerras b . /* prevent speculative execution */ 151214cf11afSPaul Mackerras 151314cf11afSPaul Mackerras/* 151414cf11afSPaul Mackerras * Space for CPU0's segment table. 151514cf11afSPaul Mackerras * 151614cf11afSPaul Mackerras * On iSeries, the hypervisor must fill in at least one entry before 151714cf11afSPaul Mackerras * we get control (with relocate on). The address is give to the hv 1518ee400b63SStephen Rothwell * as a page number (see xLparMap in lpardata.c), so this must be at a 151914cf11afSPaul Mackerras * fixed address (the linker can't compute (u64)&initial_stab >> 152014cf11afSPaul Mackerras * PAGE_SHIFT). 152114cf11afSPaul Mackerras */ 1522758438a7SMichael Ellerman . = STAB0_OFFSET /* 0x6000 */ 152314cf11afSPaul Mackerras .globl initial_stab 152414cf11afSPaul Mackerrasinitial_stab: 152514cf11afSPaul Mackerras .space 4096 152614cf11afSPaul Mackerras 152714cf11afSPaul Mackerras/* 152814cf11afSPaul Mackerras * Data area reserved for FWNMI option. 152914cf11afSPaul Mackerras * This address (0x7000) is fixed by the RPA. 153014cf11afSPaul Mackerras */ 153114cf11afSPaul Mackerras .= 0x7000 153214cf11afSPaul Mackerras .globl fwnmi_data_area 153314cf11afSPaul Mackerrasfwnmi_data_area: 153414cf11afSPaul Mackerras 153514cf11afSPaul Mackerras /* iSeries does not use the FWNMI stuff, so it is safe to put 153614cf11afSPaul Mackerras * this here, even if we later allow kernels that will boot on 153714cf11afSPaul Mackerras * both pSeries and iSeries */ 153814cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 153914cf11afSPaul Mackerras . = LPARMAP_PHYS 154014cf11afSPaul Mackerras#include "lparmap.s" 154114cf11afSPaul Mackerras/* 154214cf11afSPaul Mackerras * This ".text" is here for old compilers that generate a trailing 154314cf11afSPaul Mackerras * .note section when compiling .c files to .s 154414cf11afSPaul Mackerras */ 154514cf11afSPaul Mackerras .text 154614cf11afSPaul Mackerras#endif /* CONFIG_PPC_ISERIES */ 154714cf11afSPaul Mackerras 154814cf11afSPaul Mackerras . = 0x8000 154914cf11afSPaul Mackerras 155014cf11afSPaul Mackerras/* 1551f39b7a55SOlof Johansson * On pSeries and most other platforms, secondary processors spin 1552f39b7a55SOlof Johansson * in the following code. 155314cf11afSPaul Mackerras * At entry, r3 = this processor's number (physical cpu id) 155414cf11afSPaul Mackerras */ 1555f39b7a55SOlof Johansson_GLOBAL(generic_secondary_smp_init) 155614cf11afSPaul Mackerras mr r24,r3 155714cf11afSPaul Mackerras 155814cf11afSPaul Mackerras /* turn on 64-bit mode */ 155914cf11afSPaul Mackerras bl .enable_64b_mode 156014cf11afSPaul Mackerras isync 156114cf11afSPaul Mackerras 156214cf11afSPaul Mackerras /* Set up a paca value for this processor. Since we have the 156314cf11afSPaul Mackerras * physical cpu id in r24, we need to search the pacas to find 156414cf11afSPaul Mackerras * which logical id maps to our physical one. 156514cf11afSPaul Mackerras */ 1566e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */ 156714cf11afSPaul Mackerras li r5,0 /* logical cpu id */ 156814cf11afSPaul Mackerras1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 156914cf11afSPaul Mackerras cmpw r6,r24 /* Compare to our id */ 157014cf11afSPaul Mackerras beq 2f 157114cf11afSPaul Mackerras addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 157214cf11afSPaul Mackerras addi r5,r5,1 157314cf11afSPaul Mackerras cmpwi r5,NR_CPUS 157414cf11afSPaul Mackerras blt 1b 157514cf11afSPaul Mackerras 157614cf11afSPaul Mackerras mr r3,r24 /* not found, copy phys to r3 */ 157714cf11afSPaul Mackerras b .kexec_wait /* next kernel might do better */ 157814cf11afSPaul Mackerras 1579b5bbeb23SPaul Mackerras2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 158014cf11afSPaul Mackerras /* From now on, r24 is expected to be logical cpuid */ 158114cf11afSPaul Mackerras mr r24,r5 158214cf11afSPaul Mackerras3: HMT_LOW 158314cf11afSPaul Mackerras lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 158414cf11afSPaul Mackerras /* start. */ 158514cf11afSPaul Mackerras sync 158614cf11afSPaul Mackerras 1587f39b7a55SOlof Johansson#ifndef CONFIG_SMP 1588f39b7a55SOlof Johansson b 3b /* Never go on non-SMP */ 1589f39b7a55SOlof Johansson#else 1590f39b7a55SOlof Johansson cmpwi 0,r23,0 1591f39b7a55SOlof Johansson beq 3b /* Loop until told to go */ 1592f39b7a55SOlof Johansson 1593f39b7a55SOlof Johansson /* See if we need to call a cpu state restore handler */ 1594f39b7a55SOlof Johansson LOAD_REG_IMMEDIATE(r23, cur_cpu_spec) 1595f39b7a55SOlof Johansson ld r23,0(r23) 1596f39b7a55SOlof Johansson ld r23,CPU_SPEC_RESTORE(r23) 1597f39b7a55SOlof Johansson cmpdi 0,r23,0 1598f39b7a55SOlof Johansson beq 4f 1599f39b7a55SOlof Johansson ld r23,0(r23) 1600f39b7a55SOlof Johansson mtctr r23 1601f39b7a55SOlof Johansson bctrl 1602f39b7a55SOlof Johansson 1603f39b7a55SOlof Johansson4: /* Create a temp kernel stack for use before relocation is on. */ 160414cf11afSPaul Mackerras ld r1,PACAEMERGSP(r13) 160514cf11afSPaul Mackerras subi r1,r1,STACK_FRAME_OVERHEAD 160614cf11afSPaul Mackerras 1607f39b7a55SOlof Johansson b .__secondary_start 160814cf11afSPaul Mackerras#endif 160914cf11afSPaul Mackerras 161014cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 161114cf11afSPaul Mackerras_STATIC(__start_initialization_iSeries) 161214cf11afSPaul Mackerras /* Clear out the BSS */ 1613e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r11,__bss_stop) 1614e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r8,__bss_start) 161514cf11afSPaul Mackerras sub r11,r11,r8 /* bss size */ 161614cf11afSPaul Mackerras addi r11,r11,7 /* round up to an even double word */ 161714cf11afSPaul Mackerras rldicl. r11,r11,61,3 /* shift right by 3 */ 161814cf11afSPaul Mackerras beq 4f 161914cf11afSPaul Mackerras addi r8,r8,-8 162014cf11afSPaul Mackerras li r0,0 162114cf11afSPaul Mackerras mtctr r11 /* zero this many doublewords */ 162214cf11afSPaul Mackerras3: stdu r0,8(r8) 162314cf11afSPaul Mackerras bdnz 3b 162414cf11afSPaul Mackerras4: 1625e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r1,init_thread_union) 162614cf11afSPaul Mackerras addi r1,r1,THREAD_SIZE 162714cf11afSPaul Mackerras li r0,0 162814cf11afSPaul Mackerras stdu r0,-STACK_FRAME_OVERHEAD(r1) 162914cf11afSPaul Mackerras 1630e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r2,__toc_start) 163114cf11afSPaul Mackerras addi r2,r2,0x4000 163214cf11afSPaul Mackerras addi r2,r2,0x4000 163314cf11afSPaul Mackerras 163414cf11afSPaul Mackerras bl .iSeries_early_setup 1635ee400b63SStephen Rothwell bl .early_setup 163614cf11afSPaul Mackerras 163714cf11afSPaul Mackerras /* relocation is on at this point */ 163814cf11afSPaul Mackerras 163914cf11afSPaul Mackerras b .start_here_common 164014cf11afSPaul Mackerras#endif /* CONFIG_PPC_ISERIES */ 164114cf11afSPaul Mackerras 164214cf11afSPaul Mackerras 164314cf11afSPaul Mackerras_STATIC(__mmu_off) 164414cf11afSPaul Mackerras mfmsr r3 164514cf11afSPaul Mackerras andi. r0,r3,MSR_IR|MSR_DR 164614cf11afSPaul Mackerras beqlr 164714cf11afSPaul Mackerras andc r3,r3,r0 164814cf11afSPaul Mackerras mtspr SPRN_SRR0,r4 164914cf11afSPaul Mackerras mtspr SPRN_SRR1,r3 165014cf11afSPaul Mackerras sync 165114cf11afSPaul Mackerras rfid 165214cf11afSPaul Mackerras b . /* prevent speculative execution */ 165314cf11afSPaul Mackerras 165414cf11afSPaul Mackerras 165514cf11afSPaul Mackerras/* 165614cf11afSPaul Mackerras * Here is our main kernel entry point. We support currently 2 kind of entries 165714cf11afSPaul Mackerras * depending on the value of r5. 165814cf11afSPaul Mackerras * 165914cf11afSPaul Mackerras * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 166014cf11afSPaul Mackerras * in r3...r7 166114cf11afSPaul Mackerras * 166214cf11afSPaul Mackerras * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 166314cf11afSPaul Mackerras * DT block, r4 is a physical pointer to the kernel itself 166414cf11afSPaul Mackerras * 166514cf11afSPaul Mackerras */ 166614cf11afSPaul Mackerras_GLOBAL(__start_initialization_multiplatform) 166714cf11afSPaul Mackerras /* 166814cf11afSPaul Mackerras * Are we booted from a PROM Of-type client-interface ? 166914cf11afSPaul Mackerras */ 167014cf11afSPaul Mackerras cmpldi cr0,r5,0 167114cf11afSPaul Mackerras bne .__boot_from_prom /* yes -> prom */ 167214cf11afSPaul Mackerras 167314cf11afSPaul Mackerras /* Save parameters */ 167414cf11afSPaul Mackerras mr r31,r3 167514cf11afSPaul Mackerras mr r30,r4 167614cf11afSPaul Mackerras 167714cf11afSPaul Mackerras /* Make sure we are running in 64 bits mode */ 167814cf11afSPaul Mackerras bl .enable_64b_mode 167914cf11afSPaul Mackerras 168014cf11afSPaul Mackerras /* Setup some critical 970 SPRs before switching MMU off */ 1681f39b7a55SOlof Johansson mfspr r0,SPRN_PVR 1682f39b7a55SOlof Johansson srwi r0,r0,16 1683f39b7a55SOlof Johansson cmpwi r0,0x39 /* 970 */ 1684f39b7a55SOlof Johansson beq 1f 1685f39b7a55SOlof Johansson cmpwi r0,0x3c /* 970FX */ 1686f39b7a55SOlof Johansson beq 1f 1687f39b7a55SOlof Johansson cmpwi r0,0x44 /* 970MP */ 1688190a24f5SOlof Johansson beq 1f 1689190a24f5SOlof Johansson cmpwi r0,0x45 /* 970GX */ 1690f39b7a55SOlof Johansson bne 2f 1691f39b7a55SOlof Johansson1: bl .__cpu_preinit_ppc970 1692f39b7a55SOlof Johansson2: 169314cf11afSPaul Mackerras 169414cf11afSPaul Mackerras /* Switch off MMU if not already */ 1695e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE) 169614cf11afSPaul Mackerras add r4,r4,r30 169714cf11afSPaul Mackerras bl .__mmu_off 169814cf11afSPaul Mackerras b .__after_prom_start 169914cf11afSPaul Mackerras 170014cf11afSPaul Mackerras_STATIC(__boot_from_prom) 170114cf11afSPaul Mackerras /* Save parameters */ 170214cf11afSPaul Mackerras mr r31,r3 170314cf11afSPaul Mackerras mr r30,r4 170414cf11afSPaul Mackerras mr r29,r5 170514cf11afSPaul Mackerras mr r28,r6 170614cf11afSPaul Mackerras mr r27,r7 170714cf11afSPaul Mackerras 17086088857bSOlaf Hering /* 17096088857bSOlaf Hering * Align the stack to 16-byte boundary 17106088857bSOlaf Hering * Depending on the size and layout of the ELF sections in the initial 17116088857bSOlaf Hering * boot binary, the stack pointer will be unalignet on PowerMac 17126088857bSOlaf Hering */ 1713c05b4770SLinus Torvalds rldicr r1,r1,0,59 1714c05b4770SLinus Torvalds 171514cf11afSPaul Mackerras /* Make sure we are running in 64 bits mode */ 171614cf11afSPaul Mackerras bl .enable_64b_mode 171714cf11afSPaul Mackerras 171814cf11afSPaul Mackerras /* put a relocation offset into r3 */ 171914cf11afSPaul Mackerras bl .reloc_offset 172014cf11afSPaul Mackerras 1721e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r2,__toc_start) 172214cf11afSPaul Mackerras addi r2,r2,0x4000 172314cf11afSPaul Mackerras addi r2,r2,0x4000 172414cf11afSPaul Mackerras 172514cf11afSPaul Mackerras /* Relocate the TOC from a virt addr to a real addr */ 17265a408329SPaul Mackerras add r2,r2,r3 172714cf11afSPaul Mackerras 172814cf11afSPaul Mackerras /* Restore parameters */ 172914cf11afSPaul Mackerras mr r3,r31 173014cf11afSPaul Mackerras mr r4,r30 173114cf11afSPaul Mackerras mr r5,r29 173214cf11afSPaul Mackerras mr r6,r28 173314cf11afSPaul Mackerras mr r7,r27 173414cf11afSPaul Mackerras 173514cf11afSPaul Mackerras /* Do all of the interaction with OF client interface */ 173614cf11afSPaul Mackerras bl .prom_init 173714cf11afSPaul Mackerras /* We never return */ 173814cf11afSPaul Mackerras trap 173914cf11afSPaul Mackerras 174014cf11afSPaul Mackerras/* 174114cf11afSPaul Mackerras * At this point, r3 contains the physical address we are running at, 174214cf11afSPaul Mackerras * returned by prom_init() 174314cf11afSPaul Mackerras */ 174414cf11afSPaul Mackerras_STATIC(__after_prom_start) 174514cf11afSPaul Mackerras 174614cf11afSPaul Mackerras/* 1747758438a7SMichael Ellerman * We need to run with __start at physical address PHYSICAL_START. 174814cf11afSPaul Mackerras * This will leave some code in the first 256B of 174914cf11afSPaul Mackerras * real memory, which are reserved for software use. 175014cf11afSPaul Mackerras * The remainder of the first page is loaded with the fixed 175114cf11afSPaul Mackerras * interrupt vectors. The next two pages are filled with 175214cf11afSPaul Mackerras * unknown exception placeholders. 175314cf11afSPaul Mackerras * 175414cf11afSPaul Mackerras * Note: This process overwrites the OF exception vectors. 175514cf11afSPaul Mackerras * r26 == relocation offset 175614cf11afSPaul Mackerras * r27 == KERNELBASE 175714cf11afSPaul Mackerras */ 175814cf11afSPaul Mackerras bl .reloc_offset 175914cf11afSPaul Mackerras mr r26,r3 1760e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r27, KERNELBASE) 176114cf11afSPaul Mackerras 1762e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */ 176314cf11afSPaul Mackerras 176414cf11afSPaul Mackerras // XXX FIXME: Use phys returned by OF (r30) 17655a408329SPaul Mackerras add r4,r27,r26 /* source addr */ 176614cf11afSPaul Mackerras /* current address of _start */ 176714cf11afSPaul Mackerras /* i.e. where we are running */ 176814cf11afSPaul Mackerras /* the source addr */ 176914cf11afSPaul Mackerras 1770d0b79c54SJimi Xenidis cmpdi r4,0 /* In some cases the loader may */ 1771d0b79c54SJimi Xenidis beq .start_here_multiplatform /* have already put us at zero */ 1772d0b79c54SJimi Xenidis /* so we can skip the copy. */ 1773e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */ 177414cf11afSPaul Mackerras sub r5,r5,r27 177514cf11afSPaul Mackerras 177614cf11afSPaul Mackerras li r6,0x100 /* Start offset, the first 0x100 */ 177714cf11afSPaul Mackerras /* bytes were copied earlier. */ 177814cf11afSPaul Mackerras 177914cf11afSPaul Mackerras bl .copy_and_flush /* copy the first n bytes */ 178014cf11afSPaul Mackerras /* this includes the code being */ 178114cf11afSPaul Mackerras /* executed here. */ 178214cf11afSPaul Mackerras 1783e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */ 178414cf11afSPaul Mackerras mtctr r0 /* that we just made/relocated */ 178514cf11afSPaul Mackerras bctr 178614cf11afSPaul Mackerras 1787e58c3495SDavid Gibson4: LOAD_REG_IMMEDIATE(r5,klimit) 17885a408329SPaul Mackerras add r5,r5,r26 178914cf11afSPaul Mackerras ld r5,0(r5) /* get the value of klimit */ 179014cf11afSPaul Mackerras sub r5,r5,r27 179114cf11afSPaul Mackerras bl .copy_and_flush /* copy the rest */ 179214cf11afSPaul Mackerras b .start_here_multiplatform 179314cf11afSPaul Mackerras 179414cf11afSPaul Mackerras/* 179514cf11afSPaul Mackerras * Copy routine used to copy the kernel to start at physical address 0 179614cf11afSPaul Mackerras * and flush and invalidate the caches as needed. 179714cf11afSPaul Mackerras * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 179814cf11afSPaul Mackerras * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 179914cf11afSPaul Mackerras * 180014cf11afSPaul Mackerras * Note: this routine *only* clobbers r0, r6 and lr 180114cf11afSPaul Mackerras */ 180214cf11afSPaul Mackerras_GLOBAL(copy_and_flush) 180314cf11afSPaul Mackerras addi r5,r5,-8 180414cf11afSPaul Mackerras addi r6,r6,-8 18055a2fe38dSOlof Johansson4: li r0,8 /* Use the smallest common */ 180614cf11afSPaul Mackerras /* denominator cache line */ 180714cf11afSPaul Mackerras /* size. This results in */ 180814cf11afSPaul Mackerras /* extra cache line flushes */ 180914cf11afSPaul Mackerras /* but operation is correct. */ 181014cf11afSPaul Mackerras /* Can't get cache line size */ 181114cf11afSPaul Mackerras /* from NACA as it is being */ 181214cf11afSPaul Mackerras /* moved too. */ 181314cf11afSPaul Mackerras 181414cf11afSPaul Mackerras mtctr r0 /* put # words/line in ctr */ 181514cf11afSPaul Mackerras3: addi r6,r6,8 /* copy a cache line */ 181614cf11afSPaul Mackerras ldx r0,r6,r4 181714cf11afSPaul Mackerras stdx r0,r6,r3 181814cf11afSPaul Mackerras bdnz 3b 181914cf11afSPaul Mackerras dcbst r6,r3 /* write it to memory */ 182014cf11afSPaul Mackerras sync 182114cf11afSPaul Mackerras icbi r6,r3 /* flush the icache line */ 182214cf11afSPaul Mackerras cmpld 0,r6,r5 182314cf11afSPaul Mackerras blt 4b 182414cf11afSPaul Mackerras sync 182514cf11afSPaul Mackerras addi r5,r5,8 182614cf11afSPaul Mackerras addi r6,r6,8 182714cf11afSPaul Mackerras blr 182814cf11afSPaul Mackerras 182914cf11afSPaul Mackerras.align 8 183014cf11afSPaul Mackerrascopy_to_here: 183114cf11afSPaul Mackerras 183214cf11afSPaul Mackerras#ifdef CONFIG_SMP 183314cf11afSPaul Mackerras#ifdef CONFIG_PPC_PMAC 183414cf11afSPaul Mackerras/* 183514cf11afSPaul Mackerras * On PowerMac, secondary processors starts from the reset vector, which 183614cf11afSPaul Mackerras * is temporarily turned into a call to one of the functions below. 183714cf11afSPaul Mackerras */ 183814cf11afSPaul Mackerras .section ".text"; 183914cf11afSPaul Mackerras .align 2 ; 184014cf11afSPaul Mackerras 184135499c01SPaul Mackerras .globl __secondary_start_pmac_0 184235499c01SPaul Mackerras__secondary_start_pmac_0: 184335499c01SPaul Mackerras /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 184435499c01SPaul Mackerras li r24,0 184535499c01SPaul Mackerras b 1f 184614cf11afSPaul Mackerras li r24,1 184735499c01SPaul Mackerras b 1f 184814cf11afSPaul Mackerras li r24,2 184935499c01SPaul Mackerras b 1f 185014cf11afSPaul Mackerras li r24,3 185135499c01SPaul Mackerras1: 185214cf11afSPaul Mackerras 185314cf11afSPaul Mackerras_GLOBAL(pmac_secondary_start) 185414cf11afSPaul Mackerras /* turn on 64-bit mode */ 185514cf11afSPaul Mackerras bl .enable_64b_mode 185614cf11afSPaul Mackerras isync 185714cf11afSPaul Mackerras 185814cf11afSPaul Mackerras /* Copy some CPU settings from CPU 0 */ 1859f39b7a55SOlof Johansson bl .__restore_cpu_ppc970 186014cf11afSPaul Mackerras 186114cf11afSPaul Mackerras /* pSeries do that early though I don't think we really need it */ 186214cf11afSPaul Mackerras mfmsr r3 186314cf11afSPaul Mackerras ori r3,r3,MSR_RI 186414cf11afSPaul Mackerras mtmsrd r3 /* RI on */ 186514cf11afSPaul Mackerras 186614cf11afSPaul Mackerras /* Set up a paca value for this processor. */ 1867e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ 186814cf11afSPaul Mackerras mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 186914cf11afSPaul Mackerras add r13,r13,r4 /* for this processor. */ 1870b5bbeb23SPaul Mackerras mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 187114cf11afSPaul Mackerras 187214cf11afSPaul Mackerras /* Create a temp kernel stack for use before relocation is on. */ 187314cf11afSPaul Mackerras ld r1,PACAEMERGSP(r13) 187414cf11afSPaul Mackerras subi r1,r1,STACK_FRAME_OVERHEAD 187514cf11afSPaul Mackerras 187614cf11afSPaul Mackerras b .__secondary_start 187714cf11afSPaul Mackerras 187814cf11afSPaul Mackerras#endif /* CONFIG_PPC_PMAC */ 187914cf11afSPaul Mackerras 188014cf11afSPaul Mackerras/* 188114cf11afSPaul Mackerras * This function is called after the master CPU has released the 188214cf11afSPaul Mackerras * secondary processors. The execution environment is relocation off. 188314cf11afSPaul Mackerras * The paca for this processor has the following fields initialized at 188414cf11afSPaul Mackerras * this point: 188514cf11afSPaul Mackerras * 1. Processor number 188614cf11afSPaul Mackerras * 2. Segment table pointer (virtual address) 188714cf11afSPaul Mackerras * On entry the following are set: 188814cf11afSPaul Mackerras * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 188914cf11afSPaul Mackerras * r24 = cpu# (in Linux terms) 189014cf11afSPaul Mackerras * r13 = paca virtual address 189114cf11afSPaul Mackerras * SPRG3 = paca virtual address 189214cf11afSPaul Mackerras */ 189314cf11afSPaul Mackerras_GLOBAL(__secondary_start) 1894799d6046SPaul Mackerras /* Set thread priority to MEDIUM */ 1895799d6046SPaul Mackerras HMT_MEDIUM 189614cf11afSPaul Mackerras 1897799d6046SPaul Mackerras /* Load TOC */ 189814cf11afSPaul Mackerras ld r2,PACATOC(r13) 189914cf11afSPaul Mackerras 1900799d6046SPaul Mackerras /* Do early setup for that CPU (stab, slb, hash table pointer) */ 1901799d6046SPaul Mackerras bl .early_setup_secondary 190214cf11afSPaul Mackerras 190314cf11afSPaul Mackerras /* Initialize the kernel stack. Just a repeat for iSeries. */ 1904e58c3495SDavid Gibson LOAD_REG_ADDR(r3, current_set) 190514cf11afSPaul Mackerras sldi r28,r24,3 /* get current_set[cpu#] */ 190614cf11afSPaul Mackerras ldx r1,r3,r28 190714cf11afSPaul Mackerras addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 190814cf11afSPaul Mackerras std r1,PACAKSAVE(r13) 190914cf11afSPaul Mackerras 1910799d6046SPaul Mackerras /* Clear backchain so we get nice backtraces */ 191114cf11afSPaul Mackerras li r7,0 191214cf11afSPaul Mackerras mtlr r7 191314cf11afSPaul Mackerras 191414cf11afSPaul Mackerras /* enable MMU and jump to start_secondary */ 1915e58c3495SDavid Gibson LOAD_REG_ADDR(r3, .start_secondary_prolog) 1916e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 1917d04c56f7SPaul Mackerras#ifdef CONFIG_PPC_ISERIES 19183f639ee8SStephen RothwellBEGIN_FW_FTR_SECTION 191914cf11afSPaul Mackerras ori r4,r4,MSR_EE 19203f639ee8SStephen RothwellEND_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 192114cf11afSPaul Mackerras#endif 1922d04c56f7SPaul MackerrasBEGIN_FW_FTR_SECTION 1923d04c56f7SPaul Mackerras stb r7,PACASOFTIRQEN(r13) 1924d04c56f7SPaul Mackerras stb r7,PACAHARDIRQEN(r13) 1925d04c56f7SPaul MackerrasEND_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1926d04c56f7SPaul Mackerras 1927b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r3 1928b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r4 192914cf11afSPaul Mackerras rfid 193014cf11afSPaul Mackerras b . /* prevent speculative execution */ 193114cf11afSPaul Mackerras 193214cf11afSPaul Mackerras/* 193314cf11afSPaul Mackerras * Running with relocation on at this point. All we want to do is 193414cf11afSPaul Mackerras * zero the stack back-chain pointer before going into C code. 193514cf11afSPaul Mackerras */ 193614cf11afSPaul Mackerras_GLOBAL(start_secondary_prolog) 193714cf11afSPaul Mackerras li r3,0 193814cf11afSPaul Mackerras std r3,0(r1) /* Zero the stack frame pointer */ 193914cf11afSPaul Mackerras bl .start_secondary 1940799d6046SPaul Mackerras b . 194114cf11afSPaul Mackerras#endif 194214cf11afSPaul Mackerras 194314cf11afSPaul Mackerras/* 194414cf11afSPaul Mackerras * This subroutine clobbers r11 and r12 194514cf11afSPaul Mackerras */ 194614cf11afSPaul Mackerras_GLOBAL(enable_64b_mode) 194714cf11afSPaul Mackerras mfmsr r11 /* grab the current MSR */ 194814cf11afSPaul Mackerras li r12,1 194914cf11afSPaul Mackerras rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) 195014cf11afSPaul Mackerras or r11,r11,r12 195114cf11afSPaul Mackerras li r12,1 195214cf11afSPaul Mackerras rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) 195314cf11afSPaul Mackerras or r11,r11,r12 195414cf11afSPaul Mackerras mtmsrd r11 195514cf11afSPaul Mackerras isync 195614cf11afSPaul Mackerras blr 195714cf11afSPaul Mackerras 195814cf11afSPaul Mackerras/* 195914cf11afSPaul Mackerras * This is where the main kernel code starts. 196014cf11afSPaul Mackerras */ 196114cf11afSPaul Mackerras_STATIC(start_here_multiplatform) 196214cf11afSPaul Mackerras /* get a new offset, now that the kernel has moved. */ 196314cf11afSPaul Mackerras bl .reloc_offset 196414cf11afSPaul Mackerras mr r26,r3 196514cf11afSPaul Mackerras 196614cf11afSPaul Mackerras /* Clear out the BSS. It may have been done in prom_init, 196714cf11afSPaul Mackerras * already but that's irrelevant since prom_init will soon 196814cf11afSPaul Mackerras * be detached from the kernel completely. Besides, we need 196914cf11afSPaul Mackerras * to clear it now for kexec-style entry. 197014cf11afSPaul Mackerras */ 1971e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r11,__bss_stop) 1972e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r8,__bss_start) 197314cf11afSPaul Mackerras sub r11,r11,r8 /* bss size */ 197414cf11afSPaul Mackerras addi r11,r11,7 /* round up to an even double word */ 197514cf11afSPaul Mackerras rldicl. r11,r11,61,3 /* shift right by 3 */ 197614cf11afSPaul Mackerras beq 4f 197714cf11afSPaul Mackerras addi r8,r8,-8 197814cf11afSPaul Mackerras li r0,0 197914cf11afSPaul Mackerras mtctr r11 /* zero this many doublewords */ 198014cf11afSPaul Mackerras3: stdu r0,8(r8) 198114cf11afSPaul Mackerras bdnz 3b 198214cf11afSPaul Mackerras4: 198314cf11afSPaul Mackerras 198414cf11afSPaul Mackerras mfmsr r6 198514cf11afSPaul Mackerras ori r6,r6,MSR_RI 198614cf11afSPaul Mackerras mtmsrd r6 /* RI on */ 198714cf11afSPaul Mackerras 198814cf11afSPaul Mackerras /* The following gets the stack and TOC set up with the regs */ 198914cf11afSPaul Mackerras /* pointing to the real addr of the kernel stack. This is */ 199014cf11afSPaul Mackerras /* all done to support the C function call below which sets */ 199114cf11afSPaul Mackerras /* up the htab. This is done because we have relocated the */ 199214cf11afSPaul Mackerras /* kernel but are still running in real mode. */ 199314cf11afSPaul Mackerras 1994e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r3,init_thread_union) 19955a408329SPaul Mackerras add r3,r3,r26 199614cf11afSPaul Mackerras 199714cf11afSPaul Mackerras /* set up a stack pointer (physical address) */ 199814cf11afSPaul Mackerras addi r1,r3,THREAD_SIZE 199914cf11afSPaul Mackerras li r0,0 200014cf11afSPaul Mackerras stdu r0,-STACK_FRAME_OVERHEAD(r1) 200114cf11afSPaul Mackerras 200214cf11afSPaul Mackerras /* set up the TOC (physical address) */ 2003e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r2,__toc_start) 200414cf11afSPaul Mackerras addi r2,r2,0x4000 200514cf11afSPaul Mackerras addi r2,r2,0x4000 20065a408329SPaul Mackerras add r2,r2,r26 200714cf11afSPaul Mackerras 200814cf11afSPaul Mackerras /* Do very early kernel initializations, including initial hash table, 200914cf11afSPaul Mackerras * stab and slb setup before we turn on relocation. */ 201014cf11afSPaul Mackerras 201114cf11afSPaul Mackerras /* Restore parameters passed from prom_init/kexec */ 201214cf11afSPaul Mackerras mr r3,r31 201314cf11afSPaul Mackerras bl .early_setup 201414cf11afSPaul Mackerras 2015e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r3, .start_here_common) 2016e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 2017b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r3 2018b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r4 201914cf11afSPaul Mackerras rfid 202014cf11afSPaul Mackerras b . /* prevent speculative execution */ 202114cf11afSPaul Mackerras 202214cf11afSPaul Mackerras /* This is where all platforms converge execution */ 202314cf11afSPaul Mackerras_STATIC(start_here_common) 202414cf11afSPaul Mackerras /* relocation is on at this point */ 202514cf11afSPaul Mackerras 202614cf11afSPaul Mackerras /* The following code sets up the SP and TOC now that we are */ 202714cf11afSPaul Mackerras /* running with translation enabled. */ 202814cf11afSPaul Mackerras 2029e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r3,init_thread_union) 203014cf11afSPaul Mackerras 203114cf11afSPaul Mackerras /* set up the stack */ 203214cf11afSPaul Mackerras addi r1,r3,THREAD_SIZE 203314cf11afSPaul Mackerras li r0,0 203414cf11afSPaul Mackerras stdu r0,-STACK_FRAME_OVERHEAD(r1) 203514cf11afSPaul Mackerras 203614cf11afSPaul Mackerras /* ptr to current */ 2037e58c3495SDavid Gibson LOAD_REG_IMMEDIATE(r4, init_task) 203814cf11afSPaul Mackerras std r4,PACACURRENT(r13) 203914cf11afSPaul Mackerras 204014cf11afSPaul Mackerras /* Load the TOC */ 204114cf11afSPaul Mackerras ld r2,PACATOC(r13) 204214cf11afSPaul Mackerras std r1,PACAKSAVE(r13) 204314cf11afSPaul Mackerras 204414cf11afSPaul Mackerras bl .setup_system 204514cf11afSPaul Mackerras 204614cf11afSPaul Mackerras /* Load up the kernel context */ 204714cf11afSPaul Mackerras5: 204814cf11afSPaul Mackerras li r5,0 2049d04c56f7SPaul Mackerras stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ 2050d04c56f7SPaul Mackerras#ifdef CONFIG_PPC_ISERIES 2051d04c56f7SPaul MackerrasBEGIN_FW_FTR_SECTION 205214cf11afSPaul Mackerras mfmsr r5 205314cf11afSPaul Mackerras ori r5,r5,MSR_EE /* Hard Enabled */ 205414cf11afSPaul Mackerras mtmsrd r5 20553f639ee8SStephen RothwellEND_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 205614cf11afSPaul Mackerras#endif 2057d04c56f7SPaul MackerrasBEGIN_FW_FTR_SECTION 2058d04c56f7SPaul Mackerras stb r5,PACAHARDIRQEN(r13) 2059d04c56f7SPaul MackerrasEND_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 206014cf11afSPaul Mackerras 206114cf11afSPaul Mackerras bl .start_kernel 206214cf11afSPaul Mackerras 2063f1870f77SAnton Blanchard /* Not reached */ 2064f1870f77SAnton Blanchard BUG_OPCODE 206514cf11afSPaul Mackerras 206614cf11afSPaul Mackerras/* 206714cf11afSPaul Mackerras * We put a few things here that have to be page-aligned. 206814cf11afSPaul Mackerras * This stuff goes at the beginning of the bss, which is page-aligned. 206914cf11afSPaul Mackerras */ 207014cf11afSPaul Mackerras .section ".bss" 207114cf11afSPaul Mackerras 207214cf11afSPaul Mackerras .align PAGE_SHIFT 207314cf11afSPaul Mackerras 207414cf11afSPaul Mackerras .globl empty_zero_page 207514cf11afSPaul Mackerrasempty_zero_page: 207614cf11afSPaul Mackerras .space PAGE_SIZE 207714cf11afSPaul Mackerras 207814cf11afSPaul Mackerras .globl swapper_pg_dir 207914cf11afSPaul Mackerrasswapper_pg_dir: 208014cf11afSPaul Mackerras .space PAGE_SIZE 208114cf11afSPaul Mackerras 208214cf11afSPaul Mackerras/* 208314cf11afSPaul Mackerras * This space gets a copy of optional info passed to us by the bootstrap 208414cf11afSPaul Mackerras * Used to pass parameters into the kernel like root=/dev/sda1, etc. 208514cf11afSPaul Mackerras */ 208614cf11afSPaul Mackerras .globl cmd_line 208714cf11afSPaul Mackerrascmd_line: 208814cf11afSPaul Mackerras .space COMMAND_LINE_SIZE 2089