114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * arch/ppc64/kernel/head.S 314cf11afSPaul Mackerras * 414cf11afSPaul Mackerras * PowerPC version 514cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 614cf11afSPaul Mackerras * 714cf11afSPaul Mackerras * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 814cf11afSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 914cf11afSPaul Mackerras * Adapted for Power Macintosh by Paul Mackerras. 1014cf11afSPaul Mackerras * Low-level exception handlers and MMU support 1114cf11afSPaul Mackerras * rewritten by Paul Mackerras. 1214cf11afSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 1314cf11afSPaul Mackerras * 1414cf11afSPaul Mackerras * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 1514cf11afSPaul Mackerras * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 1614cf11afSPaul Mackerras * 1714cf11afSPaul Mackerras * This file contains the low-level support and setup for the 1814cf11afSPaul Mackerras * PowerPC-64 platform, including trap and interrupt dispatch. 1914cf11afSPaul Mackerras * 2014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 2114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 2214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 2314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 2414cf11afSPaul Mackerras */ 2514cf11afSPaul Mackerras 2614cf11afSPaul Mackerras#include <linux/config.h> 2714cf11afSPaul Mackerras#include <linux/threads.h> 28b5bbeb23SPaul Mackerras#include <asm/reg.h> 2914cf11afSPaul Mackerras#include <asm/page.h> 3014cf11afSPaul Mackerras#include <asm/mmu.h> 3114cf11afSPaul Mackerras#include <asm/systemcfg.h> 3214cf11afSPaul Mackerras#include <asm/ppc_asm.h> 3314cf11afSPaul Mackerras#include <asm/asm-offsets.h> 3414cf11afSPaul Mackerras#include <asm/bug.h> 3514cf11afSPaul Mackerras#include <asm/cputable.h> 3614cf11afSPaul Mackerras#include <asm/setup.h> 3714cf11afSPaul Mackerras#include <asm/hvcall.h> 38c43a55ffSKelly Daly#include <asm/iseries/lpar_map.h> 396cb7bfebSDavid Gibson#include <asm/thread_info.h> 4014cf11afSPaul Mackerras 4114cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 4214cf11afSPaul Mackerras#define DO_SOFT_DISABLE 4314cf11afSPaul Mackerras#endif 4414cf11afSPaul Mackerras 4514cf11afSPaul Mackerras/* 4614cf11afSPaul Mackerras * We layout physical memory as follows: 4714cf11afSPaul Mackerras * 0x0000 - 0x00ff : Secondary processor spin code 4814cf11afSPaul Mackerras * 0x0100 - 0x2fff : pSeries Interrupt prologs 4914cf11afSPaul Mackerras * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs 5014cf11afSPaul Mackerras * 0x6000 - 0x6fff : Initial (CPU0) segment table 5114cf11afSPaul Mackerras * 0x7000 - 0x7fff : FWNMI data area 5214cf11afSPaul Mackerras * 0x8000 - : Early init and support code 5314cf11afSPaul Mackerras */ 5414cf11afSPaul Mackerras 5514cf11afSPaul Mackerras/* 5614cf11afSPaul Mackerras * SPRG Usage 5714cf11afSPaul Mackerras * 5814cf11afSPaul Mackerras * Register Definition 5914cf11afSPaul Mackerras * 6014cf11afSPaul Mackerras * SPRG0 reserved for hypervisor 6114cf11afSPaul Mackerras * SPRG1 temp - used to save gpr 6214cf11afSPaul Mackerras * SPRG2 temp - used to save gpr 6314cf11afSPaul Mackerras * SPRG3 virt addr of paca 6414cf11afSPaul Mackerras */ 6514cf11afSPaul Mackerras 6614cf11afSPaul Mackerras/* 6714cf11afSPaul Mackerras * Entering into this code we make the following assumptions: 6814cf11afSPaul Mackerras * For pSeries: 6914cf11afSPaul Mackerras * 1. The MMU is off & open firmware is running in real mode. 7014cf11afSPaul Mackerras * 2. The kernel is entered at __start 7114cf11afSPaul Mackerras * 7214cf11afSPaul Mackerras * For iSeries: 7314cf11afSPaul Mackerras * 1. The MMU is on (as it always is for iSeries) 7414cf11afSPaul Mackerras * 2. The kernel is entered at system_reset_iSeries 7514cf11afSPaul Mackerras */ 7614cf11afSPaul Mackerras 7714cf11afSPaul Mackerras .text 7814cf11afSPaul Mackerras .globl _stext 7914cf11afSPaul Mackerras_stext: 8014cf11afSPaul Mackerras#ifdef CONFIG_PPC_MULTIPLATFORM 8114cf11afSPaul Mackerras_GLOBAL(__start) 8214cf11afSPaul Mackerras /* NOP this out unconditionally */ 8314cf11afSPaul MackerrasBEGIN_FTR_SECTION 8414cf11afSPaul Mackerras b .__start_initialization_multiplatform 8514cf11afSPaul MackerrasEND_FTR_SECTION(0, 1) 8614cf11afSPaul Mackerras#endif /* CONFIG_PPC_MULTIPLATFORM */ 8714cf11afSPaul Mackerras 8814cf11afSPaul Mackerras /* Catch branch to 0 in real mode */ 8914cf11afSPaul Mackerras trap 9014cf11afSPaul Mackerras 9114cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 9214cf11afSPaul Mackerras /* 9314cf11afSPaul Mackerras * At offset 0x20, there is a pointer to iSeries LPAR data. 9414cf11afSPaul Mackerras * This is required by the hypervisor 9514cf11afSPaul Mackerras */ 9614cf11afSPaul Mackerras . = 0x20 9714cf11afSPaul Mackerras .llong hvReleaseData-KERNELBASE 9814cf11afSPaul Mackerras 9914cf11afSPaul Mackerras /* 10014cf11afSPaul Mackerras * At offset 0x28 and 0x30 are offsets to the mschunks_map 10114cf11afSPaul Mackerras * array (used by the iSeries LPAR debugger to do translation 10214cf11afSPaul Mackerras * between physical addresses and absolute addresses) and 10314cf11afSPaul Mackerras * to the pidhash table (also used by the debugger) 10414cf11afSPaul Mackerras */ 10514cf11afSPaul Mackerras .llong mschunks_map-KERNELBASE 10614cf11afSPaul Mackerras .llong 0 /* pidhash-KERNELBASE SFRXXX */ 10714cf11afSPaul Mackerras 10814cf11afSPaul Mackerras /* Offset 0x38 - Pointer to start of embedded System.map */ 10914cf11afSPaul Mackerras .globl embedded_sysmap_start 11014cf11afSPaul Mackerrasembedded_sysmap_start: 11114cf11afSPaul Mackerras .llong 0 11214cf11afSPaul Mackerras /* Offset 0x40 - Pointer to end of embedded System.map */ 11314cf11afSPaul Mackerras .globl embedded_sysmap_end 11414cf11afSPaul Mackerrasembedded_sysmap_end: 11514cf11afSPaul Mackerras .llong 0 11614cf11afSPaul Mackerras 11714cf11afSPaul Mackerras#endif /* CONFIG_PPC_ISERIES */ 11814cf11afSPaul Mackerras 11914cf11afSPaul Mackerras /* Secondary processors spin on this value until it goes to 1. */ 12014cf11afSPaul Mackerras .globl __secondary_hold_spinloop 12114cf11afSPaul Mackerras__secondary_hold_spinloop: 12214cf11afSPaul Mackerras .llong 0x0 12314cf11afSPaul Mackerras 12414cf11afSPaul Mackerras /* Secondary processors write this value with their cpu # */ 12514cf11afSPaul Mackerras /* after they enter the spin loop immediately below. */ 12614cf11afSPaul Mackerras .globl __secondary_hold_acknowledge 12714cf11afSPaul Mackerras__secondary_hold_acknowledge: 12814cf11afSPaul Mackerras .llong 0x0 12914cf11afSPaul Mackerras 13014cf11afSPaul Mackerras . = 0x60 13114cf11afSPaul Mackerras/* 13214cf11afSPaul Mackerras * The following code is used on pSeries to hold secondary processors 13314cf11afSPaul Mackerras * in a spin loop after they have been freed from OpenFirmware, but 13414cf11afSPaul Mackerras * before the bulk of the kernel has been relocated. This code 13514cf11afSPaul Mackerras * is relocated to physical address 0x60 before prom_init is run. 13614cf11afSPaul Mackerras * All of it must fit below the first exception vector at 0x100. 13714cf11afSPaul Mackerras */ 13814cf11afSPaul Mackerras_GLOBAL(__secondary_hold) 13914cf11afSPaul Mackerras mfmsr r24 14014cf11afSPaul Mackerras ori r24,r24,MSR_RI 14114cf11afSPaul Mackerras mtmsrd r24 /* RI on */ 14214cf11afSPaul Mackerras 14314cf11afSPaul Mackerras /* Grab our linux cpu number */ 14414cf11afSPaul Mackerras mr r24,r3 14514cf11afSPaul Mackerras 14614cf11afSPaul Mackerras /* Tell the master cpu we're here */ 14714cf11afSPaul Mackerras /* Relocation is off & we are located at an address less */ 14814cf11afSPaul Mackerras /* than 0x100, so only need to grab low order offset. */ 14914cf11afSPaul Mackerras std r24,__secondary_hold_acknowledge@l(0) 15014cf11afSPaul Mackerras sync 15114cf11afSPaul Mackerras 15214cf11afSPaul Mackerras /* All secondary cpus wait here until told to start. */ 15314cf11afSPaul Mackerras100: ld r4,__secondary_hold_spinloop@l(0) 15414cf11afSPaul Mackerras cmpdi 0,r4,1 15514cf11afSPaul Mackerras bne 100b 15614cf11afSPaul Mackerras 15714cf11afSPaul Mackerras#ifdef CONFIG_HMT 15814cf11afSPaul Mackerras b .hmt_init 15914cf11afSPaul Mackerras#else 16014cf11afSPaul Mackerras#ifdef CONFIG_SMP 16114cf11afSPaul Mackerras mr r3,r24 16214cf11afSPaul Mackerras b .pSeries_secondary_smp_init 16314cf11afSPaul Mackerras#else 16414cf11afSPaul Mackerras BUG_OPCODE 16514cf11afSPaul Mackerras#endif 16614cf11afSPaul Mackerras#endif 16714cf11afSPaul Mackerras 16814cf11afSPaul Mackerras/* This value is used to mark exception frames on the stack. */ 16914cf11afSPaul Mackerras .section ".toc","aw" 17014cf11afSPaul Mackerrasexception_marker: 17114cf11afSPaul Mackerras .tc ID_72656773_68657265[TC],0x7265677368657265 17214cf11afSPaul Mackerras .text 17314cf11afSPaul Mackerras 17414cf11afSPaul Mackerras/* 17514cf11afSPaul Mackerras * The following macros define the code that appears as 17614cf11afSPaul Mackerras * the prologue to each of the exception handlers. They 17714cf11afSPaul Mackerras * are split into two parts to allow a single kernel binary 17814cf11afSPaul Mackerras * to be used for pSeries and iSeries. 17914cf11afSPaul Mackerras * LOL. One day... - paulus 18014cf11afSPaul Mackerras */ 18114cf11afSPaul Mackerras 18214cf11afSPaul Mackerras/* 18314cf11afSPaul Mackerras * We make as much of the exception code common between native 18414cf11afSPaul Mackerras * exception handlers (including pSeries LPAR) and iSeries LPAR 18514cf11afSPaul Mackerras * implementations as possible. 18614cf11afSPaul Mackerras */ 18714cf11afSPaul Mackerras 18814cf11afSPaul Mackerras/* 18914cf11afSPaul Mackerras * This is the start of the interrupt handlers for pSeries 19014cf11afSPaul Mackerras * This code runs with relocation off. 19114cf11afSPaul Mackerras */ 19214cf11afSPaul Mackerras#define EX_R9 0 19314cf11afSPaul Mackerras#define EX_R10 8 19414cf11afSPaul Mackerras#define EX_R11 16 19514cf11afSPaul Mackerras#define EX_R12 24 19614cf11afSPaul Mackerras#define EX_R13 32 19714cf11afSPaul Mackerras#define EX_SRR0 40 19814cf11afSPaul Mackerras#define EX_DAR 48 19914cf11afSPaul Mackerras#define EX_DSISR 56 20014cf11afSPaul Mackerras#define EX_CCR 60 2013c726f8dSBenjamin Herrenschmidt#define EX_R3 64 2023c726f8dSBenjamin Herrenschmidt#define EX_LR 72 20314cf11afSPaul Mackerras 20414cf11afSPaul Mackerras#define EXCEPTION_PROLOG_PSERIES(area, label) \ 205b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 20614cf11afSPaul Mackerras std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 20714cf11afSPaul Mackerras std r10,area+EX_R10(r13); \ 20814cf11afSPaul Mackerras std r11,area+EX_R11(r13); \ 20914cf11afSPaul Mackerras std r12,area+EX_R12(r13); \ 210b5bbeb23SPaul Mackerras mfspr r9,SPRN_SPRG1; \ 21114cf11afSPaul Mackerras std r9,area+EX_R13(r13); \ 21214cf11afSPaul Mackerras mfcr r9; \ 21314cf11afSPaul Mackerras clrrdi r12,r13,32; /* get high part of &label */ \ 21414cf11afSPaul Mackerras mfmsr r10; \ 215b5bbeb23SPaul Mackerras mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 21614cf11afSPaul Mackerras ori r12,r12,(label)@l; /* virt addr of handler */ \ 21714cf11afSPaul Mackerras ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 218b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r12; \ 219b5bbeb23SPaul Mackerras mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 220b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r10; \ 22114cf11afSPaul Mackerras rfid; \ 22214cf11afSPaul Mackerras b . /* prevent speculative execution */ 22314cf11afSPaul Mackerras 22414cf11afSPaul Mackerras/* 22514cf11afSPaul Mackerras * This is the start of the interrupt handlers for iSeries 22614cf11afSPaul Mackerras * This code runs with relocation on. 22714cf11afSPaul Mackerras */ 22814cf11afSPaul Mackerras#define EXCEPTION_PROLOG_ISERIES_1(area) \ 229b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 23014cf11afSPaul Mackerras std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 23114cf11afSPaul Mackerras std r10,area+EX_R10(r13); \ 23214cf11afSPaul Mackerras std r11,area+EX_R11(r13); \ 23314cf11afSPaul Mackerras std r12,area+EX_R12(r13); \ 234b5bbeb23SPaul Mackerras mfspr r9,SPRN_SPRG1; \ 23514cf11afSPaul Mackerras std r9,area+EX_R13(r13); \ 23614cf11afSPaul Mackerras mfcr r9 23714cf11afSPaul Mackerras 23814cf11afSPaul Mackerras#define EXCEPTION_PROLOG_ISERIES_2 \ 23914cf11afSPaul Mackerras mfmsr r10; \ 24014cf11afSPaul Mackerras ld r11,PACALPPACA+LPPACASRR0(r13); \ 24114cf11afSPaul Mackerras ld r12,PACALPPACA+LPPACASRR1(r13); \ 24214cf11afSPaul Mackerras ori r10,r10,MSR_RI; \ 24314cf11afSPaul Mackerras mtmsrd r10,1 24414cf11afSPaul Mackerras 24514cf11afSPaul Mackerras/* 24614cf11afSPaul Mackerras * The common exception prolog is used for all except a few exceptions 24714cf11afSPaul Mackerras * such as a segment miss on a kernel address. We have to be prepared 24814cf11afSPaul Mackerras * to take another exception from the point where we first touch the 24914cf11afSPaul Mackerras * kernel stack onwards. 25014cf11afSPaul Mackerras * 25114cf11afSPaul Mackerras * On entry r13 points to the paca, r9-r13 are saved in the paca, 25214cf11afSPaul Mackerras * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 25314cf11afSPaul Mackerras * SRR1, and relocation is on. 25414cf11afSPaul Mackerras */ 25514cf11afSPaul Mackerras#define EXCEPTION_PROLOG_COMMON(n, area) \ 25614cf11afSPaul Mackerras andi. r10,r12,MSR_PR; /* See if coming from user */ \ 25714cf11afSPaul Mackerras mr r10,r1; /* Save r1 */ \ 25814cf11afSPaul Mackerras subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 25914cf11afSPaul Mackerras beq- 1f; \ 26014cf11afSPaul Mackerras ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 26114cf11afSPaul Mackerras1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 26214cf11afSPaul Mackerras bge- cr1,bad_stack; /* abort if it is */ \ 26314cf11afSPaul Mackerras std r9,_CCR(r1); /* save CR in stackframe */ \ 26414cf11afSPaul Mackerras std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 26514cf11afSPaul Mackerras std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 26614cf11afSPaul Mackerras std r10,0(r1); /* make stack chain pointer */ \ 26714cf11afSPaul Mackerras std r0,GPR0(r1); /* save r0 in stackframe */ \ 26814cf11afSPaul Mackerras std r10,GPR1(r1); /* save r1 in stackframe */ \ 26914cf11afSPaul Mackerras std r2,GPR2(r1); /* save r2 in stackframe */ \ 27014cf11afSPaul Mackerras SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 27114cf11afSPaul Mackerras SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 27214cf11afSPaul Mackerras ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 27314cf11afSPaul Mackerras ld r10,area+EX_R10(r13); \ 27414cf11afSPaul Mackerras std r9,GPR9(r1); \ 27514cf11afSPaul Mackerras std r10,GPR10(r1); \ 27614cf11afSPaul Mackerras ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 27714cf11afSPaul Mackerras ld r10,area+EX_R12(r13); \ 27814cf11afSPaul Mackerras ld r11,area+EX_R13(r13); \ 27914cf11afSPaul Mackerras std r9,GPR11(r1); \ 28014cf11afSPaul Mackerras std r10,GPR12(r1); \ 28114cf11afSPaul Mackerras std r11,GPR13(r1); \ 28214cf11afSPaul Mackerras ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 28314cf11afSPaul Mackerras mflr r9; /* save LR in stackframe */ \ 28414cf11afSPaul Mackerras std r9,_LINK(r1); \ 28514cf11afSPaul Mackerras mfctr r10; /* save CTR in stackframe */ \ 28614cf11afSPaul Mackerras std r10,_CTR(r1); \ 287b5bbeb23SPaul Mackerras mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 28814cf11afSPaul Mackerras std r11,_XER(r1); \ 28914cf11afSPaul Mackerras li r9,(n)+1; \ 29014cf11afSPaul Mackerras std r9,_TRAP(r1); /* set trap number */ \ 29114cf11afSPaul Mackerras li r10,0; \ 29214cf11afSPaul Mackerras ld r11,exception_marker@toc(r2); \ 29314cf11afSPaul Mackerras std r10,RESULT(r1); /* clear regs->result */ \ 29414cf11afSPaul Mackerras std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 29514cf11afSPaul Mackerras 29614cf11afSPaul Mackerras/* 29714cf11afSPaul Mackerras * Exception vectors. 29814cf11afSPaul Mackerras */ 29914cf11afSPaul Mackerras#define STD_EXCEPTION_PSERIES(n, label) \ 30014cf11afSPaul Mackerras . = n; \ 30114cf11afSPaul Mackerras .globl label##_pSeries; \ 30214cf11afSPaul Mackerraslabel##_pSeries: \ 30314cf11afSPaul Mackerras HMT_MEDIUM; \ 304b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13; /* save r13 */ \ 30514cf11afSPaul Mackerras RUNLATCH_ON(r13); \ 30614cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 30714cf11afSPaul Mackerras 30814cf11afSPaul Mackerras#define STD_EXCEPTION_ISERIES(n, label, area) \ 30914cf11afSPaul Mackerras .globl label##_iSeries; \ 31014cf11afSPaul Mackerraslabel##_iSeries: \ 31114cf11afSPaul Mackerras HMT_MEDIUM; \ 312b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13; /* save r13 */ \ 31314cf11afSPaul Mackerras RUNLATCH_ON(r13); \ 31414cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_1(area); \ 31514cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2; \ 31614cf11afSPaul Mackerras b label##_common 31714cf11afSPaul Mackerras 31814cf11afSPaul Mackerras#define MASKABLE_EXCEPTION_ISERIES(n, label) \ 31914cf11afSPaul Mackerras .globl label##_iSeries; \ 32014cf11afSPaul Mackerraslabel##_iSeries: \ 32114cf11afSPaul Mackerras HMT_MEDIUM; \ 322b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13; /* save r13 */ \ 32314cf11afSPaul Mackerras RUNLATCH_ON(r13); \ 32414cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ 32514cf11afSPaul Mackerras lbz r10,PACAPROCENABLED(r13); \ 32614cf11afSPaul Mackerras cmpwi 0,r10,0; \ 32714cf11afSPaul Mackerras beq- label##_iSeries_masked; \ 32814cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2; \ 32914cf11afSPaul Mackerras b label##_common; \ 33014cf11afSPaul Mackerras 33114cf11afSPaul Mackerras#ifdef DO_SOFT_DISABLE 33214cf11afSPaul Mackerras#define DISABLE_INTS \ 33314cf11afSPaul Mackerras lbz r10,PACAPROCENABLED(r13); \ 33414cf11afSPaul Mackerras li r11,0; \ 33514cf11afSPaul Mackerras std r10,SOFTE(r1); \ 33614cf11afSPaul Mackerras mfmsr r10; \ 33714cf11afSPaul Mackerras stb r11,PACAPROCENABLED(r13); \ 33814cf11afSPaul Mackerras ori r10,r10,MSR_EE; \ 33914cf11afSPaul Mackerras mtmsrd r10,1 34014cf11afSPaul Mackerras 34114cf11afSPaul Mackerras#define ENABLE_INTS \ 34214cf11afSPaul Mackerras lbz r10,PACAPROCENABLED(r13); \ 34314cf11afSPaul Mackerras mfmsr r11; \ 34414cf11afSPaul Mackerras std r10,SOFTE(r1); \ 34514cf11afSPaul Mackerras ori r11,r11,MSR_EE; \ 34614cf11afSPaul Mackerras mtmsrd r11,1 34714cf11afSPaul Mackerras 34814cf11afSPaul Mackerras#else /* hard enable/disable interrupts */ 34914cf11afSPaul Mackerras#define DISABLE_INTS 35014cf11afSPaul Mackerras 35114cf11afSPaul Mackerras#define ENABLE_INTS \ 35214cf11afSPaul Mackerras ld r12,_MSR(r1); \ 35314cf11afSPaul Mackerras mfmsr r11; \ 35414cf11afSPaul Mackerras rlwimi r11,r12,0,MSR_EE; \ 35514cf11afSPaul Mackerras mtmsrd r11,1 35614cf11afSPaul Mackerras 35714cf11afSPaul Mackerras#endif 35814cf11afSPaul Mackerras 35914cf11afSPaul Mackerras#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 36014cf11afSPaul Mackerras .align 7; \ 36114cf11afSPaul Mackerras .globl label##_common; \ 36214cf11afSPaul Mackerraslabel##_common: \ 36314cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 36414cf11afSPaul Mackerras DISABLE_INTS; \ 36514cf11afSPaul Mackerras bl .save_nvgprs; \ 36614cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD; \ 36714cf11afSPaul Mackerras bl hdlr; \ 36814cf11afSPaul Mackerras b .ret_from_except 36914cf11afSPaul Mackerras 37014cf11afSPaul Mackerras#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ 37114cf11afSPaul Mackerras .align 7; \ 37214cf11afSPaul Mackerras .globl label##_common; \ 37314cf11afSPaul Mackerraslabel##_common: \ 37414cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 37514cf11afSPaul Mackerras DISABLE_INTS; \ 37614cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD; \ 37714cf11afSPaul Mackerras bl hdlr; \ 37814cf11afSPaul Mackerras b .ret_from_except_lite 37914cf11afSPaul Mackerras 38014cf11afSPaul Mackerras/* 38114cf11afSPaul Mackerras * Start of pSeries system interrupt routines 38214cf11afSPaul Mackerras */ 38314cf11afSPaul Mackerras . = 0x100 38414cf11afSPaul Mackerras .globl __start_interrupts 38514cf11afSPaul Mackerras__start_interrupts: 38614cf11afSPaul Mackerras 38714cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x100, system_reset) 38814cf11afSPaul Mackerras 38914cf11afSPaul Mackerras . = 0x200 39014cf11afSPaul Mackerras_machine_check_pSeries: 39114cf11afSPaul Mackerras HMT_MEDIUM 392b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 39314cf11afSPaul Mackerras RUNLATCH_ON(r13) 39414cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 39514cf11afSPaul Mackerras 39614cf11afSPaul Mackerras . = 0x300 39714cf11afSPaul Mackerras .globl data_access_pSeries 39814cf11afSPaul Mackerrasdata_access_pSeries: 39914cf11afSPaul Mackerras HMT_MEDIUM 400b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 40114cf11afSPaul MackerrasBEGIN_FTR_SECTION 402b5bbeb23SPaul Mackerras mtspr SPRN_SPRG2,r12 403b5bbeb23SPaul Mackerras mfspr r13,SPRN_DAR 404b5bbeb23SPaul Mackerras mfspr r12,SPRN_DSISR 40514cf11afSPaul Mackerras srdi r13,r13,60 40614cf11afSPaul Mackerras rlwimi r13,r12,16,0x20 40714cf11afSPaul Mackerras mfcr r12 40814cf11afSPaul Mackerras cmpwi r13,0x2c 40914cf11afSPaul Mackerras beq .do_stab_bolted_pSeries 41014cf11afSPaul Mackerras mtcrf 0x80,r12 411b5bbeb23SPaul Mackerras mfspr r12,SPRN_SPRG2 41214cf11afSPaul MackerrasEND_FTR_SECTION_IFCLR(CPU_FTR_SLB) 41314cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 41414cf11afSPaul Mackerras 41514cf11afSPaul Mackerras . = 0x380 41614cf11afSPaul Mackerras .globl data_access_slb_pSeries 41714cf11afSPaul Mackerrasdata_access_slb_pSeries: 41814cf11afSPaul Mackerras HMT_MEDIUM 419b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 42014cf11afSPaul Mackerras RUNLATCH_ON(r13) 421b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 4223c726f8dSBenjamin Herrenschmidt std r3,PACA_EXSLB+EX_R3(r13) 4233c726f8dSBenjamin Herrenschmidt mfspr r3,SPRN_DAR 42414cf11afSPaul Mackerras std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 4253c726f8dSBenjamin Herrenschmidt mfcr r9 4263c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 4273c726f8dSBenjamin Herrenschmidt /* Keep that around for when we re-implement dynamic VSIDs */ 4283c726f8dSBenjamin Herrenschmidt cmpdi r3,0 4293c726f8dSBenjamin Herrenschmidt bge slb_miss_user_pseries 4303c726f8dSBenjamin Herrenschmidt#endif /* __DISABLED__ */ 43114cf11afSPaul Mackerras std r10,PACA_EXSLB+EX_R10(r13) 43214cf11afSPaul Mackerras std r11,PACA_EXSLB+EX_R11(r13) 43314cf11afSPaul Mackerras std r12,PACA_EXSLB+EX_R12(r13) 4343c726f8dSBenjamin Herrenschmidt mfspr r10,SPRN_SPRG1 4353c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R13(r13) 436b5bbeb23SPaul Mackerras mfspr r12,SPRN_SRR1 /* and SRR1 */ 4373c726f8dSBenjamin Herrenschmidt b .slb_miss_realmode /* Rel. branch works in real mode */ 43814cf11afSPaul Mackerras 43914cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x400, instruction_access) 44014cf11afSPaul Mackerras 44114cf11afSPaul Mackerras . = 0x480 44214cf11afSPaul Mackerras .globl instruction_access_slb_pSeries 44314cf11afSPaul Mackerrasinstruction_access_slb_pSeries: 44414cf11afSPaul Mackerras HMT_MEDIUM 445b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 44614cf11afSPaul Mackerras RUNLATCH_ON(r13) 447b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 4483c726f8dSBenjamin Herrenschmidt std r3,PACA_EXSLB+EX_R3(r13) 4493c726f8dSBenjamin Herrenschmidt mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 45014cf11afSPaul Mackerras std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 4513c726f8dSBenjamin Herrenschmidt mfcr r9 4523c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 4533c726f8dSBenjamin Herrenschmidt /* Keep that around for when we re-implement dynamic VSIDs */ 4543c726f8dSBenjamin Herrenschmidt cmpdi r3,0 4553c726f8dSBenjamin Herrenschmidt bge slb_miss_user_pseries 4563c726f8dSBenjamin Herrenschmidt#endif /* __DISABLED__ */ 45714cf11afSPaul Mackerras std r10,PACA_EXSLB+EX_R10(r13) 45814cf11afSPaul Mackerras std r11,PACA_EXSLB+EX_R11(r13) 45914cf11afSPaul Mackerras std r12,PACA_EXSLB+EX_R12(r13) 4603c726f8dSBenjamin Herrenschmidt mfspr r10,SPRN_SPRG1 4613c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R13(r13) 462b5bbeb23SPaul Mackerras mfspr r12,SPRN_SRR1 /* and SRR1 */ 4633c726f8dSBenjamin Herrenschmidt b .slb_miss_realmode /* Rel. branch works in real mode */ 46414cf11afSPaul Mackerras 46514cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x500, hardware_interrupt) 46614cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x600, alignment) 46714cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x700, program_check) 46814cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x800, fp_unavailable) 46914cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x900, decrementer) 47014cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xa00, trap_0a) 47114cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xb00, trap_0b) 47214cf11afSPaul Mackerras 47314cf11afSPaul Mackerras . = 0xc00 47414cf11afSPaul Mackerras .globl system_call_pSeries 47514cf11afSPaul Mackerrassystem_call_pSeries: 47614cf11afSPaul Mackerras HMT_MEDIUM 47714cf11afSPaul Mackerras RUNLATCH_ON(r9) 47814cf11afSPaul Mackerras mr r9,r13 47914cf11afSPaul Mackerras mfmsr r10 480b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 481b5bbeb23SPaul Mackerras mfspr r11,SPRN_SRR0 48214cf11afSPaul Mackerras clrrdi r12,r13,32 48314cf11afSPaul Mackerras oris r12,r12,system_call_common@h 48414cf11afSPaul Mackerras ori r12,r12,system_call_common@l 485b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r12 48614cf11afSPaul Mackerras ori r10,r10,MSR_IR|MSR_DR|MSR_RI 487b5bbeb23SPaul Mackerras mfspr r12,SPRN_SRR1 488b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r10 48914cf11afSPaul Mackerras rfid 49014cf11afSPaul Mackerras b . /* prevent speculative execution */ 49114cf11afSPaul Mackerras 49214cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xd00, single_step) 49314cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xe00, trap_0e) 49414cf11afSPaul Mackerras 49514cf11afSPaul Mackerras /* We need to deal with the Altivec unavailable exception 49614cf11afSPaul Mackerras * here which is at 0xf20, thus in the middle of the 49714cf11afSPaul Mackerras * prolog code of the PerformanceMonitor one. A little 49814cf11afSPaul Mackerras * trickery is thus necessary 49914cf11afSPaul Mackerras */ 50014cf11afSPaul Mackerras . = 0xf00 50114cf11afSPaul Mackerras b performance_monitor_pSeries 50214cf11afSPaul Mackerras 50314cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) 50414cf11afSPaul Mackerras 50514cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) 50614cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(0x1700, altivec_assist) 50714cf11afSPaul Mackerras 50814cf11afSPaul Mackerras . = 0x3000 50914cf11afSPaul Mackerras 51014cf11afSPaul Mackerras/*** pSeries interrupt support ***/ 51114cf11afSPaul Mackerras 51214cf11afSPaul Mackerras /* moved from 0xf00 */ 51314cf11afSPaul Mackerras STD_EXCEPTION_PSERIES(., performance_monitor) 51414cf11afSPaul Mackerras 51514cf11afSPaul Mackerras .align 7 51614cf11afSPaul Mackerras_GLOBAL(do_stab_bolted_pSeries) 51714cf11afSPaul Mackerras mtcrf 0x80,r12 518b5bbeb23SPaul Mackerras mfspr r12,SPRN_SPRG2 51914cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 52014cf11afSPaul Mackerras 52114cf11afSPaul Mackerras/* 5223c726f8dSBenjamin Herrenschmidt * We have some room here we use that to put 5233c726f8dSBenjamin Herrenschmidt * the peries slb miss user trampoline code so it's reasonably 5243c726f8dSBenjamin Herrenschmidt * away from slb_miss_user_common to avoid problems with rfid 5253c726f8dSBenjamin Herrenschmidt * 5263c726f8dSBenjamin Herrenschmidt * This is used for when the SLB miss handler has to go virtual, 5273c726f8dSBenjamin Herrenschmidt * which doesn't happen for now anymore but will once we re-implement 5283c726f8dSBenjamin Herrenschmidt * dynamic VSIDs for shared page tables 5293c726f8dSBenjamin Herrenschmidt */ 5303c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 5313c726f8dSBenjamin Herrenschmidtslb_miss_user_pseries: 5323c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_R10(r13) 5333c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R11(r13) 5343c726f8dSBenjamin Herrenschmidt std r12,PACA_EXGEN+EX_R12(r13) 5353c726f8dSBenjamin Herrenschmidt mfspr r10,SPRG1 5363c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXSLB+EX_R9(r13) 5373c726f8dSBenjamin Herrenschmidt ld r12,PACA_EXSLB+EX_R3(r13) 5383c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_R13(r13) 5393c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R9(r13) 5403c726f8dSBenjamin Herrenschmidt std r12,PACA_EXGEN+EX_R3(r13) 5413c726f8dSBenjamin Herrenschmidt clrrdi r12,r13,32 5423c726f8dSBenjamin Herrenschmidt mfmsr r10 5433c726f8dSBenjamin Herrenschmidt mfspr r11,SRR0 /* save SRR0 */ 5443c726f8dSBenjamin Herrenschmidt ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ 5453c726f8dSBenjamin Herrenschmidt ori r10,r10,MSR_IR|MSR_DR|MSR_RI 5463c726f8dSBenjamin Herrenschmidt mtspr SRR0,r12 5473c726f8dSBenjamin Herrenschmidt mfspr r12,SRR1 /* and SRR1 */ 5483c726f8dSBenjamin Herrenschmidt mtspr SRR1,r10 5493c726f8dSBenjamin Herrenschmidt rfid 5503c726f8dSBenjamin Herrenschmidt b . /* prevent spec. execution */ 5513c726f8dSBenjamin Herrenschmidt#endif /* __DISABLED__ */ 5523c726f8dSBenjamin Herrenschmidt 5533c726f8dSBenjamin Herrenschmidt/* 55414cf11afSPaul Mackerras * Vectors for the FWNMI option. Share common code. 55514cf11afSPaul Mackerras */ 55614cf11afSPaul Mackerras .globl system_reset_fwnmi 55714cf11afSPaul Mackerrassystem_reset_fwnmi: 55814cf11afSPaul Mackerras HMT_MEDIUM 559b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 56014cf11afSPaul Mackerras RUNLATCH_ON(r13) 56114cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) 56214cf11afSPaul Mackerras 56314cf11afSPaul Mackerras .globl machine_check_fwnmi 56414cf11afSPaul Mackerrasmachine_check_fwnmi: 56514cf11afSPaul Mackerras HMT_MEDIUM 566b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 56714cf11afSPaul Mackerras RUNLATCH_ON(r13) 56814cf11afSPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 56914cf11afSPaul Mackerras 57014cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 57114cf11afSPaul Mackerras/*** ISeries-LPAR interrupt handlers ***/ 57214cf11afSPaul Mackerras 57314cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) 57414cf11afSPaul Mackerras 57514cf11afSPaul Mackerras .globl data_access_iSeries 57614cf11afSPaul Mackerrasdata_access_iSeries: 577b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 57814cf11afSPaul MackerrasBEGIN_FTR_SECTION 579b5bbeb23SPaul Mackerras mtspr SPRN_SPRG2,r12 580b5bbeb23SPaul Mackerras mfspr r13,SPRN_DAR 581b5bbeb23SPaul Mackerras mfspr r12,SPRN_DSISR 58214cf11afSPaul Mackerras srdi r13,r13,60 58314cf11afSPaul Mackerras rlwimi r13,r12,16,0x20 58414cf11afSPaul Mackerras mfcr r12 58514cf11afSPaul Mackerras cmpwi r13,0x2c 58614cf11afSPaul Mackerras beq .do_stab_bolted_iSeries 58714cf11afSPaul Mackerras mtcrf 0x80,r12 588b5bbeb23SPaul Mackerras mfspr r12,SPRN_SPRG2 58914cf11afSPaul MackerrasEND_FTR_SECTION_IFCLR(CPU_FTR_SLB) 59014cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) 59114cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2 59214cf11afSPaul Mackerras b data_access_common 59314cf11afSPaul Mackerras 59414cf11afSPaul Mackerras.do_stab_bolted_iSeries: 59514cf11afSPaul Mackerras mtcrf 0x80,r12 596b5bbeb23SPaul Mackerras mfspr r12,SPRN_SPRG2 59714cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) 59814cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2 59914cf11afSPaul Mackerras b .do_stab_bolted 60014cf11afSPaul Mackerras 60114cf11afSPaul Mackerras .globl data_access_slb_iSeries 60214cf11afSPaul Mackerrasdata_access_slb_iSeries: 603b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 6043c726f8dSBenjamin Herrenschmidt mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 60514cf11afSPaul Mackerras std r3,PACA_EXSLB+EX_R3(r13) 606b5bbeb23SPaul Mackerras mfspr r3,SPRN_DAR 6073c726f8dSBenjamin Herrenschmidt std r9,PACA_EXSLB+EX_R9(r13) 6083c726f8dSBenjamin Herrenschmidt mfcr r9 6093c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 6103c726f8dSBenjamin Herrenschmidt cmpdi r3,0 6113c726f8dSBenjamin Herrenschmidt bge slb_miss_user_iseries 6123c726f8dSBenjamin Herrenschmidt#endif 6133c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R10(r13) 6143c726f8dSBenjamin Herrenschmidt std r11,PACA_EXSLB+EX_R11(r13) 6153c726f8dSBenjamin Herrenschmidt std r12,PACA_EXSLB+EX_R12(r13) 6163c726f8dSBenjamin Herrenschmidt mfspr r10,SPRN_SPRG1 6173c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R13(r13) 6183c726f8dSBenjamin Herrenschmidt ld r12,PACALPPACA+LPPACASRR1(r13); 6193c726f8dSBenjamin Herrenschmidt b .slb_miss_realmode 62014cf11afSPaul Mackerras 62114cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) 62214cf11afSPaul Mackerras 62314cf11afSPaul Mackerras .globl instruction_access_slb_iSeries 62414cf11afSPaul Mackerrasinstruction_access_slb_iSeries: 625b5bbeb23SPaul Mackerras mtspr SPRN_SPRG1,r13 /* save r13 */ 6263c726f8dSBenjamin Herrenschmidt mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 62714cf11afSPaul Mackerras std r3,PACA_EXSLB+EX_R3(r13) 6283c726f8dSBenjamin Herrenschmidt ld r3,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */ 6293c726f8dSBenjamin Herrenschmidt std r9,PACA_EXSLB+EX_R9(r13) 6303c726f8dSBenjamin Herrenschmidt mfcr r9 6313c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 6323c726f8dSBenjamin Herrenschmidt cmpdi r3,0 6333c726f8dSBenjamin Herrenschmidt bge .slb_miss_user_iseries 6343c726f8dSBenjamin Herrenschmidt#endif 6353c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R10(r13) 6363c726f8dSBenjamin Herrenschmidt std r11,PACA_EXSLB+EX_R11(r13) 6373c726f8dSBenjamin Herrenschmidt std r12,PACA_EXSLB+EX_R12(r13) 6383c726f8dSBenjamin Herrenschmidt mfspr r10,SPRN_SPRG1 6393c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_R13(r13) 6403c726f8dSBenjamin Herrenschmidt ld r12,PACALPPACA+LPPACASRR1(r13); 6413c726f8dSBenjamin Herrenschmidt b .slb_miss_realmode 6423c726f8dSBenjamin Herrenschmidt 6433c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 6443c726f8dSBenjamin Herrenschmidtslb_miss_user_iseries: 6453c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_R10(r13) 6463c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R11(r13) 6473c726f8dSBenjamin Herrenschmidt std r12,PACA_EXGEN+EX_R12(r13) 6483c726f8dSBenjamin Herrenschmidt mfspr r10,SPRG1 6493c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXSLB+EX_R9(r13) 6503c726f8dSBenjamin Herrenschmidt ld r12,PACA_EXSLB+EX_R3(r13) 6513c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_R13(r13) 6523c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R9(r13) 6533c726f8dSBenjamin Herrenschmidt std r12,PACA_EXGEN+EX_R3(r13) 6543c726f8dSBenjamin Herrenschmidt EXCEPTION_PROLOG_ISERIES_2 6553c726f8dSBenjamin Herrenschmidt b slb_miss_user_common 6563c726f8dSBenjamin Herrenschmidt#endif 65714cf11afSPaul Mackerras 65814cf11afSPaul Mackerras MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) 65914cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) 66014cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) 66114cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) 66214cf11afSPaul Mackerras MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) 66314cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) 66414cf11afSPaul Mackerras STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) 66514cf11afSPaul Mackerras 66614cf11afSPaul Mackerras .globl system_call_iSeries 66714cf11afSPaul Mackerrassystem_call_iSeries: 66814cf11afSPaul Mackerras mr r9,r13 669b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 67014cf11afSPaul Mackerras EXCEPTION_PROLOG_ISERIES_2 67114cf11afSPaul Mackerras b system_call_common 67214cf11afSPaul Mackerras 67314cf11afSPaul Mackerras STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) 67414cf11afSPaul Mackerras STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) 67514cf11afSPaul Mackerras STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) 67614cf11afSPaul Mackerras 67714cf11afSPaul Mackerras .globl system_reset_iSeries 67814cf11afSPaul Mackerrassystem_reset_iSeries: 679b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 /* Get paca address */ 68014cf11afSPaul Mackerras mfmsr r24 68114cf11afSPaul Mackerras ori r24,r24,MSR_RI 68214cf11afSPaul Mackerras mtmsrd r24 /* RI on */ 68314cf11afSPaul Mackerras lhz r24,PACAPACAINDEX(r13) /* Get processor # */ 68414cf11afSPaul Mackerras cmpwi 0,r24,0 /* Are we processor 0? */ 68514cf11afSPaul Mackerras beq .__start_initialization_iSeries /* Start up the first processor */ 68614cf11afSPaul Mackerras mfspr r4,SPRN_CTRLF 68714cf11afSPaul Mackerras li r5,CTRL_RUNLATCH /* Turn off the run light */ 68814cf11afSPaul Mackerras andc r4,r4,r5 68914cf11afSPaul Mackerras mtspr SPRN_CTRLT,r4 69014cf11afSPaul Mackerras 69114cf11afSPaul Mackerras1: 69214cf11afSPaul Mackerras HMT_LOW 69314cf11afSPaul Mackerras#ifdef CONFIG_SMP 69414cf11afSPaul Mackerras lbz r23,PACAPROCSTART(r13) /* Test if this processor 69514cf11afSPaul Mackerras * should start */ 69614cf11afSPaul Mackerras sync 69714cf11afSPaul Mackerras LOADADDR(r3,current_set) 69814cf11afSPaul Mackerras sldi r28,r24,3 /* get current_set[cpu#] */ 69914cf11afSPaul Mackerras ldx r3,r3,r28 70014cf11afSPaul Mackerras addi r1,r3,THREAD_SIZE 70114cf11afSPaul Mackerras subi r1,r1,STACK_FRAME_OVERHEAD 70214cf11afSPaul Mackerras 70314cf11afSPaul Mackerras cmpwi 0,r23,0 70414cf11afSPaul Mackerras beq iSeries_secondary_smp_loop /* Loop until told to go */ 70514cf11afSPaul Mackerras bne .__secondary_start /* Loop until told to go */ 70614cf11afSPaul MackerrasiSeries_secondary_smp_loop: 70714cf11afSPaul Mackerras /* Let the Hypervisor know we are alive */ 70814cf11afSPaul Mackerras /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ 70914cf11afSPaul Mackerras lis r3,0x8002 71014cf11afSPaul Mackerras rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ 71114cf11afSPaul Mackerras#else /* CONFIG_SMP */ 71214cf11afSPaul Mackerras /* Yield the processor. This is required for non-SMP kernels 71314cf11afSPaul Mackerras which are running on multi-threaded machines. */ 71414cf11afSPaul Mackerras lis r3,0x8000 71514cf11afSPaul Mackerras rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ 71614cf11afSPaul Mackerras addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ 71714cf11afSPaul Mackerras li r4,0 /* "yield timed" */ 71814cf11afSPaul Mackerras li r5,-1 /* "yield forever" */ 71914cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 72014cf11afSPaul Mackerras li r0,-1 /* r0=-1 indicates a Hypervisor call */ 72114cf11afSPaul Mackerras sc /* Invoke the hypervisor via a system call */ 722b5bbeb23SPaul Mackerras mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ 72314cf11afSPaul Mackerras b 1b /* If SMP not configured, secondaries 72414cf11afSPaul Mackerras * loop forever */ 72514cf11afSPaul Mackerras 72614cf11afSPaul Mackerras .globl decrementer_iSeries_masked 72714cf11afSPaul Mackerrasdecrementer_iSeries_masked: 72814cf11afSPaul Mackerras li r11,1 72914cf11afSPaul Mackerras stb r11,PACALPPACA+LPPACADECRINT(r13) 73014cf11afSPaul Mackerras lwz r12,PACADEFAULTDECR(r13) 73114cf11afSPaul Mackerras mtspr SPRN_DEC,r12 73214cf11afSPaul Mackerras /* fall through */ 73314cf11afSPaul Mackerras 73414cf11afSPaul Mackerras .globl hardware_interrupt_iSeries_masked 73514cf11afSPaul Mackerrashardware_interrupt_iSeries_masked: 73614cf11afSPaul Mackerras mtcrf 0x80,r9 /* Restore regs */ 73714cf11afSPaul Mackerras ld r11,PACALPPACA+LPPACASRR0(r13) 73814cf11afSPaul Mackerras ld r12,PACALPPACA+LPPACASRR1(r13) 739b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r11 740b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r12 74114cf11afSPaul Mackerras ld r9,PACA_EXGEN+EX_R9(r13) 74214cf11afSPaul Mackerras ld r10,PACA_EXGEN+EX_R10(r13) 74314cf11afSPaul Mackerras ld r11,PACA_EXGEN+EX_R11(r13) 74414cf11afSPaul Mackerras ld r12,PACA_EXGEN+EX_R12(r13) 74514cf11afSPaul Mackerras ld r13,PACA_EXGEN+EX_R13(r13) 74614cf11afSPaul Mackerras rfid 74714cf11afSPaul Mackerras b . /* prevent speculative execution */ 74814cf11afSPaul Mackerras#endif /* CONFIG_PPC_ISERIES */ 74914cf11afSPaul Mackerras 75014cf11afSPaul Mackerras/*** Common interrupt handlers ***/ 75114cf11afSPaul Mackerras 75214cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) 75314cf11afSPaul Mackerras 75414cf11afSPaul Mackerras /* 75514cf11afSPaul Mackerras * Machine check is different because we use a different 75614cf11afSPaul Mackerras * save area: PACA_EXMC instead of PACA_EXGEN. 75714cf11afSPaul Mackerras */ 75814cf11afSPaul Mackerras .align 7 75914cf11afSPaul Mackerras .globl machine_check_common 76014cf11afSPaul Mackerrasmachine_check_common: 76114cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 76214cf11afSPaul Mackerras DISABLE_INTS 76314cf11afSPaul Mackerras bl .save_nvgprs 76414cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 76514cf11afSPaul Mackerras bl .machine_check_exception 76614cf11afSPaul Mackerras b .ret_from_except 76714cf11afSPaul Mackerras 76814cf11afSPaul Mackerras STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) 76914cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) 77014cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) 77114cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) 77214cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) 77314cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception) 77414cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) 77514cf11afSPaul Mackerras#ifdef CONFIG_ALTIVEC 77614cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) 77714cf11afSPaul Mackerras#else 77814cf11afSPaul Mackerras STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) 77914cf11afSPaul Mackerras#endif 78014cf11afSPaul Mackerras 78114cf11afSPaul Mackerras/* 78214cf11afSPaul Mackerras * Here we have detected that the kernel stack pointer is bad. 78314cf11afSPaul Mackerras * R9 contains the saved CR, r13 points to the paca, 78414cf11afSPaul Mackerras * r10 contains the (bad) kernel stack pointer, 78514cf11afSPaul Mackerras * r11 and r12 contain the saved SRR0 and SRR1. 78614cf11afSPaul Mackerras * We switch to using an emergency stack, save the registers there, 78714cf11afSPaul Mackerras * and call kernel_bad_stack(), which panics. 78814cf11afSPaul Mackerras */ 78914cf11afSPaul Mackerrasbad_stack: 79014cf11afSPaul Mackerras ld r1,PACAEMERGSP(r13) 79114cf11afSPaul Mackerras subi r1,r1,64+INT_FRAME_SIZE 79214cf11afSPaul Mackerras std r9,_CCR(r1) 79314cf11afSPaul Mackerras std r10,GPR1(r1) 79414cf11afSPaul Mackerras std r11,_NIP(r1) 79514cf11afSPaul Mackerras std r12,_MSR(r1) 796b5bbeb23SPaul Mackerras mfspr r11,SPRN_DAR 797b5bbeb23SPaul Mackerras mfspr r12,SPRN_DSISR 79814cf11afSPaul Mackerras std r11,_DAR(r1) 79914cf11afSPaul Mackerras std r12,_DSISR(r1) 80014cf11afSPaul Mackerras mflr r10 80114cf11afSPaul Mackerras mfctr r11 80214cf11afSPaul Mackerras mfxer r12 80314cf11afSPaul Mackerras std r10,_LINK(r1) 80414cf11afSPaul Mackerras std r11,_CTR(r1) 80514cf11afSPaul Mackerras std r12,_XER(r1) 80614cf11afSPaul Mackerras SAVE_GPR(0,r1) 80714cf11afSPaul Mackerras SAVE_GPR(2,r1) 80814cf11afSPaul Mackerras SAVE_4GPRS(3,r1) 80914cf11afSPaul Mackerras SAVE_2GPRS(7,r1) 81014cf11afSPaul Mackerras SAVE_10GPRS(12,r1) 81114cf11afSPaul Mackerras SAVE_10GPRS(22,r1) 81214cf11afSPaul Mackerras addi r11,r1,INT_FRAME_SIZE 81314cf11afSPaul Mackerras std r11,0(r1) 81414cf11afSPaul Mackerras li r12,0 81514cf11afSPaul Mackerras std r12,0(r11) 81614cf11afSPaul Mackerras ld r2,PACATOC(r13) 81714cf11afSPaul Mackerras1: addi r3,r1,STACK_FRAME_OVERHEAD 81814cf11afSPaul Mackerras bl .kernel_bad_stack 81914cf11afSPaul Mackerras b 1b 82014cf11afSPaul Mackerras 82114cf11afSPaul Mackerras/* 82214cf11afSPaul Mackerras * Return from an exception with minimal checks. 82314cf11afSPaul Mackerras * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. 82414cf11afSPaul Mackerras * If interrupts have been enabled, or anything has been 82514cf11afSPaul Mackerras * done that might have changed the scheduling status of 82614cf11afSPaul Mackerras * any task or sent any task a signal, you should use 82714cf11afSPaul Mackerras * ret_from_except or ret_from_except_lite instead of this. 82814cf11afSPaul Mackerras */ 82940ef8cbcSPaul Mackerras .globl fast_exception_return 83014cf11afSPaul Mackerrasfast_exception_return: 83114cf11afSPaul Mackerras ld r12,_MSR(r1) 83214cf11afSPaul Mackerras ld r11,_NIP(r1) 83314cf11afSPaul Mackerras andi. r3,r12,MSR_RI /* check if RI is set */ 83414cf11afSPaul Mackerras beq- unrecov_fer 83514cf11afSPaul Mackerras ld r3,_CCR(r1) 83614cf11afSPaul Mackerras ld r4,_LINK(r1) 83714cf11afSPaul Mackerras ld r5,_CTR(r1) 83814cf11afSPaul Mackerras ld r6,_XER(r1) 83914cf11afSPaul Mackerras mtcr r3 84014cf11afSPaul Mackerras mtlr r4 84114cf11afSPaul Mackerras mtctr r5 84214cf11afSPaul Mackerras mtxer r6 84314cf11afSPaul Mackerras REST_GPR(0, r1) 84414cf11afSPaul Mackerras REST_8GPRS(2, r1) 84514cf11afSPaul Mackerras 84614cf11afSPaul Mackerras mfmsr r10 84714cf11afSPaul Mackerras clrrdi r10,r10,2 /* clear RI (LE is 0 already) */ 84814cf11afSPaul Mackerras mtmsrd r10,1 84914cf11afSPaul Mackerras 850b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r12 851b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r11 85214cf11afSPaul Mackerras REST_4GPRS(10, r1) 85314cf11afSPaul Mackerras ld r1,GPR1(r1) 85414cf11afSPaul Mackerras rfid 85514cf11afSPaul Mackerras b . /* prevent speculative execution */ 85614cf11afSPaul Mackerras 85714cf11afSPaul Mackerrasunrecov_fer: 85814cf11afSPaul Mackerras bl .save_nvgprs 85914cf11afSPaul Mackerras1: addi r3,r1,STACK_FRAME_OVERHEAD 86014cf11afSPaul Mackerras bl .unrecoverable_exception 86114cf11afSPaul Mackerras b 1b 86214cf11afSPaul Mackerras 86314cf11afSPaul Mackerras/* 86414cf11afSPaul Mackerras * Here r13 points to the paca, r9 contains the saved CR, 86514cf11afSPaul Mackerras * SRR0 and SRR1 are saved in r11 and r12, 86614cf11afSPaul Mackerras * r9 - r13 are saved in paca->exgen. 86714cf11afSPaul Mackerras */ 86814cf11afSPaul Mackerras .align 7 86914cf11afSPaul Mackerras .globl data_access_common 87014cf11afSPaul Mackerrasdata_access_common: 87114cf11afSPaul Mackerras RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */ 872b5bbeb23SPaul Mackerras mfspr r10,SPRN_DAR 87314cf11afSPaul Mackerras std r10,PACA_EXGEN+EX_DAR(r13) 874b5bbeb23SPaul Mackerras mfspr r10,SPRN_DSISR 87514cf11afSPaul Mackerras stw r10,PACA_EXGEN+EX_DSISR(r13) 87614cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 87714cf11afSPaul Mackerras ld r3,PACA_EXGEN+EX_DAR(r13) 87814cf11afSPaul Mackerras lwz r4,PACA_EXGEN+EX_DSISR(r13) 87914cf11afSPaul Mackerras li r5,0x300 88014cf11afSPaul Mackerras b .do_hash_page /* Try to handle as hpte fault */ 88114cf11afSPaul Mackerras 88214cf11afSPaul Mackerras .align 7 88314cf11afSPaul Mackerras .globl instruction_access_common 88414cf11afSPaul Mackerrasinstruction_access_common: 88514cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 88614cf11afSPaul Mackerras ld r3,_NIP(r1) 88714cf11afSPaul Mackerras andis. r4,r12,0x5820 88814cf11afSPaul Mackerras li r5,0x400 88914cf11afSPaul Mackerras b .do_hash_page /* Try to handle as hpte fault */ 89014cf11afSPaul Mackerras 8913c726f8dSBenjamin Herrenschmidt/* 8923c726f8dSBenjamin Herrenschmidt * Here is the common SLB miss user that is used when going to virtual 8933c726f8dSBenjamin Herrenschmidt * mode for SLB misses, that is currently not used 8943c726f8dSBenjamin Herrenschmidt */ 8953c726f8dSBenjamin Herrenschmidt#ifdef __DISABLED__ 8963c726f8dSBenjamin Herrenschmidt .align 7 8973c726f8dSBenjamin Herrenschmidt .globl slb_miss_user_common 8983c726f8dSBenjamin Herrenschmidtslb_miss_user_common: 8993c726f8dSBenjamin Herrenschmidt mflr r10 9003c726f8dSBenjamin Herrenschmidt std r3,PACA_EXGEN+EX_DAR(r13) 9013c726f8dSBenjamin Herrenschmidt stw r9,PACA_EXGEN+EX_CCR(r13) 9023c726f8dSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_LR(r13) 9033c726f8dSBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_SRR0(r13) 9043c726f8dSBenjamin Herrenschmidt bl .slb_allocate_user 9053c726f8dSBenjamin Herrenschmidt 9063c726f8dSBenjamin Herrenschmidt ld r10,PACA_EXGEN+EX_LR(r13) 9073c726f8dSBenjamin Herrenschmidt ld r3,PACA_EXGEN+EX_R3(r13) 9083c726f8dSBenjamin Herrenschmidt lwz r9,PACA_EXGEN+EX_CCR(r13) 9093c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXGEN+EX_SRR0(r13) 9103c726f8dSBenjamin Herrenschmidt mtlr r10 9113c726f8dSBenjamin Herrenschmidt beq- slb_miss_fault 9123c726f8dSBenjamin Herrenschmidt 9133c726f8dSBenjamin Herrenschmidt andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 9143c726f8dSBenjamin Herrenschmidt beq- unrecov_user_slb 9153c726f8dSBenjamin Herrenschmidt mfmsr r10 9163c726f8dSBenjamin Herrenschmidt 9173c726f8dSBenjamin Herrenschmidt.machine push 9183c726f8dSBenjamin Herrenschmidt.machine "power4" 9193c726f8dSBenjamin Herrenschmidt mtcrf 0x80,r9 9203c726f8dSBenjamin Herrenschmidt.machine pop 9213c726f8dSBenjamin Herrenschmidt 9223c726f8dSBenjamin Herrenschmidt clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ 9233c726f8dSBenjamin Herrenschmidt mtmsrd r10,1 9243c726f8dSBenjamin Herrenschmidt 9253c726f8dSBenjamin Herrenschmidt mtspr SRR0,r11 9263c726f8dSBenjamin Herrenschmidt mtspr SRR1,r12 9273c726f8dSBenjamin Herrenschmidt 9283c726f8dSBenjamin Herrenschmidt ld r9,PACA_EXGEN+EX_R9(r13) 9293c726f8dSBenjamin Herrenschmidt ld r10,PACA_EXGEN+EX_R10(r13) 9303c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXGEN+EX_R11(r13) 9313c726f8dSBenjamin Herrenschmidt ld r12,PACA_EXGEN+EX_R12(r13) 9323c726f8dSBenjamin Herrenschmidt ld r13,PACA_EXGEN+EX_R13(r13) 9333c726f8dSBenjamin Herrenschmidt rfid 9343c726f8dSBenjamin Herrenschmidt b . 9353c726f8dSBenjamin Herrenschmidt 9363c726f8dSBenjamin Herrenschmidtslb_miss_fault: 9373c726f8dSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) 9383c726f8dSBenjamin Herrenschmidt ld r4,PACA_EXGEN+EX_DAR(r13) 9393c726f8dSBenjamin Herrenschmidt li r5,0 9403c726f8dSBenjamin Herrenschmidt std r4,_DAR(r1) 9413c726f8dSBenjamin Herrenschmidt std r5,_DSISR(r1) 9423c726f8dSBenjamin Herrenschmidt b .handle_page_fault 9433c726f8dSBenjamin Herrenschmidt 9443c726f8dSBenjamin Herrenschmidtunrecov_user_slb: 9453c726f8dSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) 9463c726f8dSBenjamin Herrenschmidt DISABLE_INTS 9473c726f8dSBenjamin Herrenschmidt bl .save_nvgprs 9483c726f8dSBenjamin Herrenschmidt1: addi r3,r1,STACK_FRAME_OVERHEAD 9493c726f8dSBenjamin Herrenschmidt bl .unrecoverable_exception 9503c726f8dSBenjamin Herrenschmidt b 1b 9513c726f8dSBenjamin Herrenschmidt 9523c726f8dSBenjamin Herrenschmidt#endif /* __DISABLED__ */ 9533c726f8dSBenjamin Herrenschmidt 9543c726f8dSBenjamin Herrenschmidt 9553c726f8dSBenjamin Herrenschmidt/* 9563c726f8dSBenjamin Herrenschmidt * r13 points to the PACA, r9 contains the saved CR, 9573c726f8dSBenjamin Herrenschmidt * r12 contain the saved SRR1, SRR0 is still ready for return 9583c726f8dSBenjamin Herrenschmidt * r3 has the faulting address 9593c726f8dSBenjamin Herrenschmidt * r9 - r13 are saved in paca->exslb. 9603c726f8dSBenjamin Herrenschmidt * r3 is saved in paca->slb_r3 9613c726f8dSBenjamin Herrenschmidt * We assume we aren't going to take any exceptions during this procedure. 9623c726f8dSBenjamin Herrenschmidt */ 9633c726f8dSBenjamin Herrenschmidt_GLOBAL(slb_miss_realmode) 9643c726f8dSBenjamin Herrenschmidt mflr r10 9653c726f8dSBenjamin Herrenschmidt 9663c726f8dSBenjamin Herrenschmidt stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 9673c726f8dSBenjamin Herrenschmidt std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 9683c726f8dSBenjamin Herrenschmidt 9693c726f8dSBenjamin Herrenschmidt bl .slb_allocate_realmode 9703c726f8dSBenjamin Herrenschmidt 9713c726f8dSBenjamin Herrenschmidt /* All done -- return from exception. */ 9723c726f8dSBenjamin Herrenschmidt 9733c726f8dSBenjamin Herrenschmidt ld r10,PACA_EXSLB+EX_LR(r13) 9743c726f8dSBenjamin Herrenschmidt ld r3,PACA_EXSLB+EX_R3(r13) 9753c726f8dSBenjamin Herrenschmidt lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 9763c726f8dSBenjamin Herrenschmidt#ifdef CONFIG_PPC_ISERIES 9773c726f8dSBenjamin Herrenschmidt ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */ 9783c726f8dSBenjamin Herrenschmidt#endif /* CONFIG_PPC_ISERIES */ 9793c726f8dSBenjamin Herrenschmidt 9803c726f8dSBenjamin Herrenschmidt mtlr r10 9813c726f8dSBenjamin Herrenschmidt 9823c726f8dSBenjamin Herrenschmidt andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 9833c726f8dSBenjamin Herrenschmidt beq- unrecov_slb 9843c726f8dSBenjamin Herrenschmidt 9853c726f8dSBenjamin Herrenschmidt.machine push 9863c726f8dSBenjamin Herrenschmidt.machine "power4" 9873c726f8dSBenjamin Herrenschmidt mtcrf 0x80,r9 9883c726f8dSBenjamin Herrenschmidt mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 9893c726f8dSBenjamin Herrenschmidt.machine pop 9903c726f8dSBenjamin Herrenschmidt 9913c726f8dSBenjamin Herrenschmidt#ifdef CONFIG_PPC_ISERIES 9923c726f8dSBenjamin Herrenschmidt mtspr SPRN_SRR0,r11 9933c726f8dSBenjamin Herrenschmidt mtspr SPRN_SRR1,r12 9943c726f8dSBenjamin Herrenschmidt#endif /* CONFIG_PPC_ISERIES */ 9953c726f8dSBenjamin Herrenschmidt ld r9,PACA_EXSLB+EX_R9(r13) 9963c726f8dSBenjamin Herrenschmidt ld r10,PACA_EXSLB+EX_R10(r13) 9973c726f8dSBenjamin Herrenschmidt ld r11,PACA_EXSLB+EX_R11(r13) 9983c726f8dSBenjamin Herrenschmidt ld r12,PACA_EXSLB+EX_R12(r13) 9993c726f8dSBenjamin Herrenschmidt ld r13,PACA_EXSLB+EX_R13(r13) 10003c726f8dSBenjamin Herrenschmidt rfid 10013c726f8dSBenjamin Herrenschmidt b . /* prevent speculative execution */ 10023c726f8dSBenjamin Herrenschmidt 10033c726f8dSBenjamin Herrenschmidtunrecov_slb: 10043c726f8dSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 10053c726f8dSBenjamin Herrenschmidt DISABLE_INTS 10063c726f8dSBenjamin Herrenschmidt bl .save_nvgprs 10073c726f8dSBenjamin Herrenschmidt1: addi r3,r1,STACK_FRAME_OVERHEAD 10083c726f8dSBenjamin Herrenschmidt bl .unrecoverable_exception 10093c726f8dSBenjamin Herrenschmidt b 1b 10103c726f8dSBenjamin Herrenschmidt 101114cf11afSPaul Mackerras .align 7 101214cf11afSPaul Mackerras .globl hardware_interrupt_common 101314cf11afSPaul Mackerras .globl hardware_interrupt_entry 101414cf11afSPaul Mackerrashardware_interrupt_common: 101514cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) 101614cf11afSPaul Mackerrashardware_interrupt_entry: 101714cf11afSPaul Mackerras DISABLE_INTS 101814cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 101914cf11afSPaul Mackerras bl .do_IRQ 102014cf11afSPaul Mackerras b .ret_from_except_lite 102114cf11afSPaul Mackerras 102214cf11afSPaul Mackerras .align 7 102314cf11afSPaul Mackerras .globl alignment_common 102414cf11afSPaul Mackerrasalignment_common: 1025b5bbeb23SPaul Mackerras mfspr r10,SPRN_DAR 102614cf11afSPaul Mackerras std r10,PACA_EXGEN+EX_DAR(r13) 1027b5bbeb23SPaul Mackerras mfspr r10,SPRN_DSISR 102814cf11afSPaul Mackerras stw r10,PACA_EXGEN+EX_DSISR(r13) 102914cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 103014cf11afSPaul Mackerras ld r3,PACA_EXGEN+EX_DAR(r13) 103114cf11afSPaul Mackerras lwz r4,PACA_EXGEN+EX_DSISR(r13) 103214cf11afSPaul Mackerras std r3,_DAR(r1) 103314cf11afSPaul Mackerras std r4,_DSISR(r1) 103414cf11afSPaul Mackerras bl .save_nvgprs 103514cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 103614cf11afSPaul Mackerras ENABLE_INTS 103714cf11afSPaul Mackerras bl .alignment_exception 103814cf11afSPaul Mackerras b .ret_from_except 103914cf11afSPaul Mackerras 104014cf11afSPaul Mackerras .align 7 104114cf11afSPaul Mackerras .globl program_check_common 104214cf11afSPaul Mackerrasprogram_check_common: 104314cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 104414cf11afSPaul Mackerras bl .save_nvgprs 104514cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 104614cf11afSPaul Mackerras ENABLE_INTS 104714cf11afSPaul Mackerras bl .program_check_exception 104814cf11afSPaul Mackerras b .ret_from_except 104914cf11afSPaul Mackerras 105014cf11afSPaul Mackerras .align 7 105114cf11afSPaul Mackerras .globl fp_unavailable_common 105214cf11afSPaul Mackerrasfp_unavailable_common: 105314cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 105414cf11afSPaul Mackerras bne .load_up_fpu /* if from user, just load it up */ 105514cf11afSPaul Mackerras bl .save_nvgprs 105614cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 105714cf11afSPaul Mackerras ENABLE_INTS 105814cf11afSPaul Mackerras bl .kernel_fp_unavailable_exception 105914cf11afSPaul Mackerras BUG_OPCODE 106014cf11afSPaul Mackerras 106114cf11afSPaul Mackerras .align 7 106214cf11afSPaul Mackerras .globl altivec_unavailable_common 106314cf11afSPaul Mackerrasaltivec_unavailable_common: 106414cf11afSPaul Mackerras EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 106514cf11afSPaul Mackerras#ifdef CONFIG_ALTIVEC 106614cf11afSPaul MackerrasBEGIN_FTR_SECTION 106714cf11afSPaul Mackerras bne .load_up_altivec /* if from user, just load it up */ 106814cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 106914cf11afSPaul Mackerras#endif 107014cf11afSPaul Mackerras bl .save_nvgprs 107114cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 107214cf11afSPaul Mackerras ENABLE_INTS 107314cf11afSPaul Mackerras bl .altivec_unavailable_exception 107414cf11afSPaul Mackerras b .ret_from_except 107514cf11afSPaul Mackerras 107614cf11afSPaul Mackerras#ifdef CONFIG_ALTIVEC 107714cf11afSPaul Mackerras/* 107814cf11afSPaul Mackerras * load_up_altivec(unused, unused, tsk) 107914cf11afSPaul Mackerras * Disable VMX for the task which had it previously, 108014cf11afSPaul Mackerras * and save its vector registers in its thread_struct. 108114cf11afSPaul Mackerras * Enables the VMX for use in the kernel on return. 108214cf11afSPaul Mackerras * On SMP we know the VMX is free, since we give it up every 108314cf11afSPaul Mackerras * switch (ie, no lazy save of the vector registers). 108414cf11afSPaul Mackerras * On entry: r13 == 'current' && last_task_used_altivec != 'current' 108514cf11afSPaul Mackerras */ 108614cf11afSPaul Mackerras_STATIC(load_up_altivec) 108714cf11afSPaul Mackerras mfmsr r5 /* grab the current MSR */ 108814cf11afSPaul Mackerras oris r5,r5,MSR_VEC@h 108914cf11afSPaul Mackerras mtmsrd r5 /* enable use of VMX now */ 109014cf11afSPaul Mackerras isync 109114cf11afSPaul Mackerras 109214cf11afSPaul Mackerras/* 109314cf11afSPaul Mackerras * For SMP, we don't do lazy VMX switching because it just gets too 109414cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 109514cf11afSPaul Mackerras * to another. Instead we call giveup_altvec in switch_to. 109614cf11afSPaul Mackerras * VRSAVE isn't dealt with here, that is done in the normal context 109714cf11afSPaul Mackerras * switch code. Note that we could rely on vrsave value to eventually 109814cf11afSPaul Mackerras * avoid saving all of the VREGs here... 109914cf11afSPaul Mackerras */ 110014cf11afSPaul Mackerras#ifndef CONFIG_SMP 110114cf11afSPaul Mackerras ld r3,last_task_used_altivec@got(r2) 110214cf11afSPaul Mackerras ld r4,0(r3) 110314cf11afSPaul Mackerras cmpdi 0,r4,0 110414cf11afSPaul Mackerras beq 1f 110514cf11afSPaul Mackerras /* Save VMX state to last_task_used_altivec's THREAD struct */ 110614cf11afSPaul Mackerras addi r4,r4,THREAD 110714cf11afSPaul Mackerras SAVE_32VRS(0,r5,r4) 110814cf11afSPaul Mackerras mfvscr vr0 110914cf11afSPaul Mackerras li r10,THREAD_VSCR 111014cf11afSPaul Mackerras stvx vr0,r10,r4 111114cf11afSPaul Mackerras /* Disable VMX for last_task_used_altivec */ 111214cf11afSPaul Mackerras ld r5,PT_REGS(r4) 111314cf11afSPaul Mackerras ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 111414cf11afSPaul Mackerras lis r6,MSR_VEC@h 111514cf11afSPaul Mackerras andc r4,r4,r6 111614cf11afSPaul Mackerras std r4,_MSR-STACK_FRAME_OVERHEAD(r5) 111714cf11afSPaul Mackerras1: 111814cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 111914cf11afSPaul Mackerras /* Hack: if we get an altivec unavailable trap with VRSAVE 112014cf11afSPaul Mackerras * set to all zeros, we assume this is a broken application 112114cf11afSPaul Mackerras * that fails to set it properly, and thus we switch it to 112214cf11afSPaul Mackerras * all 1's 112314cf11afSPaul Mackerras */ 112414cf11afSPaul Mackerras mfspr r4,SPRN_VRSAVE 112514cf11afSPaul Mackerras cmpdi 0,r4,0 112614cf11afSPaul Mackerras bne+ 1f 112714cf11afSPaul Mackerras li r4,-1 112814cf11afSPaul Mackerras mtspr SPRN_VRSAVE,r4 112914cf11afSPaul Mackerras1: 113014cf11afSPaul Mackerras /* enable use of VMX after return */ 113114cf11afSPaul Mackerras ld r4,PACACURRENT(r13) 113214cf11afSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 113314cf11afSPaul Mackerras oris r12,r12,MSR_VEC@h 113414cf11afSPaul Mackerras std r12,_MSR(r1) 113514cf11afSPaul Mackerras li r4,1 113614cf11afSPaul Mackerras li r10,THREAD_VSCR 113714cf11afSPaul Mackerras stw r4,THREAD_USED_VR(r5) 113814cf11afSPaul Mackerras lvx vr0,r10,r5 113914cf11afSPaul Mackerras mtvscr vr0 114014cf11afSPaul Mackerras REST_32VRS(0,r4,r5) 114114cf11afSPaul Mackerras#ifndef CONFIG_SMP 114214cf11afSPaul Mackerras /* Update last_task_used_math to 'current' */ 114314cf11afSPaul Mackerras subi r4,r5,THREAD /* Back to 'current' */ 114414cf11afSPaul Mackerras std r4,0(r3) 114514cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 114614cf11afSPaul Mackerras /* restore registers and return */ 114714cf11afSPaul Mackerras b fast_exception_return 114814cf11afSPaul Mackerras#endif /* CONFIG_ALTIVEC */ 114914cf11afSPaul Mackerras 115014cf11afSPaul Mackerras/* 115114cf11afSPaul Mackerras * Hash table stuff 115214cf11afSPaul Mackerras */ 115314cf11afSPaul Mackerras .align 7 115414cf11afSPaul Mackerras_GLOBAL(do_hash_page) 115514cf11afSPaul Mackerras std r3,_DAR(r1) 115614cf11afSPaul Mackerras std r4,_DSISR(r1) 115714cf11afSPaul Mackerras 115814cf11afSPaul Mackerras andis. r0,r4,0xa450 /* weird error? */ 115914cf11afSPaul Mackerras bne- .handle_page_fault /* if not, try to insert a HPTE */ 116014cf11afSPaul MackerrasBEGIN_FTR_SECTION 116114cf11afSPaul Mackerras andis. r0,r4,0x0020 /* Is it a segment table fault? */ 116214cf11afSPaul Mackerras bne- .do_ste_alloc /* If so handle it */ 116314cf11afSPaul MackerrasEND_FTR_SECTION_IFCLR(CPU_FTR_SLB) 116414cf11afSPaul Mackerras 116514cf11afSPaul Mackerras /* 116614cf11afSPaul Mackerras * We need to set the _PAGE_USER bit if MSR_PR is set or if we are 116714cf11afSPaul Mackerras * accessing a userspace segment (even from the kernel). We assume 116814cf11afSPaul Mackerras * kernel addresses always have the high bit set. 116914cf11afSPaul Mackerras */ 117014cf11afSPaul Mackerras rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ 117114cf11afSPaul Mackerras rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ 117214cf11afSPaul Mackerras orc r0,r12,r0 /* MSR_PR | ~high_bit */ 117314cf11afSPaul Mackerras rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ 117414cf11afSPaul Mackerras ori r4,r4,1 /* add _PAGE_PRESENT */ 117514cf11afSPaul Mackerras rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ 117614cf11afSPaul Mackerras 117714cf11afSPaul Mackerras /* 117814cf11afSPaul Mackerras * On iSeries, we soft-disable interrupts here, then 117914cf11afSPaul Mackerras * hard-enable interrupts so that the hash_page code can spin on 118014cf11afSPaul Mackerras * the hash_table_lock without problems on a shared processor. 118114cf11afSPaul Mackerras */ 118214cf11afSPaul Mackerras DISABLE_INTS 118314cf11afSPaul Mackerras 118414cf11afSPaul Mackerras /* 118514cf11afSPaul Mackerras * r3 contains the faulting address 118614cf11afSPaul Mackerras * r4 contains the required access permissions 118714cf11afSPaul Mackerras * r5 contains the trap number 118814cf11afSPaul Mackerras * 118914cf11afSPaul Mackerras * at return r3 = 0 for success 119014cf11afSPaul Mackerras */ 119114cf11afSPaul Mackerras bl .hash_page /* build HPTE if possible */ 119214cf11afSPaul Mackerras cmpdi r3,0 /* see if hash_page succeeded */ 119314cf11afSPaul Mackerras 119414cf11afSPaul Mackerras#ifdef DO_SOFT_DISABLE 119514cf11afSPaul Mackerras /* 119614cf11afSPaul Mackerras * If we had interrupts soft-enabled at the point where the 119714cf11afSPaul Mackerras * DSI/ISI occurred, and an interrupt came in during hash_page, 119814cf11afSPaul Mackerras * handle it now. 119914cf11afSPaul Mackerras * We jump to ret_from_except_lite rather than fast_exception_return 120014cf11afSPaul Mackerras * because ret_from_except_lite will check for and handle pending 120114cf11afSPaul Mackerras * interrupts if necessary. 120214cf11afSPaul Mackerras */ 120314cf11afSPaul Mackerras beq .ret_from_except_lite 120414cf11afSPaul Mackerras /* For a hash failure, we don't bother re-enabling interrupts */ 120514cf11afSPaul Mackerras ble- 12f 120614cf11afSPaul Mackerras 120714cf11afSPaul Mackerras /* 120814cf11afSPaul Mackerras * hash_page couldn't handle it, set soft interrupt enable back 120914cf11afSPaul Mackerras * to what it was before the trap. Note that .local_irq_restore 121014cf11afSPaul Mackerras * handles any interrupts pending at this point. 121114cf11afSPaul Mackerras */ 121214cf11afSPaul Mackerras ld r3,SOFTE(r1) 121314cf11afSPaul Mackerras bl .local_irq_restore 121414cf11afSPaul Mackerras b 11f 121514cf11afSPaul Mackerras#else 121614cf11afSPaul Mackerras beq fast_exception_return /* Return from exception on success */ 121714cf11afSPaul Mackerras ble- 12f /* Failure return from hash_page */ 121814cf11afSPaul Mackerras 121914cf11afSPaul Mackerras /* fall through */ 122014cf11afSPaul Mackerras#endif 122114cf11afSPaul Mackerras 122214cf11afSPaul Mackerras/* Here we have a page fault that hash_page can't handle. */ 122314cf11afSPaul Mackerras_GLOBAL(handle_page_fault) 122414cf11afSPaul Mackerras ENABLE_INTS 122514cf11afSPaul Mackerras11: ld r4,_DAR(r1) 122614cf11afSPaul Mackerras ld r5,_DSISR(r1) 122714cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 122814cf11afSPaul Mackerras bl .do_page_fault 122914cf11afSPaul Mackerras cmpdi r3,0 123014cf11afSPaul Mackerras beq+ .ret_from_except_lite 123114cf11afSPaul Mackerras bl .save_nvgprs 123214cf11afSPaul Mackerras mr r5,r3 123314cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 123414cf11afSPaul Mackerras lwz r4,_DAR(r1) 123514cf11afSPaul Mackerras bl .bad_page_fault 123614cf11afSPaul Mackerras b .ret_from_except 123714cf11afSPaul Mackerras 123814cf11afSPaul Mackerras/* We have a page fault that hash_page could handle but HV refused 123914cf11afSPaul Mackerras * the PTE insertion 124014cf11afSPaul Mackerras */ 124114cf11afSPaul Mackerras12: bl .save_nvgprs 124214cf11afSPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 124314cf11afSPaul Mackerras lwz r4,_DAR(r1) 124414cf11afSPaul Mackerras bl .low_hash_fault 124514cf11afSPaul Mackerras b .ret_from_except 124614cf11afSPaul Mackerras 124714cf11afSPaul Mackerras /* here we have a segment miss */ 124814cf11afSPaul Mackerras_GLOBAL(do_ste_alloc) 124914cf11afSPaul Mackerras bl .ste_allocate /* try to insert stab entry */ 125014cf11afSPaul Mackerras cmpdi r3,0 125114cf11afSPaul Mackerras beq+ fast_exception_return 125214cf11afSPaul Mackerras b .handle_page_fault 125314cf11afSPaul Mackerras 125414cf11afSPaul Mackerras/* 125514cf11afSPaul Mackerras * r13 points to the PACA, r9 contains the saved CR, 125614cf11afSPaul Mackerras * r11 and r12 contain the saved SRR0 and SRR1. 125714cf11afSPaul Mackerras * r9 - r13 are saved in paca->exslb. 125814cf11afSPaul Mackerras * We assume we aren't going to take any exceptions during this procedure. 125914cf11afSPaul Mackerras * We assume (DAR >> 60) == 0xc. 126014cf11afSPaul Mackerras */ 126114cf11afSPaul Mackerras .align 7 126214cf11afSPaul Mackerras_GLOBAL(do_stab_bolted) 126314cf11afSPaul Mackerras stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 126414cf11afSPaul Mackerras std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ 126514cf11afSPaul Mackerras 126614cf11afSPaul Mackerras /* Hash to the primary group */ 126714cf11afSPaul Mackerras ld r10,PACASTABVIRT(r13) 1268b5bbeb23SPaul Mackerras mfspr r11,SPRN_DAR 126914cf11afSPaul Mackerras srdi r11,r11,28 127014cf11afSPaul Mackerras rldimi r10,r11,7,52 /* r10 = first ste of the group */ 127114cf11afSPaul Mackerras 127214cf11afSPaul Mackerras /* Calculate VSID */ 127314cf11afSPaul Mackerras /* This is a kernel address, so protovsid = ESID */ 127414cf11afSPaul Mackerras ASM_VSID_SCRAMBLE(r11, r9) 127514cf11afSPaul Mackerras rldic r9,r11,12,16 /* r9 = vsid << 12 */ 127614cf11afSPaul Mackerras 127714cf11afSPaul Mackerras /* Search the primary group for a free entry */ 127814cf11afSPaul Mackerras1: ld r11,0(r10) /* Test valid bit of the current ste */ 127914cf11afSPaul Mackerras andi. r11,r11,0x80 128014cf11afSPaul Mackerras beq 2f 128114cf11afSPaul Mackerras addi r10,r10,16 128214cf11afSPaul Mackerras andi. r11,r10,0x70 128314cf11afSPaul Mackerras bne 1b 128414cf11afSPaul Mackerras 128514cf11afSPaul Mackerras /* Stick for only searching the primary group for now. */ 128614cf11afSPaul Mackerras /* At least for now, we use a very simple random castout scheme */ 128714cf11afSPaul Mackerras /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ 128814cf11afSPaul Mackerras mftb r11 128914cf11afSPaul Mackerras rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ 129014cf11afSPaul Mackerras ori r11,r11,0x10 129114cf11afSPaul Mackerras 129214cf11afSPaul Mackerras /* r10 currently points to an ste one past the group of interest */ 129314cf11afSPaul Mackerras /* make it point to the randomly selected entry */ 129414cf11afSPaul Mackerras subi r10,r10,128 129514cf11afSPaul Mackerras or r10,r10,r11 /* r10 is the entry to invalidate */ 129614cf11afSPaul Mackerras 129714cf11afSPaul Mackerras isync /* mark the entry invalid */ 129814cf11afSPaul Mackerras ld r11,0(r10) 129914cf11afSPaul Mackerras rldicl r11,r11,56,1 /* clear the valid bit */ 130014cf11afSPaul Mackerras rotldi r11,r11,8 130114cf11afSPaul Mackerras std r11,0(r10) 130214cf11afSPaul Mackerras sync 130314cf11afSPaul Mackerras 130414cf11afSPaul Mackerras clrrdi r11,r11,28 /* Get the esid part of the ste */ 130514cf11afSPaul Mackerras slbie r11 130614cf11afSPaul Mackerras 130714cf11afSPaul Mackerras2: std r9,8(r10) /* Store the vsid part of the ste */ 130814cf11afSPaul Mackerras eieio 130914cf11afSPaul Mackerras 1310b5bbeb23SPaul Mackerras mfspr r11,SPRN_DAR /* Get the new esid */ 131114cf11afSPaul Mackerras clrrdi r11,r11,28 /* Permits a full 32b of ESID */ 131214cf11afSPaul Mackerras ori r11,r11,0x90 /* Turn on valid and kp */ 131314cf11afSPaul Mackerras std r11,0(r10) /* Put new entry back into the stab */ 131414cf11afSPaul Mackerras 131514cf11afSPaul Mackerras sync 131614cf11afSPaul Mackerras 131714cf11afSPaul Mackerras /* All done -- return from exception. */ 131814cf11afSPaul Mackerras lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 131914cf11afSPaul Mackerras ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ 132014cf11afSPaul Mackerras 132114cf11afSPaul Mackerras andi. r10,r12,MSR_RI 132214cf11afSPaul Mackerras beq- unrecov_slb 132314cf11afSPaul Mackerras 132414cf11afSPaul Mackerras mtcrf 0x80,r9 /* restore CR */ 132514cf11afSPaul Mackerras 132614cf11afSPaul Mackerras mfmsr r10 132714cf11afSPaul Mackerras clrrdi r10,r10,2 132814cf11afSPaul Mackerras mtmsrd r10,1 132914cf11afSPaul Mackerras 1330b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r11 1331b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r12 133214cf11afSPaul Mackerras ld r9,PACA_EXSLB+EX_R9(r13) 133314cf11afSPaul Mackerras ld r10,PACA_EXSLB+EX_R10(r13) 133414cf11afSPaul Mackerras ld r11,PACA_EXSLB+EX_R11(r13) 133514cf11afSPaul Mackerras ld r12,PACA_EXSLB+EX_R12(r13) 133614cf11afSPaul Mackerras ld r13,PACA_EXSLB+EX_R13(r13) 133714cf11afSPaul Mackerras rfid 133814cf11afSPaul Mackerras b . /* prevent speculative execution */ 133914cf11afSPaul Mackerras 134014cf11afSPaul Mackerras/* 134114cf11afSPaul Mackerras * Space for CPU0's segment table. 134214cf11afSPaul Mackerras * 134314cf11afSPaul Mackerras * On iSeries, the hypervisor must fill in at least one entry before 134414cf11afSPaul Mackerras * we get control (with relocate on). The address is give to the hv 1345ee400b63SStephen Rothwell * as a page number (see xLparMap in lpardata.c), so this must be at a 134614cf11afSPaul Mackerras * fixed address (the linker can't compute (u64)&initial_stab >> 134714cf11afSPaul Mackerras * PAGE_SHIFT). 134814cf11afSPaul Mackerras */ 134914cf11afSPaul Mackerras . = STAB0_PHYS_ADDR /* 0x6000 */ 135014cf11afSPaul Mackerras .globl initial_stab 135114cf11afSPaul Mackerrasinitial_stab: 135214cf11afSPaul Mackerras .space 4096 135314cf11afSPaul Mackerras 135414cf11afSPaul Mackerras/* 135514cf11afSPaul Mackerras * Data area reserved for FWNMI option. 135614cf11afSPaul Mackerras * This address (0x7000) is fixed by the RPA. 135714cf11afSPaul Mackerras */ 135814cf11afSPaul Mackerras .= 0x7000 135914cf11afSPaul Mackerras .globl fwnmi_data_area 136014cf11afSPaul Mackerrasfwnmi_data_area: 136114cf11afSPaul Mackerras 136214cf11afSPaul Mackerras /* iSeries does not use the FWNMI stuff, so it is safe to put 136314cf11afSPaul Mackerras * this here, even if we later allow kernels that will boot on 136414cf11afSPaul Mackerras * both pSeries and iSeries */ 136514cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 136614cf11afSPaul Mackerras . = LPARMAP_PHYS 136714cf11afSPaul Mackerras#include "lparmap.s" 136814cf11afSPaul Mackerras/* 136914cf11afSPaul Mackerras * This ".text" is here for old compilers that generate a trailing 137014cf11afSPaul Mackerras * .note section when compiling .c files to .s 137114cf11afSPaul Mackerras */ 137214cf11afSPaul Mackerras .text 137314cf11afSPaul Mackerras#endif /* CONFIG_PPC_ISERIES */ 137414cf11afSPaul Mackerras 137514cf11afSPaul Mackerras . = 0x8000 137614cf11afSPaul Mackerras 137714cf11afSPaul Mackerras/* 137814cf11afSPaul Mackerras * On pSeries, secondary processors spin in the following code. 137914cf11afSPaul Mackerras * At entry, r3 = this processor's number (physical cpu id) 138014cf11afSPaul Mackerras */ 138114cf11afSPaul Mackerras_GLOBAL(pSeries_secondary_smp_init) 138214cf11afSPaul Mackerras mr r24,r3 138314cf11afSPaul Mackerras 138414cf11afSPaul Mackerras /* turn on 64-bit mode */ 138514cf11afSPaul Mackerras bl .enable_64b_mode 138614cf11afSPaul Mackerras isync 138714cf11afSPaul Mackerras 138814cf11afSPaul Mackerras /* Copy some CPU settings from CPU 0 */ 138914cf11afSPaul Mackerras bl .__restore_cpu_setup 139014cf11afSPaul Mackerras 139114cf11afSPaul Mackerras /* Set up a paca value for this processor. Since we have the 139214cf11afSPaul Mackerras * physical cpu id in r24, we need to search the pacas to find 139314cf11afSPaul Mackerras * which logical id maps to our physical one. 139414cf11afSPaul Mackerras */ 139514cf11afSPaul Mackerras LOADADDR(r13, paca) /* Get base vaddr of paca array */ 139614cf11afSPaul Mackerras li r5,0 /* logical cpu id */ 139714cf11afSPaul Mackerras1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 139814cf11afSPaul Mackerras cmpw r6,r24 /* Compare to our id */ 139914cf11afSPaul Mackerras beq 2f 140014cf11afSPaul Mackerras addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 140114cf11afSPaul Mackerras addi r5,r5,1 140214cf11afSPaul Mackerras cmpwi r5,NR_CPUS 140314cf11afSPaul Mackerras blt 1b 140414cf11afSPaul Mackerras 140514cf11afSPaul Mackerras mr r3,r24 /* not found, copy phys to r3 */ 140614cf11afSPaul Mackerras b .kexec_wait /* next kernel might do better */ 140714cf11afSPaul Mackerras 1408b5bbeb23SPaul Mackerras2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 140914cf11afSPaul Mackerras /* From now on, r24 is expected to be logical cpuid */ 141014cf11afSPaul Mackerras mr r24,r5 141114cf11afSPaul Mackerras3: HMT_LOW 141214cf11afSPaul Mackerras lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 141314cf11afSPaul Mackerras /* start. */ 141414cf11afSPaul Mackerras sync 141514cf11afSPaul Mackerras 141614cf11afSPaul Mackerras /* Create a temp kernel stack for use before relocation is on. */ 141714cf11afSPaul Mackerras ld r1,PACAEMERGSP(r13) 141814cf11afSPaul Mackerras subi r1,r1,STACK_FRAME_OVERHEAD 141914cf11afSPaul Mackerras 142014cf11afSPaul Mackerras cmpwi 0,r23,0 142114cf11afSPaul Mackerras#ifdef CONFIG_SMP 142214cf11afSPaul Mackerras bne .__secondary_start 142314cf11afSPaul Mackerras#endif 142414cf11afSPaul Mackerras b 3b /* Loop until told to go */ 142514cf11afSPaul Mackerras 142614cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 142714cf11afSPaul Mackerras_STATIC(__start_initialization_iSeries) 142814cf11afSPaul Mackerras /* Clear out the BSS */ 142914cf11afSPaul Mackerras LOADADDR(r11,__bss_stop) 143014cf11afSPaul Mackerras LOADADDR(r8,__bss_start) 143114cf11afSPaul Mackerras sub r11,r11,r8 /* bss size */ 143214cf11afSPaul Mackerras addi r11,r11,7 /* round up to an even double word */ 143314cf11afSPaul Mackerras rldicl. r11,r11,61,3 /* shift right by 3 */ 143414cf11afSPaul Mackerras beq 4f 143514cf11afSPaul Mackerras addi r8,r8,-8 143614cf11afSPaul Mackerras li r0,0 143714cf11afSPaul Mackerras mtctr r11 /* zero this many doublewords */ 143814cf11afSPaul Mackerras3: stdu r0,8(r8) 143914cf11afSPaul Mackerras bdnz 3b 144014cf11afSPaul Mackerras4: 144114cf11afSPaul Mackerras LOADADDR(r1,init_thread_union) 144214cf11afSPaul Mackerras addi r1,r1,THREAD_SIZE 144314cf11afSPaul Mackerras li r0,0 144414cf11afSPaul Mackerras stdu r0,-STACK_FRAME_OVERHEAD(r1) 144514cf11afSPaul Mackerras 144614cf11afSPaul Mackerras LOADADDR(r3,cpu_specs) 144714cf11afSPaul Mackerras LOADADDR(r4,cur_cpu_spec) 144814cf11afSPaul Mackerras li r5,0 144914cf11afSPaul Mackerras bl .identify_cpu 145014cf11afSPaul Mackerras 145114cf11afSPaul Mackerras LOADADDR(r2,__toc_start) 145214cf11afSPaul Mackerras addi r2,r2,0x4000 145314cf11afSPaul Mackerras addi r2,r2,0x4000 145414cf11afSPaul Mackerras 145514cf11afSPaul Mackerras bl .iSeries_early_setup 1456ee400b63SStephen Rothwell bl .early_setup 145714cf11afSPaul Mackerras 145814cf11afSPaul Mackerras /* relocation is on at this point */ 145914cf11afSPaul Mackerras 146014cf11afSPaul Mackerras b .start_here_common 146114cf11afSPaul Mackerras#endif /* CONFIG_PPC_ISERIES */ 146214cf11afSPaul Mackerras 146314cf11afSPaul Mackerras#ifdef CONFIG_PPC_MULTIPLATFORM 146414cf11afSPaul Mackerras 146514cf11afSPaul Mackerras_STATIC(__mmu_off) 146614cf11afSPaul Mackerras mfmsr r3 146714cf11afSPaul Mackerras andi. r0,r3,MSR_IR|MSR_DR 146814cf11afSPaul Mackerras beqlr 146914cf11afSPaul Mackerras andc r3,r3,r0 147014cf11afSPaul Mackerras mtspr SPRN_SRR0,r4 147114cf11afSPaul Mackerras mtspr SPRN_SRR1,r3 147214cf11afSPaul Mackerras sync 147314cf11afSPaul Mackerras rfid 147414cf11afSPaul Mackerras b . /* prevent speculative execution */ 147514cf11afSPaul Mackerras 147614cf11afSPaul Mackerras 147714cf11afSPaul Mackerras/* 147814cf11afSPaul Mackerras * Here is our main kernel entry point. We support currently 2 kind of entries 147914cf11afSPaul Mackerras * depending on the value of r5. 148014cf11afSPaul Mackerras * 148114cf11afSPaul Mackerras * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 148214cf11afSPaul Mackerras * in r3...r7 148314cf11afSPaul Mackerras * 148414cf11afSPaul Mackerras * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 148514cf11afSPaul Mackerras * DT block, r4 is a physical pointer to the kernel itself 148614cf11afSPaul Mackerras * 148714cf11afSPaul Mackerras */ 148814cf11afSPaul Mackerras_GLOBAL(__start_initialization_multiplatform) 148914cf11afSPaul Mackerras /* 149014cf11afSPaul Mackerras * Are we booted from a PROM Of-type client-interface ? 149114cf11afSPaul Mackerras */ 149214cf11afSPaul Mackerras cmpldi cr0,r5,0 149314cf11afSPaul Mackerras bne .__boot_from_prom /* yes -> prom */ 149414cf11afSPaul Mackerras 149514cf11afSPaul Mackerras /* Save parameters */ 149614cf11afSPaul Mackerras mr r31,r3 149714cf11afSPaul Mackerras mr r30,r4 149814cf11afSPaul Mackerras 149914cf11afSPaul Mackerras /* Make sure we are running in 64 bits mode */ 150014cf11afSPaul Mackerras bl .enable_64b_mode 150114cf11afSPaul Mackerras 150214cf11afSPaul Mackerras /* Setup some critical 970 SPRs before switching MMU off */ 150314cf11afSPaul Mackerras bl .__970_cpu_preinit 150414cf11afSPaul Mackerras 150514cf11afSPaul Mackerras /* cpu # */ 150614cf11afSPaul Mackerras li r24,0 150714cf11afSPaul Mackerras 150814cf11afSPaul Mackerras /* Switch off MMU if not already */ 150914cf11afSPaul Mackerras LOADADDR(r4, .__after_prom_start - KERNELBASE) 151014cf11afSPaul Mackerras add r4,r4,r30 151114cf11afSPaul Mackerras bl .__mmu_off 151214cf11afSPaul Mackerras b .__after_prom_start 151314cf11afSPaul Mackerras 151414cf11afSPaul Mackerras_STATIC(__boot_from_prom) 151514cf11afSPaul Mackerras /* Save parameters */ 151614cf11afSPaul Mackerras mr r31,r3 151714cf11afSPaul Mackerras mr r30,r4 151814cf11afSPaul Mackerras mr r29,r5 151914cf11afSPaul Mackerras mr r28,r6 152014cf11afSPaul Mackerras mr r27,r7 152114cf11afSPaul Mackerras 152214cf11afSPaul Mackerras /* Make sure we are running in 64 bits mode */ 152314cf11afSPaul Mackerras bl .enable_64b_mode 152414cf11afSPaul Mackerras 152514cf11afSPaul Mackerras /* put a relocation offset into r3 */ 152614cf11afSPaul Mackerras bl .reloc_offset 152714cf11afSPaul Mackerras 152814cf11afSPaul Mackerras LOADADDR(r2,__toc_start) 152914cf11afSPaul Mackerras addi r2,r2,0x4000 153014cf11afSPaul Mackerras addi r2,r2,0x4000 153114cf11afSPaul Mackerras 153214cf11afSPaul Mackerras /* Relocate the TOC from a virt addr to a real addr */ 15335a408329SPaul Mackerras add r2,r2,r3 153414cf11afSPaul Mackerras 153514cf11afSPaul Mackerras /* Restore parameters */ 153614cf11afSPaul Mackerras mr r3,r31 153714cf11afSPaul Mackerras mr r4,r30 153814cf11afSPaul Mackerras mr r5,r29 153914cf11afSPaul Mackerras mr r6,r28 154014cf11afSPaul Mackerras mr r7,r27 154114cf11afSPaul Mackerras 154214cf11afSPaul Mackerras /* Do all of the interaction with OF client interface */ 154314cf11afSPaul Mackerras bl .prom_init 154414cf11afSPaul Mackerras /* We never return */ 154514cf11afSPaul Mackerras trap 154614cf11afSPaul Mackerras 154714cf11afSPaul Mackerras/* 154814cf11afSPaul Mackerras * At this point, r3 contains the physical address we are running at, 154914cf11afSPaul Mackerras * returned by prom_init() 155014cf11afSPaul Mackerras */ 155114cf11afSPaul Mackerras_STATIC(__after_prom_start) 155214cf11afSPaul Mackerras 155314cf11afSPaul Mackerras/* 155414cf11afSPaul Mackerras * We need to run with __start at physical address 0. 155514cf11afSPaul Mackerras * This will leave some code in the first 256B of 155614cf11afSPaul Mackerras * real memory, which are reserved for software use. 155714cf11afSPaul Mackerras * The remainder of the first page is loaded with the fixed 155814cf11afSPaul Mackerras * interrupt vectors. The next two pages are filled with 155914cf11afSPaul Mackerras * unknown exception placeholders. 156014cf11afSPaul Mackerras * 156114cf11afSPaul Mackerras * Note: This process overwrites the OF exception vectors. 156214cf11afSPaul Mackerras * r26 == relocation offset 156314cf11afSPaul Mackerras * r27 == KERNELBASE 156414cf11afSPaul Mackerras */ 156514cf11afSPaul Mackerras bl .reloc_offset 156614cf11afSPaul Mackerras mr r26,r3 156714cf11afSPaul Mackerras SET_REG_TO_CONST(r27,KERNELBASE) 156814cf11afSPaul Mackerras 156914cf11afSPaul Mackerras li r3,0 /* target addr */ 157014cf11afSPaul Mackerras 157114cf11afSPaul Mackerras // XXX FIXME: Use phys returned by OF (r30) 15725a408329SPaul Mackerras add r4,r27,r26 /* source addr */ 157314cf11afSPaul Mackerras /* current address of _start */ 157414cf11afSPaul Mackerras /* i.e. where we are running */ 157514cf11afSPaul Mackerras /* the source addr */ 157614cf11afSPaul Mackerras 157714cf11afSPaul Mackerras LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */ 157814cf11afSPaul Mackerras sub r5,r5,r27 157914cf11afSPaul Mackerras 158014cf11afSPaul Mackerras li r6,0x100 /* Start offset, the first 0x100 */ 158114cf11afSPaul Mackerras /* bytes were copied earlier. */ 158214cf11afSPaul Mackerras 158314cf11afSPaul Mackerras bl .copy_and_flush /* copy the first n bytes */ 158414cf11afSPaul Mackerras /* this includes the code being */ 158514cf11afSPaul Mackerras /* executed here. */ 158614cf11afSPaul Mackerras 158714cf11afSPaul Mackerras LOADADDR(r0, 4f) /* Jump to the copy of this code */ 158814cf11afSPaul Mackerras mtctr r0 /* that we just made/relocated */ 158914cf11afSPaul Mackerras bctr 159014cf11afSPaul Mackerras 159114cf11afSPaul Mackerras4: LOADADDR(r5,klimit) 15925a408329SPaul Mackerras add r5,r5,r26 159314cf11afSPaul Mackerras ld r5,0(r5) /* get the value of klimit */ 159414cf11afSPaul Mackerras sub r5,r5,r27 159514cf11afSPaul Mackerras bl .copy_and_flush /* copy the rest */ 159614cf11afSPaul Mackerras b .start_here_multiplatform 159714cf11afSPaul Mackerras 159814cf11afSPaul Mackerras#endif /* CONFIG_PPC_MULTIPLATFORM */ 159914cf11afSPaul Mackerras 160014cf11afSPaul Mackerras/* 160114cf11afSPaul Mackerras * Copy routine used to copy the kernel to start at physical address 0 160214cf11afSPaul Mackerras * and flush and invalidate the caches as needed. 160314cf11afSPaul Mackerras * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 160414cf11afSPaul Mackerras * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 160514cf11afSPaul Mackerras * 160614cf11afSPaul Mackerras * Note: this routine *only* clobbers r0, r6 and lr 160714cf11afSPaul Mackerras */ 160814cf11afSPaul Mackerras_GLOBAL(copy_and_flush) 160914cf11afSPaul Mackerras addi r5,r5,-8 161014cf11afSPaul Mackerras addi r6,r6,-8 161114cf11afSPaul Mackerras4: li r0,16 /* Use the least common */ 161214cf11afSPaul Mackerras /* denominator cache line */ 161314cf11afSPaul Mackerras /* size. This results in */ 161414cf11afSPaul Mackerras /* extra cache line flushes */ 161514cf11afSPaul Mackerras /* but operation is correct. */ 161614cf11afSPaul Mackerras /* Can't get cache line size */ 161714cf11afSPaul Mackerras /* from NACA as it is being */ 161814cf11afSPaul Mackerras /* moved too. */ 161914cf11afSPaul Mackerras 162014cf11afSPaul Mackerras mtctr r0 /* put # words/line in ctr */ 162114cf11afSPaul Mackerras3: addi r6,r6,8 /* copy a cache line */ 162214cf11afSPaul Mackerras ldx r0,r6,r4 162314cf11afSPaul Mackerras stdx r0,r6,r3 162414cf11afSPaul Mackerras bdnz 3b 162514cf11afSPaul Mackerras dcbst r6,r3 /* write it to memory */ 162614cf11afSPaul Mackerras sync 162714cf11afSPaul Mackerras icbi r6,r3 /* flush the icache line */ 162814cf11afSPaul Mackerras cmpld 0,r6,r5 162914cf11afSPaul Mackerras blt 4b 163014cf11afSPaul Mackerras sync 163114cf11afSPaul Mackerras addi r5,r5,8 163214cf11afSPaul Mackerras addi r6,r6,8 163314cf11afSPaul Mackerras blr 163414cf11afSPaul Mackerras 163514cf11afSPaul Mackerras.align 8 163614cf11afSPaul Mackerrascopy_to_here: 163714cf11afSPaul Mackerras 163814cf11afSPaul Mackerras#ifdef CONFIG_SMP 163914cf11afSPaul Mackerras#ifdef CONFIG_PPC_PMAC 164014cf11afSPaul Mackerras/* 164114cf11afSPaul Mackerras * On PowerMac, secondary processors starts from the reset vector, which 164214cf11afSPaul Mackerras * is temporarily turned into a call to one of the functions below. 164314cf11afSPaul Mackerras */ 164414cf11afSPaul Mackerras .section ".text"; 164514cf11afSPaul Mackerras .align 2 ; 164614cf11afSPaul Mackerras 164735499c01SPaul Mackerras .globl __secondary_start_pmac_0 164835499c01SPaul Mackerras__secondary_start_pmac_0: 164935499c01SPaul Mackerras /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 165035499c01SPaul Mackerras li r24,0 165135499c01SPaul Mackerras b 1f 165214cf11afSPaul Mackerras li r24,1 165335499c01SPaul Mackerras b 1f 165414cf11afSPaul Mackerras li r24,2 165535499c01SPaul Mackerras b 1f 165614cf11afSPaul Mackerras li r24,3 165735499c01SPaul Mackerras1: 165814cf11afSPaul Mackerras 165914cf11afSPaul Mackerras_GLOBAL(pmac_secondary_start) 166014cf11afSPaul Mackerras /* turn on 64-bit mode */ 166114cf11afSPaul Mackerras bl .enable_64b_mode 166214cf11afSPaul Mackerras isync 166314cf11afSPaul Mackerras 166414cf11afSPaul Mackerras /* Copy some CPU settings from CPU 0 */ 166514cf11afSPaul Mackerras bl .__restore_cpu_setup 166614cf11afSPaul Mackerras 166714cf11afSPaul Mackerras /* pSeries do that early though I don't think we really need it */ 166814cf11afSPaul Mackerras mfmsr r3 166914cf11afSPaul Mackerras ori r3,r3,MSR_RI 167014cf11afSPaul Mackerras mtmsrd r3 /* RI on */ 167114cf11afSPaul Mackerras 167214cf11afSPaul Mackerras /* Set up a paca value for this processor. */ 167314cf11afSPaul Mackerras LOADADDR(r4, paca) /* Get base vaddr of paca array */ 167414cf11afSPaul Mackerras mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 167514cf11afSPaul Mackerras add r13,r13,r4 /* for this processor. */ 1676b5bbeb23SPaul Mackerras mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 167714cf11afSPaul Mackerras 167814cf11afSPaul Mackerras /* Create a temp kernel stack for use before relocation is on. */ 167914cf11afSPaul Mackerras ld r1,PACAEMERGSP(r13) 168014cf11afSPaul Mackerras subi r1,r1,STACK_FRAME_OVERHEAD 168114cf11afSPaul Mackerras 168214cf11afSPaul Mackerras b .__secondary_start 168314cf11afSPaul Mackerras 168414cf11afSPaul Mackerras#endif /* CONFIG_PPC_PMAC */ 168514cf11afSPaul Mackerras 168614cf11afSPaul Mackerras/* 168714cf11afSPaul Mackerras * This function is called after the master CPU has released the 168814cf11afSPaul Mackerras * secondary processors. The execution environment is relocation off. 168914cf11afSPaul Mackerras * The paca for this processor has the following fields initialized at 169014cf11afSPaul Mackerras * this point: 169114cf11afSPaul Mackerras * 1. Processor number 169214cf11afSPaul Mackerras * 2. Segment table pointer (virtual address) 169314cf11afSPaul Mackerras * On entry the following are set: 169414cf11afSPaul Mackerras * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 169514cf11afSPaul Mackerras * r24 = cpu# (in Linux terms) 169614cf11afSPaul Mackerras * r13 = paca virtual address 169714cf11afSPaul Mackerras * SPRG3 = paca virtual address 169814cf11afSPaul Mackerras */ 169914cf11afSPaul Mackerras_GLOBAL(__secondary_start) 170014cf11afSPaul Mackerras 170114cf11afSPaul Mackerras HMT_MEDIUM /* Set thread priority to MEDIUM */ 170214cf11afSPaul Mackerras 170314cf11afSPaul Mackerras ld r2,PACATOC(r13) 170414cf11afSPaul Mackerras li r6,0 170514cf11afSPaul Mackerras stb r6,PACAPROCENABLED(r13) 170614cf11afSPaul Mackerras 170714cf11afSPaul Mackerras#ifndef CONFIG_PPC_ISERIES 170814cf11afSPaul Mackerras /* Initialize the page table pointer register. */ 170914cf11afSPaul Mackerras LOADADDR(r6,_SDR1) 171014cf11afSPaul Mackerras ld r6,0(r6) /* get the value of _SDR1 */ 1711b5bbeb23SPaul Mackerras mtspr SPRN_SDR1,r6 /* set the htab location */ 171214cf11afSPaul Mackerras#endif 171314cf11afSPaul Mackerras /* Initialize the first segment table (or SLB) entry */ 171414cf11afSPaul Mackerras ld r3,PACASTABVIRT(r13) /* get addr of segment table */ 17153c726f8dSBenjamin HerrenschmidtBEGIN_FTR_SECTION 171614cf11afSPaul Mackerras bl .stab_initialize 17173c726f8dSBenjamin HerrenschmidtEND_FTR_SECTION_IFCLR(CPU_FTR_SLB) 17183c726f8dSBenjamin Herrenschmidt bl .slb_initialize 171914cf11afSPaul Mackerras 172014cf11afSPaul Mackerras /* Initialize the kernel stack. Just a repeat for iSeries. */ 172114cf11afSPaul Mackerras LOADADDR(r3,current_set) 172214cf11afSPaul Mackerras sldi r28,r24,3 /* get current_set[cpu#] */ 172314cf11afSPaul Mackerras ldx r1,r3,r28 172414cf11afSPaul Mackerras addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 172514cf11afSPaul Mackerras std r1,PACAKSAVE(r13) 172614cf11afSPaul Mackerras 172714cf11afSPaul Mackerras ld r3,PACASTABREAL(r13) /* get raddr of segment table */ 172814cf11afSPaul Mackerras ori r4,r3,1 /* turn on valid bit */ 172914cf11afSPaul Mackerras 173014cf11afSPaul Mackerras#ifdef CONFIG_PPC_ISERIES 173114cf11afSPaul Mackerras li r0,-1 /* hypervisor call */ 173214cf11afSPaul Mackerras li r3,1 173314cf11afSPaul Mackerras sldi r3,r3,63 /* 0x8000000000000000 */ 173414cf11afSPaul Mackerras ori r3,r3,4 /* 0x8000000000000004 */ 173514cf11afSPaul Mackerras sc /* HvCall_setASR */ 173614cf11afSPaul Mackerras#else 173714cf11afSPaul Mackerras /* set the ASR */ 173814cf11afSPaul Mackerras ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */ 173914cf11afSPaul Mackerras ld r3,0(r3) 174014cf11afSPaul Mackerras lwz r3,PLATFORM(r3) /* r3 = platform flags */ 174114cf11afSPaul Mackerras andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */ 174214cf11afSPaul Mackerras beq 98f /* branch if result is 0 */ 1743b5bbeb23SPaul Mackerras mfspr r3,SPRN_PVR 174414cf11afSPaul Mackerras srwi r3,r3,16 174514cf11afSPaul Mackerras cmpwi r3,0x37 /* SStar */ 174614cf11afSPaul Mackerras beq 97f 174714cf11afSPaul Mackerras cmpwi r3,0x36 /* IStar */ 174814cf11afSPaul Mackerras beq 97f 174914cf11afSPaul Mackerras cmpwi r3,0x34 /* Pulsar */ 175014cf11afSPaul Mackerras bne 98f 175114cf11afSPaul Mackerras97: li r3,H_SET_ASR /* hcall = H_SET_ASR */ 175214cf11afSPaul Mackerras HVSC /* Invoking hcall */ 175314cf11afSPaul Mackerras b 99f 175414cf11afSPaul Mackerras98: /* !(rpa hypervisor) || !(star) */ 175514cf11afSPaul Mackerras mtasr r4 /* set the stab location */ 175614cf11afSPaul Mackerras99: 175714cf11afSPaul Mackerras#endif 175814cf11afSPaul Mackerras li r7,0 175914cf11afSPaul Mackerras mtlr r7 176014cf11afSPaul Mackerras 176114cf11afSPaul Mackerras /* enable MMU and jump to start_secondary */ 176214cf11afSPaul Mackerras LOADADDR(r3,.start_secondary_prolog) 176314cf11afSPaul Mackerras SET_REG_TO_CONST(r4, MSR_KERNEL) 176414cf11afSPaul Mackerras#ifdef DO_SOFT_DISABLE 176514cf11afSPaul Mackerras ori r4,r4,MSR_EE 176614cf11afSPaul Mackerras#endif 1767b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r3 1768b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r4 176914cf11afSPaul Mackerras rfid 177014cf11afSPaul Mackerras b . /* prevent speculative execution */ 177114cf11afSPaul Mackerras 177214cf11afSPaul Mackerras/* 177314cf11afSPaul Mackerras * Running with relocation on at this point. All we want to do is 177414cf11afSPaul Mackerras * zero the stack back-chain pointer before going into C code. 177514cf11afSPaul Mackerras */ 177614cf11afSPaul Mackerras_GLOBAL(start_secondary_prolog) 177714cf11afSPaul Mackerras li r3,0 177814cf11afSPaul Mackerras std r3,0(r1) /* Zero the stack frame pointer */ 177914cf11afSPaul Mackerras bl .start_secondary 178014cf11afSPaul Mackerras#endif 178114cf11afSPaul Mackerras 178214cf11afSPaul Mackerras/* 178314cf11afSPaul Mackerras * This subroutine clobbers r11 and r12 178414cf11afSPaul Mackerras */ 178514cf11afSPaul Mackerras_GLOBAL(enable_64b_mode) 178614cf11afSPaul Mackerras mfmsr r11 /* grab the current MSR */ 178714cf11afSPaul Mackerras li r12,1 178814cf11afSPaul Mackerras rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) 178914cf11afSPaul Mackerras or r11,r11,r12 179014cf11afSPaul Mackerras li r12,1 179114cf11afSPaul Mackerras rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) 179214cf11afSPaul Mackerras or r11,r11,r12 179314cf11afSPaul Mackerras mtmsrd r11 179414cf11afSPaul Mackerras isync 179514cf11afSPaul Mackerras blr 179614cf11afSPaul Mackerras 179714cf11afSPaul Mackerras#ifdef CONFIG_PPC_MULTIPLATFORM 179814cf11afSPaul Mackerras/* 179914cf11afSPaul Mackerras * This is where the main kernel code starts. 180014cf11afSPaul Mackerras */ 180114cf11afSPaul Mackerras_STATIC(start_here_multiplatform) 180214cf11afSPaul Mackerras /* get a new offset, now that the kernel has moved. */ 180314cf11afSPaul Mackerras bl .reloc_offset 180414cf11afSPaul Mackerras mr r26,r3 180514cf11afSPaul Mackerras 180614cf11afSPaul Mackerras /* Clear out the BSS. It may have been done in prom_init, 180714cf11afSPaul Mackerras * already but that's irrelevant since prom_init will soon 180814cf11afSPaul Mackerras * be detached from the kernel completely. Besides, we need 180914cf11afSPaul Mackerras * to clear it now for kexec-style entry. 181014cf11afSPaul Mackerras */ 181114cf11afSPaul Mackerras LOADADDR(r11,__bss_stop) 181214cf11afSPaul Mackerras LOADADDR(r8,__bss_start) 181314cf11afSPaul Mackerras sub r11,r11,r8 /* bss size */ 181414cf11afSPaul Mackerras addi r11,r11,7 /* round up to an even double word */ 181514cf11afSPaul Mackerras rldicl. r11,r11,61,3 /* shift right by 3 */ 181614cf11afSPaul Mackerras beq 4f 181714cf11afSPaul Mackerras addi r8,r8,-8 181814cf11afSPaul Mackerras li r0,0 181914cf11afSPaul Mackerras mtctr r11 /* zero this many doublewords */ 182014cf11afSPaul Mackerras3: stdu r0,8(r8) 182114cf11afSPaul Mackerras bdnz 3b 182214cf11afSPaul Mackerras4: 182314cf11afSPaul Mackerras 182414cf11afSPaul Mackerras mfmsr r6 182514cf11afSPaul Mackerras ori r6,r6,MSR_RI 182614cf11afSPaul Mackerras mtmsrd r6 /* RI on */ 182714cf11afSPaul Mackerras 182814cf11afSPaul Mackerras#ifdef CONFIG_HMT 182914cf11afSPaul Mackerras /* Start up the second thread on cpu 0 */ 1830b5bbeb23SPaul Mackerras mfspr r3,SPRN_PVR 183114cf11afSPaul Mackerras srwi r3,r3,16 183214cf11afSPaul Mackerras cmpwi r3,0x34 /* Pulsar */ 183314cf11afSPaul Mackerras beq 90f 183414cf11afSPaul Mackerras cmpwi r3,0x36 /* Icestar */ 183514cf11afSPaul Mackerras beq 90f 183614cf11afSPaul Mackerras cmpwi r3,0x37 /* SStar */ 183714cf11afSPaul Mackerras beq 90f 183814cf11afSPaul Mackerras b 91f /* HMT not supported */ 183914cf11afSPaul Mackerras90: li r3,0 184014cf11afSPaul Mackerras bl .hmt_start_secondary 184114cf11afSPaul Mackerras91: 184214cf11afSPaul Mackerras#endif 184314cf11afSPaul Mackerras 184414cf11afSPaul Mackerras /* The following gets the stack and TOC set up with the regs */ 184514cf11afSPaul Mackerras /* pointing to the real addr of the kernel stack. This is */ 184614cf11afSPaul Mackerras /* all done to support the C function call below which sets */ 184714cf11afSPaul Mackerras /* up the htab. This is done because we have relocated the */ 184814cf11afSPaul Mackerras /* kernel but are still running in real mode. */ 184914cf11afSPaul Mackerras 185014cf11afSPaul Mackerras LOADADDR(r3,init_thread_union) 18515a408329SPaul Mackerras add r3,r3,r26 185214cf11afSPaul Mackerras 185314cf11afSPaul Mackerras /* set up a stack pointer (physical address) */ 185414cf11afSPaul Mackerras addi r1,r3,THREAD_SIZE 185514cf11afSPaul Mackerras li r0,0 185614cf11afSPaul Mackerras stdu r0,-STACK_FRAME_OVERHEAD(r1) 185714cf11afSPaul Mackerras 185814cf11afSPaul Mackerras /* set up the TOC (physical address) */ 185914cf11afSPaul Mackerras LOADADDR(r2,__toc_start) 186014cf11afSPaul Mackerras addi r2,r2,0x4000 186114cf11afSPaul Mackerras addi r2,r2,0x4000 18625a408329SPaul Mackerras add r2,r2,r26 186314cf11afSPaul Mackerras 186414cf11afSPaul Mackerras LOADADDR(r3,cpu_specs) 18655a408329SPaul Mackerras add r3,r3,r26 186614cf11afSPaul Mackerras LOADADDR(r4,cur_cpu_spec) 18675a408329SPaul Mackerras add r4,r4,r26 186814cf11afSPaul Mackerras mr r5,r26 186914cf11afSPaul Mackerras bl .identify_cpu 187014cf11afSPaul Mackerras 187114cf11afSPaul Mackerras /* Save some low level config HIDs of CPU0 to be copied to 187214cf11afSPaul Mackerras * other CPUs later on, or used for suspend/resume 187314cf11afSPaul Mackerras */ 187414cf11afSPaul Mackerras bl .__save_cpu_setup 187514cf11afSPaul Mackerras sync 187614cf11afSPaul Mackerras 187714cf11afSPaul Mackerras /* Setup a valid physical PACA pointer in SPRG3 for early_setup 187814cf11afSPaul Mackerras * note that boot_cpuid can always be 0 nowadays since there is 187914cf11afSPaul Mackerras * nowhere it can be initialized differently before we reach this 188014cf11afSPaul Mackerras * code 188114cf11afSPaul Mackerras */ 188214cf11afSPaul Mackerras LOADADDR(r27, boot_cpuid) 18835a408329SPaul Mackerras add r27,r27,r26 188414cf11afSPaul Mackerras lwz r27,0(r27) 188514cf11afSPaul Mackerras 188614cf11afSPaul Mackerras LOADADDR(r24, paca) /* Get base vaddr of paca array */ 188714cf11afSPaul Mackerras mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ 188814cf11afSPaul Mackerras add r13,r13,r24 /* for this processor. */ 18895a408329SPaul Mackerras add r13,r13,r26 /* convert to physical addr */ 1890b5bbeb23SPaul Mackerras mtspr SPRN_SPRG3,r13 /* PPPBBB: Temp... -Peter */ 189114cf11afSPaul Mackerras 189214cf11afSPaul Mackerras /* Do very early kernel initializations, including initial hash table, 189314cf11afSPaul Mackerras * stab and slb setup before we turn on relocation. */ 189414cf11afSPaul Mackerras 189514cf11afSPaul Mackerras /* Restore parameters passed from prom_init/kexec */ 189614cf11afSPaul Mackerras mr r3,r31 189714cf11afSPaul Mackerras bl .early_setup 189814cf11afSPaul Mackerras 189914cf11afSPaul Mackerras /* set the ASR */ 190014cf11afSPaul Mackerras ld r3,PACASTABREAL(r13) 190114cf11afSPaul Mackerras ori r4,r3,1 /* turn on valid bit */ 190214cf11afSPaul Mackerras ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */ 190314cf11afSPaul Mackerras ld r3,0(r3) 190414cf11afSPaul Mackerras lwz r3,PLATFORM(r3) /* r3 = platform flags */ 190514cf11afSPaul Mackerras andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */ 190614cf11afSPaul Mackerras beq 98f /* branch if result is 0 */ 1907b5bbeb23SPaul Mackerras mfspr r3,SPRN_PVR 190814cf11afSPaul Mackerras srwi r3,r3,16 190914cf11afSPaul Mackerras cmpwi r3,0x37 /* SStar */ 191014cf11afSPaul Mackerras beq 97f 191114cf11afSPaul Mackerras cmpwi r3,0x36 /* IStar */ 191214cf11afSPaul Mackerras beq 97f 191314cf11afSPaul Mackerras cmpwi r3,0x34 /* Pulsar */ 191414cf11afSPaul Mackerras bne 98f 191514cf11afSPaul Mackerras97: li r3,H_SET_ASR /* hcall = H_SET_ASR */ 191614cf11afSPaul Mackerras HVSC /* Invoking hcall */ 191714cf11afSPaul Mackerras b 99f 191814cf11afSPaul Mackerras98: /* !(rpa hypervisor) || !(star) */ 191914cf11afSPaul Mackerras mtasr r4 /* set the stab location */ 192014cf11afSPaul Mackerras99: 192114cf11afSPaul Mackerras /* Set SDR1 (hash table pointer) */ 192214cf11afSPaul Mackerras ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */ 192314cf11afSPaul Mackerras ld r3,0(r3) 192414cf11afSPaul Mackerras lwz r3,PLATFORM(r3) /* r3 = platform flags */ 192514cf11afSPaul Mackerras /* Test if bit 0 is set (LPAR bit) */ 192614cf11afSPaul Mackerras andi. r3,r3,PLATFORM_LPAR 192714cf11afSPaul Mackerras bne 98f /* branch if result is !0 */ 192814cf11afSPaul Mackerras LOADADDR(r6,_SDR1) /* Only if NOT LPAR */ 19295a408329SPaul Mackerras add r6,r6,r26 193014cf11afSPaul Mackerras ld r6,0(r6) /* get the value of _SDR1 */ 1931b5bbeb23SPaul Mackerras mtspr SPRN_SDR1,r6 /* set the htab location */ 193214cf11afSPaul Mackerras98: 193314cf11afSPaul Mackerras LOADADDR(r3,.start_here_common) 193414cf11afSPaul Mackerras SET_REG_TO_CONST(r4, MSR_KERNEL) 1935b5bbeb23SPaul Mackerras mtspr SPRN_SRR0,r3 1936b5bbeb23SPaul Mackerras mtspr SPRN_SRR1,r4 193714cf11afSPaul Mackerras rfid 193814cf11afSPaul Mackerras b . /* prevent speculative execution */ 193914cf11afSPaul Mackerras#endif /* CONFIG_PPC_MULTIPLATFORM */ 194014cf11afSPaul Mackerras 194114cf11afSPaul Mackerras /* This is where all platforms converge execution */ 194214cf11afSPaul Mackerras_STATIC(start_here_common) 194314cf11afSPaul Mackerras /* relocation is on at this point */ 194414cf11afSPaul Mackerras 194514cf11afSPaul Mackerras /* The following code sets up the SP and TOC now that we are */ 194614cf11afSPaul Mackerras /* running with translation enabled. */ 194714cf11afSPaul Mackerras 194814cf11afSPaul Mackerras LOADADDR(r3,init_thread_union) 194914cf11afSPaul Mackerras 195014cf11afSPaul Mackerras /* set up the stack */ 195114cf11afSPaul Mackerras addi r1,r3,THREAD_SIZE 195214cf11afSPaul Mackerras li r0,0 195314cf11afSPaul Mackerras stdu r0,-STACK_FRAME_OVERHEAD(r1) 195414cf11afSPaul Mackerras 195514cf11afSPaul Mackerras /* Apply the CPUs-specific fixups (nop out sections not relevant 195614cf11afSPaul Mackerras * to this CPU 195714cf11afSPaul Mackerras */ 195814cf11afSPaul Mackerras li r3,0 195914cf11afSPaul Mackerras bl .do_cpu_ftr_fixups 196014cf11afSPaul Mackerras 196114cf11afSPaul Mackerras LOADADDR(r26, boot_cpuid) 196214cf11afSPaul Mackerras lwz r26,0(r26) 196314cf11afSPaul Mackerras 196414cf11afSPaul Mackerras LOADADDR(r24, paca) /* Get base vaddr of paca array */ 196514cf11afSPaul Mackerras mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ 196614cf11afSPaul Mackerras add r13,r13,r24 /* for this processor. */ 1967b5bbeb23SPaul Mackerras mtspr SPRN_SPRG3,r13 196814cf11afSPaul Mackerras 196914cf11afSPaul Mackerras /* ptr to current */ 197014cf11afSPaul Mackerras LOADADDR(r4,init_task) 197114cf11afSPaul Mackerras std r4,PACACURRENT(r13) 197214cf11afSPaul Mackerras 197314cf11afSPaul Mackerras /* Load the TOC */ 197414cf11afSPaul Mackerras ld r2,PACATOC(r13) 197514cf11afSPaul Mackerras std r1,PACAKSAVE(r13) 197614cf11afSPaul Mackerras 197714cf11afSPaul Mackerras bl .setup_system 197814cf11afSPaul Mackerras 197914cf11afSPaul Mackerras /* Load up the kernel context */ 198014cf11afSPaul Mackerras5: 198114cf11afSPaul Mackerras#ifdef DO_SOFT_DISABLE 198214cf11afSPaul Mackerras li r5,0 198314cf11afSPaul Mackerras stb r5,PACAPROCENABLED(r13) /* Soft Disabled */ 198414cf11afSPaul Mackerras mfmsr r5 198514cf11afSPaul Mackerras ori r5,r5,MSR_EE /* Hard Enabled */ 198614cf11afSPaul Mackerras mtmsrd r5 198714cf11afSPaul Mackerras#endif 198814cf11afSPaul Mackerras 198914cf11afSPaul Mackerras bl .start_kernel 199014cf11afSPaul Mackerras 199114cf11afSPaul Mackerras_GLOBAL(hmt_init) 199214cf11afSPaul Mackerras#ifdef CONFIG_HMT 199314cf11afSPaul Mackerras LOADADDR(r5, hmt_thread_data) 1994b5bbeb23SPaul Mackerras mfspr r7,SPRN_PVR 199514cf11afSPaul Mackerras srwi r7,r7,16 199614cf11afSPaul Mackerras cmpwi r7,0x34 /* Pulsar */ 199714cf11afSPaul Mackerras beq 90f 199814cf11afSPaul Mackerras cmpwi r7,0x36 /* Icestar */ 199914cf11afSPaul Mackerras beq 91f 200014cf11afSPaul Mackerras cmpwi r7,0x37 /* SStar */ 200114cf11afSPaul Mackerras beq 91f 200214cf11afSPaul Mackerras b 101f 2003b5bbeb23SPaul Mackerras90: mfspr r6,SPRN_PIR 200414cf11afSPaul Mackerras andi. r6,r6,0x1f 200514cf11afSPaul Mackerras b 92f 2006b5bbeb23SPaul Mackerras91: mfspr r6,SPRN_PIR 200714cf11afSPaul Mackerras andi. r6,r6,0x3ff 200814cf11afSPaul Mackerras92: sldi r4,r24,3 200914cf11afSPaul Mackerras stwx r6,r5,r4 201014cf11afSPaul Mackerras bl .hmt_start_secondary 201114cf11afSPaul Mackerras b 101f 201214cf11afSPaul Mackerras 201314cf11afSPaul Mackerras__hmt_secondary_hold: 201414cf11afSPaul Mackerras LOADADDR(r5, hmt_thread_data) 201514cf11afSPaul Mackerras clrldi r5,r5,4 201614cf11afSPaul Mackerras li r7,0 2017b5bbeb23SPaul Mackerras mfspr r6,SPRN_PIR 2018b5bbeb23SPaul Mackerras mfspr r8,SPRN_PVR 201914cf11afSPaul Mackerras srwi r8,r8,16 202014cf11afSPaul Mackerras cmpwi r8,0x34 202114cf11afSPaul Mackerras bne 93f 202214cf11afSPaul Mackerras andi. r6,r6,0x1f 202314cf11afSPaul Mackerras b 103f 202414cf11afSPaul Mackerras93: andi. r6,r6,0x3f 202514cf11afSPaul Mackerras 202614cf11afSPaul Mackerras103: lwzx r8,r5,r7 202714cf11afSPaul Mackerras cmpw r8,r6 202814cf11afSPaul Mackerras beq 104f 202914cf11afSPaul Mackerras addi r7,r7,8 203014cf11afSPaul Mackerras b 103b 203114cf11afSPaul Mackerras 203214cf11afSPaul Mackerras104: addi r7,r7,4 203314cf11afSPaul Mackerras lwzx r9,r5,r7 203414cf11afSPaul Mackerras mr r24,r9 203514cf11afSPaul Mackerras101: 203614cf11afSPaul Mackerras#endif 203714cf11afSPaul Mackerras mr r3,r24 203814cf11afSPaul Mackerras b .pSeries_secondary_smp_init 203914cf11afSPaul Mackerras 204014cf11afSPaul Mackerras#ifdef CONFIG_HMT 204114cf11afSPaul Mackerras_GLOBAL(hmt_start_secondary) 204214cf11afSPaul Mackerras LOADADDR(r4,__hmt_secondary_hold) 204314cf11afSPaul Mackerras clrldi r4,r4,4 2044b5bbeb23SPaul Mackerras mtspr SPRN_NIADORM, r4 2045b5bbeb23SPaul Mackerras mfspr r4, SPRN_MSRDORM 204614cf11afSPaul Mackerras li r5, -65 204714cf11afSPaul Mackerras and r4, r4, r5 2048b5bbeb23SPaul Mackerras mtspr SPRN_MSRDORM, r4 204914cf11afSPaul Mackerras lis r4,0xffef 205014cf11afSPaul Mackerras ori r4,r4,0x7403 2051b5bbeb23SPaul Mackerras mtspr SPRN_TSC, r4 205214cf11afSPaul Mackerras li r4,0x1f4 2053b5bbeb23SPaul Mackerras mtspr SPRN_TST, r4 2054b5bbeb23SPaul Mackerras mfspr r4, SPRN_HID0 205514cf11afSPaul Mackerras ori r4, r4, 0x1 2056b5bbeb23SPaul Mackerras mtspr SPRN_HID0, r4 205714cf11afSPaul Mackerras mfspr r4, SPRN_CTRLF 205814cf11afSPaul Mackerras oris r4, r4, 0x40 205914cf11afSPaul Mackerras mtspr SPRN_CTRLT, r4 206014cf11afSPaul Mackerras blr 206114cf11afSPaul Mackerras#endif 206214cf11afSPaul Mackerras 206314cf11afSPaul Mackerras/* 206414cf11afSPaul Mackerras * We put a few things here that have to be page-aligned. 206514cf11afSPaul Mackerras * This stuff goes at the beginning of the bss, which is page-aligned. 206614cf11afSPaul Mackerras */ 206714cf11afSPaul Mackerras .section ".bss" 206814cf11afSPaul Mackerras 206914cf11afSPaul Mackerras .align PAGE_SHIFT 207014cf11afSPaul Mackerras 207114cf11afSPaul Mackerras .globl empty_zero_page 207214cf11afSPaul Mackerrasempty_zero_page: 207314cf11afSPaul Mackerras .space PAGE_SIZE 207414cf11afSPaul Mackerras 207514cf11afSPaul Mackerras .globl swapper_pg_dir 207614cf11afSPaul Mackerrasswapper_pg_dir: 207714cf11afSPaul Mackerras .space PAGE_SIZE 207814cf11afSPaul Mackerras 207914cf11afSPaul Mackerras/* 208014cf11afSPaul Mackerras * This space gets a copy of optional info passed to us by the bootstrap 208114cf11afSPaul Mackerras * Used to pass parameters into the kernel like root=/dev/sda1, etc. 208214cf11afSPaul Mackerras */ 208314cf11afSPaul Mackerras .globl cmd_line 208414cf11afSPaul Mackerrascmd_line: 208514cf11afSPaul Mackerras .space COMMAND_LINE_SIZE 2086