1/* 2 * Kernel execution entry point code. 3 * 4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 5 * Initial PowerPC version. 6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Rewritten for PReP 8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 9 * Low-level exception handers, MMU support, and rewrite. 10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 11 * PowerPC 8xx modifications. 12 * Copyright (c) 1998-1999 TiVo, Inc. 13 * PowerPC 403GCX modifications. 14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 15 * PowerPC 403GCX/405GP modifications. 16 * Copyright 2000 MontaVista Software Inc. 17 * PPC405 modifications 18 * PowerPC 403GCX/405GP modifications. 19 * Author: MontaVista Software, Inc. 20 * frank_rowand@mvista.com or source@mvista.com 21 * debbie_chu@mvista.com 22 * Copyright 2002-2005 MontaVista Software, Inc. 23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> 24 * 25 * This program is free software; you can redistribute it and/or modify it 26 * under the terms of the GNU General Public License as published by the 27 * Free Software Foundation; either version 2 of the License, or (at your 28 * option) any later version. 29 */ 30 31#include <linux/init.h> 32#include <asm/processor.h> 33#include <asm/page.h> 34#include <asm/mmu.h> 35#include <asm/pgtable.h> 36#include <asm/cputable.h> 37#include <asm/thread_info.h> 38#include <asm/ppc_asm.h> 39#include <asm/asm-offsets.h> 40#include <asm/ptrace.h> 41#include <asm/synch.h> 42#include <asm/export.h> 43#include "head_booke.h" 44 45 46/* As with the other PowerPC ports, it is expected that when code 47 * execution begins here, the following registers contain valid, yet 48 * optional, information: 49 * 50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 51 * r4 - Starting address of the init RAM disk 52 * r5 - Ending address of the init RAM disk 53 * r6 - Start of kernel command line string (e.g. "mem=128") 54 * r7 - End of kernel command line string 55 * 56 */ 57 __HEAD 58_ENTRY(_stext); 59_ENTRY(_start); 60 /* 61 * Reserve a word at a fixed location to store the address 62 * of abatron_pteptrs 63 */ 64 nop 65 mr r31,r3 /* save device tree ptr */ 66 li r24,0 /* CPU number */ 67 68#ifdef CONFIG_RELOCATABLE 69/* 70 * Relocate ourselves to the current runtime address. 71 * This is called only by the Boot CPU. 72 * "relocate" is called with our current runtime virutal 73 * address. 74 * r21 will be loaded with the physical runtime address of _stext 75 */ 76 bl 0f /* Get our runtime address */ 770: mflr r21 /* Make it accessible */ 78 addis r21,r21,(_stext - 0b)@ha 79 addi r21,r21,(_stext - 0b)@l /* Get our current runtime base */ 80 81 /* 82 * We have the runtime (virutal) address of our base. 83 * We calculate our shift of offset from a 256M page. 84 * We could map the 256M page we belong to at PAGE_OFFSET and 85 * get going from there. 86 */ 87 lis r4,KERNELBASE@h 88 ori r4,r4,KERNELBASE@l 89 rlwinm r6,r21,0,4,31 /* r6 = PHYS_START % 256M */ 90 rlwinm r5,r4,0,4,31 /* r5 = KERNELBASE % 256M */ 91 subf r3,r5,r6 /* r3 = r6 - r5 */ 92 add r3,r4,r3 /* Required Virutal Address */ 93 94 bl relocate 95#endif 96 97 bl init_cpu_state 98 99 /* 100 * This is where the main kernel code starts. 101 */ 102 103 /* ptr to current */ 104 lis r2,init_task@h 105 ori r2,r2,init_task@l 106 107 /* ptr to current thread */ 108 addi r4,r2,THREAD /* init task's THREAD */ 109 mtspr SPRN_SPRG_THREAD,r4 110 111 /* stack */ 112 lis r1,init_thread_union@h 113 ori r1,r1,init_thread_union@l 114 li r0,0 115 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 116 117 bl early_init 118 119#ifdef CONFIG_RELOCATABLE 120 /* 121 * Relocatable kernel support based on processing of dynamic 122 * relocation entries. 123 * 124 * r25 will contain RPN/ERPN for the start address of memory 125 * r21 will contain the current offset of _stext 126 */ 127 lis r3,kernstart_addr@ha 128 la r3,kernstart_addr@l(r3) 129 130 /* 131 * Compute the kernstart_addr. 132 * kernstart_addr => (r6,r8) 133 * kernstart_addr & ~0xfffffff => (r6,r7) 134 */ 135 rlwinm r6,r25,0,28,31 /* ERPN. Bits 32-35 of Address */ 136 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */ 137 rlwinm r8,r21,0,4,31 /* r8 = (_stext & 0xfffffff) */ 138 or r8,r7,r8 /* Compute the lower 32bit of kernstart_addr */ 139 140 /* Store kernstart_addr */ 141 stw r6,0(r3) /* higher 32bit */ 142 stw r8,4(r3) /* lower 32bit */ 143 144 /* 145 * Compute the virt_phys_offset : 146 * virt_phys_offset = stext.run - kernstart_addr 147 * 148 * stext.run = (KERNELBASE & ~0xfffffff) + (kernstart_addr & 0xfffffff) 149 * When we relocate, we have : 150 * 151 * (kernstart_addr & 0xfffffff) = (stext.run & 0xfffffff) 152 * 153 * hence: 154 * virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff) 155 * 156 */ 157 158 /* KERNELBASE&~0xfffffff => (r4,r5) */ 159 li r4, 0 /* higer 32bit */ 160 lis r5,KERNELBASE@h 161 rlwinm r5,r5,0,0,3 /* Align to 256M, lower 32bit */ 162 163 /* 164 * 64bit subtraction. 165 */ 166 subfc r5,r7,r5 167 subfe r4,r6,r4 168 169 /* Store virt_phys_offset */ 170 lis r3,virt_phys_offset@ha 171 la r3,virt_phys_offset@l(r3) 172 173 stw r4,0(r3) 174 stw r5,4(r3) 175 176#elif defined(CONFIG_DYNAMIC_MEMSTART) 177 /* 178 * Mapping based, page aligned dynamic kernel loading. 179 * 180 * r25 will contain RPN/ERPN for the start address of memory 181 * 182 * Add the difference between KERNELBASE and PAGE_OFFSET to the 183 * start of physical memory to get kernstart_addr. 184 */ 185 lis r3,kernstart_addr@ha 186 la r3,kernstart_addr@l(r3) 187 188 lis r4,KERNELBASE@h 189 ori r4,r4,KERNELBASE@l 190 lis r5,PAGE_OFFSET@h 191 ori r5,r5,PAGE_OFFSET@l 192 subf r4,r5,r4 193 194 rlwinm r6,r25,0,28,31 /* ERPN */ 195 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */ 196 add r7,r7,r4 197 198 stw r6,0(r3) 199 stw r7,4(r3) 200#endif 201 202/* 203 * Decide what sort of machine this is and initialize the MMU. 204 */ 205 li r3,0 206 mr r4,r31 207 bl machine_init 208 bl MMU_init 209 210 /* Setup PTE pointers for the Abatron bdiGDB */ 211 lis r6, swapper_pg_dir@h 212 ori r6, r6, swapper_pg_dir@l 213 lis r5, abatron_pteptrs@h 214 ori r5, r5, abatron_pteptrs@l 215 lis r4, KERNELBASE@h 216 ori r4, r4, KERNELBASE@l 217 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ 218 stw r6, 0(r5) 219 220 /* Clear the Machine Check Syndrome Register */ 221 li r0,0 222 mtspr SPRN_MCSR,r0 223 224 /* Let's move on */ 225 lis r4,start_kernel@h 226 ori r4,r4,start_kernel@l 227 lis r3,MSR_KERNEL@h 228 ori r3,r3,MSR_KERNEL@l 229 mtspr SPRN_SRR0,r4 230 mtspr SPRN_SRR1,r3 231 rfi /* change context and jump to start_kernel */ 232 233/* 234 * Interrupt vector entry code 235 * 236 * The Book E MMUs are always on so we don't need to handle 237 * interrupts in real mode as with previous PPC processors. In 238 * this case we handle interrupts in the kernel virtual address 239 * space. 240 * 241 * Interrupt vectors are dynamically placed relative to the 242 * interrupt prefix as determined by the address of interrupt_base. 243 * The interrupt vectors offsets are programmed using the labels 244 * for each interrupt vector entry. 245 * 246 * Interrupt vectors must be aligned on a 16 byte boundary. 247 * We align on a 32 byte cache line boundary for good measure. 248 */ 249 250interrupt_base: 251 /* Critical Input Interrupt */ 252 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) 253 254 /* Machine Check Interrupt */ 255 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \ 256 machine_check_exception) 257 MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception) 258 259 /* Data Storage Interrupt */ 260 DATA_STORAGE_EXCEPTION 261 262 /* Instruction Storage Interrupt */ 263 INSTRUCTION_STORAGE_EXCEPTION 264 265 /* External Input Interrupt */ 266 EXCEPTION(0x0500, BOOKE_INTERRUPT_EXTERNAL, ExternalInput, \ 267 do_IRQ, EXC_XFER_LITE) 268 269 /* Alignment Interrupt */ 270 ALIGNMENT_EXCEPTION 271 272 /* Program Interrupt */ 273 PROGRAM_EXCEPTION 274 275 /* Floating Point Unavailable Interrupt */ 276#ifdef CONFIG_PPC_FPU 277 FP_UNAVAILABLE_EXCEPTION 278#else 279 EXCEPTION(0x2010, BOOKE_INTERRUPT_FP_UNAVAIL, \ 280 FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) 281#endif 282 /* System Call Interrupt */ 283 START_EXCEPTION(SystemCall) 284 NORMAL_EXCEPTION_PROLOG(BOOKE_INTERRUPT_SYSCALL) 285 EXC_XFER_EE_LITE(0x0c00, DoSyscall) 286 287 /* Auxiliary Processor Unavailable Interrupt */ 288 EXCEPTION(0x2020, BOOKE_INTERRUPT_AP_UNAVAIL, \ 289 AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) 290 291 /* Decrementer Interrupt */ 292 DECREMENTER_EXCEPTION 293 294 /* Fixed Internal Timer Interrupt */ 295 /* TODO: Add FIT support */ 296 EXCEPTION(0x1010, BOOKE_INTERRUPT_FIT, FixedIntervalTimer, \ 297 unknown_exception, EXC_XFER_EE) 298 299 /* Watchdog Timer Interrupt */ 300 /* TODO: Add watchdog support */ 301#ifdef CONFIG_BOOKE_WDT 302 CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, WatchdogException) 303#else 304 CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, unknown_exception) 305#endif 306 307 /* Data TLB Error Interrupt */ 308 START_EXCEPTION(DataTLBError44x) 309 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 310 mtspr SPRN_SPRG_WSCRATCH1, r11 311 mtspr SPRN_SPRG_WSCRATCH2, r12 312 mtspr SPRN_SPRG_WSCRATCH3, r13 313 mfcr r11 314 mtspr SPRN_SPRG_WSCRATCH4, r11 315 mfspr r10, SPRN_DEAR /* Get faulting address */ 316 317 /* If we are faulting a kernel address, we have to use the 318 * kernel page tables. 319 */ 320 lis r11, PAGE_OFFSET@h 321 cmplw r10, r11 322 blt+ 3f 323 lis r11, swapper_pg_dir@h 324 ori r11, r11, swapper_pg_dir@l 325 326 mfspr r12,SPRN_MMUCR 327 rlwinm r12,r12,0,0,23 /* Clear TID */ 328 329 b 4f 330 331 /* Get the PGD for the current thread */ 3323: 333 mfspr r11,SPRN_SPRG_THREAD 334 lwz r11,PGDIR(r11) 335 336 /* Load PID into MMUCR TID */ 337 mfspr r12,SPRN_MMUCR 338 mfspr r13,SPRN_PID /* Get PID */ 339 rlwimi r12,r13,0,24,31 /* Set TID */ 340 3414: 342 mtspr SPRN_MMUCR,r12 343 344 /* Mask of required permission bits. Note that while we 345 * do copy ESR:ST to _PAGE_RW position as trying to write 346 * to an RO page is pretty common, we don't do it with 347 * _PAGE_DIRTY. We could do it, but it's a fairly rare 348 * event so I'd rather take the overhead when it happens 349 * rather than adding an instruction here. We should measure 350 * whether the whole thing is worth it in the first place 351 * as we could avoid loading SPRN_ESR completely in the first 352 * place... 353 * 354 * TODO: Is it worth doing that mfspr & rlwimi in the first 355 * place or can we save a couple of instructions here ? 356 */ 357 mfspr r12,SPRN_ESR 358 li r13,_PAGE_PRESENT|_PAGE_ACCESSED 359 rlwimi r13,r12,10,30,30 360 361 /* Load the PTE */ 362 /* Compute pgdir/pmd offset */ 363 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29 364 lwzx r11, r12, r11 /* Get pgd/pmd entry */ 365 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ 366 beq 2f /* Bail if no table */ 367 368 /* Compute pte address */ 369 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28 370 lwz r11, 0(r12) /* Get high word of pte entry */ 371 lwz r12, 4(r12) /* Get low word of pte entry */ 372 373 lis r10,tlb_44x_index@ha 374 375 andc. r13,r13,r12 /* Check permission */ 376 377 /* Load the next available TLB index */ 378 lwz r13,tlb_44x_index@l(r10) 379 380 bne 2f /* Bail if permission mismach */ 381 382 /* Increment, rollover, and store TLB index */ 383 addi r13,r13,1 384 385 /* Compare with watermark (instruction gets patched) */ 386 .globl tlb_44x_patch_hwater_D 387tlb_44x_patch_hwater_D: 388 cmpwi 0,r13,1 /* reserve entries */ 389 ble 5f 390 li r13,0 3915: 392 /* Store the next available TLB index */ 393 stw r13,tlb_44x_index@l(r10) 394 395 /* Re-load the faulting address */ 396 mfspr r10,SPRN_DEAR 397 398 /* Jump to common tlb load */ 399 b finish_tlb_load_44x 400 4012: 402 /* The bailout. Restore registers to pre-exception conditions 403 * and call the heavyweights to help us out. 404 */ 405 mfspr r11, SPRN_SPRG_RSCRATCH4 406 mtcr r11 407 mfspr r13, SPRN_SPRG_RSCRATCH3 408 mfspr r12, SPRN_SPRG_RSCRATCH2 409 mfspr r11, SPRN_SPRG_RSCRATCH1 410 mfspr r10, SPRN_SPRG_RSCRATCH0 411 b DataStorage 412 413 /* Instruction TLB Error Interrupt */ 414 /* 415 * Nearly the same as above, except we get our 416 * information from different registers and bailout 417 * to a different point. 418 */ 419 START_EXCEPTION(InstructionTLBError44x) 420 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 421 mtspr SPRN_SPRG_WSCRATCH1, r11 422 mtspr SPRN_SPRG_WSCRATCH2, r12 423 mtspr SPRN_SPRG_WSCRATCH3, r13 424 mfcr r11 425 mtspr SPRN_SPRG_WSCRATCH4, r11 426 mfspr r10, SPRN_SRR0 /* Get faulting address */ 427 428 /* If we are faulting a kernel address, we have to use the 429 * kernel page tables. 430 */ 431 lis r11, PAGE_OFFSET@h 432 cmplw r10, r11 433 blt+ 3f 434 lis r11, swapper_pg_dir@h 435 ori r11, r11, swapper_pg_dir@l 436 437 mfspr r12,SPRN_MMUCR 438 rlwinm r12,r12,0,0,23 /* Clear TID */ 439 440 b 4f 441 442 /* Get the PGD for the current thread */ 4433: 444 mfspr r11,SPRN_SPRG_THREAD 445 lwz r11,PGDIR(r11) 446 447 /* Load PID into MMUCR TID */ 448 mfspr r12,SPRN_MMUCR 449 mfspr r13,SPRN_PID /* Get PID */ 450 rlwimi r12,r13,0,24,31 /* Set TID */ 451 4524: 453 mtspr SPRN_MMUCR,r12 454 455 /* Make up the required permissions */ 456 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 457 458 /* Compute pgdir/pmd offset */ 459 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29 460 lwzx r11, r12, r11 /* Get pgd/pmd entry */ 461 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ 462 beq 2f /* Bail if no table */ 463 464 /* Compute pte address */ 465 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28 466 lwz r11, 0(r12) /* Get high word of pte entry */ 467 lwz r12, 4(r12) /* Get low word of pte entry */ 468 469 lis r10,tlb_44x_index@ha 470 471 andc. r13,r13,r12 /* Check permission */ 472 473 /* Load the next available TLB index */ 474 lwz r13,tlb_44x_index@l(r10) 475 476 bne 2f /* Bail if permission mismach */ 477 478 /* Increment, rollover, and store TLB index */ 479 addi r13,r13,1 480 481 /* Compare with watermark (instruction gets patched) */ 482 .globl tlb_44x_patch_hwater_I 483tlb_44x_patch_hwater_I: 484 cmpwi 0,r13,1 /* reserve entries */ 485 ble 5f 486 li r13,0 4875: 488 /* Store the next available TLB index */ 489 stw r13,tlb_44x_index@l(r10) 490 491 /* Re-load the faulting address */ 492 mfspr r10,SPRN_SRR0 493 494 /* Jump to common TLB load point */ 495 b finish_tlb_load_44x 496 4972: 498 /* The bailout. Restore registers to pre-exception conditions 499 * and call the heavyweights to help us out. 500 */ 501 mfspr r11, SPRN_SPRG_RSCRATCH4 502 mtcr r11 503 mfspr r13, SPRN_SPRG_RSCRATCH3 504 mfspr r12, SPRN_SPRG_RSCRATCH2 505 mfspr r11, SPRN_SPRG_RSCRATCH1 506 mfspr r10, SPRN_SPRG_RSCRATCH0 507 b InstructionStorage 508 509/* 510 * Both the instruction and data TLB miss get to this 511 * point to load the TLB. 512 * r10 - EA of fault 513 * r11 - PTE high word value 514 * r12 - PTE low word value 515 * r13 - TLB index 516 * MMUCR - loaded with proper value when we get here 517 * Upon exit, we reload everything and RFI. 518 */ 519finish_tlb_load_44x: 520 /* Combine RPN & ERPN an write WS 0 */ 521 rlwimi r11,r12,0,0,31-PAGE_SHIFT 522 tlbwe r11,r13,PPC44x_TLB_XLAT 523 524 /* 525 * Create WS1. This is the faulting address (EPN), 526 * page size, and valid flag. 527 */ 528 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE 529 /* Insert valid and page size */ 530 rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31 531 tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */ 532 533 /* And WS 2 */ 534 li r10,0xf85 /* Mask to apply from PTE */ 535 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */ 536 and r11,r12,r10 /* Mask PTE bits to keep */ 537 andi. r10,r12,_PAGE_USER /* User page ? */ 538 beq 1f /* nope, leave U bits empty */ 539 rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ 5401: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */ 541 542 /* Done...restore registers and get out of here. 543 */ 544 mfspr r11, SPRN_SPRG_RSCRATCH4 545 mtcr r11 546 mfspr r13, SPRN_SPRG_RSCRATCH3 547 mfspr r12, SPRN_SPRG_RSCRATCH2 548 mfspr r11, SPRN_SPRG_RSCRATCH1 549 mfspr r10, SPRN_SPRG_RSCRATCH0 550 rfi /* Force context change */ 551 552/* TLB error interrupts for 476 553 */ 554#ifdef CONFIG_PPC_47x 555 START_EXCEPTION(DataTLBError47x) 556 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */ 557 mtspr SPRN_SPRG_WSCRATCH1,r11 558 mtspr SPRN_SPRG_WSCRATCH2,r12 559 mtspr SPRN_SPRG_WSCRATCH3,r13 560 mfcr r11 561 mtspr SPRN_SPRG_WSCRATCH4,r11 562 mfspr r10,SPRN_DEAR /* Get faulting address */ 563 564 /* If we are faulting a kernel address, we have to use the 565 * kernel page tables. 566 */ 567 lis r11,PAGE_OFFSET@h 568 cmplw cr0,r10,r11 569 blt+ 3f 570 lis r11,swapper_pg_dir@h 571 ori r11,r11, swapper_pg_dir@l 572 li r12,0 /* MMUCR = 0 */ 573 b 4f 574 575 /* Get the PGD for the current thread and setup MMUCR */ 5763: mfspr r11,SPRN_SPRG3 577 lwz r11,PGDIR(r11) 578 mfspr r12,SPRN_PID /* Get PID */ 5794: mtspr SPRN_MMUCR,r12 /* Set MMUCR */ 580 581 /* Mask of required permission bits. Note that while we 582 * do copy ESR:ST to _PAGE_RW position as trying to write 583 * to an RO page is pretty common, we don't do it with 584 * _PAGE_DIRTY. We could do it, but it's a fairly rare 585 * event so I'd rather take the overhead when it happens 586 * rather than adding an instruction here. We should measure 587 * whether the whole thing is worth it in the first place 588 * as we could avoid loading SPRN_ESR completely in the first 589 * place... 590 * 591 * TODO: Is it worth doing that mfspr & rlwimi in the first 592 * place or can we save a couple of instructions here ? 593 */ 594 mfspr r12,SPRN_ESR 595 li r13,_PAGE_PRESENT|_PAGE_ACCESSED 596 rlwimi r13,r12,10,30,30 597 598 /* Load the PTE */ 599 /* Compute pgdir/pmd offset */ 600 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29 601 lwzx r11,r12,r11 /* Get pgd/pmd entry */ 602 603 /* Word 0 is EPN,V,TS,DSIZ */ 604 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE 605 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/ 606 li r12,0 607 tlbwe r10,r12,0 608 609 /* XXX can we do better ? Need to make sure tlbwe has established 610 * latch V bit in MMUCR0 before the PTE is loaded further down */ 611#ifdef CONFIG_SMP 612 isync 613#endif 614 615 rlwinm. r12,r11,0,0,20 /* Extract pt base address */ 616 /* Compute pte address */ 617 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28 618 beq 2f /* Bail if no table */ 619 lwz r11,0(r12) /* Get high word of pte entry */ 620 621 /* XXX can we do better ? maybe insert a known 0 bit from r11 into the 622 * bottom of r12 to create a data dependency... We can also use r10 623 * as destination nowadays 624 */ 625#ifdef CONFIG_SMP 626 lwsync 627#endif 628 lwz r12,4(r12) /* Get low word of pte entry */ 629 630 andc. r13,r13,r12 /* Check permission */ 631 632 /* Jump to common tlb load */ 633 beq finish_tlb_load_47x 634 6352: /* The bailout. Restore registers to pre-exception conditions 636 * and call the heavyweights to help us out. 637 */ 638 mfspr r11,SPRN_SPRG_RSCRATCH4 639 mtcr r11 640 mfspr r13,SPRN_SPRG_RSCRATCH3 641 mfspr r12,SPRN_SPRG_RSCRATCH2 642 mfspr r11,SPRN_SPRG_RSCRATCH1 643 mfspr r10,SPRN_SPRG_RSCRATCH0 644 b DataStorage 645 646 /* Instruction TLB Error Interrupt */ 647 /* 648 * Nearly the same as above, except we get our 649 * information from different registers and bailout 650 * to a different point. 651 */ 652 START_EXCEPTION(InstructionTLBError47x) 653 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */ 654 mtspr SPRN_SPRG_WSCRATCH1,r11 655 mtspr SPRN_SPRG_WSCRATCH2,r12 656 mtspr SPRN_SPRG_WSCRATCH3,r13 657 mfcr r11 658 mtspr SPRN_SPRG_WSCRATCH4,r11 659 mfspr r10,SPRN_SRR0 /* Get faulting address */ 660 661 /* If we are faulting a kernel address, we have to use the 662 * kernel page tables. 663 */ 664 lis r11,PAGE_OFFSET@h 665 cmplw cr0,r10,r11 666 blt+ 3f 667 lis r11,swapper_pg_dir@h 668 ori r11,r11, swapper_pg_dir@l 669 li r12,0 /* MMUCR = 0 */ 670 b 4f 671 672 /* Get the PGD for the current thread and setup MMUCR */ 6733: mfspr r11,SPRN_SPRG_THREAD 674 lwz r11,PGDIR(r11) 675 mfspr r12,SPRN_PID /* Get PID */ 6764: mtspr SPRN_MMUCR,r12 /* Set MMUCR */ 677 678 /* Make up the required permissions */ 679 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 680 681 /* Load PTE */ 682 /* Compute pgdir/pmd offset */ 683 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29 684 lwzx r11,r12,r11 /* Get pgd/pmd entry */ 685 686 /* Word 0 is EPN,V,TS,DSIZ */ 687 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE 688 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/ 689 li r12,0 690 tlbwe r10,r12,0 691 692 /* XXX can we do better ? Need to make sure tlbwe has established 693 * latch V bit in MMUCR0 before the PTE is loaded further down */ 694#ifdef CONFIG_SMP 695 isync 696#endif 697 698 rlwinm. r12,r11,0,0,20 /* Extract pt base address */ 699 /* Compute pte address */ 700 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28 701 beq 2f /* Bail if no table */ 702 703 lwz r11,0(r12) /* Get high word of pte entry */ 704 /* XXX can we do better ? maybe insert a known 0 bit from r11 into the 705 * bottom of r12 to create a data dependency... We can also use r10 706 * as destination nowadays 707 */ 708#ifdef CONFIG_SMP 709 lwsync 710#endif 711 lwz r12,4(r12) /* Get low word of pte entry */ 712 713 andc. r13,r13,r12 /* Check permission */ 714 715 /* Jump to common TLB load point */ 716 beq finish_tlb_load_47x 717 7182: /* The bailout. Restore registers to pre-exception conditions 719 * and call the heavyweights to help us out. 720 */ 721 mfspr r11, SPRN_SPRG_RSCRATCH4 722 mtcr r11 723 mfspr r13, SPRN_SPRG_RSCRATCH3 724 mfspr r12, SPRN_SPRG_RSCRATCH2 725 mfspr r11, SPRN_SPRG_RSCRATCH1 726 mfspr r10, SPRN_SPRG_RSCRATCH0 727 b InstructionStorage 728 729/* 730 * Both the instruction and data TLB miss get to this 731 * point to load the TLB. 732 * r10 - free to use 733 * r11 - PTE high word value 734 * r12 - PTE low word value 735 * r13 - free to use 736 * MMUCR - loaded with proper value when we get here 737 * Upon exit, we reload everything and RFI. 738 */ 739finish_tlb_load_47x: 740 /* Combine RPN & ERPN an write WS 1 */ 741 rlwimi r11,r12,0,0,31-PAGE_SHIFT 742 tlbwe r11,r13,1 743 744 /* And make up word 2 */ 745 li r10,0xf85 /* Mask to apply from PTE */ 746 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */ 747 and r11,r12,r10 /* Mask PTE bits to keep */ 748 andi. r10,r12,_PAGE_USER /* User page ? */ 749 beq 1f /* nope, leave U bits empty */ 750 rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ 7511: tlbwe r11,r13,2 752 753 /* Done...restore registers and get out of here. 754 */ 755 mfspr r11, SPRN_SPRG_RSCRATCH4 756 mtcr r11 757 mfspr r13, SPRN_SPRG_RSCRATCH3 758 mfspr r12, SPRN_SPRG_RSCRATCH2 759 mfspr r11, SPRN_SPRG_RSCRATCH1 760 mfspr r10, SPRN_SPRG_RSCRATCH0 761 rfi 762 763#endif /* CONFIG_PPC_47x */ 764 765 /* Debug Interrupt */ 766 /* 767 * This statement needs to exist at the end of the IVPR 768 * definition just in case you end up taking a debug 769 * exception within another exception. 770 */ 771 DEBUG_CRIT_EXCEPTION 772 773interrupt_end: 774 775/* 776 * Global functions 777 */ 778 779/* 780 * Adjust the machine check IVOR on 440A cores 781 */ 782_GLOBAL(__fixup_440A_mcheck) 783 li r3,MachineCheckA@l 784 mtspr SPRN_IVOR1,r3 785 sync 786 blr 787 788_GLOBAL(set_context) 789 790#ifdef CONFIG_BDI_SWITCH 791 /* Context switch the PTE pointer for the Abatron BDI2000. 792 * The PGDIR is the second parameter. 793 */ 794 lis r5, abatron_pteptrs@h 795 ori r5, r5, abatron_pteptrs@l 796 stw r4, 0x4(r5) 797#endif 798 mtspr SPRN_PID,r3 799 isync /* Force context change */ 800 blr 801 802/* 803 * Init CPU state. This is called at boot time or for secondary CPUs 804 * to setup initial TLB entries, setup IVORs, etc... 805 * 806 */ 807_GLOBAL(init_cpu_state) 808 mflr r22 809#ifdef CONFIG_PPC_47x 810 /* We use the PVR to differentiate 44x cores from 476 */ 811 mfspr r3,SPRN_PVR 812 srwi r3,r3,16 813 cmplwi cr0,r3,PVR_476FPE@h 814 beq head_start_47x 815 cmplwi cr0,r3,PVR_476@h 816 beq head_start_47x 817 cmplwi cr0,r3,PVR_476_ISS@h 818 beq head_start_47x 819#endif /* CONFIG_PPC_47x */ 820 821/* 822 * In case the firmware didn't do it, we apply some workarounds 823 * that are good for all 440 core variants here 824 */ 825 mfspr r3,SPRN_CCR0 826 rlwinm r3,r3,0,0,27 /* disable icache prefetch */ 827 isync 828 mtspr SPRN_CCR0,r3 829 isync 830 sync 831 832/* 833 * Set up the initial MMU state for 44x 834 * 835 * We are still executing code at the virtual address 836 * mappings set by the firmware for the base of RAM. 837 * 838 * We first invalidate all TLB entries but the one 839 * we are running from. We then load the KERNELBASE 840 * mappings so we can begin to use kernel addresses 841 * natively and so the interrupt vector locations are 842 * permanently pinned (necessary since Book E 843 * implementations always have translation enabled). 844 * 845 * TODO: Use the known TLB entry we are running from to 846 * determine which physical region we are located 847 * in. This can be used to determine where in RAM 848 * (on a shared CPU system) or PCI memory space 849 * (on a DRAMless system) we are located. 850 * For now, we assume a perfect world which means 851 * we are located at the base of DRAM (physical 0). 852 */ 853 854/* 855 * Search TLB for entry that we are currently using. 856 * Invalidate all entries but the one we are using. 857 */ 858 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ 859 mfspr r3,SPRN_PID /* Get PID */ 860 mfmsr r4 /* Get MSR */ 861 andi. r4,r4,MSR_IS@l /* TS=1? */ 862 beq wmmucr /* If not, leave STS=0 */ 863 oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */ 864wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ 865 sync 866 867 bl invstr /* Find our address */ 868invstr: mflr r5 /* Make it accessible */ 869 tlbsx r23,0,r5 /* Find entry we are in */ 870 li r4,0 /* Start at TLB entry 0 */ 871 li r3,0 /* Set PAGEID inval value */ 8721: cmpw r23,r4 /* Is this our entry? */ 873 beq skpinv /* If so, skip the inval */ 874 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ 875skpinv: addi r4,r4,1 /* Increment */ 876 cmpwi r4,64 /* Are we done? */ 877 bne 1b /* If not, repeat */ 878 isync /* If so, context change */ 879 880/* 881 * Configure and load pinned entry into TLB slot 63. 882 */ 883#ifdef CONFIG_NONSTATIC_KERNEL 884 /* 885 * In case of a NONSTATIC_KERNEL we reuse the TLB XLAT 886 * entries of the initial mapping set by the boot loader. 887 * The XLAT entry is stored in r25 888 */ 889 890 /* Read the XLAT entry for our current mapping */ 891 tlbre r25,r23,PPC44x_TLB_XLAT 892 893 lis r3,KERNELBASE@h 894 ori r3,r3,KERNELBASE@l 895 896 /* Use our current RPN entry */ 897 mr r4,r25 898#else 899 900 lis r3,PAGE_OFFSET@h 901 ori r3,r3,PAGE_OFFSET@l 902 903 /* Kernel is at the base of RAM */ 904 li r4, 0 /* Load the kernel physical address */ 905#endif 906 907 /* Load the kernel PID = 0 */ 908 li r0,0 909 mtspr SPRN_PID,r0 910 sync 911 912 /* Initialize MMUCR */ 913 li r5,0 914 mtspr SPRN_MMUCR,r5 915 sync 916 917 /* pageid fields */ 918 clrrwi r3,r3,10 /* Mask off the effective page number */ 919 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M 920 921 /* xlat fields */ 922 clrrwi r4,r4,10 /* Mask off the real page number */ 923 /* ERPN is 0 for first 4GB page */ 924 925 /* attrib fields */ 926 /* Added guarded bit to protect against speculative loads/stores */ 927 li r5,0 928 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) 929 930 li r0,63 /* TLB slot 63 */ 931 932 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ 933 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ 934 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ 935 936 /* Force context change */ 937 mfmsr r0 938 mtspr SPRN_SRR1, r0 939 lis r0,3f@h 940 ori r0,r0,3f@l 941 mtspr SPRN_SRR0,r0 942 sync 943 rfi 944 945 /* If necessary, invalidate original entry we used */ 9463: cmpwi r23,63 947 beq 4f 948 li r6,0 949 tlbwe r6,r23,PPC44x_TLB_PAGEID 950 isync 951 9524: 953#ifdef CONFIG_PPC_EARLY_DEBUG_44x 954 /* Add UART mapping for early debug. */ 955 956 /* pageid fields */ 957 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h 958 ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K 959 960 /* xlat fields */ 961 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h 962 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH 963 964 /* attrib fields */ 965 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G) 966 li r0,62 /* TLB slot 0 */ 967 968 tlbwe r3,r0,PPC44x_TLB_PAGEID 969 tlbwe r4,r0,PPC44x_TLB_XLAT 970 tlbwe r5,r0,PPC44x_TLB_ATTRIB 971 972 /* Force context change */ 973 isync 974#endif /* CONFIG_PPC_EARLY_DEBUG_44x */ 975 976 /* Establish the interrupt vector offsets */ 977 SET_IVOR(0, CriticalInput); 978 SET_IVOR(1, MachineCheck); 979 SET_IVOR(2, DataStorage); 980 SET_IVOR(3, InstructionStorage); 981 SET_IVOR(4, ExternalInput); 982 SET_IVOR(5, Alignment); 983 SET_IVOR(6, Program); 984 SET_IVOR(7, FloatingPointUnavailable); 985 SET_IVOR(8, SystemCall); 986 SET_IVOR(9, AuxillaryProcessorUnavailable); 987 SET_IVOR(10, Decrementer); 988 SET_IVOR(11, FixedIntervalTimer); 989 SET_IVOR(12, WatchdogTimer); 990 SET_IVOR(13, DataTLBError44x); 991 SET_IVOR(14, InstructionTLBError44x); 992 SET_IVOR(15, DebugCrit); 993 994 b head_start_common 995 996 997#ifdef CONFIG_PPC_47x 998 999#ifdef CONFIG_SMP 1000 1001/* Entry point for secondary 47x processors */ 1002_GLOBAL(start_secondary_47x) 1003 mr r24,r3 /* CPU number */ 1004 1005 bl init_cpu_state 1006 1007 /* Now we need to bolt the rest of kernel memory which 1008 * is done in C code. We must be careful because our task 1009 * struct or our stack can (and will probably) be out 1010 * of reach of the initial 256M TLB entry, so we use a 1011 * small temporary stack in .bss for that. This works 1012 * because only one CPU at a time can be in this code 1013 */ 1014 lis r1,temp_boot_stack@h 1015 ori r1,r1,temp_boot_stack@l 1016 addi r1,r1,1024-STACK_FRAME_OVERHEAD 1017 li r0,0 1018 stw r0,0(r1) 1019 bl mmu_init_secondary 1020 1021 /* Now we can get our task struct and real stack pointer */ 1022 1023 /* Get current_thread_info and current */ 1024 lis r1,secondary_ti@ha 1025 lwz r1,secondary_ti@l(r1) 1026 lwz r2,TI_TASK(r1) 1027 1028 /* Current stack pointer */ 1029 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1030 li r0,0 1031 stw r0,0(r1) 1032 1033 /* Kernel stack for exception entry in SPRG3 */ 1034 addi r4,r2,THREAD /* init task's THREAD */ 1035 mtspr SPRN_SPRG3,r4 1036 1037 b start_secondary 1038 1039#endif /* CONFIG_SMP */ 1040 1041/* 1042 * Set up the initial MMU state for 44x 1043 * 1044 * We are still executing code at the virtual address 1045 * mappings set by the firmware for the base of RAM. 1046 */ 1047 1048head_start_47x: 1049 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ 1050 mfspr r3,SPRN_PID /* Get PID */ 1051 mfmsr r4 /* Get MSR */ 1052 andi. r4,r4,MSR_IS@l /* TS=1? */ 1053 beq 1f /* If not, leave STS=0 */ 1054 oris r3,r3,PPC47x_MMUCR_STS@h /* Set STS=1 */ 10551: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ 1056 sync 1057 1058 /* Find the entry we are running from */ 1059 bl 1f 10601: mflr r23 1061 tlbsx r23,0,r23 1062 tlbre r24,r23,0 1063 tlbre r25,r23,1 1064 tlbre r26,r23,2 1065 1066/* 1067 * Cleanup time 1068 */ 1069 1070 /* Initialize MMUCR */ 1071 li r5,0 1072 mtspr SPRN_MMUCR,r5 1073 sync 1074 1075clear_all_utlb_entries: 1076 1077 #; Set initial values. 1078 1079 addis r3,0,0x8000 1080 addi r4,0,0 1081 addi r5,0,0 1082 b clear_utlb_entry 1083 1084 #; Align the loop to speed things up. 1085 1086 .align 6 1087 1088clear_utlb_entry: 1089 1090 tlbwe r4,r3,0 1091 tlbwe r5,r3,1 1092 tlbwe r5,r3,2 1093 addis r3,r3,0x2000 1094 cmpwi r3,0 1095 bne clear_utlb_entry 1096 addis r3,0,0x8000 1097 addis r4,r4,0x100 1098 cmpwi r4,0 1099 bne clear_utlb_entry 1100 1101 #; Restore original entry. 1102 1103 oris r23,r23,0x8000 /* specify the way */ 1104 tlbwe r24,r23,0 1105 tlbwe r25,r23,1 1106 tlbwe r26,r23,2 1107 1108/* 1109 * Configure and load pinned entry into TLB for the kernel core 1110 */ 1111 1112 lis r3,PAGE_OFFSET@h 1113 ori r3,r3,PAGE_OFFSET@l 1114 1115 /* Load the kernel PID = 0 */ 1116 li r0,0 1117 mtspr SPRN_PID,r0 1118 sync 1119 1120 /* Word 0 */ 1121 clrrwi r3,r3,12 /* Mask off the effective page number */ 1122 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M 1123 1124 /* Word 1 - use r25. RPN is the same as the original entry */ 1125 1126 /* Word 2 */ 1127 li r5,0 1128 ori r5,r5,PPC47x_TLB2_S_RWX 1129#ifdef CONFIG_SMP 1130 ori r5,r5,PPC47x_TLB2_M 1131#endif 1132 1133 /* We write to way 0 and bolted 0 */ 1134 lis r0,0x8800 1135 tlbwe r3,r0,0 1136 tlbwe r25,r0,1 1137 tlbwe r5,r0,2 1138 1139/* 1140 * Configure SSPCR, ISPCR and USPCR for now to search everything, we can fix 1141 * them up later 1142 */ 1143 LOAD_REG_IMMEDIATE(r3, 0x9abcdef0) 1144 mtspr SPRN_SSPCR,r3 1145 mtspr SPRN_USPCR,r3 1146 LOAD_REG_IMMEDIATE(r3, 0x12345670) 1147 mtspr SPRN_ISPCR,r3 1148 1149 /* Force context change */ 1150 mfmsr r0 1151 mtspr SPRN_SRR1, r0 1152 lis r0,3f@h 1153 ori r0,r0,3f@l 1154 mtspr SPRN_SRR0,r0 1155 sync 1156 rfi 1157 1158 /* Invalidate original entry we used */ 11593: 1160 rlwinm r24,r24,0,21,19 /* clear the "valid" bit */ 1161 tlbwe r24,r23,0 1162 addi r24,0,0 1163 tlbwe r24,r23,1 1164 tlbwe r24,r23,2 1165 isync /* Clear out the shadow TLB entries */ 1166 1167#ifdef CONFIG_PPC_EARLY_DEBUG_44x 1168 /* Add UART mapping for early debug. */ 1169 1170 /* Word 0 */ 1171 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h 1172 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_TS | PPC47x_TLB0_1M 1173 1174 /* Word 1 */ 1175 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h 1176 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH 1177 1178 /* Word 2 */ 1179 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG) 1180 1181 /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same 1182 * congruence class as the kernel, we need to make sure of it at 1183 * some point 1184 */ 1185 lis r0,0x8d00 1186 tlbwe r3,r0,0 1187 tlbwe r4,r0,1 1188 tlbwe r5,r0,2 1189 1190 /* Force context change */ 1191 isync 1192#endif /* CONFIG_PPC_EARLY_DEBUG_44x */ 1193 1194 /* Establish the interrupt vector offsets */ 1195 SET_IVOR(0, CriticalInput); 1196 SET_IVOR(1, MachineCheckA); 1197 SET_IVOR(2, DataStorage); 1198 SET_IVOR(3, InstructionStorage); 1199 SET_IVOR(4, ExternalInput); 1200 SET_IVOR(5, Alignment); 1201 SET_IVOR(6, Program); 1202 SET_IVOR(7, FloatingPointUnavailable); 1203 SET_IVOR(8, SystemCall); 1204 SET_IVOR(9, AuxillaryProcessorUnavailable); 1205 SET_IVOR(10, Decrementer); 1206 SET_IVOR(11, FixedIntervalTimer); 1207 SET_IVOR(12, WatchdogTimer); 1208 SET_IVOR(13, DataTLBError47x); 1209 SET_IVOR(14, InstructionTLBError47x); 1210 SET_IVOR(15, DebugCrit); 1211 1212 /* We configure icbi to invalidate 128 bytes at a time since the 1213 * current 32-bit kernel code isn't too happy with icache != dcache 1214 * block size. We also disable the BTAC as this can cause errors 1215 * in some circumstances (see IBM Erratum 47). 1216 */ 1217 mfspr r3,SPRN_CCR0 1218 oris r3,r3,0x0020 1219 ori r3,r3,0x0040 1220 mtspr SPRN_CCR0,r3 1221 isync 1222 1223#endif /* CONFIG_PPC_47x */ 1224 1225/* 1226 * Here we are back to code that is common between 44x and 47x 1227 * 1228 * We proceed to further kernel initialization and return to the 1229 * main kernel entry 1230 */ 1231head_start_common: 1232 /* Establish the interrupt vector base */ 1233 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 1234 mtspr SPRN_IVPR,r4 1235 1236 /* 1237 * If the kernel was loaded at a non-zero 256 MB page, we need to 1238 * mask off the most significant 4 bits to get the relative address 1239 * from the start of physical memory 1240 */ 1241 rlwinm r22,r22,0,4,31 1242 addis r22,r22,PAGE_OFFSET@h 1243 mtlr r22 1244 isync 1245 blr 1246 1247/* 1248 * We put a few things here that have to be page-aligned. This stuff 1249 * goes at the beginning of the data segment, which is page-aligned. 1250 */ 1251 .data 1252 .align PAGE_SHIFT 1253 .globl sdata 1254sdata: 1255 .globl empty_zero_page 1256empty_zero_page: 1257 .space PAGE_SIZE 1258EXPORT_SYMBOL(empty_zero_page) 1259 1260/* 1261 * To support >32-bit physical addresses, we use an 8KB pgdir. 1262 */ 1263 .globl swapper_pg_dir 1264swapper_pg_dir: 1265 .space PGD_TABLE_SIZE 1266 1267/* 1268 * Room for two PTE pointers, usually the kernel and current user pointers 1269 * to their respective root page table. 1270 */ 1271abatron_pteptrs: 1272 .space 8 1273 1274#ifdef CONFIG_SMP 1275 .align 12 1276temp_boot_stack: 1277 .space 1024 1278#endif /* CONFIG_SMP */ 1279