xref: /openbmc/linux/arch/powerpc/kernel/head_40x.S (revision b6dcefde)
1/*
2 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
3 *      Initial PowerPC version.
4 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
5 *      Rewritten for PReP
6 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
7 *      Low-level exception handers, MMU support, and rewrite.
8 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
9 *      PowerPC 8xx modifications.
10 *    Copyright (c) 1998-1999 TiVo, Inc.
11 *      PowerPC 403GCX modifications.
12 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
13 *      PowerPC 403GCX/405GP modifications.
14 *    Copyright 2000 MontaVista Software Inc.
15 *	PPC405 modifications
16 *      PowerPC 403GCX/405GP modifications.
17 * 	Author: MontaVista Software, Inc.
18 *         	frank_rowand@mvista.com or source@mvista.com
19 * 	   	debbie_chu@mvista.com
20 *
21 *
22 *    Module name: head_4xx.S
23 *
24 *    Description:
25 *      Kernel execution entry point code.
26 *
27 *    This program is free software; you can redistribute it and/or
28 *    modify it under the terms of the GNU General Public License
29 *    as published by the Free Software Foundation; either version
30 *    2 of the License, or (at your option) any later version.
31 *
32 */
33
34#include <linux/init.h>
35#include <asm/processor.h>
36#include <asm/page.h>
37#include <asm/mmu.h>
38#include <asm/pgtable.h>
39#include <asm/cputable.h>
40#include <asm/thread_info.h>
41#include <asm/ppc_asm.h>
42#include <asm/asm-offsets.h>
43
44/* As with the other PowerPC ports, it is expected that when code
45 * execution begins here, the following registers contain valid, yet
46 * optional, information:
47 *
48 *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
49 *   r4 - Starting address of the init RAM disk
50 *   r5 - Ending address of the init RAM disk
51 *   r6 - Start of kernel command line string (e.g. "mem=96m")
52 *   r7 - End of kernel command line string
53 *
54 * This is all going to change RSN when we add bi_recs.......  -- Dan
55 */
56	__HEAD
57_ENTRY(_stext);
58_ENTRY(_start);
59
60	/* Save parameters we are passed.
61	*/
62	mr	r31,r3
63	mr	r30,r4
64	mr	r29,r5
65	mr	r28,r6
66	mr	r27,r7
67
68	/* We have to turn on the MMU right away so we get cache modes
69	 * set correctly.
70	 */
71	bl	initial_mmu
72
73/* We now have the lower 16 Meg mapped into TLB entries, and the caches
74 * ready to work.
75 */
76turn_on_mmu:
77	lis	r0,MSR_KERNEL@h
78	ori	r0,r0,MSR_KERNEL@l
79	mtspr	SPRN_SRR1,r0
80	lis	r0,start_here@h
81	ori	r0,r0,start_here@l
82	mtspr	SPRN_SRR0,r0
83	SYNC
84	rfi				/* enables MMU */
85	b	.			/* prevent prefetch past rfi */
86
87/*
88 * This area is used for temporarily saving registers during the
89 * critical exception prolog.
90 */
91	. = 0xc0
92crit_save:
93_ENTRY(crit_r10)
94	.space	4
95_ENTRY(crit_r11)
96	.space	4
97_ENTRY(crit_srr0)
98	.space	4
99_ENTRY(crit_srr1)
100	.space	4
101_ENTRY(saved_ksp_limit)
102	.space	4
103
104/*
105 * Exception vector entry code. This code runs with address translation
106 * turned off (i.e. using physical addresses). We assume SPRG_THREAD has
107 * the physical address of the current task thread_struct.
108 * Note that we have to have decremented r1 before we write to any fields
109 * of the exception frame, since a critical interrupt could occur at any
110 * time, and it will write to the area immediately below the current r1.
111 */
112#define NORMAL_EXCEPTION_PROLOG						     \
113	mtspr	SPRN_SPRG_SCRATCH0,r10;	/* save two registers to work with */\
114	mtspr	SPRN_SPRG_SCRATCH1,r11;					     \
115	mtspr	SPRN_SPRG_SCRATCH2,r1;					     \
116	mfcr	r10;			/* save CR in r10 for now	   */\
117	mfspr	r11,SPRN_SRR1;		/* check whether user or kernel    */\
118	andi.	r11,r11,MSR_PR;						     \
119	beq	1f;							     \
120	mfspr	r1,SPRN_SPRG_THREAD;	/* if from user, start at top of   */\
121	lwz	r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
122	addi	r1,r1,THREAD_SIZE;					     \
1231:	subi	r1,r1,INT_FRAME_SIZE;	/* Allocate an exception frame     */\
124	tophys(r11,r1);							     \
125	stw	r10,_CCR(r11);          /* save various registers	   */\
126	stw	r12,GPR12(r11);						     \
127	stw	r9,GPR9(r11);						     \
128	mfspr	r10,SPRN_SPRG_SCRATCH0;					     \
129	stw	r10,GPR10(r11);						     \
130	mfspr	r12,SPRN_SPRG_SCRATCH1;					     \
131	stw	r12,GPR11(r11);						     \
132	mflr	r10;							     \
133	stw	r10,_LINK(r11);						     \
134	mfspr	r10,SPRN_SPRG_SCRATCH2;					     \
135	mfspr	r12,SPRN_SRR0;						     \
136	stw	r10,GPR1(r11);						     \
137	mfspr	r9,SPRN_SRR1;						     \
138	stw	r10,0(r11);						     \
139	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
140	stw	r0,GPR0(r11);						     \
141	SAVE_4GPRS(3, r11);						     \
142	SAVE_2GPRS(7, r11)
143
144/*
145 * Exception prolog for critical exceptions.  This is a little different
146 * from the normal exception prolog above since a critical exception
147 * can potentially occur at any point during normal exception processing.
148 * Thus we cannot use the same SPRG registers as the normal prolog above.
149 * Instead we use a couple of words of memory at low physical addresses.
150 * This is OK since we don't support SMP on these processors.
151 */
152#define CRITICAL_EXCEPTION_PROLOG					     \
153	stw	r10,crit_r10@l(0);	/* save two registers to work with */\
154	stw	r11,crit_r11@l(0);					     \
155	mfcr	r10;			/* save CR in r10 for now	   */\
156	mfspr	r11,SPRN_SRR3;		/* check whether user or kernel    */\
157	andi.	r11,r11,MSR_PR;						     \
158	lis	r11,critirq_ctx@ha;					     \
159	tophys(r11,r11);						     \
160	lwz	r11,critirq_ctx@l(r11);					     \
161	beq	1f;							     \
162	/* COMING FROM USER MODE */					     \
163	mfspr	r11,SPRN_SPRG_THREAD;	/* if from user, start at top of   */\
164	lwz	r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
1651:	addi	r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm  */\
166	tophys(r11,r11);						     \
167	stw	r10,_CCR(r11);          /* save various registers	   */\
168	stw	r12,GPR12(r11);						     \
169	stw	r9,GPR9(r11);						     \
170	mflr	r10;							     \
171	stw	r10,_LINK(r11);						     \
172	mfspr	r12,SPRN_DEAR;		/* save DEAR and ESR in the frame  */\
173	stw	r12,_DEAR(r11);		/* since they may have had stuff   */\
174	mfspr	r9,SPRN_ESR;		/* in them at the point where the  */\
175	stw	r9,_ESR(r11);		/* exception was taken		   */\
176	mfspr	r12,SPRN_SRR2;						     \
177	stw	r1,GPR1(r11);						     \
178	mfspr	r9,SPRN_SRR3;						     \
179	stw	r1,0(r11);						     \
180	tovirt(r1,r11);							     \
181	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
182	stw	r0,GPR0(r11);						     \
183	SAVE_4GPRS(3, r11);						     \
184	SAVE_2GPRS(7, r11)
185
186	/*
187	 * State at this point:
188	 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
189	 * r10 saved in crit_r10 and in stack frame, trashed
190	 * r11 saved in crit_r11 and in stack frame,
191	 *	now phys stack/exception frame pointer
192	 * r12 saved in stack frame, now saved SRR2
193	 * CR saved in stack frame, CR0.EQ = !SRR3.PR
194	 * LR, DEAR, ESR in stack frame
195	 * r1 saved in stack frame, now virt stack/excframe pointer
196	 * r0, r3-r8 saved in stack frame
197	 */
198
199/*
200 * Exception vectors.
201 */
202#define	START_EXCEPTION(n, label)					     \
203	. = n;								     \
204label:
205
206#define EXCEPTION(n, label, hdlr, xfer)				\
207	START_EXCEPTION(n, label);				\
208	NORMAL_EXCEPTION_PROLOG;				\
209	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
210	xfer(n, hdlr)
211
212#define CRITICAL_EXCEPTION(n, label, hdlr)			\
213	START_EXCEPTION(n, label);				\
214	CRITICAL_EXCEPTION_PROLOG;				\
215	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
216	EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
217			  NOCOPY, crit_transfer_to_handler,	\
218			  ret_from_crit_exc)
219
220#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)	\
221	li	r10,trap;					\
222	stw	r10,_TRAP(r11);					\
223	lis	r10,msr@h;					\
224	ori	r10,r10,msr@l;					\
225	copyee(r10, r9);					\
226	bl	tfer;		 				\
227	.long	hdlr;						\
228	.long	ret
229
230#define COPY_EE(d, s)		rlwimi d,s,0,16,16
231#define NOCOPY(d, s)
232
233#define EXC_XFER_STD(n, hdlr)		\
234	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
235			  ret_from_except_full)
236
237#define EXC_XFER_LITE(n, hdlr)		\
238	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
239			  ret_from_except)
240
241#define EXC_XFER_EE(n, hdlr)		\
242	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
243			  ret_from_except_full)
244
245#define EXC_XFER_EE_LITE(n, hdlr)	\
246	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
247			  ret_from_except)
248
249
250/*
251 * 0x0100 - Critical Interrupt Exception
252 */
253	CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
254
255/*
256 * 0x0200 - Machine Check Exception
257 */
258	CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
259
260/*
261 * 0x0300 - Data Storage Exception
262 * This happens for just a few reasons.  U0 set (but we don't do that),
263 * or zone protection fault (user violation, write to protected page).
264 * If this is just an update of modified status, we do that quickly
265 * and exit.  Otherwise, we call heavywight functions to do the work.
266 */
267	START_EXCEPTION(0x0300,	DataStorage)
268	mtspr	SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
269	mtspr	SPRN_SPRG_SCRATCH1, r11
270#ifdef CONFIG_403GCX
271	stw     r12, 0(r0)
272	stw     r9, 4(r0)
273	mfcr    r11
274	mfspr   r12, SPRN_PID
275	stw     r11, 8(r0)
276	stw     r12, 12(r0)
277#else
278	mtspr	SPRN_SPRG_SCRATCH3, r12
279	mtspr	SPRN_SPRG_SCRATCH4, r9
280	mfcr	r11
281	mfspr	r12, SPRN_PID
282	mtspr	SPRN_SPRG_SCRATCH6, r11
283	mtspr	SPRN_SPRG_SCRATCH5, r12
284#endif
285
286	/* First, check if it was a zone fault (which means a user
287	* tried to access a kernel or read-protected page - always
288	* a SEGV).  All other faults here must be stores, so no
289	* need to check ESR_DST as well. */
290	mfspr	r10, SPRN_ESR
291	andis.	r10, r10, ESR_DIZ@h
292	bne	2f
293
294	mfspr	r10, SPRN_DEAR		/* Get faulting address */
295
296	/* If we are faulting a kernel address, we have to use the
297	 * kernel page tables.
298	 */
299	lis	r11, PAGE_OFFSET@h
300	cmplw	r10, r11
301	blt+	3f
302	lis	r11, swapper_pg_dir@h
303	ori	r11, r11, swapper_pg_dir@l
304	li	r9, 0
305	mtspr	SPRN_PID, r9		/* TLB will have 0 TID */
306	b	4f
307
308	/* Get the PGD for the current thread.
309	 */
3103:
311	mfspr	r11,SPRN_SPRG_THREAD
312	lwz	r11,PGDIR(r11)
3134:
314	tophys(r11, r11)
315	rlwimi	r11, r10, 12, 20, 29	/* Create L1 (pgdir/pmd) address */
316	lwz	r11, 0(r11)		/* Get L1 entry */
317	rlwinm.	r12, r11, 0, 0, 19	/* Extract L2 (pte) base address */
318	beq	2f			/* Bail if no table */
319
320	rlwimi	r12, r10, 22, 20, 29	/* Compute PTE address */
321	lwz	r11, 0(r12)		/* Get Linux PTE */
322
323	andi.	r9, r11, _PAGE_RW	/* Is it writeable? */
324	beq	2f			/* Bail if not */
325
326	/* Update 'changed'.
327	*/
328	ori	r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
329	stw	r11, 0(r12)		/* Update Linux page table */
330
331	/* Most of the Linux PTE is ready to load into the TLB LO.
332	 * We set ZSEL, where only the LS-bit determines user access.
333	 * We set execute, because we don't have the granularity to
334	 * properly set this at the page level (Linux problem).
335	 * If shared is set, we cause a zero PID->TID load.
336	 * Many of these bits are software only.  Bits we don't set
337	 * here we (properly should) assume have the appropriate value.
338	 */
339	li	r12, 0x0ce2
340	andc	r11, r11, r12		/* Make sure 20, 21 are zero */
341
342	/* find the TLB index that caused the fault.  It has to be here.
343	*/
344	tlbsx	r9, 0, r10
345
346	tlbwe	r11, r9, TLB_DATA		/* Load TLB LO */
347
348	/* Done...restore registers and get out of here.
349	*/
350#ifdef CONFIG_403GCX
351	lwz     r12, 12(r0)
352	lwz     r11, 8(r0)
353	mtspr   SPRN_PID, r12
354	mtcr    r11
355	lwz     r9, 4(r0)
356	lwz     r12, 0(r0)
357#else
358	mfspr	r12, SPRN_SPRG_SCRATCH5
359	mfspr	r11, SPRN_SPRG_SCRATCH6
360	mtspr	SPRN_PID, r12
361	mtcr	r11
362	mfspr	r9, SPRN_SPRG_SCRATCH4
363	mfspr	r12, SPRN_SPRG_SCRATCH3
364#endif
365	mfspr	r11, SPRN_SPRG_SCRATCH1
366	mfspr	r10, SPRN_SPRG_SCRATCH0
367	PPC405_ERR77_SYNC
368	rfi			/* Should sync shadow TLBs */
369	b	.		/* prevent prefetch past rfi */
370
3712:
372	/* The bailout.  Restore registers to pre-exception conditions
373	 * and call the heavyweights to help us out.
374	 */
375#ifdef CONFIG_403GCX
376	lwz     r12, 12(r0)
377	lwz     r11, 8(r0)
378	mtspr   SPRN_PID, r12
379	mtcr    r11
380	lwz     r9, 4(r0)
381	lwz     r12, 0(r0)
382#else
383	mfspr	r12, SPRN_SPRG_SCRATCH5
384	mfspr	r11, SPRN_SPRG_SCRATCH6
385	mtspr	SPRN_PID, r12
386	mtcr	r11
387	mfspr	r9, SPRN_SPRG_SCRATCH4
388	mfspr	r12, SPRN_SPRG_SCRATCH3
389#endif
390	mfspr	r11, SPRN_SPRG_SCRATCH1
391	mfspr	r10, SPRN_SPRG_SCRATCH0
392	b	DataAccess
393
394/*
395 * 0x0400 - Instruction Storage Exception
396 * This is caused by a fetch from non-execute or guarded pages.
397 */
398	START_EXCEPTION(0x0400, InstructionAccess)
399	NORMAL_EXCEPTION_PROLOG
400	mr	r4,r12			/* Pass SRR0 as arg2 */
401	li	r5,0			/* Pass zero as arg3 */
402	EXC_XFER_EE_LITE(0x400, handle_page_fault)
403
404/* 0x0500 - External Interrupt Exception */
405	EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
406
407/* 0x0600 - Alignment Exception */
408	START_EXCEPTION(0x0600, Alignment)
409	NORMAL_EXCEPTION_PROLOG
410	mfspr	r4,SPRN_DEAR		/* Grab the DEAR and save it */
411	stw	r4,_DEAR(r11)
412	addi	r3,r1,STACK_FRAME_OVERHEAD
413	EXC_XFER_EE(0x600, alignment_exception)
414
415/* 0x0700 - Program Exception */
416	START_EXCEPTION(0x0700, ProgramCheck)
417	NORMAL_EXCEPTION_PROLOG
418	mfspr	r4,SPRN_ESR		/* Grab the ESR and save it */
419	stw	r4,_ESR(r11)
420	addi	r3,r1,STACK_FRAME_OVERHEAD
421	EXC_XFER_STD(0x700, program_check_exception)
422
423	EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE)
424	EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE)
425	EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE)
426	EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE)
427
428/* 0x0C00 - System Call Exception */
429	START_EXCEPTION(0x0C00,	SystemCall)
430	NORMAL_EXCEPTION_PROLOG
431	EXC_XFER_EE_LITE(0xc00, DoSyscall)
432
433	EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE)
434	EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE)
435	EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE)
436
437/* 0x1000 - Programmable Interval Timer (PIT) Exception */
438	START_EXCEPTION(0x1000, Decrementer)
439	NORMAL_EXCEPTION_PROLOG
440	lis	r0,TSR_PIS@h
441	mtspr	SPRN_TSR,r0		/* Clear the PIT exception */
442	addi	r3,r1,STACK_FRAME_OVERHEAD
443	EXC_XFER_LITE(0x1000, timer_interrupt)
444
445#if 0
446/* NOTE:
447 * FIT and WDT handlers are not implemented yet.
448 */
449
450/* 0x1010 - Fixed Interval Timer (FIT) Exception
451*/
452	STND_EXCEPTION(0x1010,	FITException,		unknown_exception)
453
454/* 0x1020 - Watchdog Timer (WDT) Exception
455*/
456#ifdef CONFIG_BOOKE_WDT
457	CRITICAL_EXCEPTION(0x1020, WDTException, WatchdogException)
458#else
459	CRITICAL_EXCEPTION(0x1020, WDTException, unknown_exception)
460#endif
461#endif
462
463/* 0x1100 - Data TLB Miss Exception
464 * As the name implies, translation is not in the MMU, so search the
465 * page tables and fix it.  The only purpose of this function is to
466 * load TLB entries from the page table if they exist.
467 */
468	START_EXCEPTION(0x1100,	DTLBMiss)
469	mtspr	SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
470	mtspr	SPRN_SPRG_SCRATCH1, r11
471#ifdef CONFIG_403GCX
472	stw     r12, 0(r0)
473	stw     r9, 4(r0)
474	mfcr    r11
475	mfspr   r12, SPRN_PID
476	stw     r11, 8(r0)
477	stw     r12, 12(r0)
478#else
479	mtspr	SPRN_SPRG_SCRATCH3, r12
480	mtspr	SPRN_SPRG_SCRATCH4, r9
481	mfcr	r11
482	mfspr	r12, SPRN_PID
483	mtspr	SPRN_SPRG_SCRATCH6, r11
484	mtspr	SPRN_SPRG_SCRATCH5, r12
485#endif
486	mfspr	r10, SPRN_DEAR		/* Get faulting address */
487
488	/* If we are faulting a kernel address, we have to use the
489	 * kernel page tables.
490	 */
491	lis	r11, PAGE_OFFSET@h
492	cmplw	r10, r11
493	blt+	3f
494	lis	r11, swapper_pg_dir@h
495	ori	r11, r11, swapper_pg_dir@l
496	li	r9, 0
497	mtspr	SPRN_PID, r9		/* TLB will have 0 TID */
498	b	4f
499
500	/* Get the PGD for the current thread.
501	 */
5023:
503	mfspr	r11,SPRN_SPRG_THREAD
504	lwz	r11,PGDIR(r11)
5054:
506	tophys(r11, r11)
507	rlwimi	r11, r10, 12, 20, 29	/* Create L1 (pgdir/pmd) address */
508	lwz	r12, 0(r11)		/* Get L1 entry */
509	andi.	r9, r12, _PMD_PRESENT	/* Check if it points to a PTE page */
510	beq	2f			/* Bail if no table */
511
512	rlwimi	r12, r10, 22, 20, 29	/* Compute PTE address */
513	lwz	r11, 0(r12)		/* Get Linux PTE */
514	andi.	r9, r11, _PAGE_PRESENT
515	beq	5f
516
517	ori	r11, r11, _PAGE_ACCESSED
518	stw	r11, 0(r12)
519
520	/* Create TLB tag.  This is the faulting address plus a static
521	 * set of bits.  These are size, valid, E, U0.
522	*/
523	li	r12, 0x00c0
524	rlwimi	r10, r12, 0, 20, 31
525
526	b	finish_tlb_load
527
5282:	/* Check for possible large-page pmd entry */
529	rlwinm.	r9, r12, 2, 22, 24
530	beq	5f
531
532	/* Create TLB tag.  This is the faulting address, plus a static
533	 * set of bits (valid, E, U0) plus the size from the PMD.
534	 */
535	ori	r9, r9, 0x40
536	rlwimi	r10, r9, 0, 20, 31
537	mr	r11, r12
538
539	b	finish_tlb_load
540
5415:
542	/* The bailout.  Restore registers to pre-exception conditions
543	 * and call the heavyweights to help us out.
544	 */
545#ifdef CONFIG_403GCX
546	lwz     r12, 12(r0)
547	lwz     r11, 8(r0)
548	mtspr   SPRN_PID, r12
549	mtcr    r11
550	lwz     r9, 4(r0)
551	lwz     r12, 0(r0)
552#else
553	mfspr	r12, SPRN_SPRG_SCRATCH5
554	mfspr	r11, SPRN_SPRG_SCRATCH6
555	mtspr	SPRN_PID, r12
556	mtcr	r11
557	mfspr	r9, SPRN_SPRG_SCRATCH4
558	mfspr	r12, SPRN_SPRG_SCRATCH3
559#endif
560	mfspr	r11, SPRN_SPRG_SCRATCH1
561	mfspr	r10, SPRN_SPRG_SCRATCH0
562	b	DataAccess
563
564/* 0x1200 - Instruction TLB Miss Exception
565 * Nearly the same as above, except we get our information from different
566 * registers and bailout to a different point.
567 */
568	START_EXCEPTION(0x1200,	ITLBMiss)
569	mtspr	SPRN_SPRG_SCRATCH0, r10	 /* Save some working registers */
570	mtspr	SPRN_SPRG_SCRATCH1, r11
571#ifdef CONFIG_403GCX
572	stw     r12, 0(r0)
573	stw     r9, 4(r0)
574	mfcr    r11
575	mfspr   r12, SPRN_PID
576	stw     r11, 8(r0)
577	stw     r12, 12(r0)
578#else
579	mtspr	SPRN_SPRG_SCRATCH3, r12
580	mtspr	SPRN_SPRG_SCRATCH4, r9
581	mfcr	r11
582	mfspr	r12, SPRN_PID
583	mtspr	SPRN_SPRG_SCRATCH6, r11
584	mtspr	SPRN_SPRG_SCRATCH5, r12
585#endif
586	mfspr	r10, SPRN_SRR0		/* Get faulting address */
587
588	/* If we are faulting a kernel address, we have to use the
589	 * kernel page tables.
590	 */
591	lis	r11, PAGE_OFFSET@h
592	cmplw	r10, r11
593	blt+	3f
594	lis	r11, swapper_pg_dir@h
595	ori	r11, r11, swapper_pg_dir@l
596	li	r9, 0
597	mtspr	SPRN_PID, r9		/* TLB will have 0 TID */
598	b	4f
599
600	/* Get the PGD for the current thread.
601	 */
6023:
603	mfspr	r11,SPRN_SPRG_THREAD
604	lwz	r11,PGDIR(r11)
6054:
606	tophys(r11, r11)
607	rlwimi	r11, r10, 12, 20, 29	/* Create L1 (pgdir/pmd) address */
608	lwz	r12, 0(r11)		/* Get L1 entry */
609	andi.	r9, r12, _PMD_PRESENT	/* Check if it points to a PTE page */
610	beq	2f			/* Bail if no table */
611
612	rlwimi	r12, r10, 22, 20, 29	/* Compute PTE address */
613	lwz	r11, 0(r12)		/* Get Linux PTE */
614	andi.	r9, r11, _PAGE_PRESENT
615	beq	5f
616
617	ori	r11, r11, _PAGE_ACCESSED
618	stw	r11, 0(r12)
619
620	/* Create TLB tag.  This is the faulting address plus a static
621	 * set of bits.  These are size, valid, E, U0.
622	*/
623	li	r12, 0x00c0
624	rlwimi	r10, r12, 0, 20, 31
625
626	b	finish_tlb_load
627
6282:	/* Check for possible large-page pmd entry */
629	rlwinm.	r9, r12, 2, 22, 24
630	beq	5f
631
632	/* Create TLB tag.  This is the faulting address, plus a static
633	 * set of bits (valid, E, U0) plus the size from the PMD.
634	 */
635	ori	r9, r9, 0x40
636	rlwimi	r10, r9, 0, 20, 31
637	mr	r11, r12
638
639	b	finish_tlb_load
640
6415:
642	/* The bailout.  Restore registers to pre-exception conditions
643	 * and call the heavyweights to help us out.
644	 */
645#ifdef CONFIG_403GCX
646	lwz     r12, 12(r0)
647	lwz     r11, 8(r0)
648	mtspr   SPRN_PID, r12
649	mtcr    r11
650	lwz     r9, 4(r0)
651	lwz     r12, 0(r0)
652#else
653	mfspr	r12, SPRN_SPRG_SCRATCH5
654	mfspr	r11, SPRN_SPRG_SCRATCH6
655	mtspr	SPRN_PID, r12
656	mtcr	r11
657	mfspr	r9, SPRN_SPRG_SCRATCH4
658	mfspr	r12, SPRN_SPRG_SCRATCH3
659#endif
660	mfspr	r11, SPRN_SPRG_SCRATCH1
661	mfspr	r10, SPRN_SPRG_SCRATCH0
662	b	InstructionAccess
663
664	EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE)
665	EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE)
666	EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
667	EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
668#ifdef CONFIG_IBM405_ERR51
669	/* 405GP errata 51 */
670	START_EXCEPTION(0x1700, Trap_17)
671	b DTLBMiss
672#else
673	EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
674#endif
675	EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
676	EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
677	EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE)
678	EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE)
679	EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE)
680	EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE)
681	EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE)
682	EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE)
683
684/* Check for a single step debug exception while in an exception
685 * handler before state has been saved.  This is to catch the case
686 * where an instruction that we are trying to single step causes
687 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
688 * the exception handler generates a single step debug exception.
689 *
690 * If we get a debug trap on the first instruction of an exception handler,
691 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
692 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
693 * The exception handler was handling a non-critical interrupt, so it will
694 * save (and later restore) the MSR via SPRN_SRR1, which will still have
695 * the MSR_DE bit set.
696 */
697	/* 0x2000 - Debug Exception */
698	START_EXCEPTION(0x2000, DebugTrap)
699	CRITICAL_EXCEPTION_PROLOG
700
701	/*
702	 * If this is a single step or branch-taken exception in an
703	 * exception entry sequence, it was probably meant to apply to
704	 * the code where the exception occurred (since exception entry
705	 * doesn't turn off DE automatically).  We simulate the effect
706	 * of turning off DE on entry to an exception handler by turning
707	 * off DE in the SRR3 value and clearing the debug status.
708	 */
709	mfspr	r10,SPRN_DBSR		/* check single-step/branch taken */
710	andis.	r10,r10,DBSR_IC@h
711	beq+	2f
712
713	andi.	r10,r9,MSR_IR|MSR_PR	/* check supervisor + MMU off */
714	beq	1f			/* branch and fix it up */
715
716	mfspr   r10,SPRN_SRR2		/* Faulting instruction address */
717	cmplwi  r10,0x2100
718	bgt+    2f			/* address above exception vectors */
719
720	/* here it looks like we got an inappropriate debug exception. */
7211:	rlwinm	r9,r9,0,~MSR_DE		/* clear DE in the SRR3 value */
722	lis	r10,DBSR_IC@h		/* clear the IC event */
723	mtspr	SPRN_DBSR,r10
724	/* restore state and get out */
725	lwz	r10,_CCR(r11)
726	lwz	r0,GPR0(r11)
727	lwz	r1,GPR1(r11)
728	mtcrf	0x80,r10
729	mtspr	SPRN_SRR2,r12
730	mtspr	SPRN_SRR3,r9
731	lwz	r9,GPR9(r11)
732	lwz	r12,GPR12(r11)
733	lwz	r10,crit_r10@l(0)
734	lwz	r11,crit_r11@l(0)
735	PPC405_ERR77_SYNC
736	rfci
737	b	.
738
739	/* continue normal handling for a critical exception... */
7402:	mfspr	r4,SPRN_DBSR
741	addi	r3,r1,STACK_FRAME_OVERHEAD
742	EXC_XFER_TEMPLATE(DebugException, 0x2002, \
743		(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
744		NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
745
746/*
747 * The other Data TLB exceptions bail out to this point
748 * if they can't resolve the lightweight TLB fault.
749 */
750DataAccess:
751	NORMAL_EXCEPTION_PROLOG
752	mfspr	r5,SPRN_ESR		/* Grab the ESR, save it, pass arg3 */
753	stw	r5,_ESR(r11)
754	mfspr	r4,SPRN_DEAR		/* Grab the DEAR, save it, pass arg2 */
755	EXC_XFER_EE_LITE(0x300, handle_page_fault)
756
757/* Other PowerPC processors, namely those derived from the 6xx-series
758 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
759 * However, for the 4xx-series processors these are neither defined nor
760 * reserved.
761 */
762
763	/* Damn, I came up one instruction too many to fit into the
764	 * exception space :-).  Both the instruction and data TLB
765	 * miss get to this point to load the TLB.
766	 * 	r10 - TLB_TAG value
767	 * 	r11 - Linux PTE
768	 *	r12, r9 - avilable to use
769	 *	PID - loaded with proper value when we get here
770	 *	Upon exit, we reload everything and RFI.
771	 * Actually, it will fit now, but oh well.....a common place
772	 * to load the TLB.
773	 */
774tlb_4xx_index:
775	.long	0
776finish_tlb_load:
777	/* load the next available TLB index.
778	*/
779	lwz	r9, tlb_4xx_index@l(0)
780	addi	r9, r9, 1
781	andi.	r9, r9, (PPC40X_TLB_SIZE-1)
782	stw	r9, tlb_4xx_index@l(0)
783
7846:
785	/*
786	 * Clear out the software-only bits in the PTE to generate the
787	 * TLB_DATA value.  These are the bottom 2 bits of the RPM, the
788	 * top 3 bits of the zone field, and M.
789	 */
790	li	r12, 0x0ce2
791	andc	r11, r11, r12
792
793	tlbwe	r11, r9, TLB_DATA		/* Load TLB LO */
794	tlbwe	r10, r9, TLB_TAG		/* Load TLB HI */
795
796	/* Done...restore registers and get out of here.
797	*/
798#ifdef CONFIG_403GCX
799	lwz     r12, 12(r0)
800	lwz     r11, 8(r0)
801	mtspr   SPRN_PID, r12
802	mtcr    r11
803	lwz     r9, 4(r0)
804	lwz     r12, 0(r0)
805#else
806	mfspr	r12, SPRN_SPRG_SCRATCH5
807	mfspr	r11, SPRN_SPRG_SCRATCH6
808	mtspr	SPRN_PID, r12
809	mtcr	r11
810	mfspr	r9, SPRN_SPRG_SCRATCH4
811	mfspr	r12, SPRN_SPRG_SCRATCH3
812#endif
813	mfspr	r11, SPRN_SPRG_SCRATCH1
814	mfspr	r10, SPRN_SPRG_SCRATCH0
815	PPC405_ERR77_SYNC
816	rfi			/* Should sync shadow TLBs */
817	b	.		/* prevent prefetch past rfi */
818
819/* extern void giveup_fpu(struct task_struct *prev)
820 *
821 * The PowerPC 4xx family of processors do not have an FPU, so this just
822 * returns.
823 */
824_ENTRY(giveup_fpu)
825	blr
826
827/* This is where the main kernel code starts.
828 */
829start_here:
830
831	/* ptr to current */
832	lis	r2,init_task@h
833	ori	r2,r2,init_task@l
834
835	/* ptr to phys current thread */
836	tophys(r4,r2)
837	addi	r4,r4,THREAD	/* init task's THREAD */
838	mtspr	SPRN_SPRG_THREAD,r4
839
840	/* stack */
841	lis	r1,init_thread_union@ha
842	addi	r1,r1,init_thread_union@l
843	li	r0,0
844	stwu	r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
845
846	bl	early_init	/* We have to do this with MMU on */
847
848/*
849 * Decide what sort of machine this is and initialize the MMU.
850 */
851	mr	r3,r31
852	mr	r4,r30
853	mr	r5,r29
854	mr	r6,r28
855	mr	r7,r27
856	bl	machine_init
857	bl	MMU_init
858
859/* Go back to running unmapped so we can load up new values
860 * and change to using our exception vectors.
861 * On the 4xx, all we have to do is invalidate the TLB to clear
862 * the old 16M byte TLB mappings.
863 */
864	lis	r4,2f@h
865	ori	r4,r4,2f@l
866	tophys(r4,r4)
867	lis	r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
868	ori	r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
869	mtspr	SPRN_SRR0,r4
870	mtspr	SPRN_SRR1,r3
871	rfi
872	b	.		/* prevent prefetch past rfi */
873
874/* Load up the kernel context */
8752:
876	sync			/* Flush to memory before changing TLB */
877	tlbia
878	isync			/* Flush shadow TLBs */
879
880	/* set up the PTE pointers for the Abatron bdiGDB.
881	*/
882	lis	r6, swapper_pg_dir@h
883	ori	r6, r6, swapper_pg_dir@l
884	lis	r5, abatron_pteptrs@h
885	ori	r5, r5, abatron_pteptrs@l
886	stw	r5, 0xf0(r0)	/* Must match your Abatron config file */
887	tophys(r5,r5)
888	stw	r6, 0(r5)
889
890/* Now turn on the MMU for real! */
891	lis	r4,MSR_KERNEL@h
892	ori	r4,r4,MSR_KERNEL@l
893	lis	r3,start_kernel@h
894	ori	r3,r3,start_kernel@l
895	mtspr	SPRN_SRR0,r3
896	mtspr	SPRN_SRR1,r4
897	rfi			/* enable MMU and jump to start_kernel */
898	b	.		/* prevent prefetch past rfi */
899
900/* Set up the initial MMU state so we can do the first level of
901 * kernel initialization.  This maps the first 16 MBytes of memory 1:1
902 * virtual to physical and more importantly sets the cache mode.
903 */
904initial_mmu:
905	tlbia			/* Invalidate all TLB entries */
906	isync
907
908	/* We should still be executing code at physical address 0x0000xxxx
909	 * at this point. However, start_here is at virtual address
910	 * 0xC000xxxx. So, set up a TLB mapping to cover this once
911	 * translation is enabled.
912	 */
913
914	lis	r3,KERNELBASE@h		/* Load the kernel virtual address */
915	ori	r3,r3,KERNELBASE@l
916	tophys(r4,r3)			/* Load the kernel physical address */
917
918	iccci	r0,r3			/* Invalidate the i-cache before use */
919
920	/* Load the kernel PID.
921	*/
922	li	r0,0
923	mtspr	SPRN_PID,r0
924	sync
925
926	/* Configure and load two entries into TLB slots 62 and 63.
927	 * In case we are pinning TLBs, these are reserved in by the
928	 * other TLB functions.  If not reserving, then it doesn't
929	 * matter where they are loaded.
930	 */
931	clrrwi	r4,r4,10		/* Mask off the real page number */
932	ori	r4,r4,(TLB_WR | TLB_EX)	/* Set the write and execute bits */
933
934	clrrwi	r3,r3,10		/* Mask off the effective page number */
935	ori	r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
936
937        li      r0,63                    /* TLB slot 63 */
938
939	tlbwe	r4,r0,TLB_DATA		/* Load the data portion of the entry */
940	tlbwe	r3,r0,TLB_TAG		/* Load the tag portion of the entry */
941
942#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE)
943
944	/* Load a TLB entry for the UART, so that ppc4xx_progress() can use
945	 * the UARTs nice and early.  We use a 4k real==virtual mapping. */
946
947	lis	r3,SERIAL_DEBUG_IO_BASE@h
948	ori	r3,r3,SERIAL_DEBUG_IO_BASE@l
949	mr	r4,r3
950	clrrwi	r4,r4,12
951	ori	r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
952
953	clrrwi	r3,r3,12
954	ori	r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
955
956	li	r0,0			/* TLB slot 0 */
957	tlbwe	r4,r0,TLB_DATA
958	tlbwe	r3,r0,TLB_TAG
959#endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */
960
961	isync
962
963	/* Establish the exception vector base
964	*/
965	lis	r4,KERNELBASE@h		/* EVPR only uses the high 16-bits */
966	tophys(r0,r4)			/* Use the physical address */
967	mtspr	SPRN_EVPR,r0
968
969	blr
970
971_GLOBAL(abort)
972        mfspr   r13,SPRN_DBCR0
973        oris    r13,r13,DBCR0_RST_SYSTEM@h
974        mtspr   SPRN_DBCR0,r13
975
976_GLOBAL(set_context)
977
978#ifdef CONFIG_BDI_SWITCH
979	/* Context switch the PTE pointer for the Abatron BDI2000.
980	 * The PGDIR is the second parameter.
981	 */
982	lis	r5, KERNELBASE@h
983	lwz	r5, 0xf0(r5)
984	stw	r4, 0x4(r5)
985#endif
986	sync
987	mtspr	SPRN_PID,r3
988	isync				/* Need an isync to flush shadow */
989					/* TLBs after changing PID */
990	blr
991
992/* We put a few things here that have to be page-aligned. This stuff
993 * goes at the beginning of the data segment, which is page-aligned.
994 */
995	.data
996	.align	12
997	.globl	sdata
998sdata:
999	.globl	empty_zero_page
1000empty_zero_page:
1001	.space	4096
1002	.globl	swapper_pg_dir
1003swapper_pg_dir:
1004	.space	PGD_TABLE_SIZE
1005
1006/* Room for two PTE pointers, usually the kernel and current user pointers
1007 * to their respective root page table.
1008 */
1009abatron_pteptrs:
1010	.space	8
1011