1/* 2 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 3 * Initial PowerPC version. 4 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 5 * Rewritten for PReP 6 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 7 * Low-level exception handers, MMU support, and rewrite. 8 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 9 * PowerPC 8xx modifications. 10 * Copyright (c) 1998-1999 TiVo, Inc. 11 * PowerPC 403GCX modifications. 12 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 13 * PowerPC 403GCX/405GP modifications. 14 * Copyright 2000 MontaVista Software Inc. 15 * PPC405 modifications 16 * PowerPC 403GCX/405GP modifications. 17 * Author: MontaVista Software, Inc. 18 * frank_rowand@mvista.com or source@mvista.com 19 * debbie_chu@mvista.com 20 * 21 * 22 * Module name: head_4xx.S 23 * 24 * Description: 25 * Kernel execution entry point code. 26 * 27 * This program is free software; you can redistribute it and/or 28 * modify it under the terms of the GNU General Public License 29 * as published by the Free Software Foundation; either version 30 * 2 of the License, or (at your option) any later version. 31 * 32 */ 33 34#include <linux/init.h> 35#include <asm/processor.h> 36#include <asm/page.h> 37#include <asm/mmu.h> 38#include <asm/pgtable.h> 39#include <asm/cputable.h> 40#include <asm/thread_info.h> 41#include <asm/ppc_asm.h> 42#include <asm/asm-offsets.h> 43#include <asm/ptrace.h> 44#include <asm/export.h> 45#include <asm/asm-405.h> 46 47/* As with the other PowerPC ports, it is expected that when code 48 * execution begins here, the following registers contain valid, yet 49 * optional, information: 50 * 51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 52 * r4 - Starting address of the init RAM disk 53 * r5 - Ending address of the init RAM disk 54 * r6 - Start of kernel command line string (e.g. "mem=96m") 55 * r7 - End of kernel command line string 56 * 57 * This is all going to change RSN when we add bi_recs....... -- Dan 58 */ 59 __HEAD 60_ENTRY(_stext); 61_ENTRY(_start); 62 63 mr r31,r3 /* save device tree ptr */ 64 65 /* We have to turn on the MMU right away so we get cache modes 66 * set correctly. 67 */ 68 bl initial_mmu 69 70/* We now have the lower 16 Meg mapped into TLB entries, and the caches 71 * ready to work. 72 */ 73turn_on_mmu: 74 lis r0,MSR_KERNEL@h 75 ori r0,r0,MSR_KERNEL@l 76 mtspr SPRN_SRR1,r0 77 lis r0,start_here@h 78 ori r0,r0,start_here@l 79 mtspr SPRN_SRR0,r0 80 SYNC 81 rfi /* enables MMU */ 82 b . /* prevent prefetch past rfi */ 83 84/* 85 * This area is used for temporarily saving registers during the 86 * critical exception prolog. 87 */ 88 . = 0xc0 89crit_save: 90_ENTRY(crit_r10) 91 .space 4 92_ENTRY(crit_r11) 93 .space 4 94_ENTRY(crit_srr0) 95 .space 4 96_ENTRY(crit_srr1) 97 .space 4 98_ENTRY(saved_ksp_limit) 99 .space 4 100 101/* 102 * Exception vector entry code. This code runs with address translation 103 * turned off (i.e. using physical addresses). We assume SPRG_THREAD has 104 * the physical address of the current task thread_struct. 105 * Note that we have to have decremented r1 before we write to any fields 106 * of the exception frame, since a critical interrupt could occur at any 107 * time, and it will write to the area immediately below the current r1. 108 */ 109#define NORMAL_EXCEPTION_PROLOG \ 110 mtspr SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\ 111 mtspr SPRN_SPRG_SCRATCH1,r11; \ 112 mtspr SPRN_SPRG_SCRATCH2,r1; \ 113 mfcr r10; /* save CR in r10 for now */\ 114 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ 115 andi. r11,r11,MSR_PR; \ 116 beq 1f; \ 117 mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 118 lwz r1,TASK_STACK-THREAD(r1); /* this thread's kernel stack */\ 119 addi r1,r1,THREAD_SIZE; \ 1201: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ 121 tophys(r11,r1); \ 122 stw r10,_CCR(r11); /* save various registers */\ 123 stw r12,GPR12(r11); \ 124 stw r9,GPR9(r11); \ 125 mfspr r10,SPRN_SPRG_SCRATCH0; \ 126 stw r10,GPR10(r11); \ 127 mfspr r12,SPRN_SPRG_SCRATCH1; \ 128 stw r12,GPR11(r11); \ 129 mflr r10; \ 130 stw r10,_LINK(r11); \ 131 mfspr r10,SPRN_SPRG_SCRATCH2; \ 132 mfspr r12,SPRN_SRR0; \ 133 stw r10,GPR1(r11); \ 134 mfspr r9,SPRN_SRR1; \ 135 stw r10,0(r11); \ 136 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 137 stw r0,GPR0(r11); \ 138 SAVE_4GPRS(3, r11); \ 139 SAVE_2GPRS(7, r11) 140 141/* 142 * Exception prolog for critical exceptions. This is a little different 143 * from the normal exception prolog above since a critical exception 144 * can potentially occur at any point during normal exception processing. 145 * Thus we cannot use the same SPRG registers as the normal prolog above. 146 * Instead we use a couple of words of memory at low physical addresses. 147 * This is OK since we don't support SMP on these processors. 148 */ 149#define CRITICAL_EXCEPTION_PROLOG \ 150 stw r10,crit_r10@l(0); /* save two registers to work with */\ 151 stw r11,crit_r11@l(0); \ 152 mfcr r10; /* save CR in r10 for now */\ 153 mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ 154 andi. r11,r11,MSR_PR; \ 155 lis r11,critirq_ctx@ha; \ 156 tophys(r11,r11); \ 157 lwz r11,critirq_ctx@l(r11); \ 158 beq 1f; \ 159 /* COMING FROM USER MODE */ \ 160 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 161 lwz r11,TASK_STACK-THREAD(r11); /* this thread's kernel stack */\ 1621: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\ 163 tophys(r11,r11); \ 164 stw r10,_CCR(r11); /* save various registers */\ 165 stw r12,GPR12(r11); \ 166 stw r9,GPR9(r11); \ 167 mflr r10; \ 168 stw r10,_LINK(r11); \ 169 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 170 stw r12,_DEAR(r11); /* since they may have had stuff */\ 171 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 172 stw r9,_ESR(r11); /* exception was taken */\ 173 mfspr r12,SPRN_SRR2; \ 174 stw r1,GPR1(r11); \ 175 mfspr r9,SPRN_SRR3; \ 176 stw r1,0(r11); \ 177 tovirt(r1,r11); \ 178 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 179 stw r0,GPR0(r11); \ 180 SAVE_4GPRS(3, r11); \ 181 SAVE_2GPRS(7, r11) 182 183 /* 184 * State at this point: 185 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE 186 * r10 saved in crit_r10 and in stack frame, trashed 187 * r11 saved in crit_r11 and in stack frame, 188 * now phys stack/exception frame pointer 189 * r12 saved in stack frame, now saved SRR2 190 * CR saved in stack frame, CR0.EQ = !SRR3.PR 191 * LR, DEAR, ESR in stack frame 192 * r1 saved in stack frame, now virt stack/excframe pointer 193 * r0, r3-r8 saved in stack frame 194 */ 195 196/* 197 * Exception vectors. 198 */ 199#define START_EXCEPTION(n, label) \ 200 . = n; \ 201label: 202 203#define EXCEPTION(n, label, hdlr, xfer) \ 204 START_EXCEPTION(n, label); \ 205 NORMAL_EXCEPTION_PROLOG; \ 206 addi r3,r1,STACK_FRAME_OVERHEAD; \ 207 xfer(n, hdlr) 208 209#define CRITICAL_EXCEPTION(n, label, hdlr) \ 210 START_EXCEPTION(n, label); \ 211 CRITICAL_EXCEPTION_PROLOG; \ 212 addi r3,r1,STACK_FRAME_OVERHEAD; \ 213 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 214 NOCOPY, crit_transfer_to_handler, \ 215 ret_from_crit_exc) 216 217#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ 218 li r10,trap; \ 219 stw r10,_TRAP(r11); \ 220 lis r10,msr@h; \ 221 ori r10,r10,msr@l; \ 222 copyee(r10, r9); \ 223 bl tfer; \ 224 .long hdlr; \ 225 .long ret 226 227#define COPY_EE(d, s) rlwimi d,s,0,16,16 228#define NOCOPY(d, s) 229 230#define EXC_XFER_STD(n, hdlr) \ 231 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ 232 ret_from_except_full) 233 234#define EXC_XFER_LITE(n, hdlr) \ 235 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ 236 ret_from_except) 237 238#define EXC_XFER_EE(n, hdlr) \ 239 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ 240 ret_from_except_full) 241 242#define EXC_XFER_EE_LITE(n, hdlr) \ 243 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ 244 ret_from_except) 245 246 247/* 248 * 0x0100 - Critical Interrupt Exception 249 */ 250 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) 251 252/* 253 * 0x0200 - Machine Check Exception 254 */ 255 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 256 257/* 258 * 0x0300 - Data Storage Exception 259 * This happens for just a few reasons. U0 set (but we don't do that), 260 * or zone protection fault (user violation, write to protected page). 261 * If this is just an update of modified status, we do that quickly 262 * and exit. Otherwise, we call heavywight functions to do the work. 263 */ 264 START_EXCEPTION(0x0300, DataStorage) 265 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ 266 mtspr SPRN_SPRG_SCRATCH1, r11 267#ifdef CONFIG_403GCX 268 stw r12, 0(r0) 269 stw r9, 4(r0) 270 mfcr r11 271 mfspr r12, SPRN_PID 272 stw r11, 8(r0) 273 stw r12, 12(r0) 274#else 275 mtspr SPRN_SPRG_SCRATCH3, r12 276 mtspr SPRN_SPRG_SCRATCH4, r9 277 mfcr r11 278 mfspr r12, SPRN_PID 279 mtspr SPRN_SPRG_SCRATCH6, r11 280 mtspr SPRN_SPRG_SCRATCH5, r12 281#endif 282 283 /* First, check if it was a zone fault (which means a user 284 * tried to access a kernel or read-protected page - always 285 * a SEGV). All other faults here must be stores, so no 286 * need to check ESR_DST as well. */ 287 mfspr r10, SPRN_ESR 288 andis. r10, r10, ESR_DIZ@h 289 bne 2f 290 291 mfspr r10, SPRN_DEAR /* Get faulting address */ 292 293 /* If we are faulting a kernel address, we have to use the 294 * kernel page tables. 295 */ 296 lis r11, PAGE_OFFSET@h 297 cmplw r10, r11 298 blt+ 3f 299 lis r11, swapper_pg_dir@h 300 ori r11, r11, swapper_pg_dir@l 301 li r9, 0 302 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 303 b 4f 304 305 /* Get the PGD for the current thread. 306 */ 3073: 308 mfspr r11,SPRN_SPRG_THREAD 309 lwz r11,PGDIR(r11) 3104: 311 tophys(r11, r11) 312 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 313 lwz r11, 0(r11) /* Get L1 entry */ 314 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */ 315 beq 2f /* Bail if no table */ 316 317 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ 318 lwz r11, 0(r12) /* Get Linux PTE */ 319 320 andi. r9, r11, _PAGE_RW /* Is it writeable? */ 321 beq 2f /* Bail if not */ 322 323 /* Update 'changed'. 324 */ 325 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE 326 stw r11, 0(r12) /* Update Linux page table */ 327 328 /* Most of the Linux PTE is ready to load into the TLB LO. 329 * We set ZSEL, where only the LS-bit determines user access. 330 * We set execute, because we don't have the granularity to 331 * properly set this at the page level (Linux problem). 332 * If shared is set, we cause a zero PID->TID load. 333 * Many of these bits are software only. Bits we don't set 334 * here we (properly should) assume have the appropriate value. 335 */ 336 li r12, 0x0ce2 337 andc r11, r11, r12 /* Make sure 20, 21 are zero */ 338 339 /* find the TLB index that caused the fault. It has to be here. 340 */ 341 tlbsx r9, 0, r10 342 343 tlbwe r11, r9, TLB_DATA /* Load TLB LO */ 344 345 /* Done...restore registers and get out of here. 346 */ 347#ifdef CONFIG_403GCX 348 lwz r12, 12(r0) 349 lwz r11, 8(r0) 350 mtspr SPRN_PID, r12 351 mtcr r11 352 lwz r9, 4(r0) 353 lwz r12, 0(r0) 354#else 355 mfspr r12, SPRN_SPRG_SCRATCH5 356 mfspr r11, SPRN_SPRG_SCRATCH6 357 mtspr SPRN_PID, r12 358 mtcr r11 359 mfspr r9, SPRN_SPRG_SCRATCH4 360 mfspr r12, SPRN_SPRG_SCRATCH3 361#endif 362 mfspr r11, SPRN_SPRG_SCRATCH1 363 mfspr r10, SPRN_SPRG_SCRATCH0 364 PPC405_ERR77_SYNC 365 rfi /* Should sync shadow TLBs */ 366 b . /* prevent prefetch past rfi */ 367 3682: 369 /* The bailout. Restore registers to pre-exception conditions 370 * and call the heavyweights to help us out. 371 */ 372#ifdef CONFIG_403GCX 373 lwz r12, 12(r0) 374 lwz r11, 8(r0) 375 mtspr SPRN_PID, r12 376 mtcr r11 377 lwz r9, 4(r0) 378 lwz r12, 0(r0) 379#else 380 mfspr r12, SPRN_SPRG_SCRATCH5 381 mfspr r11, SPRN_SPRG_SCRATCH6 382 mtspr SPRN_PID, r12 383 mtcr r11 384 mfspr r9, SPRN_SPRG_SCRATCH4 385 mfspr r12, SPRN_SPRG_SCRATCH3 386#endif 387 mfspr r11, SPRN_SPRG_SCRATCH1 388 mfspr r10, SPRN_SPRG_SCRATCH0 389 b DataAccess 390 391/* 392 * 0x0400 - Instruction Storage Exception 393 * This is caused by a fetch from non-execute or guarded pages. 394 */ 395 START_EXCEPTION(0x0400, InstructionAccess) 396 NORMAL_EXCEPTION_PROLOG 397 mr r4,r12 /* Pass SRR0 as arg2 */ 398 li r5,0 /* Pass zero as arg3 */ 399 EXC_XFER_LITE(0x400, handle_page_fault) 400 401/* 0x0500 - External Interrupt Exception */ 402 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 403 404/* 0x0600 - Alignment Exception */ 405 START_EXCEPTION(0x0600, Alignment) 406 NORMAL_EXCEPTION_PROLOG 407 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ 408 stw r4,_DEAR(r11) 409 addi r3,r1,STACK_FRAME_OVERHEAD 410 EXC_XFER_EE(0x600, alignment_exception) 411 412/* 0x0700 - Program Exception */ 413 START_EXCEPTION(0x0700, ProgramCheck) 414 NORMAL_EXCEPTION_PROLOG 415 mfspr r4,SPRN_ESR /* Grab the ESR and save it */ 416 stw r4,_ESR(r11) 417 addi r3,r1,STACK_FRAME_OVERHEAD 418 EXC_XFER_STD(0x700, program_check_exception) 419 420 EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) 421 EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) 422 EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) 423 EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) 424 425/* 0x0C00 - System Call Exception */ 426 START_EXCEPTION(0x0C00, SystemCall) 427 NORMAL_EXCEPTION_PROLOG 428 EXC_XFER_EE_LITE(0xc00, DoSyscall) 429 430 EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) 431 EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) 432 EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) 433 434/* 0x1000 - Programmable Interval Timer (PIT) Exception */ 435 . = 0x1000 436 b Decrementer 437 438/* 0x1010 - Fixed Interval Timer (FIT) Exception 439*/ 440 . = 0x1010 441 b FITException 442 443/* 0x1020 - Watchdog Timer (WDT) Exception 444*/ 445 . = 0x1020 446 b WDTException 447 448/* 0x1100 - Data TLB Miss Exception 449 * As the name implies, translation is not in the MMU, so search the 450 * page tables and fix it. The only purpose of this function is to 451 * load TLB entries from the page table if they exist. 452 */ 453 START_EXCEPTION(0x1100, DTLBMiss) 454 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ 455 mtspr SPRN_SPRG_SCRATCH1, r11 456#ifdef CONFIG_403GCX 457 stw r12, 0(r0) 458 stw r9, 4(r0) 459 mfcr r11 460 mfspr r12, SPRN_PID 461 stw r11, 8(r0) 462 stw r12, 12(r0) 463#else 464 mtspr SPRN_SPRG_SCRATCH3, r12 465 mtspr SPRN_SPRG_SCRATCH4, r9 466 mfcr r11 467 mfspr r12, SPRN_PID 468 mtspr SPRN_SPRG_SCRATCH6, r11 469 mtspr SPRN_SPRG_SCRATCH5, r12 470#endif 471 mfspr r10, SPRN_DEAR /* Get faulting address */ 472 473 /* If we are faulting a kernel address, we have to use the 474 * kernel page tables. 475 */ 476 lis r11, PAGE_OFFSET@h 477 cmplw r10, r11 478 blt+ 3f 479 lis r11, swapper_pg_dir@h 480 ori r11, r11, swapper_pg_dir@l 481 li r9, 0 482 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 483 b 4f 484 485 /* Get the PGD for the current thread. 486 */ 4873: 488 mfspr r11,SPRN_SPRG_THREAD 489 lwz r11,PGDIR(r11) 4904: 491 tophys(r11, r11) 492 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 493 lwz r12, 0(r11) /* Get L1 entry */ 494 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ 495 beq 2f /* Bail if no table */ 496 497 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ 498 lwz r11, 0(r12) /* Get Linux PTE */ 499 andi. r9, r11, _PAGE_PRESENT 500 beq 5f 501 502 ori r11, r11, _PAGE_ACCESSED 503 stw r11, 0(r12) 504 505 /* Create TLB tag. This is the faulting address plus a static 506 * set of bits. These are size, valid, E, U0. 507 */ 508 li r12, 0x00c0 509 rlwimi r10, r12, 0, 20, 31 510 511 b finish_tlb_load 512 5132: /* Check for possible large-page pmd entry */ 514 rlwinm. r9, r12, 2, 22, 24 515 beq 5f 516 517 /* Create TLB tag. This is the faulting address, plus a static 518 * set of bits (valid, E, U0) plus the size from the PMD. 519 */ 520 ori r9, r9, 0x40 521 rlwimi r10, r9, 0, 20, 31 522 mr r11, r12 523 524 b finish_tlb_load 525 5265: 527 /* The bailout. Restore registers to pre-exception conditions 528 * and call the heavyweights to help us out. 529 */ 530#ifdef CONFIG_403GCX 531 lwz r12, 12(r0) 532 lwz r11, 8(r0) 533 mtspr SPRN_PID, r12 534 mtcr r11 535 lwz r9, 4(r0) 536 lwz r12, 0(r0) 537#else 538 mfspr r12, SPRN_SPRG_SCRATCH5 539 mfspr r11, SPRN_SPRG_SCRATCH6 540 mtspr SPRN_PID, r12 541 mtcr r11 542 mfspr r9, SPRN_SPRG_SCRATCH4 543 mfspr r12, SPRN_SPRG_SCRATCH3 544#endif 545 mfspr r11, SPRN_SPRG_SCRATCH1 546 mfspr r10, SPRN_SPRG_SCRATCH0 547 b DataAccess 548 549/* 0x1200 - Instruction TLB Miss Exception 550 * Nearly the same as above, except we get our information from different 551 * registers and bailout to a different point. 552 */ 553 START_EXCEPTION(0x1200, ITLBMiss) 554 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ 555 mtspr SPRN_SPRG_SCRATCH1, r11 556#ifdef CONFIG_403GCX 557 stw r12, 0(r0) 558 stw r9, 4(r0) 559 mfcr r11 560 mfspr r12, SPRN_PID 561 stw r11, 8(r0) 562 stw r12, 12(r0) 563#else 564 mtspr SPRN_SPRG_SCRATCH3, r12 565 mtspr SPRN_SPRG_SCRATCH4, r9 566 mfcr r11 567 mfspr r12, SPRN_PID 568 mtspr SPRN_SPRG_SCRATCH6, r11 569 mtspr SPRN_SPRG_SCRATCH5, r12 570#endif 571 mfspr r10, SPRN_SRR0 /* Get faulting address */ 572 573 /* If we are faulting a kernel address, we have to use the 574 * kernel page tables. 575 */ 576 lis r11, PAGE_OFFSET@h 577 cmplw r10, r11 578 blt+ 3f 579 lis r11, swapper_pg_dir@h 580 ori r11, r11, swapper_pg_dir@l 581 li r9, 0 582 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 583 b 4f 584 585 /* Get the PGD for the current thread. 586 */ 5873: 588 mfspr r11,SPRN_SPRG_THREAD 589 lwz r11,PGDIR(r11) 5904: 591 tophys(r11, r11) 592 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 593 lwz r12, 0(r11) /* Get L1 entry */ 594 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ 595 beq 2f /* Bail if no table */ 596 597 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ 598 lwz r11, 0(r12) /* Get Linux PTE */ 599 andi. r9, r11, _PAGE_PRESENT 600 beq 5f 601 602 ori r11, r11, _PAGE_ACCESSED 603 stw r11, 0(r12) 604 605 /* Create TLB tag. This is the faulting address plus a static 606 * set of bits. These are size, valid, E, U0. 607 */ 608 li r12, 0x00c0 609 rlwimi r10, r12, 0, 20, 31 610 611 b finish_tlb_load 612 6132: /* Check for possible large-page pmd entry */ 614 rlwinm. r9, r12, 2, 22, 24 615 beq 5f 616 617 /* Create TLB tag. This is the faulting address, plus a static 618 * set of bits (valid, E, U0) plus the size from the PMD. 619 */ 620 ori r9, r9, 0x40 621 rlwimi r10, r9, 0, 20, 31 622 mr r11, r12 623 624 b finish_tlb_load 625 6265: 627 /* The bailout. Restore registers to pre-exception conditions 628 * and call the heavyweights to help us out. 629 */ 630#ifdef CONFIG_403GCX 631 lwz r12, 12(r0) 632 lwz r11, 8(r0) 633 mtspr SPRN_PID, r12 634 mtcr r11 635 lwz r9, 4(r0) 636 lwz r12, 0(r0) 637#else 638 mfspr r12, SPRN_SPRG_SCRATCH5 639 mfspr r11, SPRN_SPRG_SCRATCH6 640 mtspr SPRN_PID, r12 641 mtcr r11 642 mfspr r9, SPRN_SPRG_SCRATCH4 643 mfspr r12, SPRN_SPRG_SCRATCH3 644#endif 645 mfspr r11, SPRN_SPRG_SCRATCH1 646 mfspr r10, SPRN_SPRG_SCRATCH0 647 b InstructionAccess 648 649 EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE) 650 EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE) 651 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 652 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 653#ifdef CONFIG_IBM405_ERR51 654 /* 405GP errata 51 */ 655 START_EXCEPTION(0x1700, Trap_17) 656 b DTLBMiss 657#else 658 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 659#endif 660 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 661 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 662 EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE) 663 EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE) 664 EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE) 665 EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE) 666 EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE) 667 EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE) 668 669/* Check for a single step debug exception while in an exception 670 * handler before state has been saved. This is to catch the case 671 * where an instruction that we are trying to single step causes 672 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 673 * the exception handler generates a single step debug exception. 674 * 675 * If we get a debug trap on the first instruction of an exception handler, 676 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 677 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 678 * The exception handler was handling a non-critical interrupt, so it will 679 * save (and later restore) the MSR via SPRN_SRR1, which will still have 680 * the MSR_DE bit set. 681 */ 682 /* 0x2000 - Debug Exception */ 683 START_EXCEPTION(0x2000, DebugTrap) 684 CRITICAL_EXCEPTION_PROLOG 685 686 /* 687 * If this is a single step or branch-taken exception in an 688 * exception entry sequence, it was probably meant to apply to 689 * the code where the exception occurred (since exception entry 690 * doesn't turn off DE automatically). We simulate the effect 691 * of turning off DE on entry to an exception handler by turning 692 * off DE in the SRR3 value and clearing the debug status. 693 */ 694 mfspr r10,SPRN_DBSR /* check single-step/branch taken */ 695 andis. r10,r10,DBSR_IC@h 696 beq+ 2f 697 698 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ 699 beq 1f /* branch and fix it up */ 700 701 mfspr r10,SPRN_SRR2 /* Faulting instruction address */ 702 cmplwi r10,0x2100 703 bgt+ 2f /* address above exception vectors */ 704 705 /* here it looks like we got an inappropriate debug exception. */ 7061: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ 707 lis r10,DBSR_IC@h /* clear the IC event */ 708 mtspr SPRN_DBSR,r10 709 /* restore state and get out */ 710 lwz r10,_CCR(r11) 711 lwz r0,GPR0(r11) 712 lwz r1,GPR1(r11) 713 mtcrf 0x80,r10 714 mtspr SPRN_SRR2,r12 715 mtspr SPRN_SRR3,r9 716 lwz r9,GPR9(r11) 717 lwz r12,GPR12(r11) 718 lwz r10,crit_r10@l(0) 719 lwz r11,crit_r11@l(0) 720 PPC405_ERR77_SYNC 721 rfci 722 b . 723 724 /* continue normal handling for a critical exception... */ 7252: mfspr r4,SPRN_DBSR 726 addi r3,r1,STACK_FRAME_OVERHEAD 727 EXC_XFER_TEMPLATE(DebugException, 0x2002, \ 728 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 729 NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) 730 731 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */ 732Decrementer: 733 NORMAL_EXCEPTION_PROLOG 734 lis r0,TSR_PIS@h 735 mtspr SPRN_TSR,r0 /* Clear the PIT exception */ 736 addi r3,r1,STACK_FRAME_OVERHEAD 737 EXC_XFER_LITE(0x1000, timer_interrupt) 738 739 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */ 740FITException: 741 NORMAL_EXCEPTION_PROLOG 742 addi r3,r1,STACK_FRAME_OVERHEAD; 743 EXC_XFER_EE(0x1010, unknown_exception) 744 745 /* Watchdog Timer (WDT) Exception. (from 0x1020) */ 746WDTException: 747 CRITICAL_EXCEPTION_PROLOG; 748 addi r3,r1,STACK_FRAME_OVERHEAD; 749 EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2, 750 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), 751 NOCOPY, crit_transfer_to_handler, 752 ret_from_crit_exc) 753 754/* 755 * The other Data TLB exceptions bail out to this point 756 * if they can't resolve the lightweight TLB fault. 757 */ 758DataAccess: 759 NORMAL_EXCEPTION_PROLOG 760 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ 761 stw r5,_ESR(r11) 762 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ 763 EXC_XFER_LITE(0x300, handle_page_fault) 764 765/* Other PowerPC processors, namely those derived from the 6xx-series 766 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. 767 * However, for the 4xx-series processors these are neither defined nor 768 * reserved. 769 */ 770 771 /* Damn, I came up one instruction too many to fit into the 772 * exception space :-). Both the instruction and data TLB 773 * miss get to this point to load the TLB. 774 * r10 - TLB_TAG value 775 * r11 - Linux PTE 776 * r12, r9 - available to use 777 * PID - loaded with proper value when we get here 778 * Upon exit, we reload everything and RFI. 779 * Actually, it will fit now, but oh well.....a common place 780 * to load the TLB. 781 */ 782tlb_4xx_index: 783 .long 0 784finish_tlb_load: 785 /* load the next available TLB index. 786 */ 787 lwz r9, tlb_4xx_index@l(0) 788 addi r9, r9, 1 789 andi. r9, r9, (PPC40X_TLB_SIZE-1) 790 stw r9, tlb_4xx_index@l(0) 791 7926: 793 /* 794 * Clear out the software-only bits in the PTE to generate the 795 * TLB_DATA value. These are the bottom 2 bits of the RPM, the 796 * top 3 bits of the zone field, and M. 797 */ 798 li r12, 0x0ce2 799 andc r11, r11, r12 800 801 tlbwe r11, r9, TLB_DATA /* Load TLB LO */ 802 tlbwe r10, r9, TLB_TAG /* Load TLB HI */ 803 804 /* Done...restore registers and get out of here. 805 */ 806#ifdef CONFIG_403GCX 807 lwz r12, 12(r0) 808 lwz r11, 8(r0) 809 mtspr SPRN_PID, r12 810 mtcr r11 811 lwz r9, 4(r0) 812 lwz r12, 0(r0) 813#else 814 mfspr r12, SPRN_SPRG_SCRATCH5 815 mfspr r11, SPRN_SPRG_SCRATCH6 816 mtspr SPRN_PID, r12 817 mtcr r11 818 mfspr r9, SPRN_SPRG_SCRATCH4 819 mfspr r12, SPRN_SPRG_SCRATCH3 820#endif 821 mfspr r11, SPRN_SPRG_SCRATCH1 822 mfspr r10, SPRN_SPRG_SCRATCH0 823 PPC405_ERR77_SYNC 824 rfi /* Should sync shadow TLBs */ 825 b . /* prevent prefetch past rfi */ 826 827/* This is where the main kernel code starts. 828 */ 829start_here: 830 831 /* ptr to current */ 832 lis r2,init_task@h 833 ori r2,r2,init_task@l 834 835 /* ptr to phys current thread */ 836 tophys(r4,r2) 837 addi r4,r4,THREAD /* init task's THREAD */ 838 mtspr SPRN_SPRG_THREAD,r4 839 840 /* stack */ 841 lis r1,init_thread_union@ha 842 addi r1,r1,init_thread_union@l 843 li r0,0 844 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 845 846 bl early_init /* We have to do this with MMU on */ 847 848/* 849 * Decide what sort of machine this is and initialize the MMU. 850 */ 851 li r3,0 852 mr r4,r31 853 bl machine_init 854 bl MMU_init 855 856/* Go back to running unmapped so we can load up new values 857 * and change to using our exception vectors. 858 * On the 4xx, all we have to do is invalidate the TLB to clear 859 * the old 16M byte TLB mappings. 860 */ 861 lis r4,2f@h 862 ori r4,r4,2f@l 863 tophys(r4,r4) 864 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h 865 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l 866 mtspr SPRN_SRR0,r4 867 mtspr SPRN_SRR1,r3 868 rfi 869 b . /* prevent prefetch past rfi */ 870 871/* Load up the kernel context */ 8722: 873 sync /* Flush to memory before changing TLB */ 874 tlbia 875 isync /* Flush shadow TLBs */ 876 877 /* set up the PTE pointers for the Abatron bdiGDB. 878 */ 879 lis r6, swapper_pg_dir@h 880 ori r6, r6, swapper_pg_dir@l 881 lis r5, abatron_pteptrs@h 882 ori r5, r5, abatron_pteptrs@l 883 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 884 tophys(r5,r5) 885 stw r6, 0(r5) 886 887/* Now turn on the MMU for real! */ 888 lis r4,MSR_KERNEL@h 889 ori r4,r4,MSR_KERNEL@l 890 lis r3,start_kernel@h 891 ori r3,r3,start_kernel@l 892 mtspr SPRN_SRR0,r3 893 mtspr SPRN_SRR1,r4 894 rfi /* enable MMU and jump to start_kernel */ 895 b . /* prevent prefetch past rfi */ 896 897/* Set up the initial MMU state so we can do the first level of 898 * kernel initialization. This maps the first 16 MBytes of memory 1:1 899 * virtual to physical and more importantly sets the cache mode. 900 */ 901initial_mmu: 902 tlbia /* Invalidate all TLB entries */ 903 isync 904 905 /* We should still be executing code at physical address 0x0000xxxx 906 * at this point. However, start_here is at virtual address 907 * 0xC000xxxx. So, set up a TLB mapping to cover this once 908 * translation is enabled. 909 */ 910 911 lis r3,KERNELBASE@h /* Load the kernel virtual address */ 912 ori r3,r3,KERNELBASE@l 913 tophys(r4,r3) /* Load the kernel physical address */ 914 915 iccci r0,r3 /* Invalidate the i-cache before use */ 916 917 /* Load the kernel PID. 918 */ 919 li r0,0 920 mtspr SPRN_PID,r0 921 sync 922 923 /* Configure and load one entry into TLB slots 63 */ 924 clrrwi r4,r4,10 /* Mask off the real page number */ 925 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 926 927 clrrwi r3,r3,10 /* Mask off the effective page number */ 928 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) 929 930 li r0,63 /* TLB slot 63 */ 931 932 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ 933 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ 934 935 isync 936 937 /* Establish the exception vector base 938 */ 939 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ 940 tophys(r0,r4) /* Use the physical address */ 941 mtspr SPRN_EVPR,r0 942 943 blr 944 945_GLOBAL(abort) 946 mfspr r13,SPRN_DBCR0 947 oris r13,r13,DBCR0_RST_SYSTEM@h 948 mtspr SPRN_DBCR0,r13 949 950_GLOBAL(set_context) 951 952#ifdef CONFIG_BDI_SWITCH 953 /* Context switch the PTE pointer for the Abatron BDI2000. 954 * The PGDIR is the second parameter. 955 */ 956 lis r5, abatron_pteptrs@ha 957 stw r4, abatron_pteptrs@l + 0x4(r5) 958#endif 959 sync 960 mtspr SPRN_PID,r3 961 isync /* Need an isync to flush shadow */ 962 /* TLBs after changing PID */ 963 blr 964 965/* We put a few things here that have to be page-aligned. This stuff 966 * goes at the beginning of the data segment, which is page-aligned. 967 */ 968 .data 969 .align 12 970 .globl sdata 971sdata: 972 .globl empty_zero_page 973empty_zero_page: 974 .space 4096 975EXPORT_SYMBOL(empty_zero_page) 976 .globl swapper_pg_dir 977swapper_pg_dir: 978 .space PGD_TABLE_SIZE 979 980/* Room for two PTE pointers, usually the kernel and current user pointers 981 * to their respective root page table. 982 */ 983abatron_pteptrs: 984 .space 8 985