1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 4 * Initial PowerPC version. 5 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Rewritten for PReP 7 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 8 * Low-level exception handers, MMU support, and rewrite. 9 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 10 * PowerPC 8xx modifications. 11 * Copyright (c) 1998-1999 TiVo, Inc. 12 * PowerPC 403GCX modifications. 13 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 14 * PowerPC 403GCX/405GP modifications. 15 * Copyright 2000 MontaVista Software Inc. 16 * PPC405 modifications 17 * PowerPC 403GCX/405GP modifications. 18 * Author: MontaVista Software, Inc. 19 * frank_rowand@mvista.com or source@mvista.com 20 * debbie_chu@mvista.com 21 * 22 * Module name: head_4xx.S 23 * 24 * Description: 25 * Kernel execution entry point code. 26 */ 27 28#include <linux/init.h> 29#include <linux/pgtable.h> 30#include <asm/processor.h> 31#include <asm/page.h> 32#include <asm/mmu.h> 33#include <asm/cputable.h> 34#include <asm/thread_info.h> 35#include <asm/ppc_asm.h> 36#include <asm/asm-offsets.h> 37#include <asm/ptrace.h> 38#include <asm/export.h> 39 40#include "head_32.h" 41 42/* As with the other PowerPC ports, it is expected that when code 43 * execution begins here, the following registers contain valid, yet 44 * optional, information: 45 * 46 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 47 * r4 - Starting address of the init RAM disk 48 * r5 - Ending address of the init RAM disk 49 * r6 - Start of kernel command line string (e.g. "mem=96m") 50 * r7 - End of kernel command line string 51 * 52 * This is all going to change RSN when we add bi_recs....... -- Dan 53 */ 54 __HEAD 55_ENTRY(_stext); 56_ENTRY(_start); 57 58 mr r31,r3 /* save device tree ptr */ 59 60 /* We have to turn on the MMU right away so we get cache modes 61 * set correctly. 62 */ 63 bl initial_mmu 64 65/* We now have the lower 16 Meg mapped into TLB entries, and the caches 66 * ready to work. 67 */ 68turn_on_mmu: 69 lis r0,MSR_KERNEL@h 70 ori r0,r0,MSR_KERNEL@l 71 mtspr SPRN_SRR1,r0 72 lis r0,start_here@h 73 ori r0,r0,start_here@l 74 mtspr SPRN_SRR0,r0 75 rfi /* enables MMU */ 76 b . /* prevent prefetch past rfi */ 77 78/* 79 * This area is used for temporarily saving registers during the 80 * critical exception prolog. 81 */ 82 . = 0xc0 83crit_save: 84_ENTRY(crit_r10) 85 .space 4 86_ENTRY(crit_r11) 87 .space 4 88_ENTRY(crit_srr0) 89 .space 4 90_ENTRY(crit_srr1) 91 .space 4 92_ENTRY(crit_r1) 93 .space 4 94_ENTRY(crit_dear) 95 .space 4 96_ENTRY(crit_esr) 97 .space 4 98 99/* 100 * Exception prolog for critical exceptions. This is a little different 101 * from the normal exception prolog above since a critical exception 102 * can potentially occur at any point during normal exception processing. 103 * Thus we cannot use the same SPRG registers as the normal prolog above. 104 * Instead we use a couple of words of memory at low physical addresses. 105 * This is OK since we don't support SMP on these processors. 106 */ 107.macro CRITICAL_EXCEPTION_PROLOG trapno name 108 stw r10,crit_r10@l(0) /* save two registers to work with */ 109 stw r11,crit_r11@l(0) 110 mfspr r10,SPRN_SRR0 111 mfspr r11,SPRN_SRR1 112 stw r10,crit_srr0@l(0) 113 stw r11,crit_srr1@l(0) 114 mfspr r10,SPRN_DEAR 115 mfspr r11,SPRN_ESR 116 stw r10,crit_dear@l(0) 117 stw r11,crit_esr@l(0) 118 mfcr r10 /* save CR in r10 for now */ 119 mfspr r11,SPRN_SRR3 /* check whether user or kernel */ 120 andi. r11,r11,MSR_PR 121 lis r11,(critirq_ctx-PAGE_OFFSET)@ha 122 lwz r11,(critirq_ctx-PAGE_OFFSET)@l(r11) 123 beq 1f 124 /* COMING FROM USER MODE */ 125 mfspr r11,SPRN_SPRG_THREAD /* if from user, start at top of */ 126 lwz r11,TASK_STACK-THREAD(r11) /* this thread's kernel stack */ 1271: stw r1,crit_r1@l(0) 128 addi r1,r11,THREAD_SIZE-INT_FRAME_SIZE /* Alloc an excpt frm */ 129 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)) /* re-enable MMU */ 130 mtspr SPRN_SRR1, r11 131 lis r11, 1f@h 132 ori r11, r11, 1f@l 133 mtspr SPRN_SRR0, r11 134 rfi 135 136 .text 1371: 138\name\()_virt: 139 lwz r11,crit_r1@l(0) 140 stw r11,GPR1(r1) 141 stw r11,0(r1) 142 mr r11,r1 143 stw r10,_CCR(r11) /* save various registers */ 144 stw r12,GPR12(r11) 145 stw r9,GPR9(r11) 146 mflr r10 147 stw r10,_LINK(r11) 148 lis r9,PAGE_OFFSET@ha 149 lwz r10,crit_r10@l(r9) 150 lwz r12,crit_r11@l(r9) 151 stw r10,GPR10(r11) 152 stw r12,GPR11(r11) 153 lwz r12,crit_dear@l(r9) 154 lwz r9,crit_esr@l(r9) 155 stw r12,_DEAR(r11) /* since they may have had stuff */ 156 stw r9,_ESR(r11) /* exception was taken */ 157 mfspr r12,SPRN_SRR2 158 mfspr r9,SPRN_SRR3 159 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ 160 COMMON_EXCEPTION_PROLOG_END \trapno + 2 161_ASM_NOKPROBE_SYMBOL(\name\()_virt) 162.endm 163 164 /* 165 * State at this point: 166 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE 167 * r10 saved in crit_r10 and in stack frame, trashed 168 * r11 saved in crit_r11 and in stack frame, 169 * now phys stack/exception frame pointer 170 * r12 saved in stack frame, now saved SRR2 171 * CR saved in stack frame, CR0.EQ = !SRR3.PR 172 * LR, DEAR, ESR in stack frame 173 * r1 saved in stack frame, now virt stack/excframe pointer 174 * r0, r3-r8 saved in stack frame 175 */ 176 177/* 178 * Exception vectors. 179 */ 180#define CRITICAL_EXCEPTION(n, label, hdlr) \ 181 START_EXCEPTION(n, label); \ 182 CRITICAL_EXCEPTION_PROLOG n label; \ 183 prepare_transfer_to_handler; \ 184 bl hdlr; \ 185 b ret_from_crit_exc 186 187/* 188 * 0x0100 - Critical Interrupt Exception 189 */ 190 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) 191 192/* 193 * 0x0200 - Machine Check Exception 194 */ 195 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 196 197/* 198 * 0x0300 - Data Storage Exception 199 * This happens for just a few reasons. U0 set (but we don't do that), 200 * or zone protection fault (user violation, write to protected page). 201 * The other Data TLB exceptions bail out to this point 202 * if they can't resolve the lightweight TLB fault. 203 */ 204 START_EXCEPTION(0x0300, DataStorage) 205 EXCEPTION_PROLOG 0x300 DataStorage handle_dar_dsisr=1 206 prepare_transfer_to_handler 207 bl do_page_fault 208 b interrupt_return 209 210/* 211 * 0x0400 - Instruction Storage Exception 212 * This is caused by a fetch from non-execute or guarded pages. 213 */ 214 START_EXCEPTION(0x0400, InstructionAccess) 215 EXCEPTION_PROLOG 0x400 InstructionAccess 216 li r5,0 217 stw r5, _ESR(r11) /* Zero ESR */ 218 stw r12, _DEAR(r11) /* SRR0 as DEAR */ 219 prepare_transfer_to_handler 220 bl do_page_fault 221 b interrupt_return 222 223/* 0x0500 - External Interrupt Exception */ 224 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ) 225 226/* 0x0600 - Alignment Exception */ 227 START_EXCEPTION(0x0600, Alignment) 228 EXCEPTION_PROLOG 0x600 Alignment handle_dar_dsisr=1 229 prepare_transfer_to_handler 230 bl alignment_exception 231 REST_NVGPRS(r1) 232 b interrupt_return 233 234/* 0x0700 - Program Exception */ 235 START_EXCEPTION(0x0700, ProgramCheck) 236 EXCEPTION_PROLOG 0x700 ProgramCheck handle_dar_dsisr=1 237 prepare_transfer_to_handler 238 bl program_check_exception 239 REST_NVGPRS(r1) 240 b interrupt_return 241 242 EXCEPTION(0x0800, Trap_08, unknown_exception) 243 EXCEPTION(0x0900, Trap_09, unknown_exception) 244 EXCEPTION(0x0A00, Trap_0A, unknown_exception) 245 EXCEPTION(0x0B00, Trap_0B, unknown_exception) 246 247/* 0x0C00 - System Call Exception */ 248 START_EXCEPTION(0x0C00, SystemCall) 249 SYSCALL_ENTRY 0xc00 250/* Trap_0D is commented out to get more space for system call exception */ 251 252/* EXCEPTION(0x0D00, Trap_0D, unknown_exception) */ 253 EXCEPTION(0x0E00, Trap_0E, unknown_exception) 254 EXCEPTION(0x0F00, Trap_0F, unknown_exception) 255 256/* 0x1000 - Programmable Interval Timer (PIT) Exception */ 257 START_EXCEPTION(0x1000, DecrementerTrap) 258 b Decrementer 259 260/* 0x1010 - Fixed Interval Timer (FIT) Exception */ 261 START_EXCEPTION(0x1010, FITExceptionTrap) 262 b FITException 263 264/* 0x1020 - Watchdog Timer (WDT) Exception */ 265 START_EXCEPTION(0x1020, WDTExceptionTrap) 266 b WDTException 267 268/* 0x1100 - Data TLB Miss Exception 269 * As the name implies, translation is not in the MMU, so search the 270 * page tables and fix it. The only purpose of this function is to 271 * load TLB entries from the page table if they exist. 272 */ 273 START_EXCEPTION(0x1100, DTLBMiss) 274 mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */ 275 mtspr SPRN_SPRG_SCRATCH6, r11 276 mtspr SPRN_SPRG_SCRATCH3, r12 277 mtspr SPRN_SPRG_SCRATCH4, r9 278 mfcr r12 279 mfspr r9, SPRN_PID 280 rlwimi r12, r9, 0, 0xff 281 mfspr r10, SPRN_DEAR /* Get faulting address */ 282 283 /* If we are faulting a kernel address, we have to use the 284 * kernel page tables. 285 */ 286 lis r11, PAGE_OFFSET@h 287 cmplw r10, r11 288 blt+ 3f 289 lis r11, swapper_pg_dir@h 290 ori r11, r11, swapper_pg_dir@l 291 li r9, 0 292 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 293 b 4f 294 295 /* Get the PGD for the current thread. 296 */ 2973: 298 mfspr r11,SPRN_SPRG_THREAD 299 lwz r11,PGDIR(r11) 3004: 301 tophys(r11, r11) 302 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 303 lwz r11, 0(r11) /* Get L1 entry */ 304 andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */ 305 beq 2f /* Bail if no table */ 306 307 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ 308 lwz r11, 0(r11) /* Get Linux PTE */ 309 li r9, _PAGE_PRESENT | _PAGE_ACCESSED 310 andc. r9, r9, r11 /* Check permission */ 311 bne 5f 312 313 rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */ 314 and r9, r9, r11 /* hwwrite = dirty & rw */ 315 rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */ 316 317 /* Create TLB tag. This is the faulting address plus a static 318 * set of bits. These are size, valid, E, U0. 319 */ 320 li r9, 0x00c0 321 rlwimi r10, r9, 0, 20, 31 322 323 b finish_tlb_load 324 3252: /* Check for possible large-page pmd entry */ 326 rlwinm. r9, r11, 2, 22, 24 327 beq 5f 328 329 /* Create TLB tag. This is the faulting address, plus a static 330 * set of bits (valid, E, U0) plus the size from the PMD. 331 */ 332 ori r9, r9, 0x40 333 rlwimi r10, r9, 0, 20, 31 334 335 b finish_tlb_load 336 3375: 338 /* The bailout. Restore registers to pre-exception conditions 339 * and call the heavyweights to help us out. 340 */ 341 mtspr SPRN_PID, r12 342 mtcrf 0x80, r12 343 mfspr r9, SPRN_SPRG_SCRATCH4 344 mfspr r12, SPRN_SPRG_SCRATCH3 345 mfspr r11, SPRN_SPRG_SCRATCH6 346 mfspr r10, SPRN_SPRG_SCRATCH5 347 b DataStorage 348 349/* 0x1200 - Instruction TLB Miss Exception 350 * Nearly the same as above, except we get our information from different 351 * registers and bailout to a different point. 352 */ 353 START_EXCEPTION(0x1200, ITLBMiss) 354 mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */ 355 mtspr SPRN_SPRG_SCRATCH6, r11 356 mtspr SPRN_SPRG_SCRATCH3, r12 357 mtspr SPRN_SPRG_SCRATCH4, r9 358 mfcr r12 359 mfspr r9, SPRN_PID 360 rlwimi r12, r9, 0, 0xff 361 mfspr r10, SPRN_SRR0 /* Get faulting address */ 362 363 /* If we are faulting a kernel address, we have to use the 364 * kernel page tables. 365 */ 366 lis r11, PAGE_OFFSET@h 367 cmplw r10, r11 368 blt+ 3f 369 lis r11, swapper_pg_dir@h 370 ori r11, r11, swapper_pg_dir@l 371 li r9, 0 372 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 373 b 4f 374 375 /* Get the PGD for the current thread. 376 */ 3773: 378 mfspr r11,SPRN_SPRG_THREAD 379 lwz r11,PGDIR(r11) 3804: 381 tophys(r11, r11) 382 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 383 lwz r11, 0(r11) /* Get L1 entry */ 384 andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */ 385 beq 2f /* Bail if no table */ 386 387 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ 388 lwz r11, 0(r11) /* Get Linux PTE */ 389 li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 390 andc. r9, r9, r11 /* Check permission */ 391 bne 5f 392 393 rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */ 394 and r9, r9, r11 /* hwwrite = dirty & rw */ 395 rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */ 396 397 /* Create TLB tag. This is the faulting address plus a static 398 * set of bits. These are size, valid, E, U0. 399 */ 400 li r9, 0x00c0 401 rlwimi r10, r9, 0, 20, 31 402 403 b finish_tlb_load 404 4052: /* Check for possible large-page pmd entry */ 406 rlwinm. r9, r11, 2, 22, 24 407 beq 5f 408 409 /* Create TLB tag. This is the faulting address, plus a static 410 * set of bits (valid, E, U0) plus the size from the PMD. 411 */ 412 ori r9, r9, 0x40 413 rlwimi r10, r9, 0, 20, 31 414 415 b finish_tlb_load 416 4175: 418 /* The bailout. Restore registers to pre-exception conditions 419 * and call the heavyweights to help us out. 420 */ 421 mtspr SPRN_PID, r12 422 mtcrf 0x80, r12 423 mfspr r9, SPRN_SPRG_SCRATCH4 424 mfspr r12, SPRN_SPRG_SCRATCH3 425 mfspr r11, SPRN_SPRG_SCRATCH6 426 mfspr r10, SPRN_SPRG_SCRATCH5 427 b InstructionAccess 428 429 EXCEPTION(0x1300, Trap_13, unknown_exception) 430 EXCEPTION(0x1400, Trap_14, unknown_exception) 431 EXCEPTION(0x1500, Trap_15, unknown_exception) 432 EXCEPTION(0x1600, Trap_16, unknown_exception) 433 EXCEPTION(0x1700, Trap_17, unknown_exception) 434 EXCEPTION(0x1800, Trap_18, unknown_exception) 435 EXCEPTION(0x1900, Trap_19, unknown_exception) 436 EXCEPTION(0x1A00, Trap_1A, unknown_exception) 437 EXCEPTION(0x1B00, Trap_1B, unknown_exception) 438 EXCEPTION(0x1C00, Trap_1C, unknown_exception) 439 EXCEPTION(0x1D00, Trap_1D, unknown_exception) 440 EXCEPTION(0x1E00, Trap_1E, unknown_exception) 441 EXCEPTION(0x1F00, Trap_1F, unknown_exception) 442 443/* Check for a single step debug exception while in an exception 444 * handler before state has been saved. This is to catch the case 445 * where an instruction that we are trying to single step causes 446 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 447 * the exception handler generates a single step debug exception. 448 * 449 * If we get a debug trap on the first instruction of an exception handler, 450 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 451 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 452 * The exception handler was handling a non-critical interrupt, so it will 453 * save (and later restore) the MSR via SPRN_SRR1, which will still have 454 * the MSR_DE bit set. 455 */ 456 /* 0x2000 - Debug Exception */ 457 START_EXCEPTION(0x2000, DebugTrap) 458 CRITICAL_EXCEPTION_PROLOG 0x2000 DebugTrap 459 460 /* 461 * If this is a single step or branch-taken exception in an 462 * exception entry sequence, it was probably meant to apply to 463 * the code where the exception occurred (since exception entry 464 * doesn't turn off DE automatically). We simulate the effect 465 * of turning off DE on entry to an exception handler by turning 466 * off DE in the SRR3 value and clearing the debug status. 467 */ 468 mfspr r10,SPRN_DBSR /* check single-step/branch taken */ 469 andis. r10,r10,DBSR_IC@h 470 beq+ 2f 471 472 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ 473 beq 1f /* branch and fix it up */ 474 475 mfspr r10,SPRN_SRR2 /* Faulting instruction address */ 476 cmplwi r10,0x2100 477 bgt+ 2f /* address above exception vectors */ 478 479 /* here it looks like we got an inappropriate debug exception. */ 4801: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ 481 lis r10,DBSR_IC@h /* clear the IC event */ 482 mtspr SPRN_DBSR,r10 483 /* restore state and get out */ 484 lwz r10,_CCR(r11) 485 lwz r0,GPR0(r11) 486 lwz r1,GPR1(r11) 487 mtcrf 0x80,r10 488 mtspr SPRN_SRR2,r12 489 mtspr SPRN_SRR3,r9 490 lwz r9,GPR9(r11) 491 lwz r12,GPR12(r11) 492 lwz r10,crit_r10@l(0) 493 lwz r11,crit_r11@l(0) 494 rfci 495 b . 496 497 /* continue normal handling for a critical exception... */ 4982: mfspr r4,SPRN_DBSR 499 stw r4,_ESR(r11) /* DebugException takes DBSR in _ESR */ 500 prepare_transfer_to_handler 501 bl DebugException 502 b ret_from_crit_exc 503 504 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */ 505 __HEAD 506Decrementer: 507 EXCEPTION_PROLOG 0x1000 Decrementer 508 lis r0,TSR_PIS@h 509 mtspr SPRN_TSR,r0 /* Clear the PIT exception */ 510 prepare_transfer_to_handler 511 bl timer_interrupt 512 b interrupt_return 513 514 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */ 515 __HEAD 516FITException: 517 EXCEPTION_PROLOG 0x1010 FITException 518 prepare_transfer_to_handler 519 bl unknown_exception 520 b interrupt_return 521 522 /* Watchdog Timer (WDT) Exception. (from 0x1020) */ 523 __HEAD 524WDTException: 525 CRITICAL_EXCEPTION_PROLOG 0x1020 WDTException 526 prepare_transfer_to_handler 527 bl WatchdogException 528 b ret_from_crit_exc 529 530/* Other PowerPC processors, namely those derived from the 6xx-series 531 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. 532 * However, for the 4xx-series processors these are neither defined nor 533 * reserved. 534 */ 535 536 __HEAD 537 /* Damn, I came up one instruction too many to fit into the 538 * exception space :-). Both the instruction and data TLB 539 * miss get to this point to load the TLB. 540 * r10 - TLB_TAG value 541 * r11 - Linux PTE 542 * r9 - available to use 543 * PID - loaded with proper value when we get here 544 * Upon exit, we reload everything and RFI. 545 * Actually, it will fit now, but oh well.....a common place 546 * to load the TLB. 547 */ 548tlb_4xx_index: 549 .long 0 550finish_tlb_load: 551 /* 552 * Clear out the software-only bits in the PTE to generate the 553 * TLB_DATA value. These are the bottom 2 bits of the RPM, the 554 * top 3 bits of the zone field, and M. 555 */ 556 li r9, 0x0ce2 557 andc r11, r11, r9 558 559 /* load the next available TLB index. */ 560 lwz r9, tlb_4xx_index@l(0) 561 addi r9, r9, 1 562 andi. r9, r9, PPC40X_TLB_SIZE - 1 563 stw r9, tlb_4xx_index@l(0) 564 565 tlbwe r11, r9, TLB_DATA /* Load TLB LO */ 566 tlbwe r10, r9, TLB_TAG /* Load TLB HI */ 567 568 /* Done...restore registers and get out of here. 569 */ 570 mtspr SPRN_PID, r12 571 mtcrf 0x80, r12 572 mfspr r9, SPRN_SPRG_SCRATCH4 573 mfspr r12, SPRN_SPRG_SCRATCH3 574 mfspr r11, SPRN_SPRG_SCRATCH6 575 mfspr r10, SPRN_SPRG_SCRATCH5 576 rfi /* Should sync shadow TLBs */ 577 b . /* prevent prefetch past rfi */ 578 579/* This is where the main kernel code starts. 580 */ 581start_here: 582 583 /* ptr to current */ 584 lis r2,init_task@h 585 ori r2,r2,init_task@l 586 587 /* ptr to phys current thread */ 588 tophys(r4,r2) 589 addi r4,r4,THREAD /* init task's THREAD */ 590 mtspr SPRN_SPRG_THREAD,r4 591 592 /* stack */ 593 lis r1,init_thread_union@ha 594 addi r1,r1,init_thread_union@l 595 li r0,0 596 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 597 598 bl early_init /* We have to do this with MMU on */ 599 600/* 601 * Decide what sort of machine this is and initialize the MMU. 602 */ 603#ifdef CONFIG_KASAN 604 bl kasan_early_init 605#endif 606 li r3,0 607 mr r4,r31 608 bl machine_init 609 bl MMU_init 610 611/* Go back to running unmapped so we can load up new values 612 * and change to using our exception vectors. 613 * On the 4xx, all we have to do is invalidate the TLB to clear 614 * the old 16M byte TLB mappings. 615 */ 616 lis r4,2f@h 617 ori r4,r4,2f@l 618 tophys(r4,r4) 619 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h 620 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l 621 mtspr SPRN_SRR0,r4 622 mtspr SPRN_SRR1,r3 623 rfi 624 b . /* prevent prefetch past rfi */ 625 626/* Load up the kernel context */ 6272: 628 sync /* Flush to memory before changing TLB */ 629 tlbia 630 isync /* Flush shadow TLBs */ 631 632 /* set up the PTE pointers for the Abatron bdiGDB. 633 */ 634 lis r6, swapper_pg_dir@h 635 ori r6, r6, swapper_pg_dir@l 636 lis r5, abatron_pteptrs@h 637 ori r5, r5, abatron_pteptrs@l 638 stw r5, 0xf0(0) /* Must match your Abatron config file */ 639 tophys(r5,r5) 640 stw r6, 0(r5) 641 642/* Now turn on the MMU for real! */ 643 lis r4,MSR_KERNEL@h 644 ori r4,r4,MSR_KERNEL@l 645 lis r3,start_kernel@h 646 ori r3,r3,start_kernel@l 647 mtspr SPRN_SRR0,r3 648 mtspr SPRN_SRR1,r4 649 rfi /* enable MMU and jump to start_kernel */ 650 b . /* prevent prefetch past rfi */ 651 652/* Set up the initial MMU state so we can do the first level of 653 * kernel initialization. This maps the first 16 MBytes of memory 1:1 654 * virtual to physical and more importantly sets the cache mode. 655 */ 656initial_mmu: 657 tlbia /* Invalidate all TLB entries */ 658 isync 659 660 /* We should still be executing code at physical address 0x0000xxxx 661 * at this point. However, start_here is at virtual address 662 * 0xC000xxxx. So, set up a TLB mapping to cover this once 663 * translation is enabled. 664 */ 665 666 lis r3,KERNELBASE@h /* Load the kernel virtual address */ 667 ori r3,r3,KERNELBASE@l 668 tophys(r4,r3) /* Load the kernel physical address */ 669 670 iccci r0,r3 /* Invalidate the i-cache before use */ 671 672 /* Load the kernel PID. 673 */ 674 li r0,0 675 mtspr SPRN_PID,r0 676 sync 677 678 /* Configure and load one entry into TLB slots 63 */ 679 clrrwi r4,r4,10 /* Mask off the real page number */ 680 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 681 682 clrrwi r3,r3,10 /* Mask off the effective page number */ 683 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) 684 685 li r0,63 /* TLB slot 63 */ 686 687 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ 688 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ 689 690 isync 691 692 /* Establish the exception vector base 693 */ 694 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ 695 tophys(r0,r4) /* Use the physical address */ 696 mtspr SPRN_EVPR,r0 697 698 blr 699 700_GLOBAL(abort) 701 mfspr r13,SPRN_DBCR0 702 oris r13,r13,DBCR0_RST_SYSTEM@h 703 mtspr SPRN_DBCR0,r13 704