1/* 2 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 3 * Initial PowerPC version. 4 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 5 * Rewritten for PReP 6 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 7 * Low-level exception handers, MMU support, and rewrite. 8 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 9 * PowerPC 8xx modifications. 10 * Copyright (c) 1998-1999 TiVo, Inc. 11 * PowerPC 403GCX modifications. 12 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 13 * PowerPC 403GCX/405GP modifications. 14 * Copyright 2000 MontaVista Software Inc. 15 * PPC405 modifications 16 * PowerPC 403GCX/405GP modifications. 17 * Author: MontaVista Software, Inc. 18 * frank_rowand@mvista.com or source@mvista.com 19 * debbie_chu@mvista.com 20 * 21 * 22 * Module name: head_4xx.S 23 * 24 * Description: 25 * Kernel execution entry point code. 26 * 27 * This program is free software; you can redistribute it and/or 28 * modify it under the terms of the GNU General Public License 29 * as published by the Free Software Foundation; either version 30 * 2 of the License, or (at your option) any later version. 31 * 32 */ 33 34#include <linux/init.h> 35#include <asm/processor.h> 36#include <asm/page.h> 37#include <asm/mmu.h> 38#include <asm/pgtable.h> 39#include <asm/cputable.h> 40#include <asm/thread_info.h> 41#include <asm/ppc_asm.h> 42#include <asm/asm-offsets.h> 43#include <asm/ptrace.h> 44#include <asm/export.h> 45#include <asm/asm-405.h> 46 47#include "head_32.h" 48 49/* As with the other PowerPC ports, it is expected that when code 50 * execution begins here, the following registers contain valid, yet 51 * optional, information: 52 * 53 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 54 * r4 - Starting address of the init RAM disk 55 * r5 - Ending address of the init RAM disk 56 * r6 - Start of kernel command line string (e.g. "mem=96m") 57 * r7 - End of kernel command line string 58 * 59 * This is all going to change RSN when we add bi_recs....... -- Dan 60 */ 61 __HEAD 62_ENTRY(_stext); 63_ENTRY(_start); 64 65 mr r31,r3 /* save device tree ptr */ 66 67 /* We have to turn on the MMU right away so we get cache modes 68 * set correctly. 69 */ 70 bl initial_mmu 71 72/* We now have the lower 16 Meg mapped into TLB entries, and the caches 73 * ready to work. 74 */ 75turn_on_mmu: 76 lis r0,MSR_KERNEL@h 77 ori r0,r0,MSR_KERNEL@l 78 mtspr SPRN_SRR1,r0 79 lis r0,start_here@h 80 ori r0,r0,start_here@l 81 mtspr SPRN_SRR0,r0 82 SYNC 83 rfi /* enables MMU */ 84 b . /* prevent prefetch past rfi */ 85 86/* 87 * This area is used for temporarily saving registers during the 88 * critical exception prolog. 89 */ 90 . = 0xc0 91crit_save: 92_ENTRY(crit_r10) 93 .space 4 94_ENTRY(crit_r11) 95 .space 4 96_ENTRY(crit_srr0) 97 .space 4 98_ENTRY(crit_srr1) 99 .space 4 100_ENTRY(saved_ksp_limit) 101 .space 4 102 103/* 104 * Exception prolog for critical exceptions. This is a little different 105 * from the normal exception prolog above since a critical exception 106 * can potentially occur at any point during normal exception processing. 107 * Thus we cannot use the same SPRG registers as the normal prolog above. 108 * Instead we use a couple of words of memory at low physical addresses. 109 * This is OK since we don't support SMP on these processors. 110 */ 111#define CRITICAL_EXCEPTION_PROLOG \ 112 stw r10,crit_r10@l(0); /* save two registers to work with */\ 113 stw r11,crit_r11@l(0); \ 114 mfcr r10; /* save CR in r10 for now */\ 115 mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ 116 andi. r11,r11,MSR_PR; \ 117 lis r11,critirq_ctx@ha; \ 118 tophys(r11,r11); \ 119 lwz r11,critirq_ctx@l(r11); \ 120 beq 1f; \ 121 /* COMING FROM USER MODE */ \ 122 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 123 lwz r11,TASK_STACK-THREAD(r11); /* this thread's kernel stack */\ 1241: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\ 125 tophys(r11,r11); \ 126 stw r10,_CCR(r11); /* save various registers */\ 127 stw r12,GPR12(r11); \ 128 stw r9,GPR9(r11); \ 129 mflr r10; \ 130 stw r10,_LINK(r11); \ 131 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 132 stw r12,_DEAR(r11); /* since they may have had stuff */\ 133 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 134 stw r9,_ESR(r11); /* exception was taken */\ 135 mfspr r12,SPRN_SRR2; \ 136 stw r1,GPR1(r11); \ 137 mfspr r9,SPRN_SRR3; \ 138 stw r1,0(r11); \ 139 tovirt(r1,r11); \ 140 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 141 stw r0,GPR0(r11); \ 142 lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */\ 143 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \ 144 stw r10, 8(r11); \ 145 SAVE_4GPRS(3, r11); \ 146 SAVE_2GPRS(7, r11) 147 148 /* 149 * State at this point: 150 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE 151 * r10 saved in crit_r10 and in stack frame, trashed 152 * r11 saved in crit_r11 and in stack frame, 153 * now phys stack/exception frame pointer 154 * r12 saved in stack frame, now saved SRR2 155 * CR saved in stack frame, CR0.EQ = !SRR3.PR 156 * LR, DEAR, ESR in stack frame 157 * r1 saved in stack frame, now virt stack/excframe pointer 158 * r0, r3-r8 saved in stack frame 159 */ 160 161/* 162 * Exception vectors. 163 */ 164#define CRITICAL_EXCEPTION(n, label, hdlr) \ 165 START_EXCEPTION(n, label); \ 166 CRITICAL_EXCEPTION_PROLOG; \ 167 addi r3,r1,STACK_FRAME_OVERHEAD; \ 168 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 169 crit_transfer_to_handler, ret_from_crit_exc) 170 171/* 172 * 0x0100 - Critical Interrupt Exception 173 */ 174 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) 175 176/* 177 * 0x0200 - Machine Check Exception 178 */ 179 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 180 181/* 182 * 0x0300 - Data Storage Exception 183 * This happens for just a few reasons. U0 set (but we don't do that), 184 * or zone protection fault (user violation, write to protected page). 185 * If this is just an update of modified status, we do that quickly 186 * and exit. Otherwise, we call heavywight functions to do the work. 187 */ 188 START_EXCEPTION(0x0300, DataStorage) 189 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ 190 mtspr SPRN_SPRG_SCRATCH1, r11 191#ifdef CONFIG_403GCX 192 stw r12, 0(r0) 193 stw r9, 4(r0) 194 mfcr r11 195 mfspr r12, SPRN_PID 196 stw r11, 8(r0) 197 stw r12, 12(r0) 198#else 199 mtspr SPRN_SPRG_SCRATCH3, r12 200 mtspr SPRN_SPRG_SCRATCH4, r9 201 mfcr r11 202 mfspr r12, SPRN_PID 203 mtspr SPRN_SPRG_SCRATCH6, r11 204 mtspr SPRN_SPRG_SCRATCH5, r12 205#endif 206 207 /* First, check if it was a zone fault (which means a user 208 * tried to access a kernel or read-protected page - always 209 * a SEGV). All other faults here must be stores, so no 210 * need to check ESR_DST as well. */ 211 mfspr r10, SPRN_ESR 212 andis. r10, r10, ESR_DIZ@h 213 bne 2f 214 215 mfspr r10, SPRN_DEAR /* Get faulting address */ 216 217 /* If we are faulting a kernel address, we have to use the 218 * kernel page tables. 219 */ 220 lis r11, PAGE_OFFSET@h 221 cmplw r10, r11 222 blt+ 3f 223 lis r11, swapper_pg_dir@h 224 ori r11, r11, swapper_pg_dir@l 225 li r9, 0 226 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 227 b 4f 228 229 /* Get the PGD for the current thread. 230 */ 2313: 232 mfspr r11,SPRN_SPRG_THREAD 233 lwz r11,PGDIR(r11) 2344: 235 tophys(r11, r11) 236 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 237 lwz r11, 0(r11) /* Get L1 entry */ 238 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */ 239 beq 2f /* Bail if no table */ 240 241 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ 242 lwz r11, 0(r12) /* Get Linux PTE */ 243 244 andi. r9, r11, _PAGE_RW /* Is it writeable? */ 245 beq 2f /* Bail if not */ 246 247 /* Update 'changed'. 248 */ 249 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE 250 stw r11, 0(r12) /* Update Linux page table */ 251 252 /* Most of the Linux PTE is ready to load into the TLB LO. 253 * We set ZSEL, where only the LS-bit determines user access. 254 * We set execute, because we don't have the granularity to 255 * properly set this at the page level (Linux problem). 256 * If shared is set, we cause a zero PID->TID load. 257 * Many of these bits are software only. Bits we don't set 258 * here we (properly should) assume have the appropriate value. 259 */ 260 li r12, 0x0ce2 261 andc r11, r11, r12 /* Make sure 20, 21 are zero */ 262 263 /* find the TLB index that caused the fault. It has to be here. 264 */ 265 tlbsx r9, 0, r10 266 267 tlbwe r11, r9, TLB_DATA /* Load TLB LO */ 268 269 /* Done...restore registers and get out of here. 270 */ 271#ifdef CONFIG_403GCX 272 lwz r12, 12(r0) 273 lwz r11, 8(r0) 274 mtspr SPRN_PID, r12 275 mtcr r11 276 lwz r9, 4(r0) 277 lwz r12, 0(r0) 278#else 279 mfspr r12, SPRN_SPRG_SCRATCH5 280 mfspr r11, SPRN_SPRG_SCRATCH6 281 mtspr SPRN_PID, r12 282 mtcr r11 283 mfspr r9, SPRN_SPRG_SCRATCH4 284 mfspr r12, SPRN_SPRG_SCRATCH3 285#endif 286 mfspr r11, SPRN_SPRG_SCRATCH1 287 mfspr r10, SPRN_SPRG_SCRATCH0 288 PPC405_ERR77_SYNC 289 rfi /* Should sync shadow TLBs */ 290 b . /* prevent prefetch past rfi */ 291 2922: 293 /* The bailout. Restore registers to pre-exception conditions 294 * and call the heavyweights to help us out. 295 */ 296#ifdef CONFIG_403GCX 297 lwz r12, 12(r0) 298 lwz r11, 8(r0) 299 mtspr SPRN_PID, r12 300 mtcr r11 301 lwz r9, 4(r0) 302 lwz r12, 0(r0) 303#else 304 mfspr r12, SPRN_SPRG_SCRATCH5 305 mfspr r11, SPRN_SPRG_SCRATCH6 306 mtspr SPRN_PID, r12 307 mtcr r11 308 mfspr r9, SPRN_SPRG_SCRATCH4 309 mfspr r12, SPRN_SPRG_SCRATCH3 310#endif 311 mfspr r11, SPRN_SPRG_SCRATCH1 312 mfspr r10, SPRN_SPRG_SCRATCH0 313 b DataAccess 314 315/* 316 * 0x0400 - Instruction Storage Exception 317 * This is caused by a fetch from non-execute or guarded pages. 318 */ 319 START_EXCEPTION(0x0400, InstructionAccess) 320 EXCEPTION_PROLOG 321 mr r4,r12 /* Pass SRR0 as arg2 */ 322 li r5,0 /* Pass zero as arg3 */ 323 EXC_XFER_LITE(0x400, handle_page_fault) 324 325/* 0x0500 - External Interrupt Exception */ 326 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 327 328/* 0x0600 - Alignment Exception */ 329 START_EXCEPTION(0x0600, Alignment) 330 EXCEPTION_PROLOG 331 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ 332 stw r4,_DEAR(r11) 333 addi r3,r1,STACK_FRAME_OVERHEAD 334 EXC_XFER_STD(0x600, alignment_exception) 335 336/* 0x0700 - Program Exception */ 337 START_EXCEPTION(0x0700, ProgramCheck) 338 EXCEPTION_PROLOG 339 mfspr r4,SPRN_ESR /* Grab the ESR and save it */ 340 stw r4,_ESR(r11) 341 addi r3,r1,STACK_FRAME_OVERHEAD 342 EXC_XFER_STD(0x700, program_check_exception) 343 344 EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_STD) 345 EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_STD) 346 EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_STD) 347 EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_STD) 348 349/* 0x0C00 - System Call Exception */ 350 START_EXCEPTION(0x0C00, SystemCall) 351 SYSCALL_ENTRY 0xc00 352 353 EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_STD) 354 EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_STD) 355 EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD) 356 357/* 0x1000 - Programmable Interval Timer (PIT) Exception */ 358 . = 0x1000 359 b Decrementer 360 361/* 0x1010 - Fixed Interval Timer (FIT) Exception 362*/ 363 . = 0x1010 364 b FITException 365 366/* 0x1020 - Watchdog Timer (WDT) Exception 367*/ 368 . = 0x1020 369 b WDTException 370 371/* 0x1100 - Data TLB Miss Exception 372 * As the name implies, translation is not in the MMU, so search the 373 * page tables and fix it. The only purpose of this function is to 374 * load TLB entries from the page table if they exist. 375 */ 376 START_EXCEPTION(0x1100, DTLBMiss) 377 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ 378 mtspr SPRN_SPRG_SCRATCH1, r11 379#ifdef CONFIG_403GCX 380 stw r12, 0(r0) 381 stw r9, 4(r0) 382 mfcr r11 383 mfspr r12, SPRN_PID 384 stw r11, 8(r0) 385 stw r12, 12(r0) 386#else 387 mtspr SPRN_SPRG_SCRATCH3, r12 388 mtspr SPRN_SPRG_SCRATCH4, r9 389 mfcr r11 390 mfspr r12, SPRN_PID 391 mtspr SPRN_SPRG_SCRATCH6, r11 392 mtspr SPRN_SPRG_SCRATCH5, r12 393#endif 394 mfspr r10, SPRN_DEAR /* Get faulting address */ 395 396 /* If we are faulting a kernel address, we have to use the 397 * kernel page tables. 398 */ 399 lis r11, PAGE_OFFSET@h 400 cmplw r10, r11 401 blt+ 3f 402 lis r11, swapper_pg_dir@h 403 ori r11, r11, swapper_pg_dir@l 404 li r9, 0 405 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 406 b 4f 407 408 /* Get the PGD for the current thread. 409 */ 4103: 411 mfspr r11,SPRN_SPRG_THREAD 412 lwz r11,PGDIR(r11) 4134: 414 tophys(r11, r11) 415 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 416 lwz r12, 0(r11) /* Get L1 entry */ 417 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ 418 beq 2f /* Bail if no table */ 419 420 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ 421 lwz r11, 0(r12) /* Get Linux PTE */ 422 andi. r9, r11, _PAGE_PRESENT 423 beq 5f 424 425 ori r11, r11, _PAGE_ACCESSED 426 stw r11, 0(r12) 427 428 /* Create TLB tag. This is the faulting address plus a static 429 * set of bits. These are size, valid, E, U0. 430 */ 431 li r12, 0x00c0 432 rlwimi r10, r12, 0, 20, 31 433 434 b finish_tlb_load 435 4362: /* Check for possible large-page pmd entry */ 437 rlwinm. r9, r12, 2, 22, 24 438 beq 5f 439 440 /* Create TLB tag. This is the faulting address, plus a static 441 * set of bits (valid, E, U0) plus the size from the PMD. 442 */ 443 ori r9, r9, 0x40 444 rlwimi r10, r9, 0, 20, 31 445 mr r11, r12 446 447 b finish_tlb_load 448 4495: 450 /* The bailout. Restore registers to pre-exception conditions 451 * and call the heavyweights to help us out. 452 */ 453#ifdef CONFIG_403GCX 454 lwz r12, 12(r0) 455 lwz r11, 8(r0) 456 mtspr SPRN_PID, r12 457 mtcr r11 458 lwz r9, 4(r0) 459 lwz r12, 0(r0) 460#else 461 mfspr r12, SPRN_SPRG_SCRATCH5 462 mfspr r11, SPRN_SPRG_SCRATCH6 463 mtspr SPRN_PID, r12 464 mtcr r11 465 mfspr r9, SPRN_SPRG_SCRATCH4 466 mfspr r12, SPRN_SPRG_SCRATCH3 467#endif 468 mfspr r11, SPRN_SPRG_SCRATCH1 469 mfspr r10, SPRN_SPRG_SCRATCH0 470 b DataAccess 471 472/* 0x1200 - Instruction TLB Miss Exception 473 * Nearly the same as above, except we get our information from different 474 * registers and bailout to a different point. 475 */ 476 START_EXCEPTION(0x1200, ITLBMiss) 477 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ 478 mtspr SPRN_SPRG_SCRATCH1, r11 479#ifdef CONFIG_403GCX 480 stw r12, 0(r0) 481 stw r9, 4(r0) 482 mfcr r11 483 mfspr r12, SPRN_PID 484 stw r11, 8(r0) 485 stw r12, 12(r0) 486#else 487 mtspr SPRN_SPRG_SCRATCH3, r12 488 mtspr SPRN_SPRG_SCRATCH4, r9 489 mfcr r11 490 mfspr r12, SPRN_PID 491 mtspr SPRN_SPRG_SCRATCH6, r11 492 mtspr SPRN_SPRG_SCRATCH5, r12 493#endif 494 mfspr r10, SPRN_SRR0 /* Get faulting address */ 495 496 /* If we are faulting a kernel address, we have to use the 497 * kernel page tables. 498 */ 499 lis r11, PAGE_OFFSET@h 500 cmplw r10, r11 501 blt+ 3f 502 lis r11, swapper_pg_dir@h 503 ori r11, r11, swapper_pg_dir@l 504 li r9, 0 505 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 506 b 4f 507 508 /* Get the PGD for the current thread. 509 */ 5103: 511 mfspr r11,SPRN_SPRG_THREAD 512 lwz r11,PGDIR(r11) 5134: 514 tophys(r11, r11) 515 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 516 lwz r12, 0(r11) /* Get L1 entry */ 517 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ 518 beq 2f /* Bail if no table */ 519 520 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ 521 lwz r11, 0(r12) /* Get Linux PTE */ 522 andi. r9, r11, _PAGE_PRESENT 523 beq 5f 524 525 ori r11, r11, _PAGE_ACCESSED 526 stw r11, 0(r12) 527 528 /* Create TLB tag. This is the faulting address plus a static 529 * set of bits. These are size, valid, E, U0. 530 */ 531 li r12, 0x00c0 532 rlwimi r10, r12, 0, 20, 31 533 534 b finish_tlb_load 535 5362: /* Check for possible large-page pmd entry */ 537 rlwinm. r9, r12, 2, 22, 24 538 beq 5f 539 540 /* Create TLB tag. This is the faulting address, plus a static 541 * set of bits (valid, E, U0) plus the size from the PMD. 542 */ 543 ori r9, r9, 0x40 544 rlwimi r10, r9, 0, 20, 31 545 mr r11, r12 546 547 b finish_tlb_load 548 5495: 550 /* The bailout. Restore registers to pre-exception conditions 551 * and call the heavyweights to help us out. 552 */ 553#ifdef CONFIG_403GCX 554 lwz r12, 12(r0) 555 lwz r11, 8(r0) 556 mtspr SPRN_PID, r12 557 mtcr r11 558 lwz r9, 4(r0) 559 lwz r12, 0(r0) 560#else 561 mfspr r12, SPRN_SPRG_SCRATCH5 562 mfspr r11, SPRN_SPRG_SCRATCH6 563 mtspr SPRN_PID, r12 564 mtcr r11 565 mfspr r9, SPRN_SPRG_SCRATCH4 566 mfspr r12, SPRN_SPRG_SCRATCH3 567#endif 568 mfspr r11, SPRN_SPRG_SCRATCH1 569 mfspr r10, SPRN_SPRG_SCRATCH0 570 b InstructionAccess 571 572 EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD) 573 EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_STD) 574 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD) 575 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD) 576#ifdef CONFIG_IBM405_ERR51 577 /* 405GP errata 51 */ 578 START_EXCEPTION(0x1700, Trap_17) 579 b DTLBMiss 580#else 581 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD) 582#endif 583 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD) 584 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD) 585 EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_STD) 586 EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_STD) 587 EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_STD) 588 EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_STD) 589 EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_STD) 590 EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_STD) 591 592/* Check for a single step debug exception while in an exception 593 * handler before state has been saved. This is to catch the case 594 * where an instruction that we are trying to single step causes 595 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 596 * the exception handler generates a single step debug exception. 597 * 598 * If we get a debug trap on the first instruction of an exception handler, 599 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 600 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 601 * The exception handler was handling a non-critical interrupt, so it will 602 * save (and later restore) the MSR via SPRN_SRR1, which will still have 603 * the MSR_DE bit set. 604 */ 605 /* 0x2000 - Debug Exception */ 606 START_EXCEPTION(0x2000, DebugTrap) 607 CRITICAL_EXCEPTION_PROLOG 608 609 /* 610 * If this is a single step or branch-taken exception in an 611 * exception entry sequence, it was probably meant to apply to 612 * the code where the exception occurred (since exception entry 613 * doesn't turn off DE automatically). We simulate the effect 614 * of turning off DE on entry to an exception handler by turning 615 * off DE in the SRR3 value and clearing the debug status. 616 */ 617 mfspr r10,SPRN_DBSR /* check single-step/branch taken */ 618 andis. r10,r10,DBSR_IC@h 619 beq+ 2f 620 621 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ 622 beq 1f /* branch and fix it up */ 623 624 mfspr r10,SPRN_SRR2 /* Faulting instruction address */ 625 cmplwi r10,0x2100 626 bgt+ 2f /* address above exception vectors */ 627 628 /* here it looks like we got an inappropriate debug exception. */ 6291: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ 630 lis r10,DBSR_IC@h /* clear the IC event */ 631 mtspr SPRN_DBSR,r10 632 /* restore state and get out */ 633 lwz r10,_CCR(r11) 634 lwz r0,GPR0(r11) 635 lwz r1,GPR1(r11) 636 mtcrf 0x80,r10 637 mtspr SPRN_SRR2,r12 638 mtspr SPRN_SRR3,r9 639 lwz r9,GPR9(r11) 640 lwz r12,GPR12(r11) 641 lwz r10,crit_r10@l(0) 642 lwz r11,crit_r11@l(0) 643 PPC405_ERR77_SYNC 644 rfci 645 b . 646 647 /* continue normal handling for a critical exception... */ 6482: mfspr r4,SPRN_DBSR 649 addi r3,r1,STACK_FRAME_OVERHEAD 650 EXC_XFER_TEMPLATE(DebugException, 0x2002, \ 651 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 652 crit_transfer_to_handler, ret_from_crit_exc) 653 654 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */ 655Decrementer: 656 EXCEPTION_PROLOG 657 lis r0,TSR_PIS@h 658 mtspr SPRN_TSR,r0 /* Clear the PIT exception */ 659 addi r3,r1,STACK_FRAME_OVERHEAD 660 EXC_XFER_LITE(0x1000, timer_interrupt) 661 662 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */ 663FITException: 664 EXCEPTION_PROLOG 665 addi r3,r1,STACK_FRAME_OVERHEAD; 666 EXC_XFER_STD(0x1010, unknown_exception) 667 668 /* Watchdog Timer (WDT) Exception. (from 0x1020) */ 669WDTException: 670 CRITICAL_EXCEPTION_PROLOG; 671 addi r3,r1,STACK_FRAME_OVERHEAD; 672 EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2, 673 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), 674 crit_transfer_to_handler, ret_from_crit_exc) 675 676/* 677 * The other Data TLB exceptions bail out to this point 678 * if they can't resolve the lightweight TLB fault. 679 */ 680DataAccess: 681 EXCEPTION_PROLOG 682 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ 683 stw r5,_ESR(r11) 684 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ 685 EXC_XFER_LITE(0x300, handle_page_fault) 686 687/* Other PowerPC processors, namely those derived from the 6xx-series 688 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. 689 * However, for the 4xx-series processors these are neither defined nor 690 * reserved. 691 */ 692 693 /* Damn, I came up one instruction too many to fit into the 694 * exception space :-). Both the instruction and data TLB 695 * miss get to this point to load the TLB. 696 * r10 - TLB_TAG value 697 * r11 - Linux PTE 698 * r12, r9 - available to use 699 * PID - loaded with proper value when we get here 700 * Upon exit, we reload everything and RFI. 701 * Actually, it will fit now, but oh well.....a common place 702 * to load the TLB. 703 */ 704tlb_4xx_index: 705 .long 0 706finish_tlb_load: 707 /* load the next available TLB index. 708 */ 709 lwz r9, tlb_4xx_index@l(0) 710 addi r9, r9, 1 711 andi. r9, r9, (PPC40X_TLB_SIZE-1) 712 stw r9, tlb_4xx_index@l(0) 713 7146: 715 /* 716 * Clear out the software-only bits in the PTE to generate the 717 * TLB_DATA value. These are the bottom 2 bits of the RPM, the 718 * top 3 bits of the zone field, and M. 719 */ 720 li r12, 0x0ce2 721 andc r11, r11, r12 722 723 tlbwe r11, r9, TLB_DATA /* Load TLB LO */ 724 tlbwe r10, r9, TLB_TAG /* Load TLB HI */ 725 726 /* Done...restore registers and get out of here. 727 */ 728#ifdef CONFIG_403GCX 729 lwz r12, 12(r0) 730 lwz r11, 8(r0) 731 mtspr SPRN_PID, r12 732 mtcr r11 733 lwz r9, 4(r0) 734 lwz r12, 0(r0) 735#else 736 mfspr r12, SPRN_SPRG_SCRATCH5 737 mfspr r11, SPRN_SPRG_SCRATCH6 738 mtspr SPRN_PID, r12 739 mtcr r11 740 mfspr r9, SPRN_SPRG_SCRATCH4 741 mfspr r12, SPRN_SPRG_SCRATCH3 742#endif 743 mfspr r11, SPRN_SPRG_SCRATCH1 744 mfspr r10, SPRN_SPRG_SCRATCH0 745 PPC405_ERR77_SYNC 746 rfi /* Should sync shadow TLBs */ 747 b . /* prevent prefetch past rfi */ 748 749/* This is where the main kernel code starts. 750 */ 751start_here: 752 753 /* ptr to current */ 754 lis r2,init_task@h 755 ori r2,r2,init_task@l 756 757 /* ptr to phys current thread */ 758 tophys(r4,r2) 759 addi r4,r4,THREAD /* init task's THREAD */ 760 mtspr SPRN_SPRG_THREAD,r4 761 762 /* stack */ 763 lis r1,init_thread_union@ha 764 addi r1,r1,init_thread_union@l 765 li r0,0 766 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 767 768 bl early_init /* We have to do this with MMU on */ 769 770/* 771 * Decide what sort of machine this is and initialize the MMU. 772 */ 773#ifdef CONFIG_KASAN 774 bl kasan_early_init 775#endif 776 li r3,0 777 mr r4,r31 778 bl machine_init 779 bl MMU_init 780 781/* Go back to running unmapped so we can load up new values 782 * and change to using our exception vectors. 783 * On the 4xx, all we have to do is invalidate the TLB to clear 784 * the old 16M byte TLB mappings. 785 */ 786 lis r4,2f@h 787 ori r4,r4,2f@l 788 tophys(r4,r4) 789 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h 790 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l 791 mtspr SPRN_SRR0,r4 792 mtspr SPRN_SRR1,r3 793 rfi 794 b . /* prevent prefetch past rfi */ 795 796/* Load up the kernel context */ 7972: 798 sync /* Flush to memory before changing TLB */ 799 tlbia 800 isync /* Flush shadow TLBs */ 801 802 /* set up the PTE pointers for the Abatron bdiGDB. 803 */ 804 lis r6, swapper_pg_dir@h 805 ori r6, r6, swapper_pg_dir@l 806 lis r5, abatron_pteptrs@h 807 ori r5, r5, abatron_pteptrs@l 808 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 809 tophys(r5,r5) 810 stw r6, 0(r5) 811 812/* Now turn on the MMU for real! */ 813 lis r4,MSR_KERNEL@h 814 ori r4,r4,MSR_KERNEL@l 815 lis r3,start_kernel@h 816 ori r3,r3,start_kernel@l 817 mtspr SPRN_SRR0,r3 818 mtspr SPRN_SRR1,r4 819 rfi /* enable MMU and jump to start_kernel */ 820 b . /* prevent prefetch past rfi */ 821 822/* Set up the initial MMU state so we can do the first level of 823 * kernel initialization. This maps the first 16 MBytes of memory 1:1 824 * virtual to physical and more importantly sets the cache mode. 825 */ 826initial_mmu: 827 tlbia /* Invalidate all TLB entries */ 828 isync 829 830 /* We should still be executing code at physical address 0x0000xxxx 831 * at this point. However, start_here is at virtual address 832 * 0xC000xxxx. So, set up a TLB mapping to cover this once 833 * translation is enabled. 834 */ 835 836 lis r3,KERNELBASE@h /* Load the kernel virtual address */ 837 ori r3,r3,KERNELBASE@l 838 tophys(r4,r3) /* Load the kernel physical address */ 839 840 iccci r0,r3 /* Invalidate the i-cache before use */ 841 842 /* Load the kernel PID. 843 */ 844 li r0,0 845 mtspr SPRN_PID,r0 846 sync 847 848 /* Configure and load one entry into TLB slots 63 */ 849 clrrwi r4,r4,10 /* Mask off the real page number */ 850 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 851 852 clrrwi r3,r3,10 /* Mask off the effective page number */ 853 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) 854 855 li r0,63 /* TLB slot 63 */ 856 857 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ 858 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ 859 860 isync 861 862 /* Establish the exception vector base 863 */ 864 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ 865 tophys(r0,r4) /* Use the physical address */ 866 mtspr SPRN_EVPR,r0 867 868 blr 869 870_GLOBAL(abort) 871 mfspr r13,SPRN_DBCR0 872 oris r13,r13,DBCR0_RST_SYSTEM@h 873 mtspr SPRN_DBCR0,r13 874 875_GLOBAL(set_context) 876 877#ifdef CONFIG_BDI_SWITCH 878 /* Context switch the PTE pointer for the Abatron BDI2000. 879 * The PGDIR is the second parameter. 880 */ 881 lis r5, abatron_pteptrs@ha 882 stw r4, abatron_pteptrs@l + 0x4(r5) 883#endif 884 sync 885 mtspr SPRN_PID,r3 886 isync /* Need an isync to flush shadow */ 887 /* TLBs after changing PID */ 888 blr 889 890/* We put a few things here that have to be page-aligned. This stuff 891 * goes at the beginning of the data segment, which is page-aligned. 892 */ 893 .data 894 .align 12 895 .globl sdata 896sdata: 897 .globl empty_zero_page 898empty_zero_page: 899 .space 4096 900EXPORT_SYMBOL(empty_zero_page) 901 .globl swapper_pg_dir 902swapper_pg_dir: 903 .space PGD_TABLE_SIZE 904 905/* Room for two PTE pointers, usually the kernel and current user pointers 906 * to their respective root page table. 907 */ 908abatron_pteptrs: 909 .space 8 910