1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 4 * Initial PowerPC version. 5 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Rewritten for PReP 7 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 8 * Low-level exception handers, MMU support, and rewrite. 9 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 10 * PowerPC 8xx modifications. 11 * Copyright (c) 1998-1999 TiVo, Inc. 12 * PowerPC 403GCX modifications. 13 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 14 * PowerPC 403GCX/405GP modifications. 15 * Copyright 2000 MontaVista Software Inc. 16 * PPC405 modifications 17 * PowerPC 403GCX/405GP modifications. 18 * Author: MontaVista Software, Inc. 19 * frank_rowand@mvista.com or source@mvista.com 20 * debbie_chu@mvista.com 21 * 22 * Module name: head_4xx.S 23 * 24 * Description: 25 * Kernel execution entry point code. 26 */ 27 28#include <linux/init.h> 29#include <linux/pgtable.h> 30#include <asm/processor.h> 31#include <asm/page.h> 32#include <asm/mmu.h> 33#include <asm/cputable.h> 34#include <asm/thread_info.h> 35#include <asm/ppc_asm.h> 36#include <asm/asm-offsets.h> 37#include <asm/ptrace.h> 38#include <asm/export.h> 39 40#include "head_32.h" 41 42/* As with the other PowerPC ports, it is expected that when code 43 * execution begins here, the following registers contain valid, yet 44 * optional, information: 45 * 46 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 47 * r4 - Starting address of the init RAM disk 48 * r5 - Ending address of the init RAM disk 49 * r6 - Start of kernel command line string (e.g. "mem=96m") 50 * r7 - End of kernel command line string 51 * 52 * This is all going to change RSN when we add bi_recs....... -- Dan 53 */ 54 __HEAD 55_ENTRY(_stext); 56_ENTRY(_start); 57 58 mr r31,r3 /* save device tree ptr */ 59 60 /* We have to turn on the MMU right away so we get cache modes 61 * set correctly. 62 */ 63 bl initial_mmu 64 65/* We now have the lower 16 Meg mapped into TLB entries, and the caches 66 * ready to work. 67 */ 68turn_on_mmu: 69 lis r0,MSR_KERNEL@h 70 ori r0,r0,MSR_KERNEL@l 71 mtspr SPRN_SRR1,r0 72 lis r0,start_here@h 73 ori r0,r0,start_here@l 74 mtspr SPRN_SRR0,r0 75 rfi /* enables MMU */ 76 b . /* prevent prefetch past rfi */ 77 78/* 79 * This area is used for temporarily saving registers during the 80 * critical exception prolog. 81 */ 82 . = 0xc0 83crit_save: 84_ENTRY(crit_r10) 85 .space 4 86_ENTRY(crit_r11) 87 .space 4 88_ENTRY(crit_srr0) 89 .space 4 90_ENTRY(crit_srr1) 91 .space 4 92_ENTRY(saved_ksp_limit) 93 .space 4 94 95/* 96 * Exception prolog for critical exceptions. This is a little different 97 * from the normal exception prolog above since a critical exception 98 * can potentially occur at any point during normal exception processing. 99 * Thus we cannot use the same SPRG registers as the normal prolog above. 100 * Instead we use a couple of words of memory at low physical addresses. 101 * This is OK since we don't support SMP on these processors. 102 */ 103#define CRITICAL_EXCEPTION_PROLOG \ 104 stw r10,crit_r10@l(0); /* save two registers to work with */\ 105 stw r11,crit_r11@l(0); \ 106 mfcr r10; /* save CR in r10 for now */\ 107 mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ 108 andi. r11,r11,MSR_PR; \ 109 lis r11,critirq_ctx@ha; \ 110 tophys(r11,r11); \ 111 lwz r11,critirq_ctx@l(r11); \ 112 beq 1f; \ 113 /* COMING FROM USER MODE */ \ 114 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 115 lwz r11,TASK_STACK-THREAD(r11); /* this thread's kernel stack */\ 1161: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\ 117 tophys(r11,r11); \ 118 stw r10,_CCR(r11); /* save various registers */\ 119 stw r12,GPR12(r11); \ 120 stw r9,GPR9(r11); \ 121 mflr r10; \ 122 stw r10,_LINK(r11); \ 123 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 124 stw r12,_DEAR(r11); /* since they may have had stuff */\ 125 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 126 stw r9,_ESR(r11); /* exception was taken */\ 127 mfspr r12,SPRN_SRR2; \ 128 stw r1,GPR1(r11); \ 129 mfspr r9,SPRN_SRR3; \ 130 stw r1,0(r11); \ 131 tovirt(r1,r11); \ 132 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 133 stw r0,GPR0(r11); \ 134 lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */\ 135 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \ 136 stw r10, 8(r11); \ 137 SAVE_4GPRS(3, r11); \ 138 SAVE_2GPRS(7, r11) 139 140 /* 141 * State at this point: 142 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE 143 * r10 saved in crit_r10 and in stack frame, trashed 144 * r11 saved in crit_r11 and in stack frame, 145 * now phys stack/exception frame pointer 146 * r12 saved in stack frame, now saved SRR2 147 * CR saved in stack frame, CR0.EQ = !SRR3.PR 148 * LR, DEAR, ESR in stack frame 149 * r1 saved in stack frame, now virt stack/excframe pointer 150 * r0, r3-r8 saved in stack frame 151 */ 152 153/* 154 * Exception vectors. 155 */ 156#define CRITICAL_EXCEPTION(n, label, hdlr) \ 157 START_EXCEPTION(n, label); \ 158 CRITICAL_EXCEPTION_PROLOG; \ 159 addi r3,r1,STACK_FRAME_OVERHEAD; \ 160 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 161 crit_transfer_to_handler, ret_from_crit_exc) 162 163/* 164 * 0x0100 - Critical Interrupt Exception 165 */ 166 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) 167 168/* 169 * 0x0200 - Machine Check Exception 170 */ 171 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 172 173/* 174 * 0x0300 - Data Storage Exception 175 * This happens for just a few reasons. U0 set (but we don't do that), 176 * or zone protection fault (user violation, write to protected page). 177 * The other Data TLB exceptions bail out to this point 178 * if they can't resolve the lightweight TLB fault. 179 */ 180 START_EXCEPTION(0x0300, DataStorage) 181 EXCEPTION_PROLOG 182 mfspr r5, SPRN_ESR /* Grab the ESR, save it, pass arg3 */ 183 stw r5, _ESR(r11) 184 mfspr r4, SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ 185 stw r4, _DEAR(r11) 186 EXC_XFER_LITE(0x300, handle_page_fault) 187 188/* 189 * 0x0400 - Instruction Storage Exception 190 * This is caused by a fetch from non-execute or guarded pages. 191 */ 192 START_EXCEPTION(0x0400, InstructionAccess) 193 EXCEPTION_PROLOG 194 mr r4,r12 /* Pass SRR0 as arg2 */ 195 stw r4, _DEAR(r11) 196 li r5,0 /* Pass zero as arg3 */ 197 EXC_XFER_LITE(0x400, handle_page_fault) 198 199/* 0x0500 - External Interrupt Exception */ 200 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 201 202/* 0x0600 - Alignment Exception */ 203 START_EXCEPTION(0x0600, Alignment) 204 EXCEPTION_PROLOG 205 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ 206 stw r4,_DEAR(r11) 207 addi r3,r1,STACK_FRAME_OVERHEAD 208 EXC_XFER_STD(0x600, alignment_exception) 209 210/* 0x0700 - Program Exception */ 211 START_EXCEPTION(0x0700, ProgramCheck) 212 EXCEPTION_PROLOG 213 mfspr r4,SPRN_ESR /* Grab the ESR and save it */ 214 stw r4,_ESR(r11) 215 addi r3,r1,STACK_FRAME_OVERHEAD 216 EXC_XFER_STD(0x700, program_check_exception) 217 218 EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_STD) 219 EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_STD) 220 EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_STD) 221 EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_STD) 222 223/* 0x0C00 - System Call Exception */ 224 START_EXCEPTION(0x0C00, SystemCall) 225 SYSCALL_ENTRY 0xc00 226/* Trap_0D is commented out to get more space for system call exception */ 227 228/* EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_STD) */ 229 EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_STD) 230 EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD) 231 232/* 0x1000 - Programmable Interval Timer (PIT) Exception */ 233 . = 0x1000 234 b Decrementer 235 236/* 0x1010 - Fixed Interval Timer (FIT) Exception 237*/ 238 . = 0x1010 239 b FITException 240 241/* 0x1020 - Watchdog Timer (WDT) Exception 242*/ 243 . = 0x1020 244 b WDTException 245 246/* 0x1100 - Data TLB Miss Exception 247 * As the name implies, translation is not in the MMU, so search the 248 * page tables and fix it. The only purpose of this function is to 249 * load TLB entries from the page table if they exist. 250 */ 251 START_EXCEPTION(0x1100, DTLBMiss) 252 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ 253 mtspr SPRN_SPRG_SCRATCH1, r11 254 mtspr SPRN_SPRG_SCRATCH3, r12 255 mtspr SPRN_SPRG_SCRATCH4, r9 256 mfcr r12 257 mfspr r9, SPRN_PID 258 mtspr SPRN_SPRG_SCRATCH5, r9 259 mfspr r10, SPRN_DEAR /* Get faulting address */ 260 261 /* If we are faulting a kernel address, we have to use the 262 * kernel page tables. 263 */ 264 lis r11, PAGE_OFFSET@h 265 cmplw r10, r11 266 blt+ 3f 267 lis r11, swapper_pg_dir@h 268 ori r11, r11, swapper_pg_dir@l 269 li r9, 0 270 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 271 b 4f 272 273 /* Get the PGD for the current thread. 274 */ 2753: 276 mfspr r11,SPRN_SPRG_THREAD 277 lwz r11,PGDIR(r11) 2784: 279 tophys(r11, r11) 280 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 281 lwz r11, 0(r11) /* Get L1 entry */ 282 andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */ 283 beq 2f /* Bail if no table */ 284 285 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ 286 lwz r11, 0(r11) /* Get Linux PTE */ 287#ifdef CONFIG_SWAP 288 li r9, _PAGE_PRESENT | _PAGE_ACCESSED 289#else 290 li r9, _PAGE_PRESENT 291#endif 292 andc. r9, r9, r11 /* Check permission */ 293 bne 5f 294 295 rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */ 296 and r9, r9, r11 /* hwwrite = dirty & rw */ 297 rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */ 298 299 /* Create TLB tag. This is the faulting address plus a static 300 * set of bits. These are size, valid, E, U0. 301 */ 302 li r9, 0x00c0 303 rlwimi r10, r9, 0, 20, 31 304 305 b finish_tlb_load 306 3072: /* Check for possible large-page pmd entry */ 308 rlwinm. r9, r11, 2, 22, 24 309 beq 5f 310 311 /* Create TLB tag. This is the faulting address, plus a static 312 * set of bits (valid, E, U0) plus the size from the PMD. 313 */ 314 ori r9, r9, 0x40 315 rlwimi r10, r9, 0, 20, 31 316 317 b finish_tlb_load 318 3195: 320 /* The bailout. Restore registers to pre-exception conditions 321 * and call the heavyweights to help us out. 322 */ 323 mfspr r9, SPRN_SPRG_SCRATCH5 324 mtspr SPRN_PID, r9 325 mtcr r12 326 mfspr r9, SPRN_SPRG_SCRATCH4 327 mfspr r12, SPRN_SPRG_SCRATCH3 328 mfspr r11, SPRN_SPRG_SCRATCH1 329 mfspr r10, SPRN_SPRG_SCRATCH0 330 b DataStorage 331 332/* 0x1200 - Instruction TLB Miss Exception 333 * Nearly the same as above, except we get our information from different 334 * registers and bailout to a different point. 335 */ 336 START_EXCEPTION(0x1200, ITLBMiss) 337 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ 338 mtspr SPRN_SPRG_SCRATCH1, r11 339 mtspr SPRN_SPRG_SCRATCH3, r12 340 mtspr SPRN_SPRG_SCRATCH4, r9 341 mfcr r12 342 mfspr r9, SPRN_PID 343 mtspr SPRN_SPRG_SCRATCH5, r9 344 mfspr r10, SPRN_SRR0 /* Get faulting address */ 345 346 /* If we are faulting a kernel address, we have to use the 347 * kernel page tables. 348 */ 349 lis r11, PAGE_OFFSET@h 350 cmplw r10, r11 351 blt+ 3f 352 lis r11, swapper_pg_dir@h 353 ori r11, r11, swapper_pg_dir@l 354 li r9, 0 355 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 356 b 4f 357 358 /* Get the PGD for the current thread. 359 */ 3603: 361 mfspr r11,SPRN_SPRG_THREAD 362 lwz r11,PGDIR(r11) 3634: 364 tophys(r11, r11) 365 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 366 lwz r11, 0(r11) /* Get L1 entry */ 367 andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */ 368 beq 2f /* Bail if no table */ 369 370 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ 371 lwz r11, 0(r11) /* Get Linux PTE */ 372#ifdef CONFIG_SWAP 373 li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 374#else 375 li r9, _PAGE_PRESENT | _PAGE_EXEC 376#endif 377 andc. r9, r9, r11 /* Check permission */ 378 bne 5f 379 380 rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */ 381 and r9, r9, r11 /* hwwrite = dirty & rw */ 382 rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */ 383 384 /* Create TLB tag. This is the faulting address plus a static 385 * set of bits. These are size, valid, E, U0. 386 */ 387 li r9, 0x00c0 388 rlwimi r10, r9, 0, 20, 31 389 390 b finish_tlb_load 391 3922: /* Check for possible large-page pmd entry */ 393 rlwinm. r9, r11, 2, 22, 24 394 beq 5f 395 396 /* Create TLB tag. This is the faulting address, plus a static 397 * set of bits (valid, E, U0) plus the size from the PMD. 398 */ 399 ori r9, r9, 0x40 400 rlwimi r10, r9, 0, 20, 31 401 402 b finish_tlb_load 403 4045: 405 /* The bailout. Restore registers to pre-exception conditions 406 * and call the heavyweights to help us out. 407 */ 408 mfspr r9, SPRN_SPRG_SCRATCH5 409 mtspr SPRN_PID, r9 410 mtcr r12 411 mfspr r9, SPRN_SPRG_SCRATCH4 412 mfspr r12, SPRN_SPRG_SCRATCH3 413 mfspr r11, SPRN_SPRG_SCRATCH1 414 mfspr r10, SPRN_SPRG_SCRATCH0 415 b InstructionAccess 416 417 EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD) 418 EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_STD) 419 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD) 420 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD) 421 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD) 422 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD) 423 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD) 424 EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_STD) 425 EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_STD) 426 EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_STD) 427 EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_STD) 428 EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_STD) 429 EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_STD) 430 431/* Check for a single step debug exception while in an exception 432 * handler before state has been saved. This is to catch the case 433 * where an instruction that we are trying to single step causes 434 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 435 * the exception handler generates a single step debug exception. 436 * 437 * If we get a debug trap on the first instruction of an exception handler, 438 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 439 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 440 * The exception handler was handling a non-critical interrupt, so it will 441 * save (and later restore) the MSR via SPRN_SRR1, which will still have 442 * the MSR_DE bit set. 443 */ 444 /* 0x2000 - Debug Exception */ 445 START_EXCEPTION(0x2000, DebugTrap) 446 CRITICAL_EXCEPTION_PROLOG 447 448 /* 449 * If this is a single step or branch-taken exception in an 450 * exception entry sequence, it was probably meant to apply to 451 * the code where the exception occurred (since exception entry 452 * doesn't turn off DE automatically). We simulate the effect 453 * of turning off DE on entry to an exception handler by turning 454 * off DE in the SRR3 value and clearing the debug status. 455 */ 456 mfspr r10,SPRN_DBSR /* check single-step/branch taken */ 457 andis. r10,r10,DBSR_IC@h 458 beq+ 2f 459 460 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ 461 beq 1f /* branch and fix it up */ 462 463 mfspr r10,SPRN_SRR2 /* Faulting instruction address */ 464 cmplwi r10,0x2100 465 bgt+ 2f /* address above exception vectors */ 466 467 /* here it looks like we got an inappropriate debug exception. */ 4681: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ 469 lis r10,DBSR_IC@h /* clear the IC event */ 470 mtspr SPRN_DBSR,r10 471 /* restore state and get out */ 472 lwz r10,_CCR(r11) 473 lwz r0,GPR0(r11) 474 lwz r1,GPR1(r11) 475 mtcrf 0x80,r10 476 mtspr SPRN_SRR2,r12 477 mtspr SPRN_SRR3,r9 478 lwz r9,GPR9(r11) 479 lwz r12,GPR12(r11) 480 lwz r10,crit_r10@l(0) 481 lwz r11,crit_r11@l(0) 482 rfci 483 b . 484 485 /* continue normal handling for a critical exception... */ 4862: mfspr r4,SPRN_DBSR 487 addi r3,r1,STACK_FRAME_OVERHEAD 488 EXC_XFER_TEMPLATE(DebugException, 0x2002, \ 489 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 490 crit_transfer_to_handler, ret_from_crit_exc) 491 492 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */ 493Decrementer: 494 EXCEPTION_PROLOG 495 lis r0,TSR_PIS@h 496 mtspr SPRN_TSR,r0 /* Clear the PIT exception */ 497 addi r3,r1,STACK_FRAME_OVERHEAD 498 EXC_XFER_LITE(0x1000, timer_interrupt) 499 500 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */ 501FITException: 502 EXCEPTION_PROLOG 503 addi r3,r1,STACK_FRAME_OVERHEAD; 504 EXC_XFER_STD(0x1010, unknown_exception) 505 506 /* Watchdog Timer (WDT) Exception. (from 0x1020) */ 507WDTException: 508 CRITICAL_EXCEPTION_PROLOG; 509 addi r3,r1,STACK_FRAME_OVERHEAD; 510 EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2, 511 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), 512 crit_transfer_to_handler, ret_from_crit_exc) 513 514/* Other PowerPC processors, namely those derived from the 6xx-series 515 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. 516 * However, for the 4xx-series processors these are neither defined nor 517 * reserved. 518 */ 519 520 /* Damn, I came up one instruction too many to fit into the 521 * exception space :-). Both the instruction and data TLB 522 * miss get to this point to load the TLB. 523 * r10 - TLB_TAG value 524 * r11 - Linux PTE 525 * r9 - available to use 526 * PID - loaded with proper value when we get here 527 * Upon exit, we reload everything and RFI. 528 * Actually, it will fit now, but oh well.....a common place 529 * to load the TLB. 530 */ 531tlb_4xx_index: 532 .long 0 533finish_tlb_load: 534 /* 535 * Clear out the software-only bits in the PTE to generate the 536 * TLB_DATA value. These are the bottom 2 bits of the RPM, the 537 * top 3 bits of the zone field, and M. 538 */ 539 li r9, 0x0ce2 540 andc r11, r11, r9 541 542 /* load the next available TLB index. */ 543 lwz r9, tlb_4xx_index@l(0) 544 addi r9, r9, 1 545 andi. r9, r9, PPC40X_TLB_SIZE - 1 546 stw r9, tlb_4xx_index@l(0) 547 548 tlbwe r11, r9, TLB_DATA /* Load TLB LO */ 549 tlbwe r10, r9, TLB_TAG /* Load TLB HI */ 550 551 /* Done...restore registers and get out of here. 552 */ 553 mfspr r9, SPRN_SPRG_SCRATCH5 554 mtspr SPRN_PID, r9 555 mtcr r12 556 mfspr r9, SPRN_SPRG_SCRATCH4 557 mfspr r12, SPRN_SPRG_SCRATCH3 558 mfspr r11, SPRN_SPRG_SCRATCH1 559 mfspr r10, SPRN_SPRG_SCRATCH0 560 rfi /* Should sync shadow TLBs */ 561 b . /* prevent prefetch past rfi */ 562 563/* This is where the main kernel code starts. 564 */ 565start_here: 566 567 /* ptr to current */ 568 lis r2,init_task@h 569 ori r2,r2,init_task@l 570 571 /* ptr to phys current thread */ 572 tophys(r4,r2) 573 addi r4,r4,THREAD /* init task's THREAD */ 574 mtspr SPRN_SPRG_THREAD,r4 575 576 /* stack */ 577 lis r1,init_thread_union@ha 578 addi r1,r1,init_thread_union@l 579 li r0,0 580 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 581 582 bl early_init /* We have to do this with MMU on */ 583 584/* 585 * Decide what sort of machine this is and initialize the MMU. 586 */ 587#ifdef CONFIG_KASAN 588 bl kasan_early_init 589#endif 590 li r3,0 591 mr r4,r31 592 bl machine_init 593 bl MMU_init 594 595/* Go back to running unmapped so we can load up new values 596 * and change to using our exception vectors. 597 * On the 4xx, all we have to do is invalidate the TLB to clear 598 * the old 16M byte TLB mappings. 599 */ 600 lis r4,2f@h 601 ori r4,r4,2f@l 602 tophys(r4,r4) 603 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h 604 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l 605 mtspr SPRN_SRR0,r4 606 mtspr SPRN_SRR1,r3 607 rfi 608 b . /* prevent prefetch past rfi */ 609 610/* Load up the kernel context */ 6112: 612 sync /* Flush to memory before changing TLB */ 613 tlbia 614 isync /* Flush shadow TLBs */ 615 616 /* set up the PTE pointers for the Abatron bdiGDB. 617 */ 618 lis r6, swapper_pg_dir@h 619 ori r6, r6, swapper_pg_dir@l 620 lis r5, abatron_pteptrs@h 621 ori r5, r5, abatron_pteptrs@l 622 stw r5, 0xf0(0) /* Must match your Abatron config file */ 623 tophys(r5,r5) 624 stw r6, 0(r5) 625 626/* Now turn on the MMU for real! */ 627 lis r4,MSR_KERNEL@h 628 ori r4,r4,MSR_KERNEL@l 629 lis r3,start_kernel@h 630 ori r3,r3,start_kernel@l 631 mtspr SPRN_SRR0,r3 632 mtspr SPRN_SRR1,r4 633 rfi /* enable MMU and jump to start_kernel */ 634 b . /* prevent prefetch past rfi */ 635 636/* Set up the initial MMU state so we can do the first level of 637 * kernel initialization. This maps the first 16 MBytes of memory 1:1 638 * virtual to physical and more importantly sets the cache mode. 639 */ 640initial_mmu: 641 tlbia /* Invalidate all TLB entries */ 642 isync 643 644 /* We should still be executing code at physical address 0x0000xxxx 645 * at this point. However, start_here is at virtual address 646 * 0xC000xxxx. So, set up a TLB mapping to cover this once 647 * translation is enabled. 648 */ 649 650 lis r3,KERNELBASE@h /* Load the kernel virtual address */ 651 ori r3,r3,KERNELBASE@l 652 tophys(r4,r3) /* Load the kernel physical address */ 653 654 iccci r0,r3 /* Invalidate the i-cache before use */ 655 656 /* Load the kernel PID. 657 */ 658 li r0,0 659 mtspr SPRN_PID,r0 660 sync 661 662 /* Configure and load one entry into TLB slots 63 */ 663 clrrwi r4,r4,10 /* Mask off the real page number */ 664 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 665 666 clrrwi r3,r3,10 /* Mask off the effective page number */ 667 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) 668 669 li r0,63 /* TLB slot 63 */ 670 671 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ 672 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ 673 674 isync 675 676 /* Establish the exception vector base 677 */ 678 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ 679 tophys(r0,r4) /* Use the physical address */ 680 mtspr SPRN_EVPR,r0 681 682 blr 683 684_GLOBAL(abort) 685 mfspr r13,SPRN_DBCR0 686 oris r13,r13,DBCR0_RST_SYSTEM@h 687 mtspr SPRN_DBCR0,r13 688 689_GLOBAL(set_context) 690 691#ifdef CONFIG_BDI_SWITCH 692 /* Context switch the PTE pointer for the Abatron BDI2000. 693 * The PGDIR is the second parameter. 694 */ 695 lis r5, abatron_pteptrs@ha 696 stw r4, abatron_pteptrs@l + 0x4(r5) 697#endif 698 sync 699 mtspr SPRN_PID,r3 700 isync /* Need an isync to flush shadow */ 701 /* TLBs after changing PID */ 702 blr 703 704/* We put a few things here that have to be page-aligned. This stuff 705 * goes at the beginning of the data segment, which is page-aligned. 706 */ 707 .data 708 .align 12 709 .globl sdata 710sdata: 711 .globl empty_zero_page 712empty_zero_page: 713 .space 4096 714EXPORT_SYMBOL(empty_zero_page) 715 .globl swapper_pg_dir 716swapper_pg_dir: 717 .space PGD_TABLE_SIZE 718 719/* Room for two PTE pointers, usually the kernel and current user pointers 720 * to their respective root page table. 721 */ 722abatron_pteptrs: 723 .space 8 724