1/* 2 * FPU support code, moved here from head.S so that it can be used 3 * by chips which use other head-whatever.S files. 4 * 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Copyright (C) 1996 Paul Mackerras. 8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 */ 16 17#include <asm/reg.h> 18#include <asm/page.h> 19#include <asm/mmu.h> 20#include <asm/pgtable.h> 21#include <asm/cputable.h> 22#include <asm/cache.h> 23#include <asm/thread_info.h> 24#include <asm/ppc_asm.h> 25#include <asm/asm-offsets.h> 26#include <asm/ptrace.h> 27#include <asm/export.h> 28#include <asm/asm-compat.h> 29 30#ifdef CONFIG_VSX 31#define __REST_32FPVSRS(n,c,base) \ 32BEGIN_FTR_SECTION \ 33 b 2f; \ 34END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 35 REST_32FPRS(n,base); \ 36 b 3f; \ 372: REST_32VSRS(n,c,base); \ 383: 39 40#define __SAVE_32FPVSRS(n,c,base) \ 41BEGIN_FTR_SECTION \ 42 b 2f; \ 43END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 44 SAVE_32FPRS(n,base); \ 45 b 3f; \ 462: SAVE_32VSRS(n,c,base); \ 473: 48#else 49#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 50#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 51#endif 52#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 53#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 54 55/* 56 * Load state from memory into FP registers including FPSCR. 57 * Assumes the caller has enabled FP in the MSR. 58 */ 59_GLOBAL(load_fp_state) 60 lfd fr0,FPSTATE_FPSCR(r3) 61 MTFSF_L(fr0) 62 REST_32FPVSRS(0, R4, R3) 63 blr 64EXPORT_SYMBOL(load_fp_state) 65 66/* 67 * Store FP state into memory, including FPSCR 68 * Assumes the caller has enabled FP in the MSR. 69 */ 70_GLOBAL(store_fp_state) 71 SAVE_32FPVSRS(0, R4, R3) 72 mffs fr0 73 stfd fr0,FPSTATE_FPSCR(r3) 74 blr 75EXPORT_SYMBOL(store_fp_state) 76 77/* 78 * This task wants to use the FPU now. 79 * On UP, disable FP for the task which had the FPU previously, 80 * and save its floating-point registers in its thread_struct. 81 * Load up this task's FP registers from its thread_struct, 82 * enable the FPU for the current task and return to the task. 83 * Note that on 32-bit this can only use registers that will be 84 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 85 */ 86_GLOBAL(load_up_fpu) 87 mfmsr r5 88 ori r5,r5,MSR_FP 89#ifdef CONFIG_VSX 90BEGIN_FTR_SECTION 91 oris r5,r5,MSR_VSX@h 92END_FTR_SECTION_IFSET(CPU_FTR_VSX) 93#endif 94 SYNC 95 MTMSRD(r5) /* enable use of fpu now */ 96 isync 97 /* enable use of FP after return */ 98#ifdef CONFIG_PPC32 99 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 100 lwz r4,THREAD_FPEXC_MODE(r5) 101 ori r9,r9,MSR_FP /* enable FP for current */ 102 or r9,r9,r4 103#else 104 ld r4,PACACURRENT(r13) 105 addi r5,r4,THREAD /* Get THREAD */ 106 lwz r4,THREAD_FPEXC_MODE(r5) 107 ori r12,r12,MSR_FP 108 or r12,r12,r4 109 std r12,_MSR(r1) 110#endif 111 /* Don't care if r4 overflows, this is desired behaviour */ 112 lbz r4,THREAD_LOAD_FP(r5) 113 addi r4,r4,1 114 stb r4,THREAD_LOAD_FP(r5) 115 addi r10,r5,THREAD_FPSTATE 116 lfd fr0,FPSTATE_FPSCR(r10) 117 MTFSF_L(fr0) 118 REST_32FPVSRS(0, R4, R10) 119 /* restore registers and return */ 120 /* we haven't used ctr or xer or lr */ 121 blr 122 123/* 124 * save_fpu(tsk) 125 * Save the floating-point registers in its thread_struct. 126 * Enables the FPU for use in the kernel on return. 127 */ 128_GLOBAL(save_fpu) 129 addi r3,r3,THREAD /* want THREAD of task */ 130 PPC_LL r6,THREAD_FPSAVEAREA(r3) 131 PPC_LL r5,PT_REGS(r3) 132 PPC_LCMPI 0,r6,0 133 bne 2f 134 addi r6,r3,THREAD_FPSTATE 1352: SAVE_32FPVSRS(0, R4, R6) 136 mffs fr0 137 stfd fr0,FPSTATE_FPSCR(r6) 138 blr 139 140/* 141 * These are used in the alignment trap handler when emulating 142 * single-precision loads and stores. 143 */ 144 145_GLOBAL(cvt_fd) 146 lfs 0,0(r3) 147 stfd 0,0(r4) 148 blr 149 150_GLOBAL(cvt_df) 151 lfd 0,0(r3) 152 stfs 0,0(r4) 153 blr 154