1/* 2 * FPU support code, moved here from head.S so that it can be used 3 * by chips which use other head-whatever.S files. 4 * 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Copyright (C) 1996 Paul Mackerras. 8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 */ 16 17#include <asm/reg.h> 18#include <asm/page.h> 19#include <asm/mmu.h> 20#include <asm/pgtable.h> 21#include <asm/cputable.h> 22#include <asm/cache.h> 23#include <asm/thread_info.h> 24#include <asm/ppc_asm.h> 25#include <asm/asm-offsets.h> 26#include <asm/ptrace.h> 27#include <asm/export.h> 28 29#ifdef CONFIG_VSX 30#define __REST_32FPVSRS(n,c,base) \ 31BEGIN_FTR_SECTION \ 32 b 2f; \ 33END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 34 REST_32FPRS(n,base); \ 35 b 3f; \ 362: REST_32VSRS(n,c,base); \ 373: 38 39#define __SAVE_32FPVSRS(n,c,base) \ 40BEGIN_FTR_SECTION \ 41 b 2f; \ 42END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 43 SAVE_32FPRS(n,base); \ 44 b 3f; \ 452: SAVE_32VSRS(n,c,base); \ 463: 47#else 48#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 49#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 50#endif 51#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 52#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 53 54/* 55 * Load state from memory into FP registers including FPSCR. 56 * Assumes the caller has enabled FP in the MSR. 57 */ 58_GLOBAL(load_fp_state) 59 lfd fr0,FPSTATE_FPSCR(r3) 60 MTFSF_L(fr0) 61 REST_32FPVSRS(0, R4, R3) 62 blr 63EXPORT_SYMBOL(load_fp_state) 64 65/* 66 * Store FP state into memory, including FPSCR 67 * Assumes the caller has enabled FP in the MSR. 68 */ 69_GLOBAL(store_fp_state) 70 SAVE_32FPVSRS(0, R4, R3) 71 mffs fr0 72 stfd fr0,FPSTATE_FPSCR(r3) 73 blr 74EXPORT_SYMBOL(store_fp_state) 75 76/* 77 * This task wants to use the FPU now. 78 * On UP, disable FP for the task which had the FPU previously, 79 * and save its floating-point registers in its thread_struct. 80 * Load up this task's FP registers from its thread_struct, 81 * enable the FPU for the current task and return to the task. 82 * Note that on 32-bit this can only use registers that will be 83 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 84 */ 85_GLOBAL(load_up_fpu) 86 mfmsr r5 87 ori r5,r5,MSR_FP 88#ifdef CONFIG_VSX 89BEGIN_FTR_SECTION 90 oris r5,r5,MSR_VSX@h 91END_FTR_SECTION_IFSET(CPU_FTR_VSX) 92#endif 93 SYNC 94 MTMSRD(r5) /* enable use of fpu now */ 95 isync 96 /* enable use of FP after return */ 97#ifdef CONFIG_PPC32 98 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 99 lwz r4,THREAD_FPEXC_MODE(r5) 100 ori r9,r9,MSR_FP /* enable FP for current */ 101 or r9,r9,r4 102#else 103 ld r4,PACACURRENT(r13) 104 addi r5,r4,THREAD /* Get THREAD */ 105 lwz r4,THREAD_FPEXC_MODE(r5) 106 ori r12,r12,MSR_FP 107 or r12,r12,r4 108 std r12,_MSR(r1) 109#endif 110 /* Don't care if r4 overflows, this is desired behaviour */ 111 lbz r4,THREAD_LOAD_FP(r5) 112 addi r4,r4,1 113 stb r4,THREAD_LOAD_FP(r5) 114 addi r10,r5,THREAD_FPSTATE 115 lfd fr0,FPSTATE_FPSCR(r10) 116 MTFSF_L(fr0) 117 REST_32FPVSRS(0, R4, R10) 118 /* restore registers and return */ 119 /* we haven't used ctr or xer or lr */ 120 blr 121 122/* 123 * save_fpu(tsk) 124 * Save the floating-point registers in its thread_struct. 125 * Enables the FPU for use in the kernel on return. 126 */ 127_GLOBAL(save_fpu) 128 addi r3,r3,THREAD /* want THREAD of task */ 129 PPC_LL r6,THREAD_FPSAVEAREA(r3) 130 PPC_LL r5,PT_REGS(r3) 131 PPC_LCMPI 0,r6,0 132 bne 2f 133 addi r6,r3,THREAD_FPSTATE 1342: SAVE_32FPVSRS(0, R4, R6) 135 mffs fr0 136 stfd fr0,FPSTATE_FPSCR(r6) 137 blr 138 139/* 140 * These are used in the alignment trap handler when emulating 141 * single-precision loads and stores. 142 */ 143 144_GLOBAL(cvt_fd) 145 lfs 0,0(r3) 146 stfd 0,0(r4) 147 blr 148 149_GLOBAL(cvt_df) 150 lfd 0,0(r3) 151 stfs 0,0(r4) 152 blr 153