1/* 2 * FPU support code, moved here from head.S so that it can be used 3 * by chips which use other head-whatever.S files. 4 * 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Copyright (C) 1996 Paul Mackerras. 8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 */ 16 17#include <asm/reg.h> 18#include <asm/page.h> 19#include <asm/mmu.h> 20#include <asm/pgtable.h> 21#include <asm/cputable.h> 22#include <asm/cache.h> 23#include <asm/thread_info.h> 24#include <asm/ppc_asm.h> 25#include <asm/asm-offsets.h> 26#include <asm/ptrace.h> 27 28#ifdef CONFIG_VSX 29#define __REST_32FPVSRS(n,c,base) \ 30BEGIN_FTR_SECTION \ 31 b 2f; \ 32END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 33 REST_32FPRS(n,base); \ 34 b 3f; \ 352: REST_32VSRS(n,c,base); \ 363: 37 38#define __SAVE_32FPVSRS(n,c,base) \ 39BEGIN_FTR_SECTION \ 40 b 2f; \ 41END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 42 SAVE_32FPRS(n,base); \ 43 b 3f; \ 442: SAVE_32VSRS(n,c,base); \ 453: 46#else 47#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 48#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 49#endif 50#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 51#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 52 53#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 54/* void do_load_up_transact_fpu(struct thread_struct *thread) 55 * 56 * This is similar to load_up_fpu but for the transactional version of the FP 57 * register set. It doesn't mess with the task MSR or valid flags. 58 * Furthermore, we don't do lazy FP with TM currently. 59 */ 60_GLOBAL(do_load_up_transact_fpu) 61 mfmsr r6 62 ori r5,r6,MSR_FP 63#ifdef CONFIG_VSX 64BEGIN_FTR_SECTION 65 oris r5,r5,MSR_VSX@h 66END_FTR_SECTION_IFSET(CPU_FTR_VSX) 67#endif 68 SYNC 69 MTMSRD(r5) 70 71 addi r7,r3,THREAD_TRANSACT_FPSTATE 72 lfd fr0,FPSTATE_FPSCR(r7) 73 MTFSF_L(fr0) 74 REST_32FPVSRS(0, R4, R7) 75 76 blr 77#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 78 79/* 80 * Enable use of the FPU, and VSX if possible, for the caller. 81 */ 82_GLOBAL(fp_enable) 83 mfmsr r3 84 ori r3,r3,MSR_FP 85#ifdef CONFIG_VSX 86BEGIN_FTR_SECTION 87 oris r3,r3,MSR_VSX@h 88END_FTR_SECTION_IFSET(CPU_FTR_VSX) 89#endif 90 SYNC 91 MTMSRD(r3) 92 isync /* (not necessary for arch 2.02 and later) */ 93 blr 94 95/* 96 * Load state from memory into FP registers including FPSCR. 97 * Assumes the caller has enabled FP in the MSR. 98 */ 99_GLOBAL(load_fp_state) 100 lfd fr0,FPSTATE_FPSCR(r3) 101 MTFSF_L(fr0) 102 REST_32FPVSRS(0, R4, R3) 103 blr 104 105/* 106 * Store FP state into memory, including FPSCR 107 * Assumes the caller has enabled FP in the MSR. 108 */ 109_GLOBAL(store_fp_state) 110 SAVE_32FPVSRS(0, R4, R3) 111 mffs fr0 112 stfd fr0,FPSTATE_FPSCR(r3) 113 blr 114 115/* 116 * This task wants to use the FPU now. 117 * On UP, disable FP for the task which had the FPU previously, 118 * and save its floating-point registers in its thread_struct. 119 * Load up this task's FP registers from its thread_struct, 120 * enable the FPU for the current task and return to the task. 121 * Note that on 32-bit this can only use registers that will be 122 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 123 */ 124_GLOBAL(load_up_fpu) 125 mfmsr r5 126 ori r5,r5,MSR_FP 127#ifdef CONFIG_VSX 128BEGIN_FTR_SECTION 129 oris r5,r5,MSR_VSX@h 130END_FTR_SECTION_IFSET(CPU_FTR_VSX) 131#endif 132 SYNC 133 MTMSRD(r5) /* enable use of fpu now */ 134 isync 135/* 136 * For SMP, we don't do lazy FPU switching because it just gets too 137 * horrendously complex, especially when a task switches from one CPU 138 * to another. Instead we call giveup_fpu in switch_to. 139 */ 140#ifndef CONFIG_SMP 141 LOAD_REG_ADDRBASE(r3, last_task_used_math) 142 toreal(r3) 143 PPC_LL r4,ADDROFF(last_task_used_math)(r3) 144 PPC_LCMPI 0,r4,0 145 beq 1f 146 toreal(r4) 147 addi r4,r4,THREAD /* want last_task_used_math->thread */ 148 addi r10,r4,THREAD_FPSTATE 149 SAVE_32FPVSRS(0, R5, R10) 150 mffs fr0 151 stfd fr0,FPSTATE_FPSCR(r10) 152 PPC_LL r5,PT_REGS(r4) 153 toreal(r5) 154 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 155 li r10,MSR_FP|MSR_FE0|MSR_FE1 156 andc r4,r4,r10 /* disable FP for previous task */ 157 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1581: 159#endif /* CONFIG_SMP */ 160 /* enable use of FP after return */ 161#ifdef CONFIG_PPC32 162 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 163 lwz r4,THREAD_FPEXC_MODE(r5) 164 ori r9,r9,MSR_FP /* enable FP for current */ 165 or r9,r9,r4 166#else 167 ld r4,PACACURRENT(r13) 168 addi r5,r4,THREAD /* Get THREAD */ 169 lwz r4,THREAD_FPEXC_MODE(r5) 170 ori r12,r12,MSR_FP 171 or r12,r12,r4 172 std r12,_MSR(r1) 173#endif 174 addi r10,r5,THREAD_FPSTATE 175 lfd fr0,FPSTATE_FPSCR(r10) 176 MTFSF_L(fr0) 177 REST_32FPVSRS(0, R4, R10) 178#ifndef CONFIG_SMP 179 subi r4,r5,THREAD 180 fromreal(r4) 181 PPC_STL r4,ADDROFF(last_task_used_math)(r3) 182#endif /* CONFIG_SMP */ 183 /* restore registers and return */ 184 /* we haven't used ctr or xer or lr */ 185 blr 186 187/* 188 * giveup_fpu(tsk) 189 * Disable FP for the task given as the argument, 190 * and save the floating-point registers in its thread_struct. 191 * Enables the FPU for use in the kernel on return. 192 */ 193_GLOBAL(giveup_fpu) 194 mfmsr r5 195 ori r5,r5,MSR_FP 196#ifdef CONFIG_VSX 197BEGIN_FTR_SECTION 198 oris r5,r5,MSR_VSX@h 199END_FTR_SECTION_IFSET(CPU_FTR_VSX) 200#endif 201 SYNC_601 202 ISYNC_601 203 MTMSRD(r5) /* enable use of fpu now */ 204 SYNC_601 205 isync 206 PPC_LCMPI 0,r3,0 207 beqlr- /* if no previous owner, done */ 208 addi r3,r3,THREAD /* want THREAD of task */ 209 PPC_LL r6,THREAD_FPSAVEAREA(r3) 210 PPC_LL r5,PT_REGS(r3) 211 PPC_LCMPI 0,r6,0 212 bne 2f 213 addi r6,r3,THREAD_FPSTATE 2142: PPC_LCMPI 0,r5,0 215 SAVE_32FPVSRS(0, R4, R6) 216 mffs fr0 217 stfd fr0,FPSTATE_FPSCR(r6) 218 beq 1f 219 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 220 li r3,MSR_FP|MSR_FE0|MSR_FE1 221#ifdef CONFIG_VSX 222BEGIN_FTR_SECTION 223 oris r3,r3,MSR_VSX@h 224END_FTR_SECTION_IFSET(CPU_FTR_VSX) 225#endif 226 andc r4,r4,r3 /* disable FP for previous task */ 227 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 2281: 229#ifndef CONFIG_SMP 230 li r5,0 231 LOAD_REG_ADDRBASE(r4,last_task_used_math) 232 PPC_STL r5,ADDROFF(last_task_used_math)(r4) 233#endif /* CONFIG_SMP */ 234 blr 235 236/* 237 * These are used in the alignment trap handler when emulating 238 * single-precision loads and stores. 239 */ 240 241_GLOBAL(cvt_fd) 242 lfs 0,0(r3) 243 stfd 0,0(r4) 244 blr 245 246_GLOBAL(cvt_df) 247 lfd 0,0(r3) 248 stfs 0,0(r4) 249 blr 250