1/* 2 * FPU support code, moved here from head.S so that it can be used 3 * by chips which use other head-whatever.S files. 4 * 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Copyright (C) 1996 Paul Mackerras. 8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 */ 16 17#include <asm/reg.h> 18#include <asm/page.h> 19#include <asm/mmu.h> 20#include <asm/pgtable.h> 21#include <asm/cputable.h> 22#include <asm/cache.h> 23#include <asm/thread_info.h> 24#include <asm/ppc_asm.h> 25#include <asm/asm-offsets.h> 26#include <asm/ptrace.h> 27#include <asm/export.h> 28 29#ifdef CONFIG_VSX 30#define __REST_32FPVSRS(n,c,base) \ 31BEGIN_FTR_SECTION \ 32 b 2f; \ 33END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 34 REST_32FPRS(n,base); \ 35 b 3f; \ 362: REST_32VSRS(n,c,base); \ 373: 38 39#define __SAVE_32FPVSRS(n,c,base) \ 40BEGIN_FTR_SECTION \ 41 b 2f; \ 42END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 43 SAVE_32FPRS(n,base); \ 44 b 3f; \ 452: SAVE_32VSRS(n,c,base); \ 463: 47#else 48#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 49#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 50#endif 51#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 52#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 53 54#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 55/* void do_load_up_transact_fpu(struct thread_struct *thread) 56 * 57 * This is similar to load_up_fpu but for the transactional version of the FP 58 * register set. It doesn't mess with the task MSR or valid flags. 59 * Furthermore, we don't do lazy FP with TM currently. 60 */ 61_GLOBAL(do_load_up_transact_fpu) 62 mfmsr r6 63 ori r5,r6,MSR_FP 64#ifdef CONFIG_VSX 65BEGIN_FTR_SECTION 66 oris r5,r5,MSR_VSX@h 67END_FTR_SECTION_IFSET(CPU_FTR_VSX) 68#endif 69 SYNC 70 MTMSRD(r5) 71 72 addi r7,r3,THREAD_TRANSACT_FPSTATE 73 lfd fr0,FPSTATE_FPSCR(r7) 74 MTFSF_L(fr0) 75 REST_32FPVSRS(0, R4, R7) 76 77 blr 78#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 79 80/* 81 * Load state from memory into FP registers including FPSCR. 82 * Assumes the caller has enabled FP in the MSR. 83 */ 84_GLOBAL(load_fp_state) 85 lfd fr0,FPSTATE_FPSCR(r3) 86 MTFSF_L(fr0) 87 REST_32FPVSRS(0, R4, R3) 88 blr 89EXPORT_SYMBOL(load_fp_state) 90 91/* 92 * Store FP state into memory, including FPSCR 93 * Assumes the caller has enabled FP in the MSR. 94 */ 95_GLOBAL(store_fp_state) 96 SAVE_32FPVSRS(0, R4, R3) 97 mffs fr0 98 stfd fr0,FPSTATE_FPSCR(r3) 99 blr 100EXPORT_SYMBOL(store_fp_state) 101 102/* 103 * This task wants to use the FPU now. 104 * On UP, disable FP for the task which had the FPU previously, 105 * and save its floating-point registers in its thread_struct. 106 * Load up this task's FP registers from its thread_struct, 107 * enable the FPU for the current task and return to the task. 108 * Note that on 32-bit this can only use registers that will be 109 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 110 */ 111_GLOBAL(load_up_fpu) 112 mfmsr r5 113 ori r5,r5,MSR_FP 114#ifdef CONFIG_VSX 115BEGIN_FTR_SECTION 116 oris r5,r5,MSR_VSX@h 117END_FTR_SECTION_IFSET(CPU_FTR_VSX) 118#endif 119 SYNC 120 MTMSRD(r5) /* enable use of fpu now */ 121 isync 122 /* enable use of FP after return */ 123#ifdef CONFIG_PPC32 124 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 125 lwz r4,THREAD_FPEXC_MODE(r5) 126 ori r9,r9,MSR_FP /* enable FP for current */ 127 or r9,r9,r4 128#else 129 ld r4,PACACURRENT(r13) 130 addi r5,r4,THREAD /* Get THREAD */ 131 lwz r4,THREAD_FPEXC_MODE(r5) 132 ori r12,r12,MSR_FP 133 or r12,r12,r4 134 std r12,_MSR(r1) 135#endif 136 /* Don't care if r4 overflows, this is desired behaviour */ 137 lbz r4,THREAD_LOAD_FP(r5) 138 addi r4,r4,1 139 stb r4,THREAD_LOAD_FP(r5) 140 addi r10,r5,THREAD_FPSTATE 141 lfd fr0,FPSTATE_FPSCR(r10) 142 MTFSF_L(fr0) 143 REST_32FPVSRS(0, R4, R10) 144 /* restore registers and return */ 145 /* we haven't used ctr or xer or lr */ 146 blr 147 148/* 149 * save_fpu(tsk) 150 * Save the floating-point registers in its thread_struct. 151 * Enables the FPU for use in the kernel on return. 152 */ 153_GLOBAL(save_fpu) 154 addi r3,r3,THREAD /* want THREAD of task */ 155 PPC_LL r6,THREAD_FPSAVEAREA(r3) 156 PPC_LL r5,PT_REGS(r3) 157 PPC_LCMPI 0,r6,0 158 bne 2f 159 addi r6,r3,THREAD_FPSTATE 1602: SAVE_32FPVSRS(0, R4, R6) 161 mffs fr0 162 stfd fr0,FPSTATE_FPSCR(r6) 163 blr 164 165/* 166 * These are used in the alignment trap handler when emulating 167 * single-precision loads and stores. 168 */ 169 170_GLOBAL(cvt_fd) 171 lfs 0,0(r3) 172 stfd 0,0(r4) 173 blr 174 175_GLOBAL(cvt_df) 176 lfd 0,0(r3) 177 stfs 0,0(r4) 178 blr 179