1/* 2 * FPU support code, moved here from head.S so that it can be used 3 * by chips which use other head-whatever.S files. 4 * 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Copyright (C) 1996 Paul Mackerras. 8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 */ 16 17#include <asm/reg.h> 18#include <asm/page.h> 19#include <asm/mmu.h> 20#include <asm/pgtable.h> 21#include <asm/cputable.h> 22#include <asm/cache.h> 23#include <asm/thread_info.h> 24#include <asm/ppc_asm.h> 25#include <asm/asm-offsets.h> 26#include <asm/ptrace.h> 27 28#ifdef CONFIG_VSX 29#define __REST_32FPVSRS(n,c,base) \ 30BEGIN_FTR_SECTION \ 31 b 2f; \ 32END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 33 REST_32FPRS(n,base); \ 34 b 3f; \ 352: REST_32VSRS(n,c,base); \ 363: 37 38#define __REST_32FPVSRS_TRANSACT(n,c,base) \ 39BEGIN_FTR_SECTION \ 40 b 2f; \ 41END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 42 REST_32FPRS_TRANSACT(n,base); \ 43 b 3f; \ 442: REST_32VSRS_TRANSACT(n,c,base); \ 453: 46 47#define __SAVE_32FPVSRS(n,c,base) \ 48BEGIN_FTR_SECTION \ 49 b 2f; \ 50END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 51 SAVE_32FPRS(n,base); \ 52 b 3f; \ 532: SAVE_32VSRS(n,c,base); \ 543: 55#else 56#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 57#define __REST_32FPVSRS_TRANSACT(n,b,base) REST_32FPRS(n, base) 58#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 59#endif 60#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 61#define REST_32FPVSRS_TRANSACT(n,c,base) \ 62 __REST_32FPVSRS_TRANSACT(n,__REG_##c,__REG_##base) 63#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 64 65/* 66 * This task wants to use the FPU now. 67 * On UP, disable FP for the task which had the FPU previously, 68 * and save its floating-point registers in its thread_struct. 69 * Load up this task's FP registers from its thread_struct, 70 * enable the FPU for the current task and return to the task. 71 */ 72_GLOBAL(load_up_fpu) 73 mfmsr r5 74 ori r5,r5,MSR_FP 75#ifdef CONFIG_VSX 76BEGIN_FTR_SECTION 77 oris r5,r5,MSR_VSX@h 78END_FTR_SECTION_IFSET(CPU_FTR_VSX) 79#endif 80 SYNC 81 MTMSRD(r5) /* enable use of fpu now */ 82 isync 83/* 84 * For SMP, we don't do lazy FPU switching because it just gets too 85 * horrendously complex, especially when a task switches from one CPU 86 * to another. Instead we call giveup_fpu in switch_to. 87 */ 88#ifndef CONFIG_SMP 89 LOAD_REG_ADDRBASE(r3, last_task_used_math) 90 toreal(r3) 91 PPC_LL r4,ADDROFF(last_task_used_math)(r3) 92 PPC_LCMPI 0,r4,0 93 beq 1f 94 toreal(r4) 95 addi r4,r4,THREAD /* want last_task_used_math->thread */ 96 SAVE_32FPVSRS(0, R5, R4) 97 mffs fr0 98 stfd fr0,THREAD_FPSCR(r4) 99 PPC_LL r5,PT_REGS(r4) 100 toreal(r5) 101 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 102 li r10,MSR_FP|MSR_FE0|MSR_FE1 103 andc r4,r4,r10 /* disable FP for previous task */ 104 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1051: 106#endif /* CONFIG_SMP */ 107 /* enable use of FP after return */ 108#ifdef CONFIG_PPC32 109 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 110 lwz r4,THREAD_FPEXC_MODE(r5) 111 ori r9,r9,MSR_FP /* enable FP for current */ 112 or r9,r9,r4 113#else 114 ld r4,PACACURRENT(r13) 115 addi r5,r4,THREAD /* Get THREAD */ 116 lwz r4,THREAD_FPEXC_MODE(r5) 117 ori r12,r12,MSR_FP 118 or r12,r12,r4 119 std r12,_MSR(r1) 120#endif 121 lfd fr0,THREAD_FPSCR(r5) 122 MTFSF_L(fr0) 123 REST_32FPVSRS(0, R4, R5) 124#ifndef CONFIG_SMP 125 subi r4,r5,THREAD 126 fromreal(r4) 127 PPC_STL r4,ADDROFF(last_task_used_math)(r3) 128#endif /* CONFIG_SMP */ 129 /* restore registers and return */ 130 /* we haven't used ctr or xer or lr */ 131 blr 132 133/* 134 * giveup_fpu(tsk) 135 * Disable FP for the task given as the argument, 136 * and save the floating-point registers in its thread_struct. 137 * Enables the FPU for use in the kernel on return. 138 */ 139_GLOBAL(giveup_fpu) 140 mfmsr r5 141 ori r5,r5,MSR_FP 142#ifdef CONFIG_VSX 143BEGIN_FTR_SECTION 144 oris r5,r5,MSR_VSX@h 145END_FTR_SECTION_IFSET(CPU_FTR_VSX) 146#endif 147 SYNC_601 148 ISYNC_601 149 MTMSRD(r5) /* enable use of fpu now */ 150 SYNC_601 151 isync 152 PPC_LCMPI 0,r3,0 153 beqlr- /* if no previous owner, done */ 154 addi r3,r3,THREAD /* want THREAD of task */ 155 PPC_LL r5,PT_REGS(r3) 156 PPC_LCMPI 0,r5,0 157 SAVE_32FPVSRS(0, R4 ,R3) 158 mffs fr0 159 stfd fr0,THREAD_FPSCR(r3) 160 beq 1f 161 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 162 li r3,MSR_FP|MSR_FE0|MSR_FE1 163#ifdef CONFIG_VSX 164BEGIN_FTR_SECTION 165 oris r3,r3,MSR_VSX@h 166END_FTR_SECTION_IFSET(CPU_FTR_VSX) 167#endif 168 andc r4,r4,r3 /* disable FP for previous task */ 169 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1701: 171#ifndef CONFIG_SMP 172 li r5,0 173 LOAD_REG_ADDRBASE(r4,last_task_used_math) 174 PPC_STL r5,ADDROFF(last_task_used_math)(r4) 175#endif /* CONFIG_SMP */ 176 blr 177 178/* 179 * These are used in the alignment trap handler when emulating 180 * single-precision loads and stores. 181 */ 182 183_GLOBAL(cvt_fd) 184 lfs 0,0(r3) 185 stfd 0,0(r4) 186 blr 187 188_GLOBAL(cvt_df) 189 lfd 0,0(r3) 190 stfs 0,0(r4) 191 blr 192