1/* 2 * FPU support code, moved here from head.S so that it can be used 3 * by chips which use other head-whatever.S files. 4 * 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Copyright (C) 1996 Paul Mackerras. 8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 */ 16 17#include <asm/reg.h> 18#include <asm/page.h> 19#include <asm/mmu.h> 20#include <asm/pgtable.h> 21#include <asm/cputable.h> 22#include <asm/cache.h> 23#include <asm/thread_info.h> 24#include <asm/ppc_asm.h> 25#include <asm/asm-offsets.h> 26#include <asm/ptrace.h> 27 28#ifdef CONFIG_VSX 29#define __REST_32FPVSRS(n,c,base) \ 30BEGIN_FTR_SECTION \ 31 b 2f; \ 32END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 33 REST_32FPRS(n,base); \ 34 b 3f; \ 352: REST_32VSRS(n,c,base); \ 363: 37 38#define __SAVE_32FPVSRS(n,c,base) \ 39BEGIN_FTR_SECTION \ 40 b 2f; \ 41END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 42 SAVE_32FPRS(n,base); \ 43 b 3f; \ 442: SAVE_32VSRS(n,c,base); \ 453: 46#else 47#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 48#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 49#endif 50#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 51#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 52 53#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 54/* void do_load_up_transact_fpu(struct thread_struct *thread) 55 * 56 * This is similar to load_up_fpu but for the transactional version of the FP 57 * register set. It doesn't mess with the task MSR or valid flags. 58 * Furthermore, we don't do lazy FP with TM currently. 59 */ 60_GLOBAL(do_load_up_transact_fpu) 61 mfmsr r6 62 ori r5,r6,MSR_FP 63#ifdef CONFIG_VSX 64BEGIN_FTR_SECTION 65 oris r5,r5,MSR_VSX@h 66END_FTR_SECTION_IFSET(CPU_FTR_VSX) 67#endif 68 SYNC 69 MTMSRD(r5) 70 71 addi r7,r3,THREAD_TRANSACT_FPSTATE 72 lfd fr0,FPSTATE_FPSCR(r7) 73 MTFSF_L(fr0) 74 REST_32FPVSRS(0, R4, R7) 75 76 /* FP/VSX off again */ 77 MTMSRD(r6) 78 SYNC 79 80 blr 81#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 82 83/* 84 * Load state from memory into FP registers including FPSCR. 85 * Assumes the caller has enabled FP in the MSR. 86 */ 87_GLOBAL(load_fp_state) 88 lfd fr0,FPSTATE_FPSCR(r3) 89 MTFSF_L(fr0) 90 REST_32FPVSRS(0, R4, R3) 91 blr 92 93/* 94 * Store FP state into memory, including FPSCR 95 * Assumes the caller has enabled FP in the MSR. 96 */ 97_GLOBAL(store_fp_state) 98 SAVE_32FPVSRS(0, R4, R3) 99 mffs fr0 100 stfd fr0,FPSTATE_FPSCR(r3) 101 blr 102 103/* 104 * This task wants to use the FPU now. 105 * On UP, disable FP for the task which had the FPU previously, 106 * and save its floating-point registers in its thread_struct. 107 * Load up this task's FP registers from its thread_struct, 108 * enable the FPU for the current task and return to the task. 109 * Note that on 32-bit this can only use registers that will be 110 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 111 */ 112_GLOBAL(load_up_fpu) 113 mfmsr r5 114 ori r5,r5,MSR_FP 115#ifdef CONFIG_VSX 116BEGIN_FTR_SECTION 117 oris r5,r5,MSR_VSX@h 118END_FTR_SECTION_IFSET(CPU_FTR_VSX) 119#endif 120 SYNC 121 MTMSRD(r5) /* enable use of fpu now */ 122 isync 123/* 124 * For SMP, we don't do lazy FPU switching because it just gets too 125 * horrendously complex, especially when a task switches from one CPU 126 * to another. Instead we call giveup_fpu in switch_to. 127 */ 128#ifndef CONFIG_SMP 129 LOAD_REG_ADDRBASE(r3, last_task_used_math) 130 toreal(r3) 131 PPC_LL r4,ADDROFF(last_task_used_math)(r3) 132 PPC_LCMPI 0,r4,0 133 beq 1f 134 toreal(r4) 135 addi r4,r4,THREAD /* want last_task_used_math->thread */ 136 addi r10,r4,THREAD_FPSTATE 137 SAVE_32FPVSRS(0, R5, R10) 138 mffs fr0 139 stfd fr0,FPSTATE_FPSCR(r10) 140 PPC_LL r5,PT_REGS(r4) 141 toreal(r5) 142 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 143 li r10,MSR_FP|MSR_FE0|MSR_FE1 144 andc r4,r4,r10 /* disable FP for previous task */ 145 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1461: 147#endif /* CONFIG_SMP */ 148 /* enable use of FP after return */ 149#ifdef CONFIG_PPC32 150 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 151 lwz r4,THREAD_FPEXC_MODE(r5) 152 ori r9,r9,MSR_FP /* enable FP for current */ 153 or r9,r9,r4 154#else 155 ld r4,PACACURRENT(r13) 156 addi r5,r4,THREAD /* Get THREAD */ 157 lwz r4,THREAD_FPEXC_MODE(r5) 158 ori r12,r12,MSR_FP 159 or r12,r12,r4 160 std r12,_MSR(r1) 161#endif 162 addi r10,r5,THREAD_FPSTATE 163 lfd fr0,FPSTATE_FPSCR(r10) 164 MTFSF_L(fr0) 165 REST_32FPVSRS(0, R4, R10) 166#ifndef CONFIG_SMP 167 subi r4,r5,THREAD 168 fromreal(r4) 169 PPC_STL r4,ADDROFF(last_task_used_math)(r3) 170#endif /* CONFIG_SMP */ 171 /* restore registers and return */ 172 /* we haven't used ctr or xer or lr */ 173 blr 174 175/* 176 * giveup_fpu(tsk) 177 * Disable FP for the task given as the argument, 178 * and save the floating-point registers in its thread_struct. 179 * Enables the FPU for use in the kernel on return. 180 */ 181_GLOBAL(giveup_fpu) 182 mfmsr r5 183 ori r5,r5,MSR_FP 184#ifdef CONFIG_VSX 185BEGIN_FTR_SECTION 186 oris r5,r5,MSR_VSX@h 187END_FTR_SECTION_IFSET(CPU_FTR_VSX) 188#endif 189 SYNC_601 190 ISYNC_601 191 MTMSRD(r5) /* enable use of fpu now */ 192 SYNC_601 193 isync 194 PPC_LCMPI 0,r3,0 195 beqlr- /* if no previous owner, done */ 196 addi r3,r3,THREAD /* want THREAD of task */ 197 PPC_LL r6,THREAD_FPSAVEAREA(r3) 198 PPC_LL r5,PT_REGS(r3) 199 PPC_LCMPI 0,r6,0 200 bne 2f 201 addi r6,r3,THREAD_FPSTATE 2022: PPC_LCMPI 0,r5,0 203 SAVE_32FPVSRS(0, R4, R6) 204 mffs fr0 205 stfd fr0,FPSTATE_FPSCR(r6) 206 beq 1f 207 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 208 li r3,MSR_FP|MSR_FE0|MSR_FE1 209#ifdef CONFIG_VSX 210BEGIN_FTR_SECTION 211 oris r3,r3,MSR_VSX@h 212END_FTR_SECTION_IFSET(CPU_FTR_VSX) 213#endif 214 andc r4,r4,r3 /* disable FP for previous task */ 215 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 2161: 217#ifndef CONFIG_SMP 218 li r5,0 219 LOAD_REG_ADDRBASE(r4,last_task_used_math) 220 PPC_STL r5,ADDROFF(last_task_used_math)(r4) 221#endif /* CONFIG_SMP */ 222 blr 223 224/* 225 * These are used in the alignment trap handler when emulating 226 * single-precision loads and stores. 227 */ 228 229_GLOBAL(cvt_fd) 230 lfs 0,0(r3) 231 stfd 0,0(r4) 232 blr 233 234_GLOBAL(cvt_df) 235 lfd 0,0(r3) 236 stfs 0,0(r4) 237 blr 238