114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 314cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 414cf11afSPaul Mackerras * 5fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 8fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9fea23bfeSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras * 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 17b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1814cf11afSPaul Mackerras#include <asm/page.h> 1914cf11afSPaul Mackerras#include <asm/mmu.h> 2014cf11afSPaul Mackerras#include <asm/pgtable.h> 2114cf11afSPaul Mackerras#include <asm/cputable.h> 2214cf11afSPaul Mackerras#include <asm/cache.h> 2314cf11afSPaul Mackerras#include <asm/thread_info.h> 2414cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2514cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2646f52210SStephen Rothwell#include <asm/ptrace.h> 279445aa1aSAl Viro#include <asm/export.h> 28ec0c464cSChristophe Leroy#include <asm/asm-compat.h> 292c86cd18SChristophe Leroy#include <asm/feature-fixups.h> 3014cf11afSPaul Mackerras 3172ffff5bSMichael Neuling#ifdef CONFIG_VSX 320b7673c3SMichael Neuling#define __REST_32FPVSRS(n,c,base) \ 3372ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3472ffff5bSMichael Neuling b 2f; \ 3572ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 3672ffff5bSMichael Neuling REST_32FPRS(n,base); \ 3772ffff5bSMichael Neuling b 3f; \ 3872ffff5bSMichael Neuling2: REST_32VSRS(n,c,base); \ 3972ffff5bSMichael Neuling3: 4072ffff5bSMichael Neuling 410b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,c,base) \ 4272ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 4372ffff5bSMichael Neuling b 2f; \ 4472ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 4572ffff5bSMichael Neuling SAVE_32FPRS(n,base); \ 4672ffff5bSMichael Neuling b 3f; \ 4772ffff5bSMichael Neuling2: SAVE_32VSRS(n,c,base); \ 4872ffff5bSMichael Neuling3: 4972ffff5bSMichael Neuling#else 500b7673c3SMichael Neuling#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 510b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 5272ffff5bSMichael Neuling#endif 530b7673c3SMichael Neuling#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 540b7673c3SMichael Neuling#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 5572ffff5bSMichael Neuling 5614cf11afSPaul Mackerras/* 5718461960SPaul Mackerras * Load state from memory into FP registers including FPSCR. 5818461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR. 5918461960SPaul Mackerras */ 6018461960SPaul Mackerras_GLOBAL(load_fp_state) 6118461960SPaul Mackerras lfd fr0,FPSTATE_FPSCR(r3) 6218461960SPaul Mackerras MTFSF_L(fr0) 6318461960SPaul Mackerras REST_32FPVSRS(0, R4, R3) 6418461960SPaul Mackerras blr 659445aa1aSAl ViroEXPORT_SYMBOL(load_fp_state) 66e2b36d59SNicholas Piggin_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */ 6718461960SPaul Mackerras 6818461960SPaul Mackerras/* 6918461960SPaul Mackerras * Store FP state into memory, including FPSCR 7018461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR. 7118461960SPaul Mackerras */ 7218461960SPaul Mackerras_GLOBAL(store_fp_state) 7318461960SPaul Mackerras SAVE_32FPVSRS(0, R4, R3) 7418461960SPaul Mackerras mffs fr0 7518461960SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r3) 7618461960SPaul Mackerras blr 779445aa1aSAl ViroEXPORT_SYMBOL(store_fp_state) 7818461960SPaul Mackerras 7918461960SPaul Mackerras/* 8014cf11afSPaul Mackerras * This task wants to use the FPU now. 8114cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 8214cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 8314cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 8414cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 85955c1cabSPaul Mackerras * Note that on 32-bit this can only use registers that will be 86955c1cabSPaul Mackerras * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 8714cf11afSPaul Mackerras */ 88b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 8914cf11afSPaul Mackerras mfmsr r5 9014cf11afSPaul Mackerras ori r5,r5,MSR_FP 91ce48b210SMichael Neuling#ifdef CONFIG_VSX 92ce48b210SMichael NeulingBEGIN_FTR_SECTION 93ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 94ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 95ce48b210SMichael Neuling#endif 9614cf11afSPaul Mackerras SYNC 9714cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 9814cf11afSPaul Mackerras isync 9914cf11afSPaul Mackerras /* enable use of FP after return */ 100b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 101ee43eb78SBenjamin Herrenschmidt mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 10214cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 10314cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 10414cf11afSPaul Mackerras or r9,r9,r4 105b85a046aSPaul Mackerras#else 106b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 107b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 108e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 109b85a046aSPaul Mackerras ori r12,r12,MSR_FP 110b85a046aSPaul Mackerras or r12,r12,r4 111b85a046aSPaul Mackerras std r12,_MSR(r1) 112b85a046aSPaul Mackerras#endif 11370fe3d98SCyril Bur /* Don't care if r4 overflows, this is desired behaviour */ 11470fe3d98SCyril Bur lbz r4,THREAD_LOAD_FP(r5) 11570fe3d98SCyril Bur addi r4,r4,1 11670fe3d98SCyril Bur stb r4,THREAD_LOAD_FP(r5) 117955c1cabSPaul Mackerras addi r10,r5,THREAD_FPSTATE 118955c1cabSPaul Mackerras lfd fr0,FPSTATE_FPSCR(r10) 1193a2c48cfSAnton Blanchard MTFSF_L(fr0) 120955c1cabSPaul Mackerras REST_32FPVSRS(0, R4, R10) 12114cf11afSPaul Mackerras /* restore registers and return */ 12214cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 1236f3d8e69SMichael Neuling blr 12414cf11afSPaul Mackerras 12514cf11afSPaul Mackerras/* 1268792468dSCyril Bur * save_fpu(tsk) 1278792468dSCyril Bur * Save the floating-point registers in its thread_struct. 12814cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 12914cf11afSPaul Mackerras */ 1308792468dSCyril Bur_GLOBAL(save_fpu) 13114cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 13218461960SPaul Mackerras PPC_LL r6,THREAD_FPSAVEAREA(r3) 1333ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 13418461960SPaul Mackerras PPC_LCMPI 0,r6,0 13518461960SPaul Mackerras bne 2f 136de79f7b9SPaul Mackerras addi r6,r3,THREAD_FPSTATE 1378792468dSCyril Bur2: SAVE_32FPVSRS(0, R4, R6) 13814cf11afSPaul Mackerras mffs fr0 139de79f7b9SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r6) 14014cf11afSPaul Mackerras blr 14125c8a78bSDavid Gibson 14225c8a78bSDavid Gibson/* 14325c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 14425c8a78bSDavid Gibson * single-precision loads and stores. 14525c8a78bSDavid Gibson */ 14625c8a78bSDavid Gibson 14725c8a78bSDavid Gibson_GLOBAL(cvt_fd) 14825c8a78bSDavid Gibson lfs 0,0(r3) 14925c8a78bSDavid Gibson stfd 0,0(r4) 15025c8a78bSDavid Gibson blr 15125c8a78bSDavid Gibson 15225c8a78bSDavid Gibson_GLOBAL(cvt_df) 15325c8a78bSDavid Gibson lfd 0,0(r3) 15425c8a78bSDavid Gibson stfs 0,0(r4) 15525c8a78bSDavid Gibson blr 156