114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 314cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 414cf11afSPaul Mackerras * 5fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 8fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9fea23bfeSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras * 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 17b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1814cf11afSPaul Mackerras#include <asm/page.h> 1914cf11afSPaul Mackerras#include <asm/mmu.h> 2014cf11afSPaul Mackerras#include <asm/pgtable.h> 2114cf11afSPaul Mackerras#include <asm/cputable.h> 2214cf11afSPaul Mackerras#include <asm/cache.h> 2314cf11afSPaul Mackerras#include <asm/thread_info.h> 2414cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2514cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2646f52210SStephen Rothwell#include <asm/ptrace.h> 2714cf11afSPaul Mackerras 2872ffff5bSMichael Neuling#ifdef CONFIG_VSX 290b7673c3SMichael Neuling#define __REST_32FPVSRS(n,c,base) \ 3072ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3172ffff5bSMichael Neuling b 2f; \ 3272ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 3372ffff5bSMichael Neuling REST_32FPRS(n,base); \ 3472ffff5bSMichael Neuling b 3f; \ 3572ffff5bSMichael Neuling2: REST_32VSRS(n,c,base); \ 3672ffff5bSMichael Neuling3: 3772ffff5bSMichael Neuling 380b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,c,base) \ 3972ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 4072ffff5bSMichael Neuling b 2f; \ 4172ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 4272ffff5bSMichael Neuling SAVE_32FPRS(n,base); \ 4372ffff5bSMichael Neuling b 3f; \ 4472ffff5bSMichael Neuling2: SAVE_32VSRS(n,c,base); \ 4572ffff5bSMichael Neuling3: 4672ffff5bSMichael Neuling#else 470b7673c3SMichael Neuling#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 480b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 4972ffff5bSMichael Neuling#endif 500b7673c3SMichael Neuling#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 510b7673c3SMichael Neuling#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 5272ffff5bSMichael Neuling 53a2dcbb32SMichael Neuling#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 54a2dcbb32SMichael Neuling/* void do_load_up_transact_fpu(struct thread_struct *thread) 55a2dcbb32SMichael Neuling * 56a2dcbb32SMichael Neuling * This is similar to load_up_fpu but for the transactional version of the FP 57a2dcbb32SMichael Neuling * register set. It doesn't mess with the task MSR or valid flags. 58a2dcbb32SMichael Neuling * Furthermore, we don't do lazy FP with TM currently. 59a2dcbb32SMichael Neuling */ 60a2dcbb32SMichael Neuling_GLOBAL(do_load_up_transact_fpu) 61a2dcbb32SMichael Neuling mfmsr r6 62a2dcbb32SMichael Neuling ori r5,r6,MSR_FP 63a2dcbb32SMichael Neuling#ifdef CONFIG_VSX 64a2dcbb32SMichael NeulingBEGIN_FTR_SECTION 65a2dcbb32SMichael Neuling oris r5,r5,MSR_VSX@h 66a2dcbb32SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 67a2dcbb32SMichael Neuling#endif 68a2dcbb32SMichael Neuling SYNC 69a2dcbb32SMichael Neuling MTMSRD(r5) 70a2dcbb32SMichael Neuling 71de79f7b9SPaul Mackerras addi r7,r3,THREAD_TRANSACT_FPSTATE 72de79f7b9SPaul Mackerras lfd fr0,FPSTATE_FPSCR(r7) 73a2dcbb32SMichael Neuling MTFSF_L(fr0) 74de79f7b9SPaul Mackerras REST_32FPVSRS(0, R4, R7) 75a2dcbb32SMichael Neuling 76a2dcbb32SMichael Neuling /* FP/VSX off again */ 77a2dcbb32SMichael Neuling MTMSRD(r6) 78a2dcbb32SMichael Neuling SYNC 79a2dcbb32SMichael Neuling 80a2dcbb32SMichael Neuling blr 81a2dcbb32SMichael Neuling#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 82a2dcbb32SMichael Neuling 8314cf11afSPaul Mackerras/* 8414cf11afSPaul Mackerras * This task wants to use the FPU now. 8514cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 8614cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 8714cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 8814cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 8914cf11afSPaul Mackerras */ 90b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 9114cf11afSPaul Mackerras mfmsr r5 9214cf11afSPaul Mackerras ori r5,r5,MSR_FP 93ce48b210SMichael Neuling#ifdef CONFIG_VSX 94ce48b210SMichael NeulingBEGIN_FTR_SECTION 95ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 96ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 97ce48b210SMichael Neuling#endif 9814cf11afSPaul Mackerras SYNC 9914cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 10014cf11afSPaul Mackerras isync 10114cf11afSPaul Mackerras/* 10214cf11afSPaul Mackerras * For SMP, we don't do lazy FPU switching because it just gets too 10314cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 10414cf11afSPaul Mackerras * to another. Instead we call giveup_fpu in switch_to. 10514cf11afSPaul Mackerras */ 10614cf11afSPaul Mackerras#ifndef CONFIG_SMP 107e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r3, last_task_used_math) 1086316222eSPaul Mackerras toreal(r3) 109e58c3495SDavid Gibson PPC_LL r4,ADDROFF(last_task_used_math)(r3) 1103ddfbcf1SDavid Gibson PPC_LCMPI 0,r4,0 11114cf11afSPaul Mackerras beq 1f 1126316222eSPaul Mackerras toreal(r4) 11314cf11afSPaul Mackerras addi r4,r4,THREAD /* want last_task_used_math->thread */ 114de79f7b9SPaul Mackerras addi r8,r4,THREAD_FPSTATE 115de79f7b9SPaul Mackerras SAVE_32FPVSRS(0, R5, R8) 11614cf11afSPaul Mackerras mffs fr0 117de79f7b9SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r8) 1183ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r4) 1196316222eSPaul Mackerras toreal(r5) 1203ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 12114cf11afSPaul Mackerras li r10,MSR_FP|MSR_FE0|MSR_FE1 12214cf11afSPaul Mackerras andc r4,r4,r10 /* disable FP for previous task */ 1233ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 12414cf11afSPaul Mackerras1: 12514cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 12614cf11afSPaul Mackerras /* enable use of FP after return */ 127b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 128ee43eb78SBenjamin Herrenschmidt mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 12914cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 13014cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 13114cf11afSPaul Mackerras or r9,r9,r4 132b85a046aSPaul Mackerras#else 133b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 134b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 135e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 136b85a046aSPaul Mackerras ori r12,r12,MSR_FP 137b85a046aSPaul Mackerras or r12,r12,r4 138b85a046aSPaul Mackerras std r12,_MSR(r1) 139b85a046aSPaul Mackerras#endif 140de79f7b9SPaul Mackerras addi r7,r5,THREAD_FPSTATE 141de79f7b9SPaul Mackerras lfd fr0,FPSTATE_FPSCR(r7) 1423a2c48cfSAnton Blanchard MTFSF_L(fr0) 143de79f7b9SPaul Mackerras REST_32FPVSRS(0, R4, R7) 14414cf11afSPaul Mackerras#ifndef CONFIG_SMP 14514cf11afSPaul Mackerras subi r4,r5,THREAD 1466316222eSPaul Mackerras fromreal(r4) 147e58c3495SDavid Gibson PPC_STL r4,ADDROFF(last_task_used_math)(r3) 14814cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 14914cf11afSPaul Mackerras /* restore registers and return */ 15014cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 1516f3d8e69SMichael Neuling blr 15214cf11afSPaul Mackerras 15314cf11afSPaul Mackerras/* 15414cf11afSPaul Mackerras * giveup_fpu(tsk) 15514cf11afSPaul Mackerras * Disable FP for the task given as the argument, 15614cf11afSPaul Mackerras * and save the floating-point registers in its thread_struct. 15714cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 15814cf11afSPaul Mackerras */ 159b85a046aSPaul Mackerras_GLOBAL(giveup_fpu) 16014cf11afSPaul Mackerras mfmsr r5 16114cf11afSPaul Mackerras ori r5,r5,MSR_FP 162ce48b210SMichael Neuling#ifdef CONFIG_VSX 163ce48b210SMichael NeulingBEGIN_FTR_SECTION 164ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 165ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 166ce48b210SMichael Neuling#endif 16714cf11afSPaul Mackerras SYNC_601 16814cf11afSPaul Mackerras ISYNC_601 16914cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 17014cf11afSPaul Mackerras SYNC_601 17114cf11afSPaul Mackerras isync 1723ddfbcf1SDavid Gibson PPC_LCMPI 0,r3,0 17314cf11afSPaul Mackerras beqlr- /* if no previous owner, done */ 17414cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 1753ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 1763ddfbcf1SDavid Gibson PPC_LCMPI 0,r5,0 177de79f7b9SPaul Mackerras addi r6,r3,THREAD_FPSTATE 178de79f7b9SPaul Mackerras SAVE_32FPVSRS(0, R4, R6) 17914cf11afSPaul Mackerras mffs fr0 180de79f7b9SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r6) 18114cf11afSPaul Mackerras beq 1f 1823ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 18314cf11afSPaul Mackerras li r3,MSR_FP|MSR_FE0|MSR_FE1 1847e875e9dSMichael Neuling#ifdef CONFIG_VSX 1857e875e9dSMichael NeulingBEGIN_FTR_SECTION 1867e875e9dSMichael Neuling oris r3,r3,MSR_VSX@h 1877e875e9dSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 1887e875e9dSMichael Neuling#endif 18914cf11afSPaul Mackerras andc r4,r4,r3 /* disable FP for previous task */ 1903ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 19114cf11afSPaul Mackerras1: 19214cf11afSPaul Mackerras#ifndef CONFIG_SMP 19314cf11afSPaul Mackerras li r5,0 194e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r4,last_task_used_math) 195e58c3495SDavid Gibson PPC_STL r5,ADDROFF(last_task_used_math)(r4) 19614cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 19714cf11afSPaul Mackerras blr 19825c8a78bSDavid Gibson 19925c8a78bSDavid Gibson/* 20025c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 20125c8a78bSDavid Gibson * single-precision loads and stores. 20225c8a78bSDavid Gibson */ 20325c8a78bSDavid Gibson 20425c8a78bSDavid Gibson_GLOBAL(cvt_fd) 20525c8a78bSDavid Gibson lfs 0,0(r3) 20625c8a78bSDavid Gibson stfd 0,0(r4) 20725c8a78bSDavid Gibson blr 20825c8a78bSDavid Gibson 20925c8a78bSDavid Gibson_GLOBAL(cvt_df) 21025c8a78bSDavid Gibson lfd 0,0(r3) 21125c8a78bSDavid Gibson stfs 0,0(r4) 21225c8a78bSDavid Gibson blr 213