114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 314cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 414cf11afSPaul Mackerras * 5fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 8fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9fea23bfeSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras * 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 17b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1814cf11afSPaul Mackerras#include <asm/page.h> 1914cf11afSPaul Mackerras#include <asm/mmu.h> 2014cf11afSPaul Mackerras#include <asm/pgtable.h> 2114cf11afSPaul Mackerras#include <asm/cputable.h> 2214cf11afSPaul Mackerras#include <asm/cache.h> 2314cf11afSPaul Mackerras#include <asm/thread_info.h> 2414cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2514cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2646f52210SStephen Rothwell#include <asm/ptrace.h> 2714cf11afSPaul Mackerras 2872ffff5bSMichael Neuling#ifdef CONFIG_VSX 290b7673c3SMichael Neuling#define __REST_32FPVSRS(n,c,base) \ 3072ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3172ffff5bSMichael Neuling b 2f; \ 3272ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 3372ffff5bSMichael Neuling REST_32FPRS(n,base); \ 3472ffff5bSMichael Neuling b 3f; \ 3572ffff5bSMichael Neuling2: REST_32VSRS(n,c,base); \ 3672ffff5bSMichael Neuling3: 3772ffff5bSMichael Neuling 388b3c34cfSMichael Neuling#define __REST_32FPVSRS_TRANSACT(n,c,base) \ 398b3c34cfSMichael NeulingBEGIN_FTR_SECTION \ 408b3c34cfSMichael Neuling b 2f; \ 418b3c34cfSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 428b3c34cfSMichael Neuling REST_32FPRS_TRANSACT(n,base); \ 438b3c34cfSMichael Neuling b 3f; \ 448b3c34cfSMichael Neuling2: REST_32VSRS_TRANSACT(n,c,base); \ 458b3c34cfSMichael Neuling3: 468b3c34cfSMichael Neuling 470b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,c,base) \ 4872ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 4972ffff5bSMichael Neuling b 2f; \ 5072ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 5172ffff5bSMichael Neuling SAVE_32FPRS(n,base); \ 5272ffff5bSMichael Neuling b 3f; \ 5372ffff5bSMichael Neuling2: SAVE_32VSRS(n,c,base); \ 5472ffff5bSMichael Neuling3: 5572ffff5bSMichael Neuling#else 560b7673c3SMichael Neuling#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 578b3c34cfSMichael Neuling#define __REST_32FPVSRS_TRANSACT(n,b,base) REST_32FPRS(n, base) 580b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 5972ffff5bSMichael Neuling#endif 600b7673c3SMichael Neuling#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 618b3c34cfSMichael Neuling#define REST_32FPVSRS_TRANSACT(n,c,base) \ 628b3c34cfSMichael Neuling __REST_32FPVSRS_TRANSACT(n,__REG_##c,__REG_##base) 630b7673c3SMichael Neuling#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 6472ffff5bSMichael Neuling 65a2dcbb32SMichael Neuling#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 66a2dcbb32SMichael Neuling/* 67a2dcbb32SMichael Neuling * Wrapper to call load_up_fpu from C. 68a2dcbb32SMichael Neuling * void do_load_up_fpu(struct pt_regs *regs); 69a2dcbb32SMichael Neuling */ 70a2dcbb32SMichael Neuling_GLOBAL(do_load_up_fpu) 71a2dcbb32SMichael Neuling mflr r0 72a2dcbb32SMichael Neuling std r0, 16(r1) 73a2dcbb32SMichael Neuling stdu r1, -112(r1) 74a2dcbb32SMichael Neuling 75a2dcbb32SMichael Neuling subi r6, r3, STACK_FRAME_OVERHEAD 76a2dcbb32SMichael Neuling /* load_up_fpu expects r12=MSR, r13=PACA, and returns 77a2dcbb32SMichael Neuling * with r12 = new MSR. 78a2dcbb32SMichael Neuling */ 79a2dcbb32SMichael Neuling ld r12,_MSR(r6) 80a2dcbb32SMichael Neuling GET_PACA(r13) 81a2dcbb32SMichael Neuling 82a2dcbb32SMichael Neuling bl load_up_fpu 83a2dcbb32SMichael Neuling std r12,_MSR(r6) 84a2dcbb32SMichael Neuling 85a2dcbb32SMichael Neuling ld r0, 112+16(r1) 86a2dcbb32SMichael Neuling addi r1, r1, 112 87a2dcbb32SMichael Neuling mtlr r0 88a2dcbb32SMichael Neuling blr 89a2dcbb32SMichael Neuling 90a2dcbb32SMichael Neuling 91a2dcbb32SMichael Neuling/* void do_load_up_transact_fpu(struct thread_struct *thread) 92a2dcbb32SMichael Neuling * 93a2dcbb32SMichael Neuling * This is similar to load_up_fpu but for the transactional version of the FP 94a2dcbb32SMichael Neuling * register set. It doesn't mess with the task MSR or valid flags. 95a2dcbb32SMichael Neuling * Furthermore, we don't do lazy FP with TM currently. 96a2dcbb32SMichael Neuling */ 97a2dcbb32SMichael Neuling_GLOBAL(do_load_up_transact_fpu) 98a2dcbb32SMichael Neuling mfmsr r6 99a2dcbb32SMichael Neuling ori r5,r6,MSR_FP 100a2dcbb32SMichael Neuling#ifdef CONFIG_VSX 101a2dcbb32SMichael NeulingBEGIN_FTR_SECTION 102a2dcbb32SMichael Neuling oris r5,r5,MSR_VSX@h 103a2dcbb32SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 104a2dcbb32SMichael Neuling#endif 105a2dcbb32SMichael Neuling SYNC 106a2dcbb32SMichael Neuling MTMSRD(r5) 107a2dcbb32SMichael Neuling 108a2dcbb32SMichael Neuling lfd fr0,THREAD_TRANSACT_FPSCR(r3) 109a2dcbb32SMichael Neuling MTFSF_L(fr0) 110a2dcbb32SMichael Neuling REST_32FPVSRS_TRANSACT(0, R4, R3) 111a2dcbb32SMichael Neuling 112a2dcbb32SMichael Neuling /* FP/VSX off again */ 113a2dcbb32SMichael Neuling MTMSRD(r6) 114a2dcbb32SMichael Neuling SYNC 115a2dcbb32SMichael Neuling 116a2dcbb32SMichael Neuling blr 117a2dcbb32SMichael Neuling#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 118a2dcbb32SMichael Neuling 11914cf11afSPaul Mackerras/* 12014cf11afSPaul Mackerras * This task wants to use the FPU now. 12114cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 12214cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 12314cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 12414cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 12514cf11afSPaul Mackerras */ 126b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 12714cf11afSPaul Mackerras mfmsr r5 12814cf11afSPaul Mackerras ori r5,r5,MSR_FP 129ce48b210SMichael Neuling#ifdef CONFIG_VSX 130ce48b210SMichael NeulingBEGIN_FTR_SECTION 131ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 132ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 133ce48b210SMichael Neuling#endif 13414cf11afSPaul Mackerras SYNC 13514cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 13614cf11afSPaul Mackerras isync 13714cf11afSPaul Mackerras/* 13814cf11afSPaul Mackerras * For SMP, we don't do lazy FPU switching because it just gets too 13914cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 14014cf11afSPaul Mackerras * to another. Instead we call giveup_fpu in switch_to. 14114cf11afSPaul Mackerras */ 14214cf11afSPaul Mackerras#ifndef CONFIG_SMP 143e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r3, last_task_used_math) 1446316222eSPaul Mackerras toreal(r3) 145e58c3495SDavid Gibson PPC_LL r4,ADDROFF(last_task_used_math)(r3) 1463ddfbcf1SDavid Gibson PPC_LCMPI 0,r4,0 14714cf11afSPaul Mackerras beq 1f 1486316222eSPaul Mackerras toreal(r4) 14914cf11afSPaul Mackerras addi r4,r4,THREAD /* want last_task_used_math->thread */ 1500b7673c3SMichael Neuling SAVE_32FPVSRS(0, R5, R4) 15114cf11afSPaul Mackerras mffs fr0 15225c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r4) 1533ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r4) 1546316222eSPaul Mackerras toreal(r5) 1553ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 15614cf11afSPaul Mackerras li r10,MSR_FP|MSR_FE0|MSR_FE1 15714cf11afSPaul Mackerras andc r4,r4,r10 /* disable FP for previous task */ 1583ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 15914cf11afSPaul Mackerras1: 16014cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 16114cf11afSPaul Mackerras /* enable use of FP after return */ 162b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 163ee43eb78SBenjamin Herrenschmidt mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 16414cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 16514cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 16614cf11afSPaul Mackerras or r9,r9,r4 167b85a046aSPaul Mackerras#else 168b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 169b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 170e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 171b85a046aSPaul Mackerras ori r12,r12,MSR_FP 172b85a046aSPaul Mackerras or r12,r12,r4 173b85a046aSPaul Mackerras std r12,_MSR(r1) 174b85a046aSPaul Mackerras#endif 17525c8a78bSDavid Gibson lfd fr0,THREAD_FPSCR(r5) 1763a2c48cfSAnton Blanchard MTFSF_L(fr0) 177c75df6f9SMichael Neuling REST_32FPVSRS(0, R4, R5) 17814cf11afSPaul Mackerras#ifndef CONFIG_SMP 17914cf11afSPaul Mackerras subi r4,r5,THREAD 1806316222eSPaul Mackerras fromreal(r4) 181e58c3495SDavid Gibson PPC_STL r4,ADDROFF(last_task_used_math)(r3) 18214cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 18314cf11afSPaul Mackerras /* restore registers and return */ 18414cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 1856f3d8e69SMichael Neuling blr 18614cf11afSPaul Mackerras 18714cf11afSPaul Mackerras/* 18814cf11afSPaul Mackerras * giveup_fpu(tsk) 18914cf11afSPaul Mackerras * Disable FP for the task given as the argument, 19014cf11afSPaul Mackerras * and save the floating-point registers in its thread_struct. 19114cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 19214cf11afSPaul Mackerras */ 193b85a046aSPaul Mackerras_GLOBAL(giveup_fpu) 19414cf11afSPaul Mackerras mfmsr r5 19514cf11afSPaul Mackerras ori r5,r5,MSR_FP 196ce48b210SMichael Neuling#ifdef CONFIG_VSX 197ce48b210SMichael NeulingBEGIN_FTR_SECTION 198ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 199ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 200ce48b210SMichael Neuling#endif 20114cf11afSPaul Mackerras SYNC_601 20214cf11afSPaul Mackerras ISYNC_601 20314cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 20414cf11afSPaul Mackerras SYNC_601 20514cf11afSPaul Mackerras isync 2063ddfbcf1SDavid Gibson PPC_LCMPI 0,r3,0 20714cf11afSPaul Mackerras beqlr- /* if no previous owner, done */ 20814cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 2093ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 2103ddfbcf1SDavid Gibson PPC_LCMPI 0,r5,0 211c75df6f9SMichael Neuling SAVE_32FPVSRS(0, R4 ,R3) 21214cf11afSPaul Mackerras mffs fr0 21325c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r3) 21414cf11afSPaul Mackerras beq 1f 2153ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 21614cf11afSPaul Mackerras li r3,MSR_FP|MSR_FE0|MSR_FE1 2177e875e9dSMichael Neuling#ifdef CONFIG_VSX 2187e875e9dSMichael NeulingBEGIN_FTR_SECTION 2197e875e9dSMichael Neuling oris r3,r3,MSR_VSX@h 2207e875e9dSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 2217e875e9dSMichael Neuling#endif 22214cf11afSPaul Mackerras andc r4,r4,r3 /* disable FP for previous task */ 2233ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 22414cf11afSPaul Mackerras1: 22514cf11afSPaul Mackerras#ifndef CONFIG_SMP 22614cf11afSPaul Mackerras li r5,0 227e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r4,last_task_used_math) 228e58c3495SDavid Gibson PPC_STL r5,ADDROFF(last_task_used_math)(r4) 22914cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 23014cf11afSPaul Mackerras blr 23125c8a78bSDavid Gibson 23225c8a78bSDavid Gibson/* 23325c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 23425c8a78bSDavid Gibson * single-precision loads and stores. 23525c8a78bSDavid Gibson */ 23625c8a78bSDavid Gibson 23725c8a78bSDavid Gibson_GLOBAL(cvt_fd) 23825c8a78bSDavid Gibson lfs 0,0(r3) 23925c8a78bSDavid Gibson stfd 0,0(r4) 24025c8a78bSDavid Gibson blr 24125c8a78bSDavid Gibson 24225c8a78bSDavid Gibson_GLOBAL(cvt_df) 24325c8a78bSDavid Gibson lfd 0,0(r3) 24425c8a78bSDavid Gibson stfs 0,0(r4) 24525c8a78bSDavid Gibson blr 246