12874c5fdSThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-or-later */ 214cf11afSPaul Mackerras/* 314cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 414cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 514cf11afSPaul Mackerras * 6fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 9fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 1014cf11afSPaul Mackerras */ 1114cf11afSPaul Mackerras 1239326182SMasahiro Yamada#include <linux/export.h> 13b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1414cf11afSPaul Mackerras#include <asm/page.h> 1514cf11afSPaul Mackerras#include <asm/mmu.h> 1614cf11afSPaul Mackerras#include <asm/cputable.h> 1714cf11afSPaul Mackerras#include <asm/cache.h> 1814cf11afSPaul Mackerras#include <asm/thread_info.h> 1914cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2014cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2146f52210SStephen Rothwell#include <asm/ptrace.h> 22ec0c464cSChristophe Leroy#include <asm/asm-compat.h> 232c86cd18SChristophe Leroy#include <asm/feature-fixups.h> 2414cf11afSPaul Mackerras 2572ffff5bSMichael Neuling#ifdef CONFIG_VSX 26*76aeadbdSTimothy Pearson#define __REST_1FPVSR(n,c,base) \ 27*76aeadbdSTimothy PearsonBEGIN_FTR_SECTION \ 28*76aeadbdSTimothy Pearson b 2f; \ 29*76aeadbdSTimothy PearsonEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 30*76aeadbdSTimothy Pearson REST_FPR(n,base); \ 31*76aeadbdSTimothy Pearson b 3f; \ 32*76aeadbdSTimothy Pearson2: REST_VSR(n,c,base); \ 33*76aeadbdSTimothy Pearson3: 34*76aeadbdSTimothy Pearson 350b7673c3SMichael Neuling#define __REST_32FPVSRS(n,c,base) \ 3672ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3772ffff5bSMichael Neuling b 2f; \ 3872ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 3972ffff5bSMichael Neuling REST_32FPRS(n,base); \ 4072ffff5bSMichael Neuling b 3f; \ 4172ffff5bSMichael Neuling2: REST_32VSRS(n,c,base); \ 4272ffff5bSMichael Neuling3: 4372ffff5bSMichael Neuling 440b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,c,base) \ 4572ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 4672ffff5bSMichael Neuling b 2f; \ 4772ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 4872ffff5bSMichael Neuling SAVE_32FPRS(n,base); \ 4972ffff5bSMichael Neuling b 3f; \ 5072ffff5bSMichael Neuling2: SAVE_32VSRS(n,c,base); \ 5172ffff5bSMichael Neuling3: 5272ffff5bSMichael Neuling#else 53*76aeadbdSTimothy Pearson#define __REST_1FPVSR(n,b,base) REST_FPR(n, base) 540b7673c3SMichael Neuling#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 550b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 5672ffff5bSMichael Neuling#endif 57*76aeadbdSTimothy Pearson#define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base) 580b7673c3SMichael Neuling#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 590b7673c3SMichael Neuling#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 6072ffff5bSMichael Neuling 6114cf11afSPaul Mackerras/* 6218461960SPaul Mackerras * Load state from memory into FP registers including FPSCR. 6318461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR. 6418461960SPaul Mackerras */ 6518461960SPaul Mackerras_GLOBAL(load_fp_state) 6618461960SPaul Mackerras lfd fr0,FPSTATE_FPSCR(r3) 6718461960SPaul Mackerras MTFSF_L(fr0) 6818461960SPaul Mackerras REST_32FPVSRS(0, R4, R3) 6918461960SPaul Mackerras blr 709445aa1aSAl ViroEXPORT_SYMBOL(load_fp_state) 71e2b36d59SNicholas Piggin_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */ 7218461960SPaul Mackerras 7318461960SPaul Mackerras/* 7418461960SPaul Mackerras * Store FP state into memory, including FPSCR 7518461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR. 7618461960SPaul Mackerras */ 7718461960SPaul Mackerras_GLOBAL(store_fp_state) 7818461960SPaul Mackerras SAVE_32FPVSRS(0, R4, R3) 7918461960SPaul Mackerras mffs fr0 8018461960SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r3) 81*76aeadbdSTimothy Pearson REST_1FPVSR(0, R4, R3) 8218461960SPaul Mackerras blr 839445aa1aSAl ViroEXPORT_SYMBOL(store_fp_state) 8418461960SPaul Mackerras 8518461960SPaul Mackerras/* 8614cf11afSPaul Mackerras * This task wants to use the FPU now. 8714cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 8814cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 8914cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 9014cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 91955c1cabSPaul Mackerras * Note that on 32-bit this can only use registers that will be 92955c1cabSPaul Mackerras * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 9314cf11afSPaul Mackerras */ 94b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 9514cf11afSPaul Mackerras mfmsr r5 96ff0b0d6eSNicholas Piggin#ifdef CONFIG_PPC_BOOK3S_64 97ff0b0d6eSNicholas Piggin /* interrupt doesn't set MSR[RI] and HPT can fault on current access */ 98ff0b0d6eSNicholas Piggin ori r5,r5,MSR_FP|MSR_RI 99ff0b0d6eSNicholas Piggin#else 10014cf11afSPaul Mackerras ori r5,r5,MSR_FP 101ff0b0d6eSNicholas Piggin#endif 102ce48b210SMichael Neuling#ifdef CONFIG_VSX 103ce48b210SMichael NeulingBEGIN_FTR_SECTION 104ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 105ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 106ce48b210SMichael Neuling#endif 10714cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 10814cf11afSPaul Mackerras isync 10914cf11afSPaul Mackerras /* enable use of FP after return */ 110b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 11151ed00e7SChristophe Leroy addi r5,r2,THREAD 11214cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 11314cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 11414cf11afSPaul Mackerras or r9,r9,r4 115b85a046aSPaul Mackerras#else 116b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 117b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 118e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 119b85a046aSPaul Mackerras ori r12,r12,MSR_FP 120b85a046aSPaul Mackerras or r12,r12,r4 121b85a046aSPaul Mackerras std r12,_MSR(r1) 12259dc5bfcSNicholas Piggin#ifdef CONFIG_PPC_BOOK3S_64 12359dc5bfcSNicholas Piggin li r4,0 12459dc5bfcSNicholas Piggin stb r4,PACASRR_VALID(r13) 12559dc5bfcSNicholas Piggin#endif 126b85a046aSPaul Mackerras#endif 127b2b46304SNicholas Piggin li r4,1 12870fe3d98SCyril Bur stb r4,THREAD_LOAD_FP(r5) 129955c1cabSPaul Mackerras addi r10,r5,THREAD_FPSTATE 130955c1cabSPaul Mackerras lfd fr0,FPSTATE_FPSCR(r10) 1313a2c48cfSAnton Blanchard MTFSF_L(fr0) 132955c1cabSPaul Mackerras REST_32FPVSRS(0, R4, R10) 13314cf11afSPaul Mackerras /* restore registers and return */ 13414cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 1356f3d8e69SMichael Neuling blr 1365f32e836SChristophe Leroy_ASM_NOKPROBE_SYMBOL(load_up_fpu) 13714cf11afSPaul Mackerras 13814cf11afSPaul Mackerras/* 1398792468dSCyril Bur * save_fpu(tsk) 1408792468dSCyril Bur * Save the floating-point registers in its thread_struct. 14114cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 14214cf11afSPaul Mackerras */ 1438792468dSCyril Bur_GLOBAL(save_fpu) 14414cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 14518461960SPaul Mackerras PPC_LL r6,THREAD_FPSAVEAREA(r3) 1463ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 14718461960SPaul Mackerras PPC_LCMPI 0,r6,0 14818461960SPaul Mackerras bne 2f 149de79f7b9SPaul Mackerras addi r6,r3,THREAD_FPSTATE 1508792468dSCyril Bur2: SAVE_32FPVSRS(0, R4, R6) 15114cf11afSPaul Mackerras mffs fr0 152de79f7b9SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r6) 153*76aeadbdSTimothy Pearson REST_1FPVSR(0, R4, R6) 15414cf11afSPaul Mackerras blr 155