114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 314cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 414cf11afSPaul Mackerras * 5fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 8fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9fea23bfeSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras * 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 17b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1814cf11afSPaul Mackerras#include <asm/page.h> 1914cf11afSPaul Mackerras#include <asm/mmu.h> 2014cf11afSPaul Mackerras#include <asm/pgtable.h> 2114cf11afSPaul Mackerras#include <asm/cputable.h> 2214cf11afSPaul Mackerras#include <asm/cache.h> 2314cf11afSPaul Mackerras#include <asm/thread_info.h> 2414cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2514cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2614cf11afSPaul Mackerras 2772ffff5bSMichael Neuling#ifdef CONFIG_VSX 2872ffff5bSMichael Neuling#define REST_32FPVSRS(n,c,base) \ 2972ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3072ffff5bSMichael Neuling b 2f; \ 3172ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 3272ffff5bSMichael Neuling REST_32FPRS(n,base); \ 3372ffff5bSMichael Neuling b 3f; \ 3472ffff5bSMichael Neuling2: REST_32VSRS(n,c,base); \ 3572ffff5bSMichael Neuling3: 3672ffff5bSMichael Neuling 3772ffff5bSMichael Neuling#define SAVE_32FPVSRS(n,c,base) \ 3872ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3972ffff5bSMichael Neuling b 2f; \ 4072ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 4172ffff5bSMichael Neuling SAVE_32FPRS(n,base); \ 4272ffff5bSMichael Neuling b 3f; \ 4372ffff5bSMichael Neuling2: SAVE_32VSRS(n,c,base); \ 4472ffff5bSMichael Neuling3: 4572ffff5bSMichael Neuling#else 4672ffff5bSMichael Neuling#define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 4772ffff5bSMichael Neuling#define SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 4872ffff5bSMichael Neuling#endif 4972ffff5bSMichael Neuling 5014cf11afSPaul Mackerras/* 5114cf11afSPaul Mackerras * This task wants to use the FPU now. 5214cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 5314cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 5414cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 5514cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 5614cf11afSPaul Mackerras */ 57b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 5814cf11afSPaul Mackerras mfmsr r5 5914cf11afSPaul Mackerras ori r5,r5,MSR_FP 6014cf11afSPaul Mackerras SYNC 6114cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 6214cf11afSPaul Mackerras isync 6314cf11afSPaul Mackerras/* 6414cf11afSPaul Mackerras * For SMP, we don't do lazy FPU switching because it just gets too 6514cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 6614cf11afSPaul Mackerras * to another. Instead we call giveup_fpu in switch_to. 6714cf11afSPaul Mackerras */ 6814cf11afSPaul Mackerras#ifndef CONFIG_SMP 69e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r3, last_task_used_math) 706316222eSPaul Mackerras toreal(r3) 71e58c3495SDavid Gibson PPC_LL r4,ADDROFF(last_task_used_math)(r3) 723ddfbcf1SDavid Gibson PPC_LCMPI 0,r4,0 7314cf11afSPaul Mackerras beq 1f 746316222eSPaul Mackerras toreal(r4) 7514cf11afSPaul Mackerras addi r4,r4,THREAD /* want last_task_used_math->thread */ 7614cf11afSPaul Mackerras SAVE_32FPRS(0, r4) 7714cf11afSPaul Mackerras mffs fr0 7825c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r4) 793ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r4) 806316222eSPaul Mackerras toreal(r5) 813ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 8214cf11afSPaul Mackerras li r10,MSR_FP|MSR_FE0|MSR_FE1 8314cf11afSPaul Mackerras andc r4,r4,r10 /* disable FP for previous task */ 843ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 8514cf11afSPaul Mackerras1: 8614cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 8714cf11afSPaul Mackerras /* enable use of FP after return */ 88b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 8914cf11afSPaul Mackerras mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ 9014cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 9114cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 9214cf11afSPaul Mackerras or r9,r9,r4 93b85a046aSPaul Mackerras#else 94b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 95b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 96e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 97b85a046aSPaul Mackerras ori r12,r12,MSR_FP 98b85a046aSPaul Mackerras or r12,r12,r4 99b85a046aSPaul Mackerras std r12,_MSR(r1) 100b85a046aSPaul Mackerras#endif 10125c8a78bSDavid Gibson lfd fr0,THREAD_FPSCR(r5) 1023a2c48cfSAnton Blanchard MTFSF_L(fr0) 10314cf11afSPaul Mackerras REST_32FPRS(0, r5) 10414cf11afSPaul Mackerras#ifndef CONFIG_SMP 10514cf11afSPaul Mackerras subi r4,r5,THREAD 1066316222eSPaul Mackerras fromreal(r4) 107e58c3495SDavid Gibson PPC_STL r4,ADDROFF(last_task_used_math)(r3) 10814cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 10914cf11afSPaul Mackerras /* restore registers and return */ 11014cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 1116f3d8e69SMichael Neuling blr 11214cf11afSPaul Mackerras 11314cf11afSPaul Mackerras/* 11414cf11afSPaul Mackerras * giveup_fpu(tsk) 11514cf11afSPaul Mackerras * Disable FP for the task given as the argument, 11614cf11afSPaul Mackerras * and save the floating-point registers in its thread_struct. 11714cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 11814cf11afSPaul Mackerras */ 119b85a046aSPaul Mackerras_GLOBAL(giveup_fpu) 12014cf11afSPaul Mackerras mfmsr r5 12114cf11afSPaul Mackerras ori r5,r5,MSR_FP 12214cf11afSPaul Mackerras SYNC_601 12314cf11afSPaul Mackerras ISYNC_601 12414cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 12514cf11afSPaul Mackerras SYNC_601 12614cf11afSPaul Mackerras isync 1273ddfbcf1SDavid Gibson PPC_LCMPI 0,r3,0 12814cf11afSPaul Mackerras beqlr- /* if no previous owner, done */ 12914cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 1303ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 1313ddfbcf1SDavid Gibson PPC_LCMPI 0,r5,0 13214cf11afSPaul Mackerras SAVE_32FPRS(0, r3) 13314cf11afSPaul Mackerras mffs fr0 13425c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r3) 13514cf11afSPaul Mackerras beq 1f 1363ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 13714cf11afSPaul Mackerras li r3,MSR_FP|MSR_FE0|MSR_FE1 13814cf11afSPaul Mackerras andc r4,r4,r3 /* disable FP for previous task */ 1393ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 14014cf11afSPaul Mackerras1: 14114cf11afSPaul Mackerras#ifndef CONFIG_SMP 14214cf11afSPaul Mackerras li r5,0 143e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r4,last_task_used_math) 144e58c3495SDavid Gibson PPC_STL r5,ADDROFF(last_task_used_math)(r4) 14514cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 14614cf11afSPaul Mackerras blr 14725c8a78bSDavid Gibson 14825c8a78bSDavid Gibson/* 14925c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 15025c8a78bSDavid Gibson * single-precision loads and stores. 15125c8a78bSDavid Gibson * We restore and save the fpscr so the task gets the same result 15225c8a78bSDavid Gibson * and exceptions as if the cpu had performed the load or store. 15325c8a78bSDavid Gibson */ 15425c8a78bSDavid Gibson 15525c8a78bSDavid Gibson_GLOBAL(cvt_fd) 15625c8a78bSDavid Gibson lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ 1573a2c48cfSAnton Blanchard MTFSF_L(0) 15825c8a78bSDavid Gibson lfs 0,0(r3) 15925c8a78bSDavid Gibson stfd 0,0(r4) 16025c8a78bSDavid Gibson mffs 0 16125c8a78bSDavid Gibson stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */ 16225c8a78bSDavid Gibson blr 16325c8a78bSDavid Gibson 16425c8a78bSDavid Gibson_GLOBAL(cvt_df) 16525c8a78bSDavid Gibson lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ 1663a2c48cfSAnton Blanchard MTFSF_L(0) 16725c8a78bSDavid Gibson lfd 0,0(r3) 16825c8a78bSDavid Gibson stfs 0,0(r4) 16925c8a78bSDavid Gibson mffs 0 17025c8a78bSDavid Gibson stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */ 17125c8a78bSDavid Gibson blr 172