xref: /openbmc/linux/arch/powerpc/kernel/fpu.S (revision 70fe3d98)
114cf11afSPaul Mackerras/*
214cf11afSPaul Mackerras *  FPU support code, moved here from head.S so that it can be used
314cf11afSPaul Mackerras *  by chips which use other head-whatever.S files.
414cf11afSPaul Mackerras *
5fea23bfeSPaul Mackerras *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6fea23bfeSPaul Mackerras *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7fea23bfeSPaul Mackerras *    Copyright (C) 1996 Paul Mackerras.
8fea23bfeSPaul Mackerras *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
9fea23bfeSPaul Mackerras *
1014cf11afSPaul Mackerras *  This program is free software; you can redistribute it and/or
1114cf11afSPaul Mackerras *  modify it under the terms of the GNU General Public License
1214cf11afSPaul Mackerras *  as published by the Free Software Foundation; either version
1314cf11afSPaul Mackerras *  2 of the License, or (at your option) any later version.
1414cf11afSPaul Mackerras *
1514cf11afSPaul Mackerras */
1614cf11afSPaul Mackerras
17b3b8dc6cSPaul Mackerras#include <asm/reg.h>
1814cf11afSPaul Mackerras#include <asm/page.h>
1914cf11afSPaul Mackerras#include <asm/mmu.h>
2014cf11afSPaul Mackerras#include <asm/pgtable.h>
2114cf11afSPaul Mackerras#include <asm/cputable.h>
2214cf11afSPaul Mackerras#include <asm/cache.h>
2314cf11afSPaul Mackerras#include <asm/thread_info.h>
2414cf11afSPaul Mackerras#include <asm/ppc_asm.h>
2514cf11afSPaul Mackerras#include <asm/asm-offsets.h>
2646f52210SStephen Rothwell#include <asm/ptrace.h>
2714cf11afSPaul Mackerras
2872ffff5bSMichael Neuling#ifdef CONFIG_VSX
290b7673c3SMichael Neuling#define __REST_32FPVSRS(n,c,base)					\
3072ffff5bSMichael NeulingBEGIN_FTR_SECTION							\
3172ffff5bSMichael Neuling	b	2f;							\
3272ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
3372ffff5bSMichael Neuling	REST_32FPRS(n,base);						\
3472ffff5bSMichael Neuling	b	3f;							\
3572ffff5bSMichael Neuling2:	REST_32VSRS(n,c,base);						\
3672ffff5bSMichael Neuling3:
3772ffff5bSMichael Neuling
380b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,c,base)					\
3972ffff5bSMichael NeulingBEGIN_FTR_SECTION							\
4072ffff5bSMichael Neuling	b	2f;							\
4172ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
4272ffff5bSMichael Neuling	SAVE_32FPRS(n,base);						\
4372ffff5bSMichael Neuling	b	3f;							\
4472ffff5bSMichael Neuling2:	SAVE_32VSRS(n,c,base);						\
4572ffff5bSMichael Neuling3:
4672ffff5bSMichael Neuling#else
470b7673c3SMichael Neuling#define __REST_32FPVSRS(n,b,base)	REST_32FPRS(n, base)
480b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,b,base)	SAVE_32FPRS(n, base)
4972ffff5bSMichael Neuling#endif
500b7673c3SMichael Neuling#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
510b7673c3SMichael Neuling#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
5272ffff5bSMichael Neuling
53a2dcbb32SMichael Neuling#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
54a2dcbb32SMichael Neuling/* void do_load_up_transact_fpu(struct thread_struct *thread)
55a2dcbb32SMichael Neuling *
56a2dcbb32SMichael Neuling * This is similar to load_up_fpu but for the transactional version of the FP
57a2dcbb32SMichael Neuling * register set.  It doesn't mess with the task MSR or valid flags.
58a2dcbb32SMichael Neuling * Furthermore, we don't do lazy FP with TM currently.
59a2dcbb32SMichael Neuling */
60a2dcbb32SMichael Neuling_GLOBAL(do_load_up_transact_fpu)
61a2dcbb32SMichael Neuling	mfmsr	r6
62a2dcbb32SMichael Neuling	ori	r5,r6,MSR_FP
63a2dcbb32SMichael Neuling#ifdef CONFIG_VSX
64a2dcbb32SMichael NeulingBEGIN_FTR_SECTION
65a2dcbb32SMichael Neuling	oris	r5,r5,MSR_VSX@h
66a2dcbb32SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX)
67a2dcbb32SMichael Neuling#endif
68a2dcbb32SMichael Neuling	SYNC
69a2dcbb32SMichael Neuling	MTMSRD(r5)
70a2dcbb32SMichael Neuling
71de79f7b9SPaul Mackerras	addi	r7,r3,THREAD_TRANSACT_FPSTATE
72de79f7b9SPaul Mackerras	lfd	fr0,FPSTATE_FPSCR(r7)
73a2dcbb32SMichael Neuling	MTFSF_L(fr0)
74de79f7b9SPaul Mackerras	REST_32FPVSRS(0, R4, R7)
75a2dcbb32SMichael Neuling
76a2dcbb32SMichael Neuling	blr
77a2dcbb32SMichael Neuling#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
78a2dcbb32SMichael Neuling
7914cf11afSPaul Mackerras/*
8018461960SPaul Mackerras * Load state from memory into FP registers including FPSCR.
8118461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR.
8218461960SPaul Mackerras */
8318461960SPaul Mackerras_GLOBAL(load_fp_state)
8418461960SPaul Mackerras	lfd	fr0,FPSTATE_FPSCR(r3)
8518461960SPaul Mackerras	MTFSF_L(fr0)
8618461960SPaul Mackerras	REST_32FPVSRS(0, R4, R3)
8718461960SPaul Mackerras	blr
8818461960SPaul Mackerras
8918461960SPaul Mackerras/*
9018461960SPaul Mackerras * Store FP state into memory, including FPSCR
9118461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR.
9218461960SPaul Mackerras */
9318461960SPaul Mackerras_GLOBAL(store_fp_state)
9418461960SPaul Mackerras	SAVE_32FPVSRS(0, R4, R3)
9518461960SPaul Mackerras	mffs	fr0
9618461960SPaul Mackerras	stfd	fr0,FPSTATE_FPSCR(r3)
9718461960SPaul Mackerras	blr
9818461960SPaul Mackerras
9918461960SPaul Mackerras/*
10014cf11afSPaul Mackerras * This task wants to use the FPU now.
10114cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously,
10214cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct.
10314cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct,
10414cf11afSPaul Mackerras * enable the FPU for the current task and return to the task.
105955c1cabSPaul Mackerras * Note that on 32-bit this can only use registers that will be
106955c1cabSPaul Mackerras * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
10714cf11afSPaul Mackerras */
108b85a046aSPaul Mackerras_GLOBAL(load_up_fpu)
10914cf11afSPaul Mackerras	mfmsr	r5
11014cf11afSPaul Mackerras	ori	r5,r5,MSR_FP
111ce48b210SMichael Neuling#ifdef CONFIG_VSX
112ce48b210SMichael NeulingBEGIN_FTR_SECTION
113ce48b210SMichael Neuling	oris	r5,r5,MSR_VSX@h
114ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX)
115ce48b210SMichael Neuling#endif
11614cf11afSPaul Mackerras	SYNC
11714cf11afSPaul Mackerras	MTMSRD(r5)			/* enable use of fpu now */
11814cf11afSPaul Mackerras	isync
11914cf11afSPaul Mackerras	/* enable use of FP after return */
120b85a046aSPaul Mackerras#ifdef CONFIG_PPC32
121ee43eb78SBenjamin Herrenschmidt	mfspr	r5,SPRN_SPRG_THREAD	/* current task's THREAD (phys) */
12214cf11afSPaul Mackerras	lwz	r4,THREAD_FPEXC_MODE(r5)
12314cf11afSPaul Mackerras	ori	r9,r9,MSR_FP		/* enable FP for current */
12414cf11afSPaul Mackerras	or	r9,r9,r4
125b85a046aSPaul Mackerras#else
126b85a046aSPaul Mackerras	ld	r4,PACACURRENT(r13)
127b85a046aSPaul Mackerras	addi	r5,r4,THREAD		/* Get THREAD */
128e2f5a3c1SPaul Mackerras	lwz	r4,THREAD_FPEXC_MODE(r5)
129b85a046aSPaul Mackerras	ori	r12,r12,MSR_FP
130b85a046aSPaul Mackerras	or	r12,r12,r4
131b85a046aSPaul Mackerras	std	r12,_MSR(r1)
132b85a046aSPaul Mackerras#endif
13370fe3d98SCyril Bur	/* Don't care if r4 overflows, this is desired behaviour */
13470fe3d98SCyril Bur	lbz	r4,THREAD_LOAD_FP(r5)
13570fe3d98SCyril Bur	addi	r4,r4,1
13670fe3d98SCyril Bur	stb	r4,THREAD_LOAD_FP(r5)
137955c1cabSPaul Mackerras	addi	r10,r5,THREAD_FPSTATE
138955c1cabSPaul Mackerras	lfd	fr0,FPSTATE_FPSCR(r10)
1393a2c48cfSAnton Blanchard	MTFSF_L(fr0)
140955c1cabSPaul Mackerras	REST_32FPVSRS(0, R4, R10)
14114cf11afSPaul Mackerras	/* restore registers and return */
14214cf11afSPaul Mackerras	/* we haven't used ctr or xer or lr */
1436f3d8e69SMichael Neuling	blr
14414cf11afSPaul Mackerras
14514cf11afSPaul Mackerras/*
14698da581eSAnton Blanchard * __giveup_fpu(tsk)
14714cf11afSPaul Mackerras * Disable FP for the task given as the argument,
14814cf11afSPaul Mackerras * and save the floating-point registers in its thread_struct.
14914cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return.
15014cf11afSPaul Mackerras */
15198da581eSAnton Blanchard_GLOBAL(__giveup_fpu)
15214cf11afSPaul Mackerras	addi	r3,r3,THREAD	        /* want THREAD of task */
15318461960SPaul Mackerras	PPC_LL	r6,THREAD_FPSAVEAREA(r3)
1543ddfbcf1SDavid Gibson	PPC_LL	r5,PT_REGS(r3)
15518461960SPaul Mackerras	PPC_LCMPI	0,r6,0
15618461960SPaul Mackerras	bne	2f
157de79f7b9SPaul Mackerras	addi	r6,r3,THREAD_FPSTATE
15818461960SPaul Mackerras2:	PPC_LCMPI	0,r5,0
159de79f7b9SPaul Mackerras	SAVE_32FPVSRS(0, R4, R6)
16014cf11afSPaul Mackerras	mffs	fr0
161de79f7b9SPaul Mackerras	stfd	fr0,FPSTATE_FPSCR(r6)
16214cf11afSPaul Mackerras	beq	1f
1633ddfbcf1SDavid Gibson	PPC_LL	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
16414cf11afSPaul Mackerras	li	r3,MSR_FP|MSR_FE0|MSR_FE1
1657e875e9dSMichael Neuling#ifdef CONFIG_VSX
1667e875e9dSMichael NeulingBEGIN_FTR_SECTION
1677e875e9dSMichael Neuling	oris	r3,r3,MSR_VSX@h
1687e875e9dSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX)
1697e875e9dSMichael Neuling#endif
17014cf11afSPaul Mackerras	andc	r4,r4,r3		/* disable FP for previous task */
1713ddfbcf1SDavid Gibson	PPC_STL	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
17214cf11afSPaul Mackerras1:
17314cf11afSPaul Mackerras	blr
17425c8a78bSDavid Gibson
17525c8a78bSDavid Gibson/*
17625c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating
17725c8a78bSDavid Gibson * single-precision loads and stores.
17825c8a78bSDavid Gibson */
17925c8a78bSDavid Gibson
18025c8a78bSDavid Gibson_GLOBAL(cvt_fd)
18125c8a78bSDavid Gibson	lfs	0,0(r3)
18225c8a78bSDavid Gibson	stfd	0,0(r4)
18325c8a78bSDavid Gibson	blr
18425c8a78bSDavid Gibson
18525c8a78bSDavid Gibson_GLOBAL(cvt_df)
18625c8a78bSDavid Gibson	lfd	0,0(r3)
18725c8a78bSDavid Gibson	stfs	0,0(r4)
18825c8a78bSDavid Gibson	blr
189