114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 314cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 414cf11afSPaul Mackerras * 5fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 8fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9fea23bfeSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras * 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 17b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1814cf11afSPaul Mackerras#include <asm/page.h> 1914cf11afSPaul Mackerras#include <asm/mmu.h> 2014cf11afSPaul Mackerras#include <asm/pgtable.h> 2114cf11afSPaul Mackerras#include <asm/cputable.h> 2214cf11afSPaul Mackerras#include <asm/cache.h> 2314cf11afSPaul Mackerras#include <asm/thread_info.h> 2414cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2514cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2614cf11afSPaul Mackerras 2714cf11afSPaul Mackerras/* 2814cf11afSPaul Mackerras * This task wants to use the FPU now. 2914cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 3014cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 3114cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 3214cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 3314cf11afSPaul Mackerras */ 34b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 3514cf11afSPaul Mackerras mfmsr r5 3614cf11afSPaul Mackerras ori r5,r5,MSR_FP 3714cf11afSPaul Mackerras SYNC 3814cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 3914cf11afSPaul Mackerras isync 4014cf11afSPaul Mackerras/* 4114cf11afSPaul Mackerras * For SMP, we don't do lazy FPU switching because it just gets too 4214cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 4314cf11afSPaul Mackerras * to another. Instead we call giveup_fpu in switch_to. 4414cf11afSPaul Mackerras */ 4514cf11afSPaul Mackerras#ifndef CONFIG_SMP 46e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r3, last_task_used_math) 476316222eSPaul Mackerras toreal(r3) 48e58c3495SDavid Gibson PPC_LL r4,ADDROFF(last_task_used_math)(r3) 493ddfbcf1SDavid Gibson PPC_LCMPI 0,r4,0 5014cf11afSPaul Mackerras beq 1f 516316222eSPaul Mackerras toreal(r4) 5214cf11afSPaul Mackerras addi r4,r4,THREAD /* want last_task_used_math->thread */ 5314cf11afSPaul Mackerras SAVE_32FPRS(0, r4) 5414cf11afSPaul Mackerras mffs fr0 5525c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r4) 563ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r4) 576316222eSPaul Mackerras toreal(r5) 583ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 5914cf11afSPaul Mackerras li r10,MSR_FP|MSR_FE0|MSR_FE1 6014cf11afSPaul Mackerras andc r4,r4,r10 /* disable FP for previous task */ 613ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 6214cf11afSPaul Mackerras1: 6314cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 6414cf11afSPaul Mackerras /* enable use of FP after return */ 65b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 6614cf11afSPaul Mackerras mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ 6714cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 6814cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 6914cf11afSPaul Mackerras or r9,r9,r4 70b85a046aSPaul Mackerras#else 71b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 72b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 73e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 74b85a046aSPaul Mackerras ori r12,r12,MSR_FP 75b85a046aSPaul Mackerras or r12,r12,r4 76b85a046aSPaul Mackerras std r12,_MSR(r1) 77b85a046aSPaul Mackerras#endif 7825c8a78bSDavid Gibson lfd fr0,THREAD_FPSCR(r5) 793a2c48cfSAnton Blanchard MTFSF_L(fr0) 8014cf11afSPaul Mackerras REST_32FPRS(0, r5) 8114cf11afSPaul Mackerras#ifndef CONFIG_SMP 8214cf11afSPaul Mackerras subi r4,r5,THREAD 836316222eSPaul Mackerras fromreal(r4) 84e58c3495SDavid Gibson PPC_STL r4,ADDROFF(last_task_used_math)(r3) 8514cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 8614cf11afSPaul Mackerras /* restore registers and return */ 8714cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 886f3d8e69SMichael Neuling blr 8914cf11afSPaul Mackerras 9014cf11afSPaul Mackerras/* 9114cf11afSPaul Mackerras * giveup_fpu(tsk) 9214cf11afSPaul Mackerras * Disable FP for the task given as the argument, 9314cf11afSPaul Mackerras * and save the floating-point registers in its thread_struct. 9414cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 9514cf11afSPaul Mackerras */ 96b85a046aSPaul Mackerras_GLOBAL(giveup_fpu) 9714cf11afSPaul Mackerras mfmsr r5 9814cf11afSPaul Mackerras ori r5,r5,MSR_FP 9914cf11afSPaul Mackerras SYNC_601 10014cf11afSPaul Mackerras ISYNC_601 10114cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 10214cf11afSPaul Mackerras SYNC_601 10314cf11afSPaul Mackerras isync 1043ddfbcf1SDavid Gibson PPC_LCMPI 0,r3,0 10514cf11afSPaul Mackerras beqlr- /* if no previous owner, done */ 10614cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 1073ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 1083ddfbcf1SDavid Gibson PPC_LCMPI 0,r5,0 10914cf11afSPaul Mackerras SAVE_32FPRS(0, r3) 11014cf11afSPaul Mackerras mffs fr0 11125c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r3) 11214cf11afSPaul Mackerras beq 1f 1133ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 11414cf11afSPaul Mackerras li r3,MSR_FP|MSR_FE0|MSR_FE1 11514cf11afSPaul Mackerras andc r4,r4,r3 /* disable FP for previous task */ 1163ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 11714cf11afSPaul Mackerras1: 11814cf11afSPaul Mackerras#ifndef CONFIG_SMP 11914cf11afSPaul Mackerras li r5,0 120e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r4,last_task_used_math) 121e58c3495SDavid Gibson PPC_STL r5,ADDROFF(last_task_used_math)(r4) 12214cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 12314cf11afSPaul Mackerras blr 12425c8a78bSDavid Gibson 12525c8a78bSDavid Gibson/* 12625c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 12725c8a78bSDavid Gibson * single-precision loads and stores. 12825c8a78bSDavid Gibson * We restore and save the fpscr so the task gets the same result 12925c8a78bSDavid Gibson * and exceptions as if the cpu had performed the load or store. 13025c8a78bSDavid Gibson */ 13125c8a78bSDavid Gibson 13225c8a78bSDavid Gibson_GLOBAL(cvt_fd) 13325c8a78bSDavid Gibson lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ 1343a2c48cfSAnton Blanchard MTFSF_L(0) 13525c8a78bSDavid Gibson lfs 0,0(r3) 13625c8a78bSDavid Gibson stfd 0,0(r4) 13725c8a78bSDavid Gibson mffs 0 13825c8a78bSDavid Gibson stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */ 13925c8a78bSDavid Gibson blr 14025c8a78bSDavid Gibson 14125c8a78bSDavid Gibson_GLOBAL(cvt_df) 14225c8a78bSDavid Gibson lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ 1433a2c48cfSAnton Blanchard MTFSF_L(0) 14425c8a78bSDavid Gibson lfd 0,0(r3) 14525c8a78bSDavid Gibson stfs 0,0(r4) 14625c8a78bSDavid Gibson mffs 0 14725c8a78bSDavid Gibson stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */ 14825c8a78bSDavid Gibson blr 149