12874c5fdSThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-or-later */ 214cf11afSPaul Mackerras/* 314cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 414cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 514cf11afSPaul Mackerras * 6fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 9fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 1014cf11afSPaul Mackerras */ 1114cf11afSPaul Mackerras 12b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1314cf11afSPaul Mackerras#include <asm/page.h> 1414cf11afSPaul Mackerras#include <asm/mmu.h> 1514cf11afSPaul Mackerras#include <asm/pgtable.h> 1614cf11afSPaul Mackerras#include <asm/cputable.h> 1714cf11afSPaul Mackerras#include <asm/cache.h> 1814cf11afSPaul Mackerras#include <asm/thread_info.h> 1914cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2014cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2146f52210SStephen Rothwell#include <asm/ptrace.h> 229445aa1aSAl Viro#include <asm/export.h> 23ec0c464cSChristophe Leroy#include <asm/asm-compat.h> 242c86cd18SChristophe Leroy#include <asm/feature-fixups.h> 2514cf11afSPaul Mackerras 2672ffff5bSMichael Neuling#ifdef CONFIG_VSX 270b7673c3SMichael Neuling#define __REST_32FPVSRS(n,c,base) \ 2872ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 2972ffff5bSMichael Neuling b 2f; \ 3072ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 3172ffff5bSMichael Neuling REST_32FPRS(n,base); \ 3272ffff5bSMichael Neuling b 3f; \ 3372ffff5bSMichael Neuling2: REST_32VSRS(n,c,base); \ 3472ffff5bSMichael Neuling3: 3572ffff5bSMichael Neuling 360b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,c,base) \ 3772ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3872ffff5bSMichael Neuling b 2f; \ 3972ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 4072ffff5bSMichael Neuling SAVE_32FPRS(n,base); \ 4172ffff5bSMichael Neuling b 3f; \ 4272ffff5bSMichael Neuling2: SAVE_32VSRS(n,c,base); \ 4372ffff5bSMichael Neuling3: 4472ffff5bSMichael Neuling#else 450b7673c3SMichael Neuling#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 460b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 4772ffff5bSMichael Neuling#endif 480b7673c3SMichael Neuling#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 490b7673c3SMichael Neuling#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 5072ffff5bSMichael Neuling 5114cf11afSPaul Mackerras/* 5218461960SPaul Mackerras * Load state from memory into FP registers including FPSCR. 5318461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR. 5418461960SPaul Mackerras */ 5518461960SPaul Mackerras_GLOBAL(load_fp_state) 5618461960SPaul Mackerras lfd fr0,FPSTATE_FPSCR(r3) 5718461960SPaul Mackerras MTFSF_L(fr0) 5818461960SPaul Mackerras REST_32FPVSRS(0, R4, R3) 5918461960SPaul Mackerras blr 609445aa1aSAl ViroEXPORT_SYMBOL(load_fp_state) 61e2b36d59SNicholas Piggin_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */ 6218461960SPaul Mackerras 6318461960SPaul Mackerras/* 6418461960SPaul Mackerras * Store FP state into memory, including FPSCR 6518461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR. 6618461960SPaul Mackerras */ 6718461960SPaul Mackerras_GLOBAL(store_fp_state) 6818461960SPaul Mackerras SAVE_32FPVSRS(0, R4, R3) 6918461960SPaul Mackerras mffs fr0 7018461960SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r3) 7118461960SPaul Mackerras blr 729445aa1aSAl ViroEXPORT_SYMBOL(store_fp_state) 7318461960SPaul Mackerras 7418461960SPaul Mackerras/* 7514cf11afSPaul Mackerras * This task wants to use the FPU now. 7614cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 7714cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 7814cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 7914cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 80955c1cabSPaul Mackerras * Note that on 32-bit this can only use registers that will be 81955c1cabSPaul Mackerras * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 8214cf11afSPaul Mackerras */ 83b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 8414cf11afSPaul Mackerras mfmsr r5 8514cf11afSPaul Mackerras ori r5,r5,MSR_FP 86ce48b210SMichael Neuling#ifdef CONFIG_VSX 87ce48b210SMichael NeulingBEGIN_FTR_SECTION 88ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 89ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 90ce48b210SMichael Neuling#endif 9114cf11afSPaul Mackerras SYNC 9214cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 9314cf11afSPaul Mackerras isync 9414cf11afSPaul Mackerras /* enable use of FP after return */ 95b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 96ee43eb78SBenjamin Herrenschmidt mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 97cd08f109SChristophe Leroy#ifdef CONFIG_VMAP_STACK 98cd08f109SChristophe Leroy tovirt(r5, r5) 99cd08f109SChristophe Leroy#endif 10014cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 10114cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 10214cf11afSPaul Mackerras or r9,r9,r4 103b85a046aSPaul Mackerras#else 104b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 105b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 106e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 107b85a046aSPaul Mackerras ori r12,r12,MSR_FP 108b85a046aSPaul Mackerras or r12,r12,r4 109b85a046aSPaul Mackerras std r12,_MSR(r1) 110b85a046aSPaul Mackerras#endif 11170fe3d98SCyril Bur /* Don't care if r4 overflows, this is desired behaviour */ 11270fe3d98SCyril Bur lbz r4,THREAD_LOAD_FP(r5) 11370fe3d98SCyril Bur addi r4,r4,1 11470fe3d98SCyril Bur stb r4,THREAD_LOAD_FP(r5) 115955c1cabSPaul Mackerras addi r10,r5,THREAD_FPSTATE 116955c1cabSPaul Mackerras lfd fr0,FPSTATE_FPSCR(r10) 1173a2c48cfSAnton Blanchard MTFSF_L(fr0) 118955c1cabSPaul Mackerras REST_32FPVSRS(0, R4, R10) 11914cf11afSPaul Mackerras /* restore registers and return */ 12014cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 1216f3d8e69SMichael Neuling blr 1225f32e836SChristophe Leroy_ASM_NOKPROBE_SYMBOL(load_up_fpu) 12314cf11afSPaul Mackerras 12414cf11afSPaul Mackerras/* 1258792468dSCyril Bur * save_fpu(tsk) 1268792468dSCyril Bur * Save the floating-point registers in its thread_struct. 12714cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 12814cf11afSPaul Mackerras */ 1298792468dSCyril Bur_GLOBAL(save_fpu) 13014cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 13118461960SPaul Mackerras PPC_LL r6,THREAD_FPSAVEAREA(r3) 1323ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 13318461960SPaul Mackerras PPC_LCMPI 0,r6,0 13418461960SPaul Mackerras bne 2f 135de79f7b9SPaul Mackerras addi r6,r3,THREAD_FPSTATE 1368792468dSCyril Bur2: SAVE_32FPVSRS(0, R4, R6) 13714cf11afSPaul Mackerras mffs fr0 138de79f7b9SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r6) 13914cf11afSPaul Mackerras blr 14025c8a78bSDavid Gibson 14125c8a78bSDavid Gibson/* 14225c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 14325c8a78bSDavid Gibson * single-precision loads and stores. 14425c8a78bSDavid Gibson */ 14525c8a78bSDavid Gibson 14625c8a78bSDavid Gibson_GLOBAL(cvt_fd) 14725c8a78bSDavid Gibson lfs 0,0(r3) 14825c8a78bSDavid Gibson stfd 0,0(r4) 14925c8a78bSDavid Gibson blr 15025c8a78bSDavid Gibson 15125c8a78bSDavid Gibson_GLOBAL(cvt_df) 15225c8a78bSDavid Gibson lfd 0,0(r3) 15325c8a78bSDavid Gibson stfs 0,0(r4) 15425c8a78bSDavid Gibson blr 155