114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 314cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 414cf11afSPaul Mackerras * 514cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 614cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 714cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 814cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 914cf11afSPaul Mackerras * 1014cf11afSPaul Mackerras */ 1114cf11afSPaul Mackerras 1214cf11afSPaul Mackerras#include <linux/config.h> 13b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1414cf11afSPaul Mackerras#include <asm/page.h> 1514cf11afSPaul Mackerras#include <asm/mmu.h> 1614cf11afSPaul Mackerras#include <asm/pgtable.h> 1714cf11afSPaul Mackerras#include <asm/cputable.h> 1814cf11afSPaul Mackerras#include <asm/cache.h> 1914cf11afSPaul Mackerras#include <asm/thread_info.h> 2014cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2114cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2214cf11afSPaul Mackerras 2314cf11afSPaul Mackerras/* 2414cf11afSPaul Mackerras * This task wants to use the FPU now. 2514cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 2614cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 2714cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 2814cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 2914cf11afSPaul Mackerras */ 30b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 3114cf11afSPaul Mackerras mfmsr r5 3214cf11afSPaul Mackerras ori r5,r5,MSR_FP 3314cf11afSPaul Mackerras SYNC 3414cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 3514cf11afSPaul Mackerras isync 3614cf11afSPaul Mackerras/* 3714cf11afSPaul Mackerras * For SMP, we don't do lazy FPU switching because it just gets too 3814cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 3914cf11afSPaul Mackerras * to another. Instead we call giveup_fpu in switch_to. 4014cf11afSPaul Mackerras */ 4114cf11afSPaul Mackerras#ifndef CONFIG_SMP 42e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r3, last_task_used_math) 436316222eSPaul Mackerras toreal(r3) 44e58c3495SDavid Gibson PPC_LL r4,ADDROFF(last_task_used_math)(r3) 453ddfbcf1SDavid Gibson PPC_LCMPI 0,r4,0 4614cf11afSPaul Mackerras beq 1f 476316222eSPaul Mackerras toreal(r4) 4814cf11afSPaul Mackerras addi r4,r4,THREAD /* want last_task_used_math->thread */ 4914cf11afSPaul Mackerras SAVE_32FPRS(0, r4) 5014cf11afSPaul Mackerras mffs fr0 5125c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r4) 523ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r4) 536316222eSPaul Mackerras toreal(r5) 543ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 5514cf11afSPaul Mackerras li r10,MSR_FP|MSR_FE0|MSR_FE1 5614cf11afSPaul Mackerras andc r4,r4,r10 /* disable FP for previous task */ 573ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 5814cf11afSPaul Mackerras1: 5914cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 6014cf11afSPaul Mackerras /* enable use of FP after return */ 61b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 6214cf11afSPaul Mackerras mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ 6314cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 6414cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 6514cf11afSPaul Mackerras or r9,r9,r4 66b85a046aSPaul Mackerras#else 67b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 68b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 69e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 70b85a046aSPaul Mackerras ori r12,r12,MSR_FP 71b85a046aSPaul Mackerras or r12,r12,r4 72b85a046aSPaul Mackerras std r12,_MSR(r1) 73b85a046aSPaul Mackerras#endif 7425c8a78bSDavid Gibson lfd fr0,THREAD_FPSCR(r5) 753a2c48cfSAnton Blanchard MTFSF_L(fr0) 7614cf11afSPaul Mackerras REST_32FPRS(0, r5) 7714cf11afSPaul Mackerras#ifndef CONFIG_SMP 7814cf11afSPaul Mackerras subi r4,r5,THREAD 796316222eSPaul Mackerras fromreal(r4) 80e58c3495SDavid Gibson PPC_STL r4,ADDROFF(last_task_used_math)(r3) 8114cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 8214cf11afSPaul Mackerras /* restore registers and return */ 8314cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 8414cf11afSPaul Mackerras b fast_exception_return 8514cf11afSPaul Mackerras 8614cf11afSPaul Mackerras/* 8714cf11afSPaul Mackerras * giveup_fpu(tsk) 8814cf11afSPaul Mackerras * Disable FP for the task given as the argument, 8914cf11afSPaul Mackerras * and save the floating-point registers in its thread_struct. 9014cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 9114cf11afSPaul Mackerras */ 92b85a046aSPaul Mackerras_GLOBAL(giveup_fpu) 9314cf11afSPaul Mackerras mfmsr r5 9414cf11afSPaul Mackerras ori r5,r5,MSR_FP 9514cf11afSPaul Mackerras SYNC_601 9614cf11afSPaul Mackerras ISYNC_601 9714cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 9814cf11afSPaul Mackerras SYNC_601 9914cf11afSPaul Mackerras isync 1003ddfbcf1SDavid Gibson PPC_LCMPI 0,r3,0 10114cf11afSPaul Mackerras beqlr- /* if no previous owner, done */ 10214cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 1033ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 1043ddfbcf1SDavid Gibson PPC_LCMPI 0,r5,0 10514cf11afSPaul Mackerras SAVE_32FPRS(0, r3) 10614cf11afSPaul Mackerras mffs fr0 10725c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r3) 10814cf11afSPaul Mackerras beq 1f 1093ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 11014cf11afSPaul Mackerras li r3,MSR_FP|MSR_FE0|MSR_FE1 11114cf11afSPaul Mackerras andc r4,r4,r3 /* disable FP for previous task */ 1123ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 11314cf11afSPaul Mackerras1: 11414cf11afSPaul Mackerras#ifndef CONFIG_SMP 11514cf11afSPaul Mackerras li r5,0 116e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r4,last_task_used_math) 117e58c3495SDavid Gibson PPC_STL r5,ADDROFF(last_task_used_math)(r4) 11814cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 11914cf11afSPaul Mackerras blr 12025c8a78bSDavid Gibson 12125c8a78bSDavid Gibson/* 12225c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 12325c8a78bSDavid Gibson * single-precision loads and stores. 12425c8a78bSDavid Gibson * We restore and save the fpscr so the task gets the same result 12525c8a78bSDavid Gibson * and exceptions as if the cpu had performed the load or store. 12625c8a78bSDavid Gibson */ 12725c8a78bSDavid Gibson 12825c8a78bSDavid Gibson_GLOBAL(cvt_fd) 12925c8a78bSDavid Gibson lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ 1303a2c48cfSAnton Blanchard MTFSF_L(0) 13125c8a78bSDavid Gibson lfs 0,0(r3) 13225c8a78bSDavid Gibson stfd 0,0(r4) 13325c8a78bSDavid Gibson mffs 0 13425c8a78bSDavid Gibson stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */ 13525c8a78bSDavid Gibson blr 13625c8a78bSDavid Gibson 13725c8a78bSDavid Gibson_GLOBAL(cvt_df) 13825c8a78bSDavid Gibson lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ 1393a2c48cfSAnton Blanchard MTFSF_L(0) 14025c8a78bSDavid Gibson lfd 0,0(r3) 14125c8a78bSDavid Gibson stfs 0,0(r4) 14225c8a78bSDavid Gibson mffs 0 14325c8a78bSDavid Gibson stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */ 14425c8a78bSDavid Gibson blr 145