114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 314cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 414cf11afSPaul Mackerras * 5fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 8fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9fea23bfeSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras * 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 17b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1814cf11afSPaul Mackerras#include <asm/page.h> 1914cf11afSPaul Mackerras#include <asm/mmu.h> 2014cf11afSPaul Mackerras#include <asm/pgtable.h> 2114cf11afSPaul Mackerras#include <asm/cputable.h> 2214cf11afSPaul Mackerras#include <asm/cache.h> 2314cf11afSPaul Mackerras#include <asm/thread_info.h> 2414cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2514cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2646f52210SStephen Rothwell#include <asm/ptrace.h> 2714cf11afSPaul Mackerras 2872ffff5bSMichael Neuling#ifdef CONFIG_VSX 290b7673c3SMichael Neuling#define __REST_32FPVSRS(n,c,base) \ 3072ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3172ffff5bSMichael Neuling b 2f; \ 3272ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 3372ffff5bSMichael Neuling REST_32FPRS(n,base); \ 3472ffff5bSMichael Neuling b 3f; \ 3572ffff5bSMichael Neuling2: REST_32VSRS(n,c,base); \ 3672ffff5bSMichael Neuling3: 3772ffff5bSMichael Neuling 380b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,c,base) \ 3972ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 4072ffff5bSMichael Neuling b 2f; \ 4172ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 4272ffff5bSMichael Neuling SAVE_32FPRS(n,base); \ 4372ffff5bSMichael Neuling b 3f; \ 4472ffff5bSMichael Neuling2: SAVE_32VSRS(n,c,base); \ 4572ffff5bSMichael Neuling3: 4672ffff5bSMichael Neuling#else 470b7673c3SMichael Neuling#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 480b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 4972ffff5bSMichael Neuling#endif 500b7673c3SMichael Neuling#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 510b7673c3SMichael Neuling#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 5272ffff5bSMichael Neuling 53a2dcbb32SMichael Neuling#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 54a2dcbb32SMichael Neuling/* void do_load_up_transact_fpu(struct thread_struct *thread) 55a2dcbb32SMichael Neuling * 56a2dcbb32SMichael Neuling * This is similar to load_up_fpu but for the transactional version of the FP 57a2dcbb32SMichael Neuling * register set. It doesn't mess with the task MSR or valid flags. 58a2dcbb32SMichael Neuling * Furthermore, we don't do lazy FP with TM currently. 59a2dcbb32SMichael Neuling */ 60a2dcbb32SMichael Neuling_GLOBAL(do_load_up_transact_fpu) 61a2dcbb32SMichael Neuling mfmsr r6 62a2dcbb32SMichael Neuling ori r5,r6,MSR_FP 63a2dcbb32SMichael Neuling#ifdef CONFIG_VSX 64a2dcbb32SMichael NeulingBEGIN_FTR_SECTION 65a2dcbb32SMichael Neuling oris r5,r5,MSR_VSX@h 66a2dcbb32SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 67a2dcbb32SMichael Neuling#endif 68a2dcbb32SMichael Neuling SYNC 69a2dcbb32SMichael Neuling MTMSRD(r5) 70a2dcbb32SMichael Neuling 71de79f7b9SPaul Mackerras addi r7,r3,THREAD_TRANSACT_FPSTATE 72de79f7b9SPaul Mackerras lfd fr0,FPSTATE_FPSCR(r7) 73a2dcbb32SMichael Neuling MTFSF_L(fr0) 74de79f7b9SPaul Mackerras REST_32FPVSRS(0, R4, R7) 75a2dcbb32SMichael Neuling 76a2dcbb32SMichael Neuling /* FP/VSX off again */ 77a2dcbb32SMichael Neuling MTMSRD(r6) 78a2dcbb32SMichael Neuling SYNC 79a2dcbb32SMichael Neuling 80a2dcbb32SMichael Neuling blr 81a2dcbb32SMichael Neuling#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 82a2dcbb32SMichael Neuling 8314cf11afSPaul Mackerras/* 8418461960SPaul Mackerras * Load state from memory into FP registers including FPSCR. 8518461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR. 8618461960SPaul Mackerras */ 8718461960SPaul Mackerras_GLOBAL(load_fp_state) 8818461960SPaul Mackerras lfd fr0,FPSTATE_FPSCR(r3) 8918461960SPaul Mackerras MTFSF_L(fr0) 9018461960SPaul Mackerras REST_32FPVSRS(0, R4, R3) 9118461960SPaul Mackerras blr 9218461960SPaul Mackerras 9318461960SPaul Mackerras/* 9418461960SPaul Mackerras * Store FP state into memory, including FPSCR 9518461960SPaul Mackerras * Assumes the caller has enabled FP in the MSR. 9618461960SPaul Mackerras */ 9718461960SPaul Mackerras_GLOBAL(store_fp_state) 9818461960SPaul Mackerras SAVE_32FPVSRS(0, R4, R3) 9918461960SPaul Mackerras mffs fr0 10018461960SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r3) 10118461960SPaul Mackerras blr 10218461960SPaul Mackerras 10318461960SPaul Mackerras/* 10414cf11afSPaul Mackerras * This task wants to use the FPU now. 10514cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 10614cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 10714cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 10814cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 10914cf11afSPaul Mackerras */ 110b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 11114cf11afSPaul Mackerras mfmsr r5 11214cf11afSPaul Mackerras ori r5,r5,MSR_FP 113ce48b210SMichael Neuling#ifdef CONFIG_VSX 114ce48b210SMichael NeulingBEGIN_FTR_SECTION 115ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 116ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 117ce48b210SMichael Neuling#endif 11814cf11afSPaul Mackerras SYNC 11914cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 12014cf11afSPaul Mackerras isync 12114cf11afSPaul Mackerras/* 12214cf11afSPaul Mackerras * For SMP, we don't do lazy FPU switching because it just gets too 12314cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 12414cf11afSPaul Mackerras * to another. Instead we call giveup_fpu in switch_to. 12514cf11afSPaul Mackerras */ 12614cf11afSPaul Mackerras#ifndef CONFIG_SMP 127e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r3, last_task_used_math) 1286316222eSPaul Mackerras toreal(r3) 129e58c3495SDavid Gibson PPC_LL r4,ADDROFF(last_task_used_math)(r3) 1303ddfbcf1SDavid Gibson PPC_LCMPI 0,r4,0 13114cf11afSPaul Mackerras beq 1f 1326316222eSPaul Mackerras toreal(r4) 13314cf11afSPaul Mackerras addi r4,r4,THREAD /* want last_task_used_math->thread */ 134de79f7b9SPaul Mackerras addi r8,r4,THREAD_FPSTATE 135de79f7b9SPaul Mackerras SAVE_32FPVSRS(0, R5, R8) 13614cf11afSPaul Mackerras mffs fr0 137de79f7b9SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r8) 1383ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r4) 1396316222eSPaul Mackerras toreal(r5) 1403ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 14114cf11afSPaul Mackerras li r10,MSR_FP|MSR_FE0|MSR_FE1 14214cf11afSPaul Mackerras andc r4,r4,r10 /* disable FP for previous task */ 1433ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 14414cf11afSPaul Mackerras1: 14514cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 14614cf11afSPaul Mackerras /* enable use of FP after return */ 147b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 148ee43eb78SBenjamin Herrenschmidt mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 14914cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 15014cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 15114cf11afSPaul Mackerras or r9,r9,r4 152b85a046aSPaul Mackerras#else 153b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 154b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 155e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 156b85a046aSPaul Mackerras ori r12,r12,MSR_FP 157b85a046aSPaul Mackerras or r12,r12,r4 158b85a046aSPaul Mackerras std r12,_MSR(r1) 159b85a046aSPaul Mackerras#endif 160de79f7b9SPaul Mackerras addi r7,r5,THREAD_FPSTATE 161de79f7b9SPaul Mackerras lfd fr0,FPSTATE_FPSCR(r7) 1623a2c48cfSAnton Blanchard MTFSF_L(fr0) 163de79f7b9SPaul Mackerras REST_32FPVSRS(0, R4, R7) 16414cf11afSPaul Mackerras#ifndef CONFIG_SMP 16514cf11afSPaul Mackerras subi r4,r5,THREAD 1666316222eSPaul Mackerras fromreal(r4) 167e58c3495SDavid Gibson PPC_STL r4,ADDROFF(last_task_used_math)(r3) 16814cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 16914cf11afSPaul Mackerras /* restore registers and return */ 17014cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 1716f3d8e69SMichael Neuling blr 17214cf11afSPaul Mackerras 17314cf11afSPaul Mackerras/* 17414cf11afSPaul Mackerras * giveup_fpu(tsk) 17514cf11afSPaul Mackerras * Disable FP for the task given as the argument, 17614cf11afSPaul Mackerras * and save the floating-point registers in its thread_struct. 17714cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 17814cf11afSPaul Mackerras */ 179b85a046aSPaul Mackerras_GLOBAL(giveup_fpu) 18014cf11afSPaul Mackerras mfmsr r5 18114cf11afSPaul Mackerras ori r5,r5,MSR_FP 182ce48b210SMichael Neuling#ifdef CONFIG_VSX 183ce48b210SMichael NeulingBEGIN_FTR_SECTION 184ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 185ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 186ce48b210SMichael Neuling#endif 18714cf11afSPaul Mackerras SYNC_601 18814cf11afSPaul Mackerras ISYNC_601 18914cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 19014cf11afSPaul Mackerras SYNC_601 19114cf11afSPaul Mackerras isync 1923ddfbcf1SDavid Gibson PPC_LCMPI 0,r3,0 19314cf11afSPaul Mackerras beqlr- /* if no previous owner, done */ 19414cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 19518461960SPaul Mackerras PPC_LL r6,THREAD_FPSAVEAREA(r3) 1963ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 19718461960SPaul Mackerras PPC_LCMPI 0,r6,0 19818461960SPaul Mackerras bne 2f 199de79f7b9SPaul Mackerras addi r6,r3,THREAD_FPSTATE 20018461960SPaul Mackerras2: PPC_LCMPI 0,r5,0 201de79f7b9SPaul Mackerras SAVE_32FPVSRS(0, R4, R6) 20214cf11afSPaul Mackerras mffs fr0 203de79f7b9SPaul Mackerras stfd fr0,FPSTATE_FPSCR(r6) 20414cf11afSPaul Mackerras beq 1f 2053ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 20614cf11afSPaul Mackerras li r3,MSR_FP|MSR_FE0|MSR_FE1 2077e875e9dSMichael Neuling#ifdef CONFIG_VSX 2087e875e9dSMichael NeulingBEGIN_FTR_SECTION 2097e875e9dSMichael Neuling oris r3,r3,MSR_VSX@h 2107e875e9dSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 2117e875e9dSMichael Neuling#endif 21214cf11afSPaul Mackerras andc r4,r4,r3 /* disable FP for previous task */ 2133ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 21414cf11afSPaul Mackerras1: 21514cf11afSPaul Mackerras#ifndef CONFIG_SMP 21614cf11afSPaul Mackerras li r5,0 217e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r4,last_task_used_math) 218e58c3495SDavid Gibson PPC_STL r5,ADDROFF(last_task_used_math)(r4) 21914cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 22014cf11afSPaul Mackerras blr 22125c8a78bSDavid Gibson 22225c8a78bSDavid Gibson/* 22325c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 22425c8a78bSDavid Gibson * single-precision loads and stores. 22525c8a78bSDavid Gibson */ 22625c8a78bSDavid Gibson 22725c8a78bSDavid Gibson_GLOBAL(cvt_fd) 22825c8a78bSDavid Gibson lfs 0,0(r3) 22925c8a78bSDavid Gibson stfd 0,0(r4) 23025c8a78bSDavid Gibson blr 23125c8a78bSDavid Gibson 23225c8a78bSDavid Gibson_GLOBAL(cvt_df) 23325c8a78bSDavid Gibson lfd 0,0(r3) 23425c8a78bSDavid Gibson stfs 0,0(r4) 23525c8a78bSDavid Gibson blr 236