114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * FPU support code, moved here from head.S so that it can be used 314cf11afSPaul Mackerras * by chips which use other head-whatever.S files. 414cf11afSPaul Mackerras * 5fea23bfeSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6fea23bfeSPaul Mackerras * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7fea23bfeSPaul Mackerras * Copyright (C) 1996 Paul Mackerras. 8fea23bfeSPaul Mackerras * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 9fea23bfeSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras * 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 17b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1814cf11afSPaul Mackerras#include <asm/page.h> 1914cf11afSPaul Mackerras#include <asm/mmu.h> 2014cf11afSPaul Mackerras#include <asm/pgtable.h> 2114cf11afSPaul Mackerras#include <asm/cputable.h> 2214cf11afSPaul Mackerras#include <asm/cache.h> 2314cf11afSPaul Mackerras#include <asm/thread_info.h> 2414cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2514cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2646f52210SStephen Rothwell#include <asm/ptrace.h> 2714cf11afSPaul Mackerras 2872ffff5bSMichael Neuling#ifdef CONFIG_VSX 290b7673c3SMichael Neuling#define __REST_32FPVSRS(n,c,base) \ 3072ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 3172ffff5bSMichael Neuling b 2f; \ 3272ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 3372ffff5bSMichael Neuling REST_32FPRS(n,base); \ 3472ffff5bSMichael Neuling b 3f; \ 3572ffff5bSMichael Neuling2: REST_32VSRS(n,c,base); \ 3672ffff5bSMichael Neuling3: 3772ffff5bSMichael Neuling 380b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,c,base) \ 3972ffff5bSMichael NeulingBEGIN_FTR_SECTION \ 4072ffff5bSMichael Neuling b 2f; \ 4172ffff5bSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 4272ffff5bSMichael Neuling SAVE_32FPRS(n,base); \ 4372ffff5bSMichael Neuling b 3f; \ 4472ffff5bSMichael Neuling2: SAVE_32VSRS(n,c,base); \ 4572ffff5bSMichael Neuling3: 4672ffff5bSMichael Neuling#else 470b7673c3SMichael Neuling#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 480b7673c3SMichael Neuling#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 4972ffff5bSMichael Neuling#endif 500b7673c3SMichael Neuling#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 510b7673c3SMichael Neuling#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 5272ffff5bSMichael Neuling 5314cf11afSPaul Mackerras/* 5414cf11afSPaul Mackerras * This task wants to use the FPU now. 5514cf11afSPaul Mackerras * On UP, disable FP for the task which had the FPU previously, 5614cf11afSPaul Mackerras * and save its floating-point registers in its thread_struct. 5714cf11afSPaul Mackerras * Load up this task's FP registers from its thread_struct, 5814cf11afSPaul Mackerras * enable the FPU for the current task and return to the task. 5914cf11afSPaul Mackerras */ 60b85a046aSPaul Mackerras_GLOBAL(load_up_fpu) 6114cf11afSPaul Mackerras mfmsr r5 6214cf11afSPaul Mackerras ori r5,r5,MSR_FP 63ce48b210SMichael Neuling#ifdef CONFIG_VSX 64ce48b210SMichael NeulingBEGIN_FTR_SECTION 65ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 66ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 67ce48b210SMichael Neuling#endif 6814cf11afSPaul Mackerras SYNC 6914cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 7014cf11afSPaul Mackerras isync 7114cf11afSPaul Mackerras/* 7214cf11afSPaul Mackerras * For SMP, we don't do lazy FPU switching because it just gets too 7314cf11afSPaul Mackerras * horrendously complex, especially when a task switches from one CPU 7414cf11afSPaul Mackerras * to another. Instead we call giveup_fpu in switch_to. 7514cf11afSPaul Mackerras */ 7614cf11afSPaul Mackerras#ifndef CONFIG_SMP 77e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r3, last_task_used_math) 786316222eSPaul Mackerras toreal(r3) 79e58c3495SDavid Gibson PPC_LL r4,ADDROFF(last_task_used_math)(r3) 803ddfbcf1SDavid Gibson PPC_LCMPI 0,r4,0 8114cf11afSPaul Mackerras beq 1f 826316222eSPaul Mackerras toreal(r4) 8314cf11afSPaul Mackerras addi r4,r4,THREAD /* want last_task_used_math->thread */ 840b7673c3SMichael Neuling SAVE_32FPVSRS(0, R5, R4) 8514cf11afSPaul Mackerras mffs fr0 8625c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r4) 873ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r4) 886316222eSPaul Mackerras toreal(r5) 893ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 9014cf11afSPaul Mackerras li r10,MSR_FP|MSR_FE0|MSR_FE1 9114cf11afSPaul Mackerras andc r4,r4,r10 /* disable FP for previous task */ 923ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 9314cf11afSPaul Mackerras1: 9414cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 9514cf11afSPaul Mackerras /* enable use of FP after return */ 96b85a046aSPaul Mackerras#ifdef CONFIG_PPC32 97ee43eb78SBenjamin Herrenschmidt mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 9814cf11afSPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 9914cf11afSPaul Mackerras ori r9,r9,MSR_FP /* enable FP for current */ 10014cf11afSPaul Mackerras or r9,r9,r4 101b85a046aSPaul Mackerras#else 102b85a046aSPaul Mackerras ld r4,PACACURRENT(r13) 103b85a046aSPaul Mackerras addi r5,r4,THREAD /* Get THREAD */ 104e2f5a3c1SPaul Mackerras lwz r4,THREAD_FPEXC_MODE(r5) 105b85a046aSPaul Mackerras ori r12,r12,MSR_FP 106b85a046aSPaul Mackerras or r12,r12,r4 107b85a046aSPaul Mackerras std r12,_MSR(r1) 108b85a046aSPaul Mackerras#endif 10925c8a78bSDavid Gibson lfd fr0,THREAD_FPSCR(r5) 1103a2c48cfSAnton Blanchard MTFSF_L(fr0) 111c75df6f9SMichael Neuling REST_32FPVSRS(0, R4, R5) 11214cf11afSPaul Mackerras#ifndef CONFIG_SMP 11314cf11afSPaul Mackerras subi r4,r5,THREAD 1146316222eSPaul Mackerras fromreal(r4) 115e58c3495SDavid Gibson PPC_STL r4,ADDROFF(last_task_used_math)(r3) 11614cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 11714cf11afSPaul Mackerras /* restore registers and return */ 11814cf11afSPaul Mackerras /* we haven't used ctr or xer or lr */ 1196f3d8e69SMichael Neuling blr 12014cf11afSPaul Mackerras 12114cf11afSPaul Mackerras/* 12214cf11afSPaul Mackerras * giveup_fpu(tsk) 12314cf11afSPaul Mackerras * Disable FP for the task given as the argument, 12414cf11afSPaul Mackerras * and save the floating-point registers in its thread_struct. 12514cf11afSPaul Mackerras * Enables the FPU for use in the kernel on return. 12614cf11afSPaul Mackerras */ 127b85a046aSPaul Mackerras_GLOBAL(giveup_fpu) 12814cf11afSPaul Mackerras mfmsr r5 12914cf11afSPaul Mackerras ori r5,r5,MSR_FP 130ce48b210SMichael Neuling#ifdef CONFIG_VSX 131ce48b210SMichael NeulingBEGIN_FTR_SECTION 132ce48b210SMichael Neuling oris r5,r5,MSR_VSX@h 133ce48b210SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 134ce48b210SMichael Neuling#endif 13514cf11afSPaul Mackerras SYNC_601 13614cf11afSPaul Mackerras ISYNC_601 13714cf11afSPaul Mackerras MTMSRD(r5) /* enable use of fpu now */ 13814cf11afSPaul Mackerras SYNC_601 13914cf11afSPaul Mackerras isync 1403ddfbcf1SDavid Gibson PPC_LCMPI 0,r3,0 14114cf11afSPaul Mackerras beqlr- /* if no previous owner, done */ 14214cf11afSPaul Mackerras addi r3,r3,THREAD /* want THREAD of task */ 1433ddfbcf1SDavid Gibson PPC_LL r5,PT_REGS(r3) 1443ddfbcf1SDavid Gibson PPC_LCMPI 0,r5,0 145c75df6f9SMichael Neuling SAVE_32FPVSRS(0, R4 ,R3) 14614cf11afSPaul Mackerras mffs fr0 14725c8a78bSDavid Gibson stfd fr0,THREAD_FPSCR(r3) 14814cf11afSPaul Mackerras beq 1f 1493ddfbcf1SDavid Gibson PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 15014cf11afSPaul Mackerras li r3,MSR_FP|MSR_FE0|MSR_FE1 1517e875e9dSMichael Neuling#ifdef CONFIG_VSX 1527e875e9dSMichael NeulingBEGIN_FTR_SECTION 1537e875e9dSMichael Neuling oris r3,r3,MSR_VSX@h 1547e875e9dSMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 1557e875e9dSMichael Neuling#endif 15614cf11afSPaul Mackerras andc r4,r4,r3 /* disable FP for previous task */ 1573ddfbcf1SDavid Gibson PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 15814cf11afSPaul Mackerras1: 15914cf11afSPaul Mackerras#ifndef CONFIG_SMP 16014cf11afSPaul Mackerras li r5,0 161e58c3495SDavid Gibson LOAD_REG_ADDRBASE(r4,last_task_used_math) 162e58c3495SDavid Gibson PPC_STL r5,ADDROFF(last_task_used_math)(r4) 16314cf11afSPaul Mackerras#endif /* CONFIG_SMP */ 16414cf11afSPaul Mackerras blr 16525c8a78bSDavid Gibson 16625c8a78bSDavid Gibson/* 16725c8a78bSDavid Gibson * These are used in the alignment trap handler when emulating 16825c8a78bSDavid Gibson * single-precision loads and stores. 16925c8a78bSDavid Gibson */ 17025c8a78bSDavid Gibson 17125c8a78bSDavid Gibson_GLOBAL(cvt_fd) 17225c8a78bSDavid Gibson lfs 0,0(r3) 17325c8a78bSDavid Gibson stfd 0,0(r4) 17425c8a78bSDavid Gibson blr 17525c8a78bSDavid Gibson 17625c8a78bSDavid Gibson_GLOBAL(cvt_df) 17725c8a78bSDavid Gibson lfd 0,0(r3) 17825c8a78bSDavid Gibson stfs 0,0(r4) 17925c8a78bSDavid Gibson blr 180