1/* 2 * This file contains the 64-bit "server" PowerPC variant 3 * of the low level exception handling including exception 4 * vectors, exception return, part of the slb and stab 5 * handling and other fixed offset specific things. 6 * 7 * This file is meant to be #included from head_64.S due to 8 * position dependent assembly. 9 * 10 * Most of this originates from head_64.S and thus has the same 11 * copyright history. 12 * 13 */ 14 15#include <asm/hw_irq.h> 16#include <asm/exception-64s.h> 17#include <asm/ptrace.h> 18#include <asm/cpuidle.h> 19#include <asm/head-64.h> 20 21/* 22 * There are a few constraints to be concerned with. 23 * - Real mode exceptions code/data must be located at their physical location. 24 * - Virtual mode exceptions must be mapped at their 0xc000... location. 25 * - Fixed location code must not call directly beyond the __end_interrupts 26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 27 * must be used. 28 * - LOAD_HANDLER targets must be within first 64K of physical 0 / 29 * virtual 0xc00... 30 * - Conditional branch targets must be within +/-32K of caller. 31 * 32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 33 * therefore don't have to run in physically located code or rfid to 34 * virtual mode kernel code. However on relocatable kernels they do have 35 * to branch to KERNELBASE offset because the rest of the kernel (outside 36 * the exception vectors) may be located elsewhere. 37 * 38 * Virtual exceptions correspond with physical, except their entry points 39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000 40 * offset applied. Virtual exceptions are enabled with the Alternate 41 * Interrupt Location (AIL) bit set in the LPCR. However this does not 42 * guarantee they will be delivered virtually. Some conditions (see the ISA) 43 * cause exceptions to be delivered in real mode. 44 * 45 * It's impossible to receive interrupts below 0x300 via AIL. 46 * 47 * KVM: None of the virtual exceptions are from the guest. Anything that 48 * escalated to HV=1 from HV=0 is delivered via real mode handlers. 49 * 50 * 51 * We layout physical memory as follows: 52 * 0x0000 - 0x00ff : Secondary processor spin code 53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 54 * 0x1900 - 0x3fff : Real mode trampolines 55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 56 * 0x5900 - 0x6fff : Relon mode trampolines 57 * 0x7000 - 0x7fff : FWNMI data area 58 * 0x8000 - .... : Common interrupt handlers, remaining early 59 * setup code, rest of kernel. 60 * 61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 63 * vectors there. 64 */ 65OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 66OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 67OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 68OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 69#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 70/* 71 * Data area reserved for FWNMI option. 72 * This address (0x7000) is fixed by the RPA. 73 * pseries and powernv need to keep the whole page from 74 * 0x7000 to 0x8000 free for use by the firmware 75 */ 76ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 77OPEN_TEXT_SECTION(0x8000) 78#else 79OPEN_TEXT_SECTION(0x7000) 80#endif 81 82USE_FIXED_SECTION(real_vectors) 83 84/* 85 * This is the start of the interrupt handlers for pSeries 86 * This code runs with relocation off. 87 * Code from here to __end_interrupts gets copied down to real 88 * address 0x100 when we are running a relocatable kernel. 89 * Therefore any relative branches in this section must only 90 * branch to labels in this section. 91 */ 92 .globl __start_interrupts 93__start_interrupts: 94 95/* No virt vectors corresponding with 0x0..0x100 */ 96EXC_VIRT_NONE(0x4000, 0x4100) 97 98 99#ifdef CONFIG_PPC_P7_NAP 100 /* 101 * If running native on arch 2.06 or later, check if we are waking up 102 * from nap/sleep/winkle, and branch to idle handler. 103 */ 104#define IDLETEST(n) \ 105 BEGIN_FTR_SECTION ; \ 106 mfspr r10,SPRN_SRR1 ; \ 107 rlwinm. r10,r10,47-31,30,31 ; \ 108 beq- 1f ; \ 109 cmpwi cr3,r10,2 ; \ 110 BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \ 1111: \ 112 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 113#else 114#define IDLETEST NOTEST 115#endif 116 117EXC_REAL_BEGIN(system_reset, 0x100, 0x200) 118 SET_SCRATCH0(r13) 119 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, 120 IDLETEST, 0x100) 121 122EXC_REAL_END(system_reset, 0x100, 0x200) 123EXC_VIRT_NONE(0x4100, 0x4200) 124 125#ifdef CONFIG_PPC_P7_NAP 126EXC_COMMON_BEGIN(system_reset_idle_common) 127 bl pnv_restore_hyp_resource 128 129 li r0,PNV_THREAD_RUNNING 130 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ 131 132#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 133 li r0,KVM_HWTHREAD_IN_KERNEL 134 stb r0,HSTATE_HWTHREAD_STATE(r13) 135 /* Order setting hwthread_state vs. testing hwthread_req */ 136 sync 137 lbz r0,HSTATE_HWTHREAD_REQ(r13) 138 cmpwi r0,0 139 beq 1f 140 b kvm_start_guest 1411: 142#endif 143 144 /* Return SRR1 from power7_nap() */ 145 mfspr r3,SPRN_SRR1 146 blt cr3,2f 147 b pnv_wakeup_loss 1482: b pnv_wakeup_noloss 149#endif 150 151EXC_COMMON(system_reset_common, 0x100, system_reset_exception) 152 153#ifdef CONFIG_PPC_PSERIES 154/* 155 * Vectors for the FWNMI option. Share common code. 156 */ 157TRAMP_REAL_BEGIN(system_reset_fwnmi) 158 SET_SCRATCH0(r13) /* save r13 */ 159 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, 160 NOTEST, 0x100) 161#endif /* CONFIG_PPC_PSERIES */ 162 163 164EXC_REAL_BEGIN(machine_check, 0x200, 0x300) 165 /* This is moved out of line as it can be patched by FW, but 166 * some code path might still want to branch into the original 167 * vector 168 */ 169 SET_SCRATCH0(r13) /* save r13 */ 170 /* 171 * Running native on arch 2.06 or later, we may wakeup from winkle 172 * inside machine check. If yes, then last bit of HSPGR0 would be set 173 * to 1. Hence clear it unconditionally. 174 */ 175 GET_PACA(r13) 176 clrrdi r13,r13,1 177 SET_PACA(r13) 178 EXCEPTION_PROLOG_0(PACA_EXMC) 179BEGIN_FTR_SECTION 180 b machine_check_powernv_early 181FTR_SECTION_ELSE 182 b machine_check_pSeries_0 183ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 184EXC_REAL_END(machine_check, 0x200, 0x300) 185EXC_VIRT_NONE(0x4200, 0x4300) 186TRAMP_REAL_BEGIN(machine_check_powernv_early) 187BEGIN_FTR_SECTION 188 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) 189 /* 190 * Register contents: 191 * R13 = PACA 192 * R9 = CR 193 * Original R9 to R13 is saved on PACA_EXMC 194 * 195 * Switch to mc_emergency stack and handle re-entrancy (we limit 196 * the nested MCE upto level 4 to avoid stack overflow). 197 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 198 * 199 * We use paca->in_mce to check whether this is the first entry or 200 * nested machine check. We increment paca->in_mce to track nested 201 * machine checks. 202 * 203 * If this is the first entry then set stack pointer to 204 * paca->mc_emergency_sp, otherwise r1 is already pointing to 205 * stack frame on mc_emergency stack. 206 * 207 * NOTE: We are here with MSR_ME=0 (off), which means we risk a 208 * checkstop if we get another machine check exception before we do 209 * rfid with MSR_ME=1. 210 */ 211 mr r11,r1 /* Save r1 */ 212 lhz r10,PACA_IN_MCE(r13) 213 cmpwi r10,0 /* Are we in nested machine check */ 214 bne 0f /* Yes, we are. */ 215 /* First machine check entry */ 216 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 2170: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 218 addi r10,r10,1 /* increment paca->in_mce */ 219 sth r10,PACA_IN_MCE(r13) 220 /* Limit nested MCE to level 4 to avoid stack overflow */ 221 cmpwi r10,4 222 bgt 2f /* Check if we hit limit of 4 */ 223 std r11,GPR1(r1) /* Save r1 on the stack. */ 224 std r11,0(r1) /* make stack chain pointer */ 225 mfspr r11,SPRN_SRR0 /* Save SRR0 */ 226 std r11,_NIP(r1) 227 mfspr r11,SPRN_SRR1 /* Save SRR1 */ 228 std r11,_MSR(r1) 229 mfspr r11,SPRN_DAR /* Save DAR */ 230 std r11,_DAR(r1) 231 mfspr r11,SPRN_DSISR /* Save DSISR */ 232 std r11,_DSISR(r1) 233 std r9,_CCR(r1) /* Save CR in stackframe */ 234 /* Save r9 through r13 from EXMC save area to stack frame. */ 235 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 236 mfmsr r11 /* get MSR value */ 237 ori r11,r11,MSR_ME /* turn on ME bit */ 238 ori r11,r11,MSR_RI /* turn on RI bit */ 239 LOAD_HANDLER(r12, machine_check_handle_early) 2401: mtspr SPRN_SRR0,r12 241 mtspr SPRN_SRR1,r11 242 rfid 243 b . /* prevent speculative execution */ 2442: 245 /* Stack overflow. Stay on emergency stack and panic. 246 * Keep the ME bit off while panic-ing, so that if we hit 247 * another machine check we checkstop. 248 */ 249 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 250 ld r11,PACAKMSR(r13) 251 LOAD_HANDLER(r12, unrecover_mce) 252 li r10,MSR_ME 253 andc r11,r11,r10 /* Turn off MSR_ME */ 254 b 1b 255 b . /* prevent speculative execution */ 256END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 257 258TRAMP_REAL_BEGIN(machine_check_pSeries) 259 .globl machine_check_fwnmi 260machine_check_fwnmi: 261 SET_SCRATCH0(r13) /* save r13 */ 262 EXCEPTION_PROLOG_0(PACA_EXMC) 263machine_check_pSeries_0: 264 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) 265 /* 266 * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the 267 * difference that MSR_RI is not enabled, because PACA_EXMC is being 268 * used, so nested machine check corrupts it. machine_check_common 269 * enables MSR_RI. 270 */ 271 ld r10,PACAKMSR(r13) 272 xori r10,r10,MSR_RI 273 mfspr r11,SPRN_SRR0 274 LOAD_HANDLER(r12, machine_check_common) 275 mtspr SPRN_SRR0,r12 276 mfspr r12,SPRN_SRR1 277 mtspr SPRN_SRR1,r10 278 rfid 279 b . /* prevent speculative execution */ 280 281TRAMP_KVM_SKIP(PACA_EXMC, 0x200) 282 283EXC_COMMON_BEGIN(machine_check_common) 284 /* 285 * Machine check is different because we use a different 286 * save area: PACA_EXMC instead of PACA_EXGEN. 287 */ 288 mfspr r10,SPRN_DAR 289 std r10,PACA_EXMC+EX_DAR(r13) 290 mfspr r10,SPRN_DSISR 291 stw r10,PACA_EXMC+EX_DSISR(r13) 292 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 293 FINISH_NAP 294 RECONCILE_IRQ_STATE(r10, r11) 295 ld r3,PACA_EXMC+EX_DAR(r13) 296 lwz r4,PACA_EXMC+EX_DSISR(r13) 297 /* Enable MSR_RI when finished with PACA_EXMC */ 298 li r10,MSR_RI 299 mtmsrd r10,1 300 std r3,_DAR(r1) 301 std r4,_DSISR(r1) 302 bl save_nvgprs 303 addi r3,r1,STACK_FRAME_OVERHEAD 304 bl machine_check_exception 305 b ret_from_except 306 307#define MACHINE_CHECK_HANDLER_WINDUP \ 308 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 309 li r0,MSR_RI; \ 310 mfmsr r9; /* get MSR value */ \ 311 andc r9,r9,r0; \ 312 mtmsrd r9,1; /* Clear MSR_RI */ \ 313 /* Move original SRR0 and SRR1 into the respective regs */ \ 314 ld r9,_MSR(r1); \ 315 mtspr SPRN_SRR1,r9; \ 316 ld r3,_NIP(r1); \ 317 mtspr SPRN_SRR0,r3; \ 318 ld r9,_CTR(r1); \ 319 mtctr r9; \ 320 ld r9,_XER(r1); \ 321 mtxer r9; \ 322 ld r9,_LINK(r1); \ 323 mtlr r9; \ 324 REST_GPR(0, r1); \ 325 REST_8GPRS(2, r1); \ 326 REST_GPR(10, r1); \ 327 ld r11,_CCR(r1); \ 328 mtcr r11; \ 329 /* Decrement paca->in_mce. */ \ 330 lhz r12,PACA_IN_MCE(r13); \ 331 subi r12,r12,1; \ 332 sth r12,PACA_IN_MCE(r13); \ 333 REST_GPR(11, r1); \ 334 REST_2GPRS(12, r1); \ 335 /* restore original r1. */ \ 336 ld r1,GPR1(r1) 337 338 /* 339 * Handle machine check early in real mode. We come here with 340 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 341 */ 342EXC_COMMON_BEGIN(machine_check_handle_early) 343 std r0,GPR0(r1) /* Save r0 */ 344 EXCEPTION_PROLOG_COMMON_3(0x200) 345 bl save_nvgprs 346 addi r3,r1,STACK_FRAME_OVERHEAD 347 bl machine_check_early 348 std r3,RESULT(r1) /* Save result */ 349 ld r12,_MSR(r1) 350#ifdef CONFIG_PPC_P7_NAP 351 /* 352 * Check if thread was in power saving mode. We come here when any 353 * of the following is true: 354 * a. thread wasn't in power saving mode 355 * b. thread was in power saving mode with no state loss, 356 * supervisor state loss or hypervisor state loss. 357 * 358 * Go back to nap/sleep/winkle mode again if (b) is true. 359 */ 360 rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ 361 beq 4f /* No, it wasn;t */ 362 /* Thread was in power saving mode. Go back to nap again. */ 363 cmpwi r11,2 364 blt 3f 365 /* Supervisor/Hypervisor state loss */ 366 li r0,1 367 stb r0,PACA_NAPSTATELOST(r13) 3683: bl machine_check_queue_event 369 MACHINE_CHECK_HANDLER_WINDUP 370 GET_PACA(r13) 371 ld r1,PACAR1(r13) 372 /* 373 * Check what idle state this CPU was in and go back to same mode 374 * again. 375 */ 376 lbz r3,PACA_THREAD_IDLE_STATE(r13) 377 cmpwi r3,PNV_THREAD_NAP 378 bgt 10f 379 IDLE_STATE_ENTER_SEQ(PPC_NAP) 380 /* No return */ 38110: 382 cmpwi r3,PNV_THREAD_SLEEP 383 bgt 2f 384 IDLE_STATE_ENTER_SEQ(PPC_SLEEP) 385 /* No return */ 386 3872: 388 /* 389 * Go back to winkle. Please note that this thread was woken up in 390 * machine check from winkle and have not restored the per-subcore 391 * state. Hence before going back to winkle, set last bit of HSPGR0 392 * to 1. This will make sure that if this thread gets woken up 393 * again at reset vector 0x100 then it will get chance to restore 394 * the subcore state. 395 */ 396 ori r13,r13,1 397 SET_PACA(r13) 398 IDLE_STATE_ENTER_SEQ(PPC_WINKLE) 399 /* No return */ 4004: 401#endif 402 /* 403 * Check if we are coming from hypervisor userspace. If yes then we 404 * continue in host kernel in V mode to deliver the MC event. 405 */ 406 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 407 beq 5f 408 andi. r11,r12,MSR_PR /* See if coming from user. */ 409 bne 9f /* continue in V mode if we are. */ 410 4115: 412#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 413 /* 414 * We are coming from kernel context. Check if we are coming from 415 * guest. if yes, then we can continue. We will fall through 416 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 417 */ 418 lbz r11,HSTATE_IN_GUEST(r13) 419 cmpwi r11,0 /* Check if coming from guest */ 420 bne 9f /* continue if we are. */ 421#endif 422 /* 423 * At this point we are not sure about what context we come from. 424 * Queue up the MCE event and return from the interrupt. 425 * But before that, check if this is an un-recoverable exception. 426 * If yes, then stay on emergency stack and panic. 427 */ 428 andi. r11,r12,MSR_RI 429 bne 2f 4301: mfspr r11,SPRN_SRR0 431 LOAD_HANDLER(r10,unrecover_mce) 432 mtspr SPRN_SRR0,r10 433 ld r10,PACAKMSR(r13) 434 /* 435 * We are going down. But there are chances that we might get hit by 436 * another MCE during panic path and we may run into unstable state 437 * with no way out. Hence, turn ME bit off while going down, so that 438 * when another MCE is hit during panic path, system will checkstop 439 * and hypervisor will get restarted cleanly by SP. 440 */ 441 li r3,MSR_ME 442 andc r10,r10,r3 /* Turn off MSR_ME */ 443 mtspr SPRN_SRR1,r10 444 rfid 445 b . 4462: 447 /* 448 * Check if we have successfully handled/recovered from error, if not 449 * then stay on emergency stack and panic. 450 */ 451 ld r3,RESULT(r1) /* Load result */ 452 cmpdi r3,0 /* see if we handled MCE successfully */ 453 454 beq 1b /* if !handled then panic */ 455 /* 456 * Return from MC interrupt. 457 * Queue up the MCE event so that we can log it later, while 458 * returning from kernel or opal call. 459 */ 460 bl machine_check_queue_event 461 MACHINE_CHECK_HANDLER_WINDUP 462 rfid 4639: 464 /* Deliver the machine check to host kernel in V mode. */ 465 MACHINE_CHECK_HANDLER_WINDUP 466 b machine_check_pSeries 467 468EXC_COMMON_BEGIN(unrecover_mce) 469 /* Invoke machine_check_exception to print MCE event and panic. */ 470 addi r3,r1,STACK_FRAME_OVERHEAD 471 bl machine_check_exception 472 /* 473 * We will not reach here. Even if we did, there is no way out. Call 474 * unrecoverable_exception and die. 475 */ 4761: addi r3,r1,STACK_FRAME_OVERHEAD 477 bl unrecoverable_exception 478 b 1b 479 480 481EXC_REAL(data_access, 0x300, 0x380) 482EXC_VIRT(data_access, 0x4300, 0x4380, 0x300) 483TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 484 485EXC_COMMON_BEGIN(data_access_common) 486 /* 487 * Here r13 points to the paca, r9 contains the saved CR, 488 * SRR0 and SRR1 are saved in r11 and r12, 489 * r9 - r13 are saved in paca->exgen. 490 */ 491 mfspr r10,SPRN_DAR 492 std r10,PACA_EXGEN+EX_DAR(r13) 493 mfspr r10,SPRN_DSISR 494 stw r10,PACA_EXGEN+EX_DSISR(r13) 495 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 496 RECONCILE_IRQ_STATE(r10, r11) 497 ld r12,_MSR(r1) 498 ld r3,PACA_EXGEN+EX_DAR(r13) 499 lwz r4,PACA_EXGEN+EX_DSISR(r13) 500 li r5,0x300 501 std r3,_DAR(r1) 502 std r4,_DSISR(r1) 503BEGIN_MMU_FTR_SECTION 504 b do_hash_page /* Try to handle as hpte fault */ 505MMU_FTR_SECTION_ELSE 506 b handle_page_fault 507ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 508 509 510EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) 511 SET_SCRATCH0(r13) 512 EXCEPTION_PROLOG_0(PACA_EXSLB) 513 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) 514 std r3,PACA_EXSLB+EX_R3(r13) 515 mfspr r3,SPRN_DAR 516 mfspr r12,SPRN_SRR1 517 crset 4*cr6+eq 518#ifndef CONFIG_RELOCATABLE 519 b slb_miss_realmode 520#else 521 /* 522 * We can't just use a direct branch to slb_miss_realmode 523 * because the distance from here to there depends on where 524 * the kernel ends up being put. 525 */ 526 mfctr r11 527 LOAD_HANDLER(r10, slb_miss_realmode) 528 mtctr r10 529 bctr 530#endif 531EXC_REAL_END(data_access_slb, 0x380, 0x400) 532 533EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) 534 SET_SCRATCH0(r13) 535 EXCEPTION_PROLOG_0(PACA_EXSLB) 536 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) 537 std r3,PACA_EXSLB+EX_R3(r13) 538 mfspr r3,SPRN_DAR 539 mfspr r12,SPRN_SRR1 540 crset 4*cr6+eq 541#ifndef CONFIG_RELOCATABLE 542 b slb_miss_realmode 543#else 544 /* 545 * We can't just use a direct branch to slb_miss_realmode 546 * because the distance from here to there depends on where 547 * the kernel ends up being put. 548 */ 549 mfctr r11 550 LOAD_HANDLER(r10, slb_miss_realmode) 551 mtctr r10 552 bctr 553#endif 554EXC_VIRT_END(data_access_slb, 0x4380, 0x4400) 555TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 556 557 558EXC_REAL(instruction_access, 0x400, 0x480) 559EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) 560TRAMP_KVM(PACA_EXGEN, 0x400) 561 562EXC_COMMON_BEGIN(instruction_access_common) 563 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 564 RECONCILE_IRQ_STATE(r10, r11) 565 ld r12,_MSR(r1) 566 ld r3,_NIP(r1) 567 andis. r4,r12,0x5820 568 li r5,0x400 569 std r3,_DAR(r1) 570 std r4,_DSISR(r1) 571BEGIN_MMU_FTR_SECTION 572 b do_hash_page /* Try to handle as hpte fault */ 573MMU_FTR_SECTION_ELSE 574 b handle_page_fault 575ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 576 577 578EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) 579 SET_SCRATCH0(r13) 580 EXCEPTION_PROLOG_0(PACA_EXSLB) 581 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) 582 std r3,PACA_EXSLB+EX_R3(r13) 583 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 584 mfspr r12,SPRN_SRR1 585 crclr 4*cr6+eq 586#ifndef CONFIG_RELOCATABLE 587 b slb_miss_realmode 588#else 589 mfctr r11 590 LOAD_HANDLER(r10, slb_miss_realmode) 591 mtctr r10 592 bctr 593#endif 594EXC_REAL_END(instruction_access_slb, 0x480, 0x500) 595 596EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) 597 SET_SCRATCH0(r13) 598 EXCEPTION_PROLOG_0(PACA_EXSLB) 599 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) 600 std r3,PACA_EXSLB+EX_R3(r13) 601 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 602 mfspr r12,SPRN_SRR1 603 crclr 4*cr6+eq 604#ifndef CONFIG_RELOCATABLE 605 b slb_miss_realmode 606#else 607 mfctr r11 608 LOAD_HANDLER(r10, slb_miss_realmode) 609 mtctr r10 610 bctr 611#endif 612EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) 613TRAMP_KVM(PACA_EXSLB, 0x480) 614 615 616/* This handler is used by both 0x380 and 0x480 slb miss interrupts */ 617EXC_COMMON_BEGIN(slb_miss_realmode) 618 /* 619 * r13 points to the PACA, r9 contains the saved CR, 620 * r12 contain the saved SRR1, SRR0 is still ready for return 621 * r3 has the faulting address 622 * r9 - r13 are saved in paca->exslb. 623 * r3 is saved in paca->slb_r3 624 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss 625 * We assume we aren't going to take any exceptions during this 626 * procedure. 627 */ 628 mflr r10 629#ifdef CONFIG_RELOCATABLE 630 mtctr r11 631#endif 632 633 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 634 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 635 std r3,PACA_EXSLB+EX_DAR(r13) 636 637 crset 4*cr0+eq 638#ifdef CONFIG_PPC_STD_MMU_64 639BEGIN_MMU_FTR_SECTION 640 bl slb_allocate_realmode 641END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) 642#endif 643 644 ld r10,PACA_EXSLB+EX_LR(r13) 645 ld r3,PACA_EXSLB+EX_R3(r13) 646 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 647 mtlr r10 648 649 beq 8f /* if bad address, make full stack frame */ 650 651 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 652 beq- 2f 653 654 /* All done -- return from exception. */ 655 656.machine push 657.machine "power4" 658 mtcrf 0x80,r9 659 mtcrf 0x02,r9 /* I/D indication is in cr6 */ 660 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 661.machine pop 662 663 RESTORE_PPR_PACA(PACA_EXSLB, r9) 664 ld r9,PACA_EXSLB+EX_R9(r13) 665 ld r10,PACA_EXSLB+EX_R10(r13) 666 ld r11,PACA_EXSLB+EX_R11(r13) 667 ld r12,PACA_EXSLB+EX_R12(r13) 668 ld r13,PACA_EXSLB+EX_R13(r13) 669 rfid 670 b . /* prevent speculative execution */ 671 6722: mfspr r11,SPRN_SRR0 673 LOAD_HANDLER(r10,unrecov_slb) 674 mtspr SPRN_SRR0,r10 675 ld r10,PACAKMSR(r13) 676 mtspr SPRN_SRR1,r10 677 rfid 678 b . 679 6808: mfspr r11,SPRN_SRR0 681 LOAD_HANDLER(r10,bad_addr_slb) 682 mtspr SPRN_SRR0,r10 683 ld r10,PACAKMSR(r13) 684 mtspr SPRN_SRR1,r10 685 rfid 686 b . 687 688EXC_COMMON_BEGIN(unrecov_slb) 689 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 690 RECONCILE_IRQ_STATE(r10, r11) 691 bl save_nvgprs 6921: addi r3,r1,STACK_FRAME_OVERHEAD 693 bl unrecoverable_exception 694 b 1b 695 696EXC_COMMON_BEGIN(bad_addr_slb) 697 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) 698 RECONCILE_IRQ_STATE(r10, r11) 699 ld r3, PACA_EXSLB+EX_DAR(r13) 700 std r3, _DAR(r1) 701 beq cr6, 2f 702 li r10, 0x480 /* fix trap number for I-SLB miss */ 703 std r10, _TRAP(r1) 7042: bl save_nvgprs 705 addi r3, r1, STACK_FRAME_OVERHEAD 706 bl slb_miss_bad_addr 707 b ret_from_except 708 709EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) 710 .globl hardware_interrupt_hv; 711hardware_interrupt_hv: 712 BEGIN_FTR_SECTION 713 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 714 EXC_HV, SOFTEN_TEST_HV) 715do_kvm_H0x500: 716 KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) 717 FTR_SECTION_ELSE 718 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 719 EXC_STD, SOFTEN_TEST_PR) 720do_kvm_0x500: 721 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) 722 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 723EXC_REAL_END(hardware_interrupt, 0x500, 0x600) 724 725EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) 726 .globl hardware_interrupt_relon_hv; 727hardware_interrupt_relon_hv: 728 BEGIN_FTR_SECTION 729 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) 730 FTR_SECTION_ELSE 731 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) 732 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 733EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) 734 735EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 736 737 738EXC_REAL(alignment, 0x600, 0x700) 739EXC_VIRT(alignment, 0x4600, 0x4700, 0x600) 740TRAMP_KVM(PACA_EXGEN, 0x600) 741EXC_COMMON_BEGIN(alignment_common) 742 mfspr r10,SPRN_DAR 743 std r10,PACA_EXGEN+EX_DAR(r13) 744 mfspr r10,SPRN_DSISR 745 stw r10,PACA_EXGEN+EX_DSISR(r13) 746 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 747 ld r3,PACA_EXGEN+EX_DAR(r13) 748 lwz r4,PACA_EXGEN+EX_DSISR(r13) 749 std r3,_DAR(r1) 750 std r4,_DSISR(r1) 751 bl save_nvgprs 752 RECONCILE_IRQ_STATE(r10, r11) 753 addi r3,r1,STACK_FRAME_OVERHEAD 754 bl alignment_exception 755 b ret_from_except 756 757 758EXC_REAL(program_check, 0x700, 0x800) 759EXC_VIRT(program_check, 0x4700, 0x4800, 0x700) 760TRAMP_KVM(PACA_EXGEN, 0x700) 761EXC_COMMON_BEGIN(program_check_common) 762 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 763 bl save_nvgprs 764 RECONCILE_IRQ_STATE(r10, r11) 765 addi r3,r1,STACK_FRAME_OVERHEAD 766 bl program_check_exception 767 b ret_from_except 768 769 770EXC_REAL(fp_unavailable, 0x800, 0x900) 771EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) 772TRAMP_KVM(PACA_EXGEN, 0x800) 773EXC_COMMON_BEGIN(fp_unavailable_common) 774 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 775 bne 1f /* if from user, just load it up */ 776 bl save_nvgprs 777 RECONCILE_IRQ_STATE(r10, r11) 778 addi r3,r1,STACK_FRAME_OVERHEAD 779 bl kernel_fp_unavailable_exception 780 BUG_OPCODE 7811: 782#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 783BEGIN_FTR_SECTION 784 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 785 * transaction), go do TM stuff 786 */ 787 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 788 bne- 2f 789END_FTR_SECTION_IFSET(CPU_FTR_TM) 790#endif 791 bl load_up_fpu 792 b fast_exception_return 793#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 7942: /* User process was in a transaction */ 795 bl save_nvgprs 796 RECONCILE_IRQ_STATE(r10, r11) 797 addi r3,r1,STACK_FRAME_OVERHEAD 798 bl fp_unavailable_tm 799 b ret_from_except 800#endif 801 802 803EXC_REAL_MASKABLE(decrementer, 0x900, 0x980) 804EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) 805TRAMP_KVM(PACA_EXGEN, 0x900) 806EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 807 808 809EXC_REAL_HV(hdecrementer, 0x980, 0xa00) 810EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) 811TRAMP_KVM_HV(PACA_EXGEN, 0x980) 812EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 813 814 815EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) 816EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) 817TRAMP_KVM(PACA_EXGEN, 0xa00) 818#ifdef CONFIG_PPC_DOORBELL 819EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 820#else 821EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 822#endif 823 824 825EXC_REAL(trap_0b, 0xb00, 0xc00) 826EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) 827TRAMP_KVM(PACA_EXGEN, 0xb00) 828EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 829 830#define LOAD_SYSCALL_HANDLER(reg) \ 831 __LOAD_HANDLER(reg, system_call_common) 832 833/* Syscall routine is used twice, in reloc-off and reloc-on paths */ 834#define SYSCALL_PSERIES_1 \ 835BEGIN_FTR_SECTION \ 836 cmpdi r0,0x1ebe ; \ 837 beq- 1f ; \ 838END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 839 mr r9,r13 ; \ 840 GET_PACA(r13) ; \ 841 mfspr r11,SPRN_SRR0 ; \ 8420: 843 844#define SYSCALL_PSERIES_2_RFID \ 845 mfspr r12,SPRN_SRR1 ; \ 846 LOAD_SYSCALL_HANDLER(r10) ; \ 847 mtspr SPRN_SRR0,r10 ; \ 848 ld r10,PACAKMSR(r13) ; \ 849 mtspr SPRN_SRR1,r10 ; \ 850 rfid ; \ 851 b . ; /* prevent speculative execution */ 852 853#define SYSCALL_PSERIES_3 \ 854 /* Fast LE/BE switch system call */ \ 8551: mfspr r12,SPRN_SRR1 ; \ 856 xori r12,r12,MSR_LE ; \ 857 mtspr SPRN_SRR1,r12 ; \ 858 rfid ; /* return to userspace */ \ 859 b . ; /* prevent speculative execution */ 860 861#if defined(CONFIG_RELOCATABLE) 862 /* 863 * We can't branch directly so we do it via the CTR which 864 * is volatile across system calls. 865 */ 866#define SYSCALL_PSERIES_2_DIRECT \ 867 LOAD_SYSCALL_HANDLER(r12) ; \ 868 mtctr r12 ; \ 869 mfspr r12,SPRN_SRR1 ; \ 870 li r10,MSR_RI ; \ 871 mtmsrd r10,1 ; \ 872 bctr ; 873#else 874 /* We can branch directly */ 875#define SYSCALL_PSERIES_2_DIRECT \ 876 mfspr r12,SPRN_SRR1 ; \ 877 li r10,MSR_RI ; \ 878 mtmsrd r10,1 ; /* Set RI (EE=0) */ \ 879 b system_call_common ; 880#endif 881 882EXC_REAL_BEGIN(system_call, 0xc00, 0xd00) 883 /* 884 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems 885 * that support it) before changing to HMT_MEDIUM. That allows the KVM 886 * code to save that value into the guest state (it is the guest's PPR 887 * value). Otherwise just change to HMT_MEDIUM as userspace has 888 * already saved the PPR. 889 */ 890#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 891 SET_SCRATCH0(r13) 892 GET_PACA(r13) 893 std r9,PACA_EXGEN+EX_R9(r13) 894 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); 895 HMT_MEDIUM; 896 std r10,PACA_EXGEN+EX_R10(r13) 897 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); 898 mfcr r9 899 KVMTEST_PR(0xc00) 900 GET_SCRATCH0(r13) 901#else 902 HMT_MEDIUM; 903#endif 904 SYSCALL_PSERIES_1 905 SYSCALL_PSERIES_2_RFID 906 SYSCALL_PSERIES_3 907EXC_REAL_END(system_call, 0xc00, 0xd00) 908 909EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) 910 HMT_MEDIUM 911 SYSCALL_PSERIES_1 912 SYSCALL_PSERIES_2_DIRECT 913 SYSCALL_PSERIES_3 914EXC_VIRT_END(system_call, 0x4c00, 0x4d00) 915 916TRAMP_KVM(PACA_EXGEN, 0xc00) 917 918 919EXC_REAL(single_step, 0xd00, 0xe00) 920EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) 921TRAMP_KVM(PACA_EXGEN, 0xd00) 922EXC_COMMON(single_step_common, 0xd00, single_step_exception) 923 924EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) 925EXC_VIRT_NONE(0x4e00, 0x4e20) 926TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 927EXC_COMMON_BEGIN(h_data_storage_common) 928 mfspr r10,SPRN_HDAR 929 std r10,PACA_EXGEN+EX_DAR(r13) 930 mfspr r10,SPRN_HDSISR 931 stw r10,PACA_EXGEN+EX_DSISR(r13) 932 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) 933 bl save_nvgprs 934 RECONCILE_IRQ_STATE(r10, r11) 935 addi r3,r1,STACK_FRAME_OVERHEAD 936 bl unknown_exception 937 b ret_from_except 938 939 940EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) 941EXC_VIRT_NONE(0x4e20, 0x4e40) 942TRAMP_KVM_HV(PACA_EXGEN, 0xe20) 943EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 944 945 946EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) 947EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60, 0xe40) 948TRAMP_KVM_HV(PACA_EXGEN, 0xe40) 949EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 950 951 952/* 953 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 954 * first, and then eventaully from there to the trampoline to get into virtual 955 * mode. 956 */ 957__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) 958__TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) 959EXC_VIRT_NONE(0x4e60, 0x4e80) 960TRAMP_KVM_HV(PACA_EXGEN, 0xe60) 961TRAMP_REAL_BEGIN(hmi_exception_early) 962 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) 963 mr r10,r1 /* Save r1 */ 964 ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 965 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 966 std r9,_CCR(r1) /* save CR in stackframe */ 967 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 968 std r11,_NIP(r1) /* save HSRR0 in stackframe */ 969 mfspr r12,SPRN_HSRR1 /* Save SRR1 */ 970 std r12,_MSR(r1) /* save SRR1 in stackframe */ 971 std r10,0(r1) /* make stack chain pointer */ 972 std r0,GPR0(r1) /* save r0 in stackframe */ 973 std r10,GPR1(r1) /* save r1 in stackframe */ 974 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 975 EXCEPTION_PROLOG_COMMON_3(0xe60) 976 addi r3,r1,STACK_FRAME_OVERHEAD 977 bl hmi_exception_realmode 978 /* Windup the stack. */ 979 /* Move original HSRR0 and HSRR1 into the respective regs */ 980 ld r9,_MSR(r1) 981 mtspr SPRN_HSRR1,r9 982 ld r3,_NIP(r1) 983 mtspr SPRN_HSRR0,r3 984 ld r9,_CTR(r1) 985 mtctr r9 986 ld r9,_XER(r1) 987 mtxer r9 988 ld r9,_LINK(r1) 989 mtlr r9 990 REST_GPR(0, r1) 991 REST_8GPRS(2, r1) 992 REST_GPR(10, r1) 993 ld r11,_CCR(r1) 994 mtcr r11 995 REST_GPR(11, r1) 996 REST_2GPRS(12, r1) 997 /* restore original r1. */ 998 ld r1,GPR1(r1) 999 1000 /* 1001 * Go to virtual mode and pull the HMI event information from 1002 * firmware. 1003 */ 1004 .globl hmi_exception_after_realmode 1005hmi_exception_after_realmode: 1006 SET_SCRATCH0(r13) 1007 EXCEPTION_PROLOG_0(PACA_EXGEN) 1008 b tramp_real_hmi_exception 1009 1010EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) 1011 1012 1013EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) 1014EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0, 0xe80) 1015TRAMP_KVM_HV(PACA_EXGEN, 0xe80) 1016#ifdef CONFIG_PPC_DOORBELL 1017EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 1018#else 1019EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 1020#endif 1021 1022 1023EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) 1024EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0, 0xea0) 1025TRAMP_KVM_HV(PACA_EXGEN, 0xea0) 1026EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 1027 1028 1029EXC_REAL_NONE(0xec0, 0xf00) 1030EXC_VIRT_NONE(0x4ec0, 0x4f00) 1031 1032 1033EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) 1034EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20, 0xf00) 1035TRAMP_KVM(PACA_EXGEN, 0xf00) 1036EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1037 1038 1039EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) 1040EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40, 0xf20) 1041TRAMP_KVM(PACA_EXGEN, 0xf20) 1042EXC_COMMON_BEGIN(altivec_unavailable_common) 1043 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1044#ifdef CONFIG_ALTIVEC 1045BEGIN_FTR_SECTION 1046 beq 1f 1047#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1048 BEGIN_FTR_SECTION_NESTED(69) 1049 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1050 * transaction), go do TM stuff 1051 */ 1052 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1053 bne- 2f 1054 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1055#endif 1056 bl load_up_altivec 1057 b fast_exception_return 1058#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 10592: /* User process was in a transaction */ 1060 bl save_nvgprs 1061 RECONCILE_IRQ_STATE(r10, r11) 1062 addi r3,r1,STACK_FRAME_OVERHEAD 1063 bl altivec_unavailable_tm 1064 b ret_from_except 1065#endif 10661: 1067END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1068#endif 1069 bl save_nvgprs 1070 RECONCILE_IRQ_STATE(r10, r11) 1071 addi r3,r1,STACK_FRAME_OVERHEAD 1072 bl altivec_unavailable_exception 1073 b ret_from_except 1074 1075 1076EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) 1077EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60, 0xf40) 1078TRAMP_KVM(PACA_EXGEN, 0xf40) 1079EXC_COMMON_BEGIN(vsx_unavailable_common) 1080 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 1081#ifdef CONFIG_VSX 1082BEGIN_FTR_SECTION 1083 beq 1f 1084#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1085 BEGIN_FTR_SECTION_NESTED(69) 1086 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1087 * transaction), go do TM stuff 1088 */ 1089 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1090 bne- 2f 1091 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1092#endif 1093 b load_up_vsx 1094#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 10952: /* User process was in a transaction */ 1096 bl save_nvgprs 1097 RECONCILE_IRQ_STATE(r10, r11) 1098 addi r3,r1,STACK_FRAME_OVERHEAD 1099 bl vsx_unavailable_tm 1100 b ret_from_except 1101#endif 11021: 1103END_FTR_SECTION_IFSET(CPU_FTR_VSX) 1104#endif 1105 bl save_nvgprs 1106 RECONCILE_IRQ_STATE(r10, r11) 1107 addi r3,r1,STACK_FRAME_OVERHEAD 1108 bl vsx_unavailable_exception 1109 b ret_from_except 1110 1111 1112EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) 1113EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80, 0xf60) 1114TRAMP_KVM(PACA_EXGEN, 0xf60) 1115EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 1116 1117 1118EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) 1119EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0, 0xf80) 1120TRAMP_KVM_HV(PACA_EXGEN, 0xf80) 1121EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 1122 1123 1124EXC_REAL_NONE(0xfa0, 0x1200) 1125EXC_VIRT_NONE(0x4fa0, 0x5200) 1126 1127#ifdef CONFIG_CBE_RAS 1128EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) 1129EXC_VIRT_NONE(0x5200, 0x5300) 1130TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1131EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1132#else /* CONFIG_CBE_RAS */ 1133EXC_REAL_NONE(0x1200, 0x1300) 1134EXC_VIRT_NONE(0x5200, 0x5300) 1135#endif 1136 1137 1138EXC_REAL(instruction_breakpoint, 0x1300, 0x1400) 1139EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) 1140TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 1141EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 1142 1143EXC_REAL_NONE(0x1400, 0x1500) 1144EXC_VIRT_NONE(0x5400, 0x5500) 1145 1146EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) 1147 mtspr SPRN_SPRG_HSCRATCH0,r13 1148 EXCEPTION_PROLOG_0(PACA_EXGEN) 1149 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) 1150 1151#ifdef CONFIG_PPC_DENORMALISATION 1152 mfspr r10,SPRN_HSRR1 1153 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 1154 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1155 addi r11,r11,-4 /* HSRR0 is next instruction */ 1156 bne+ denorm_assist 1157#endif 1158 1159 KVMTEST_PR(0x1500) 1160 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) 1161EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) 1162 1163#ifdef CONFIG_PPC_DENORMALISATION 1164EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) 1165 b exc_real_0x1500_denorm_exception_hv 1166EXC_VIRT_END(denorm_exception, 0x5500, 0x5600) 1167#else 1168EXC_VIRT_NONE(0x5500, 0x5600) 1169#endif 1170 1171TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) 1172 1173#ifdef CONFIG_PPC_DENORMALISATION 1174TRAMP_REAL_BEGIN(denorm_assist) 1175BEGIN_FTR_SECTION 1176/* 1177 * To denormalise we need to move a copy of the register to itself. 1178 * For POWER6 do that here for all FP regs. 1179 */ 1180 mfmsr r10 1181 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1182 xori r10,r10,(MSR_FE0|MSR_FE1) 1183 mtmsrd r10 1184 sync 1185 1186#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 1187#define FMR4(n) FMR2(n) ; FMR2(n+2) 1188#define FMR8(n) FMR4(n) ; FMR4(n+4) 1189#define FMR16(n) FMR8(n) ; FMR8(n+8) 1190#define FMR32(n) FMR16(n) ; FMR16(n+16) 1191 FMR32(0) 1192 1193FTR_SECTION_ELSE 1194/* 1195 * To denormalise we need to move a copy of the register to itself. 1196 * For POWER7 do that here for the first 32 VSX registers only. 1197 */ 1198 mfmsr r10 1199 oris r10,r10,MSR_VSX@h 1200 mtmsrd r10 1201 sync 1202 1203#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) 1204#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) 1205#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) 1206#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) 1207#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) 1208 XVCPSGNDP32(0) 1209 1210ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1211 1212BEGIN_FTR_SECTION 1213 b denorm_done 1214END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1215/* 1216 * To denormalise we need to move a copy of the register to itself. 1217 * For POWER8 we need to do that for all 64 VSX registers 1218 */ 1219 XVCPSGNDP32(32) 1220denorm_done: 1221 mtspr SPRN_HSRR0,r11 1222 mtcrf 0x80,r9 1223 ld r9,PACA_EXGEN+EX_R9(r13) 1224 RESTORE_PPR_PACA(PACA_EXGEN, r10) 1225BEGIN_FTR_SECTION 1226 ld r10,PACA_EXGEN+EX_CFAR(r13) 1227 mtspr SPRN_CFAR,r10 1228END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1229 ld r10,PACA_EXGEN+EX_R10(r13) 1230 ld r11,PACA_EXGEN+EX_R11(r13) 1231 ld r12,PACA_EXGEN+EX_R12(r13) 1232 ld r13,PACA_EXGEN+EX_R13(r13) 1233 HRFID 1234 b . 1235#endif 1236 1237EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) 1238 1239 1240#ifdef CONFIG_CBE_RAS 1241EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) 1242EXC_VIRT_NONE(0x5600, 0x5700) 1243TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 1244EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1245#else /* CONFIG_CBE_RAS */ 1246EXC_REAL_NONE(0x1600, 0x1700) 1247EXC_VIRT_NONE(0x5600, 0x5700) 1248#endif 1249 1250 1251EXC_REAL(altivec_assist, 0x1700, 0x1800) 1252EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) 1253TRAMP_KVM(PACA_EXGEN, 0x1700) 1254#ifdef CONFIG_ALTIVEC 1255EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 1256#else 1257EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 1258#endif 1259 1260 1261#ifdef CONFIG_CBE_RAS 1262EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) 1263EXC_VIRT_NONE(0x5800, 0x5900) 1264TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 1265EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 1266#else /* CONFIG_CBE_RAS */ 1267EXC_REAL_NONE(0x1800, 0x1900) 1268EXC_VIRT_NONE(0x5800, 0x5900) 1269#endif 1270 1271 1272/* 1273 * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 1274 * - If it was a decrementer interrupt, we bump the dec to max and and return. 1275 * - If it was a doorbell we return immediately since doorbells are edge 1276 * triggered and won't automatically refire. 1277 * - If it was a HMI we return immediately since we handled it in realmode 1278 * and it won't refire. 1279 * - else we hard disable and return. 1280 * This is called with r10 containing the value to OR to the paca field. 1281 */ 1282#define MASKED_INTERRUPT(_H) \ 1283masked_##_H##interrupt: \ 1284 std r11,PACA_EXGEN+EX_R11(r13); \ 1285 lbz r11,PACAIRQHAPPENED(r13); \ 1286 or r11,r11,r10; \ 1287 stb r11,PACAIRQHAPPENED(r13); \ 1288 cmpwi r10,PACA_IRQ_DEC; \ 1289 bne 1f; \ 1290 lis r10,0x7fff; \ 1291 ori r10,r10,0xffff; \ 1292 mtspr SPRN_DEC,r10; \ 1293 b 2f; \ 12941: cmpwi r10,PACA_IRQ_DBELL; \ 1295 beq 2f; \ 1296 cmpwi r10,PACA_IRQ_HMI; \ 1297 beq 2f; \ 1298 mfspr r10,SPRN_##_H##SRR1; \ 1299 rldicl r10,r10,48,1; /* clear MSR_EE */ \ 1300 rotldi r10,r10,16; \ 1301 mtspr SPRN_##_H##SRR1,r10; \ 13022: mtcrf 0x80,r9; \ 1303 ld r9,PACA_EXGEN+EX_R9(r13); \ 1304 ld r10,PACA_EXGEN+EX_R10(r13); \ 1305 ld r11,PACA_EXGEN+EX_R11(r13); \ 1306 GET_SCRATCH0(r13); \ 1307 ##_H##rfid; \ 1308 b . 1309 1310/* 1311 * Real mode exceptions actually use this too, but alternate 1312 * instruction code patches (which end up in the common .text area) 1313 * cannot reach these if they are put there. 1314 */ 1315USE_FIXED_SECTION(virt_trampolines) 1316 MASKED_INTERRUPT() 1317 MASKED_INTERRUPT(H) 1318 1319#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1320TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 1321 /* 1322 * Here all GPRs are unchanged from when the interrupt happened 1323 * except for r13, which is saved in SPRG_SCRATCH0. 1324 */ 1325 mfspr r13, SPRN_SRR0 1326 addi r13, r13, 4 1327 mtspr SPRN_SRR0, r13 1328 GET_SCRATCH0(r13) 1329 rfid 1330 b . 1331 1332TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 1333 /* 1334 * Here all GPRs are unchanged from when the interrupt happened 1335 * except for r13, which is saved in SPRG_SCRATCH0. 1336 */ 1337 mfspr r13, SPRN_HSRR0 1338 addi r13, r13, 4 1339 mtspr SPRN_HSRR0, r13 1340 GET_SCRATCH0(r13) 1341 hrfid 1342 b . 1343#endif 1344 1345/* 1346 * Ensure that any handlers that get invoked from the exception prologs 1347 * above are below the first 64KB (0x10000) of the kernel image because 1348 * the prologs assemble the addresses of these handlers using the 1349 * LOAD_HANDLER macro, which uses an ori instruction. 1350 */ 1351 1352/*** Common interrupt handlers ***/ 1353 1354 1355 /* 1356 * Relocation-on interrupts: A subset of the interrupts can be delivered 1357 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 1358 * it. Addresses are the same as the original interrupt addresses, but 1359 * offset by 0xc000000000004000. 1360 * It's impossible to receive interrupts below 0x300 via this mechanism. 1361 * KVM: None of these traps are from the guest ; anything that escalated 1362 * to HV=1 from HV=0 is delivered via real mode handlers. 1363 */ 1364 1365 /* 1366 * This uses the standard macro, since the original 0x300 vector 1367 * only has extra guff for STAB-based processors -- which never 1368 * come here. 1369 */ 1370 1371EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 1372 b __ppc64_runlatch_on 1373 1374USE_FIXED_SECTION(virt_trampolines) 1375 /* 1376 * The __end_interrupts marker must be past the out-of-line (OOL) 1377 * handlers, so that they are copied to real address 0x100 when running 1378 * a relocatable kernel. This ensures they can be reached from the short 1379 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 1380 * directly, without using LOAD_HANDLER(). 1381 */ 1382 .align 7 1383 .globl __end_interrupts 1384__end_interrupts: 1385DEFINE_FIXED_SYMBOL(__end_interrupts) 1386 1387#ifdef CONFIG_PPC_970_NAP 1388EXC_COMMON_BEGIN(power4_fixup_nap) 1389 andc r9,r9,r10 1390 std r9,TI_LOCAL_FLAGS(r11) 1391 ld r10,_LINK(r1) /* make idle task do the */ 1392 std r10,_NIP(r1) /* equivalent of a blr */ 1393 blr 1394#endif 1395 1396CLOSE_FIXED_SECTION(real_vectors); 1397CLOSE_FIXED_SECTION(real_trampolines); 1398CLOSE_FIXED_SECTION(virt_vectors); 1399CLOSE_FIXED_SECTION(virt_trampolines); 1400 1401USE_TEXT_SECTION() 1402 1403/* 1404 * Hash table stuff 1405 */ 1406 .align 7 1407do_hash_page: 1408#ifdef CONFIG_PPC_STD_MMU_64 1409 andis. r0,r4,0xa410 /* weird error? */ 1410 bne- handle_page_fault /* if not, try to insert a HPTE */ 1411 andis. r0,r4,DSISR_DABRMATCH@h 1412 bne- handle_dabr_fault 1413 CURRENT_THREAD_INFO(r11, r1) 1414 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 1415 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 1416 bne 77f /* then don't call hash_page now */ 1417 1418 /* 1419 * r3 contains the faulting address 1420 * r4 msr 1421 * r5 contains the trap number 1422 * r6 contains dsisr 1423 * 1424 * at return r3 = 0 for success, 1 for page fault, negative for error 1425 */ 1426 mr r4,r12 1427 ld r6,_DSISR(r1) 1428 bl __hash_page /* build HPTE if possible */ 1429 cmpdi r3,0 /* see if __hash_page succeeded */ 1430 1431 /* Success */ 1432 beq fast_exc_return_irq /* Return from exception on success */ 1433 1434 /* Error */ 1435 blt- 13f 1436#endif /* CONFIG_PPC_STD_MMU_64 */ 1437 1438/* Here we have a page fault that hash_page can't handle. */ 1439handle_page_fault: 144011: ld r4,_DAR(r1) 1441 ld r5,_DSISR(r1) 1442 addi r3,r1,STACK_FRAME_OVERHEAD 1443 bl do_page_fault 1444 cmpdi r3,0 1445 beq+ 12f 1446 bl save_nvgprs 1447 mr r5,r3 1448 addi r3,r1,STACK_FRAME_OVERHEAD 1449 lwz r4,_DAR(r1) 1450 bl bad_page_fault 1451 b ret_from_except 1452 1453/* We have a data breakpoint exception - handle it */ 1454handle_dabr_fault: 1455 bl save_nvgprs 1456 ld r4,_DAR(r1) 1457 ld r5,_DSISR(r1) 1458 addi r3,r1,STACK_FRAME_OVERHEAD 1459 bl do_break 146012: b ret_from_except_lite 1461 1462 1463#ifdef CONFIG_PPC_STD_MMU_64 1464/* We have a page fault that hash_page could handle but HV refused 1465 * the PTE insertion 1466 */ 146713: bl save_nvgprs 1468 mr r5,r3 1469 addi r3,r1,STACK_FRAME_OVERHEAD 1470 ld r4,_DAR(r1) 1471 bl low_hash_fault 1472 b ret_from_except 1473#endif 1474 1475/* 1476 * We come here as a result of a DSI at a point where we don't want 1477 * to call hash_page, such as when we are accessing memory (possibly 1478 * user memory) inside a PMU interrupt that occurred while interrupts 1479 * were soft-disabled. We want to invoke the exception handler for 1480 * the access, or panic if there isn't a handler. 1481 */ 148277: bl save_nvgprs 1483 mr r4,r3 1484 addi r3,r1,STACK_FRAME_OVERHEAD 1485 li r5,SIGSEGV 1486 bl bad_page_fault 1487 b ret_from_except 1488 1489/* 1490 * Here we have detected that the kernel stack pointer is bad. 1491 * R9 contains the saved CR, r13 points to the paca, 1492 * r10 contains the (bad) kernel stack pointer, 1493 * r11 and r12 contain the saved SRR0 and SRR1. 1494 * We switch to using an emergency stack, save the registers there, 1495 * and call kernel_bad_stack(), which panics. 1496 */ 1497bad_stack: 1498 ld r1,PACAEMERGSP(r13) 1499 subi r1,r1,64+INT_FRAME_SIZE 1500 std r9,_CCR(r1) 1501 std r10,GPR1(r1) 1502 std r11,_NIP(r1) 1503 std r12,_MSR(r1) 1504 mfspr r11,SPRN_DAR 1505 mfspr r12,SPRN_DSISR 1506 std r11,_DAR(r1) 1507 std r12,_DSISR(r1) 1508 mflr r10 1509 mfctr r11 1510 mfxer r12 1511 std r10,_LINK(r1) 1512 std r11,_CTR(r1) 1513 std r12,_XER(r1) 1514 SAVE_GPR(0,r1) 1515 SAVE_GPR(2,r1) 1516 ld r10,EX_R3(r3) 1517 std r10,GPR3(r1) 1518 SAVE_GPR(4,r1) 1519 SAVE_4GPRS(5,r1) 1520 ld r9,EX_R9(r3) 1521 ld r10,EX_R10(r3) 1522 SAVE_2GPRS(9,r1) 1523 ld r9,EX_R11(r3) 1524 ld r10,EX_R12(r3) 1525 ld r11,EX_R13(r3) 1526 std r9,GPR11(r1) 1527 std r10,GPR12(r1) 1528 std r11,GPR13(r1) 1529BEGIN_FTR_SECTION 1530 ld r10,EX_CFAR(r3) 1531 std r10,ORIG_GPR3(r1) 1532END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1533 SAVE_8GPRS(14,r1) 1534 SAVE_10GPRS(22,r1) 1535 lhz r12,PACA_TRAP_SAVE(r13) 1536 std r12,_TRAP(r1) 1537 addi r11,r1,INT_FRAME_SIZE 1538 std r11,0(r1) 1539 li r12,0 1540 std r12,0(r11) 1541 ld r2,PACATOC(r13) 1542 ld r11,exception_marker@toc(r2) 1543 std r12,RESULT(r1) 1544 std r11,STACK_FRAME_OVERHEAD-16(r1) 15451: addi r3,r1,STACK_FRAME_OVERHEAD 1546 bl kernel_bad_stack 1547 b 1b 1548 1549/* 1550 * Called from arch_local_irq_enable when an interrupt needs 1551 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 1552 * which kind of interrupt. MSR:EE is already off. We generate a 1553 * stackframe like if a real interrupt had happened. 1554 * 1555 * Note: While MSR:EE is off, we need to make sure that _MSR 1556 * in the generated frame has EE set to 1 or the exception 1557 * handler will not properly re-enable them. 1558 */ 1559_GLOBAL(__replay_interrupt) 1560 /* We are going to jump to the exception common code which 1561 * will retrieve various register values from the PACA which 1562 * we don't give a damn about, so we don't bother storing them. 1563 */ 1564 mfmsr r12 1565 mflr r11 1566 mfcr r9 1567 ori r12,r12,MSR_EE 1568 cmpwi r3,0x900 1569 beq decrementer_common 1570 cmpwi r3,0x500 1571 beq hardware_interrupt_common 1572BEGIN_FTR_SECTION 1573 cmpwi r3,0xe80 1574 beq h_doorbell_common 1575 cmpwi r3,0xea0 1576 beq h_virt_irq_common 1577 cmpwi r3,0xe60 1578 beq hmi_exception_common 1579FTR_SECTION_ELSE 1580 cmpwi r3,0xa00 1581 beq doorbell_super_common 1582ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1583 blr 1584