1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This file contains the 64-bit "server" PowerPC variant 4 * of the low level exception handling including exception 5 * vectors, exception return, part of the slb and stab 6 * handling and other fixed offset specific things. 7 * 8 * This file is meant to be #included from head_64.S due to 9 * position dependent assembly. 10 * 11 * Most of this originates from head_64.S and thus has the same 12 * copyright history. 13 * 14 */ 15 16#include <asm/hw_irq.h> 17#include <asm/exception-64s.h> 18#include <asm/ptrace.h> 19#include <asm/cpuidle.h> 20#include <asm/head-64.h> 21 22/* 23 * There are a few constraints to be concerned with. 24 * - Real mode exceptions code/data must be located at their physical location. 25 * - Virtual mode exceptions must be mapped at their 0xc000... location. 26 * - Fixed location code must not call directly beyond the __end_interrupts 27 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 28 * must be used. 29 * - LOAD_HANDLER targets must be within first 64K of physical 0 / 30 * virtual 0xc00... 31 * - Conditional branch targets must be within +/-32K of caller. 32 * 33 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 34 * therefore don't have to run in physically located code or rfid to 35 * virtual mode kernel code. However on relocatable kernels they do have 36 * to branch to KERNELBASE offset because the rest of the kernel (outside 37 * the exception vectors) may be located elsewhere. 38 * 39 * Virtual exceptions correspond with physical, except their entry points 40 * are offset by 0xc000000000000000 and also tend to get an added 0x4000 41 * offset applied. Virtual exceptions are enabled with the Alternate 42 * Interrupt Location (AIL) bit set in the LPCR. However this does not 43 * guarantee they will be delivered virtually. Some conditions (see the ISA) 44 * cause exceptions to be delivered in real mode. 45 * 46 * It's impossible to receive interrupts below 0x300 via AIL. 47 * 48 * KVM: None of the virtual exceptions are from the guest. Anything that 49 * escalated to HV=1 from HV=0 is delivered via real mode handlers. 50 * 51 * 52 * We layout physical memory as follows: 53 * 0x0000 - 0x00ff : Secondary processor spin code 54 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 55 * 0x1900 - 0x3fff : Real mode trampolines 56 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 57 * 0x5900 - 0x6fff : Relon mode trampolines 58 * 0x7000 - 0x7fff : FWNMI data area 59 * 0x8000 - .... : Common interrupt handlers, remaining early 60 * setup code, rest of kernel. 61 * 62 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 63 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 64 * vectors there. 65 */ 66OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 67OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 68OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 69OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 70#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 71/* 72 * Data area reserved for FWNMI option. 73 * This address (0x7000) is fixed by the RPA. 74 * pseries and powernv need to keep the whole page from 75 * 0x7000 to 0x8000 free for use by the firmware 76 */ 77ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 78OPEN_TEXT_SECTION(0x8000) 79#else 80OPEN_TEXT_SECTION(0x7000) 81#endif 82 83USE_FIXED_SECTION(real_vectors) 84 85/* 86 * This is the start of the interrupt handlers for pSeries 87 * This code runs with relocation off. 88 * Code from here to __end_interrupts gets copied down to real 89 * address 0x100 when we are running a relocatable kernel. 90 * Therefore any relative branches in this section must only 91 * branch to labels in this section. 92 */ 93 .globl __start_interrupts 94__start_interrupts: 95 96/* No virt vectors corresponding with 0x0..0x100 */ 97EXC_VIRT_NONE(0x4000, 0x100) 98 99 100#ifdef CONFIG_PPC_P7_NAP 101 /* 102 * If running native on arch 2.06 or later, check if we are waking up 103 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 104 * bits 46:47. A non-0 value indicates that we are coming from a power 105 * saving state. The idle wakeup handler initially runs in real mode, 106 * but we branch to the 0xc000... address so we can turn on relocation 107 * with mtmsr. 108 */ 109#define IDLETEST(n) \ 110 BEGIN_FTR_SECTION ; \ 111 mfspr r10,SPRN_SRR1 ; \ 112 rlwinm. r10,r10,47-31,30,31 ; \ 113 beq- 1f ; \ 114 cmpwi cr3,r10,2 ; \ 115 BRANCH_TO_C000(r10, system_reset_idle_common) ; \ 1161: \ 117 KVMTEST_PR(n) ; \ 118 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 119#else 120#define IDLETEST NOTEST 121#endif 122 123EXC_REAL_BEGIN(system_reset, 0x100, 0x100) 124 SET_SCRATCH0(r13) 125 /* 126 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 127 * being used, so a nested NMI exception would corrupt it. 128 */ 129 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD, 130 IDLETEST, 0x100) 131 132EXC_REAL_END(system_reset, 0x100, 0x100) 133EXC_VIRT_NONE(0x4100, 0x100) 134TRAMP_KVM(PACA_EXNMI, 0x100) 135 136#ifdef CONFIG_PPC_P7_NAP 137EXC_COMMON_BEGIN(system_reset_idle_common) 138 mfspr r12,SPRN_SRR1 139 b pnv_powersave_wakeup 140#endif 141 142EXC_COMMON_BEGIN(system_reset_common) 143 /* 144 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 145 * to recover, but nested NMI will notice in_nmi and not recover 146 * because of the use of the NMI stack. in_nmi reentrancy is tested in 147 * system_reset_exception. 148 */ 149 lhz r10,PACA_IN_NMI(r13) 150 addi r10,r10,1 151 sth r10,PACA_IN_NMI(r13) 152 li r10,MSR_RI 153 mtmsrd r10,1 154 155 mr r10,r1 156 ld r1,PACA_NMI_EMERG_SP(r13) 157 subi r1,r1,INT_FRAME_SIZE 158 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, 159 system_reset, system_reset_exception, 160 ADD_NVGPRS;ADD_RECONCILE) 161 162 /* 163 * The stack is no longer in use, decrement in_nmi. 164 */ 165 lhz r10,PACA_IN_NMI(r13) 166 subi r10,r10,1 167 sth r10,PACA_IN_NMI(r13) 168 169 b ret_from_except 170 171#ifdef CONFIG_PPC_PSERIES 172/* 173 * Vectors for the FWNMI option. Share common code. 174 */ 175TRAMP_REAL_BEGIN(system_reset_fwnmi) 176 SET_SCRATCH0(r13) /* save r13 */ 177 /* See comment at system_reset exception */ 178 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, 179 EXC_STD, NOTEST, 0x100) 180#endif /* CONFIG_PPC_PSERIES */ 181 182 183EXC_REAL_BEGIN(machine_check, 0x200, 0x100) 184 /* This is moved out of line as it can be patched by FW, but 185 * some code path might still want to branch into the original 186 * vector 187 */ 188 SET_SCRATCH0(r13) /* save r13 */ 189 EXCEPTION_PROLOG_0(PACA_EXMC) 190BEGIN_FTR_SECTION 191 b machine_check_powernv_early 192FTR_SECTION_ELSE 193 b machine_check_pSeries_0 194ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 195EXC_REAL_END(machine_check, 0x200, 0x100) 196EXC_VIRT_NONE(0x4200, 0x100) 197TRAMP_REAL_BEGIN(machine_check_powernv_early) 198BEGIN_FTR_SECTION 199 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) 200 /* 201 * Register contents: 202 * R13 = PACA 203 * R9 = CR 204 * Original R9 to R13 is saved on PACA_EXMC 205 * 206 * Switch to mc_emergency stack and handle re-entrancy (we limit 207 * the nested MCE upto level 4 to avoid stack overflow). 208 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 209 * 210 * We use paca->in_mce to check whether this is the first entry or 211 * nested machine check. We increment paca->in_mce to track nested 212 * machine checks. 213 * 214 * If this is the first entry then set stack pointer to 215 * paca->mc_emergency_sp, otherwise r1 is already pointing to 216 * stack frame on mc_emergency stack. 217 * 218 * NOTE: We are here with MSR_ME=0 (off), which means we risk a 219 * checkstop if we get another machine check exception before we do 220 * rfid with MSR_ME=1. 221 * 222 * This interrupt can wake directly from idle. If that is the case, 223 * the machine check is handled then the idle wakeup code is called 224 * to restore state. In that case, the POWER9 DD1 idle PACA workaround 225 * is not applied in the early machine check code, which will cause 226 * bugs. 227 */ 228 mr r11,r1 /* Save r1 */ 229 lhz r10,PACA_IN_MCE(r13) 230 cmpwi r10,0 /* Are we in nested machine check */ 231 bne 0f /* Yes, we are. */ 232 /* First machine check entry */ 233 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 2340: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 235 addi r10,r10,1 /* increment paca->in_mce */ 236 sth r10,PACA_IN_MCE(r13) 237 /* Limit nested MCE to level 4 to avoid stack overflow */ 238 cmpwi r10,MAX_MCE_DEPTH 239 bgt 2f /* Check if we hit limit of 4 */ 240 std r11,GPR1(r1) /* Save r1 on the stack. */ 241 std r11,0(r1) /* make stack chain pointer */ 242 mfspr r11,SPRN_SRR0 /* Save SRR0 */ 243 std r11,_NIP(r1) 244 mfspr r11,SPRN_SRR1 /* Save SRR1 */ 245 std r11,_MSR(r1) 246 mfspr r11,SPRN_DAR /* Save DAR */ 247 std r11,_DAR(r1) 248 mfspr r11,SPRN_DSISR /* Save DSISR */ 249 std r11,_DSISR(r1) 250 std r9,_CCR(r1) /* Save CR in stackframe */ 251 /* Save r9 through r13 from EXMC save area to stack frame. */ 252 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 253 mfmsr r11 /* get MSR value */ 254 ori r11,r11,MSR_ME /* turn on ME bit */ 255 ori r11,r11,MSR_RI /* turn on RI bit */ 256 LOAD_HANDLER(r12, machine_check_handle_early) 2571: mtspr SPRN_SRR0,r12 258 mtspr SPRN_SRR1,r11 259 rfid 260 b . /* prevent speculative execution */ 2612: 262 /* Stack overflow. Stay on emergency stack and panic. 263 * Keep the ME bit off while panic-ing, so that if we hit 264 * another machine check we checkstop. 265 */ 266 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 267 ld r11,PACAKMSR(r13) 268 LOAD_HANDLER(r12, unrecover_mce) 269 li r10,MSR_ME 270 andc r11,r11,r10 /* Turn off MSR_ME */ 271 b 1b 272 b . /* prevent speculative execution */ 273END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 274 275TRAMP_REAL_BEGIN(machine_check_pSeries) 276 .globl machine_check_fwnmi 277machine_check_fwnmi: 278 SET_SCRATCH0(r13) /* save r13 */ 279 EXCEPTION_PROLOG_0(PACA_EXMC) 280machine_check_pSeries_0: 281 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) 282 /* 283 * MSR_RI is not enabled, because PACA_EXMC is being used, so a 284 * nested machine check corrupts it. machine_check_common enables 285 * MSR_RI. 286 */ 287 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD) 288 289TRAMP_KVM_SKIP(PACA_EXMC, 0x200) 290 291EXC_COMMON_BEGIN(machine_check_common) 292 /* 293 * Machine check is different because we use a different 294 * save area: PACA_EXMC instead of PACA_EXGEN. 295 */ 296 mfspr r10,SPRN_DAR 297 std r10,PACA_EXMC+EX_DAR(r13) 298 mfspr r10,SPRN_DSISR 299 stw r10,PACA_EXMC+EX_DSISR(r13) 300 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 301 FINISH_NAP 302 RECONCILE_IRQ_STATE(r10, r11) 303 ld r3,PACA_EXMC+EX_DAR(r13) 304 lwz r4,PACA_EXMC+EX_DSISR(r13) 305 /* Enable MSR_RI when finished with PACA_EXMC */ 306 li r10,MSR_RI 307 mtmsrd r10,1 308 std r3,_DAR(r1) 309 std r4,_DSISR(r1) 310 bl save_nvgprs 311 addi r3,r1,STACK_FRAME_OVERHEAD 312 bl machine_check_exception 313 b ret_from_except 314 315#define MACHINE_CHECK_HANDLER_WINDUP \ 316 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 317 li r0,MSR_RI; \ 318 mfmsr r9; /* get MSR value */ \ 319 andc r9,r9,r0; \ 320 mtmsrd r9,1; /* Clear MSR_RI */ \ 321 /* Move original SRR0 and SRR1 into the respective regs */ \ 322 ld r9,_MSR(r1); \ 323 mtspr SPRN_SRR1,r9; \ 324 ld r3,_NIP(r1); \ 325 mtspr SPRN_SRR0,r3; \ 326 ld r9,_CTR(r1); \ 327 mtctr r9; \ 328 ld r9,_XER(r1); \ 329 mtxer r9; \ 330 ld r9,_LINK(r1); \ 331 mtlr r9; \ 332 REST_GPR(0, r1); \ 333 REST_8GPRS(2, r1); \ 334 REST_GPR(10, r1); \ 335 ld r11,_CCR(r1); \ 336 mtcr r11; \ 337 /* Decrement paca->in_mce. */ \ 338 lhz r12,PACA_IN_MCE(r13); \ 339 subi r12,r12,1; \ 340 sth r12,PACA_IN_MCE(r13); \ 341 REST_GPR(11, r1); \ 342 REST_2GPRS(12, r1); \ 343 /* restore original r1. */ \ 344 ld r1,GPR1(r1) 345 346#ifdef CONFIG_PPC_P7_NAP 347/* 348 * This is an idle wakeup. Low level machine check has already been 349 * done. Queue the event then call the idle code to do the wake up. 350 */ 351EXC_COMMON_BEGIN(machine_check_idle_common) 352 bl machine_check_queue_event 353 354 /* 355 * We have not used any non-volatile GPRs here, and as a rule 356 * most exception code including machine check does not. 357 * Therefore PACA_NAPSTATELOST does not need to be set. Idle 358 * wakeup will restore volatile registers. 359 * 360 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. 361 * 362 * Then decrement MCE nesting after finishing with the stack. 363 */ 364 ld r3,_MSR(r1) 365 366 lhz r11,PACA_IN_MCE(r13) 367 subi r11,r11,1 368 sth r11,PACA_IN_MCE(r13) 369 370 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ 371 /* Recoverability could be improved by reducing the use of SRR1. */ 372 li r11,0 373 mtmsrd r11,1 374 375 b pnv_powersave_wakeup_mce 376#endif 377 /* 378 * Handle machine check early in real mode. We come here with 379 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 380 */ 381EXC_COMMON_BEGIN(machine_check_handle_early) 382 std r0,GPR0(r1) /* Save r0 */ 383 EXCEPTION_PROLOG_COMMON_3(0x200) 384 bl save_nvgprs 385 addi r3,r1,STACK_FRAME_OVERHEAD 386 bl machine_check_early 387 std r3,RESULT(r1) /* Save result */ 388 ld r12,_MSR(r1) 389 390#ifdef CONFIG_PPC_P7_NAP 391 /* 392 * Check if thread was in power saving mode. We come here when any 393 * of the following is true: 394 * a. thread wasn't in power saving mode 395 * b. thread was in power saving mode with no state loss, 396 * supervisor state loss or hypervisor state loss. 397 * 398 * Go back to nap/sleep/winkle mode again if (b) is true. 399 */ 400 BEGIN_FTR_SECTION 401 rlwinm. r11,r12,47-31,30,31 402 bne machine_check_idle_common 403 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 404#endif 405 406 /* 407 * Check if we are coming from hypervisor userspace. If yes then we 408 * continue in host kernel in V mode to deliver the MC event. 409 */ 410 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 411 beq 5f 412 andi. r11,r12,MSR_PR /* See if coming from user. */ 413 bne 9f /* continue in V mode if we are. */ 414 4155: 416#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 417 /* 418 * We are coming from kernel context. Check if we are coming from 419 * guest. if yes, then we can continue. We will fall through 420 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 421 */ 422 lbz r11,HSTATE_IN_GUEST(r13) 423 cmpwi r11,0 /* Check if coming from guest */ 424 bne 9f /* continue if we are. */ 425#endif 426 /* 427 * At this point we are not sure about what context we come from. 428 * Queue up the MCE event and return from the interrupt. 429 * But before that, check if this is an un-recoverable exception. 430 * If yes, then stay on emergency stack and panic. 431 */ 432 andi. r11,r12,MSR_RI 433 bne 2f 4341: mfspr r11,SPRN_SRR0 435 LOAD_HANDLER(r10,unrecover_mce) 436 mtspr SPRN_SRR0,r10 437 ld r10,PACAKMSR(r13) 438 /* 439 * We are going down. But there are chances that we might get hit by 440 * another MCE during panic path and we may run into unstable state 441 * with no way out. Hence, turn ME bit off while going down, so that 442 * when another MCE is hit during panic path, system will checkstop 443 * and hypervisor will get restarted cleanly by SP. 444 */ 445 li r3,MSR_ME 446 andc r10,r10,r3 /* Turn off MSR_ME */ 447 mtspr SPRN_SRR1,r10 448 rfid 449 b . 4502: 451 /* 452 * Check if we have successfully handled/recovered from error, if not 453 * then stay on emergency stack and panic. 454 */ 455 ld r3,RESULT(r1) /* Load result */ 456 cmpdi r3,0 /* see if we handled MCE successfully */ 457 458 beq 1b /* if !handled then panic */ 459 /* 460 * Return from MC interrupt. 461 * Queue up the MCE event so that we can log it later, while 462 * returning from kernel or opal call. 463 */ 464 bl machine_check_queue_event 465 MACHINE_CHECK_HANDLER_WINDUP 466 rfid 4679: 468 /* Deliver the machine check to host kernel in V mode. */ 469 MACHINE_CHECK_HANDLER_WINDUP 470 b machine_check_pSeries 471 472EXC_COMMON_BEGIN(unrecover_mce) 473 /* Invoke machine_check_exception to print MCE event and panic. */ 474 addi r3,r1,STACK_FRAME_OVERHEAD 475 bl machine_check_exception 476 /* 477 * We will not reach here. Even if we did, there is no way out. Call 478 * unrecoverable_exception and die. 479 */ 4801: addi r3,r1,STACK_FRAME_OVERHEAD 481 bl unrecoverable_exception 482 b 1b 483 484 485EXC_REAL(data_access, 0x300, 0x80) 486EXC_VIRT(data_access, 0x4300, 0x80, 0x300) 487TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 488 489EXC_COMMON_BEGIN(data_access_common) 490 /* 491 * Here r13 points to the paca, r9 contains the saved CR, 492 * SRR0 and SRR1 are saved in r11 and r12, 493 * r9 - r13 are saved in paca->exgen. 494 */ 495 mfspr r10,SPRN_DAR 496 std r10,PACA_EXGEN+EX_DAR(r13) 497 mfspr r10,SPRN_DSISR 498 stw r10,PACA_EXGEN+EX_DSISR(r13) 499 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 500 RECONCILE_IRQ_STATE(r10, r11) 501 ld r12,_MSR(r1) 502 ld r3,PACA_EXGEN+EX_DAR(r13) 503 lwz r4,PACA_EXGEN+EX_DSISR(r13) 504 li r5,0x300 505 std r3,_DAR(r1) 506 std r4,_DSISR(r1) 507BEGIN_MMU_FTR_SECTION 508 b do_hash_page /* Try to handle as hpte fault */ 509MMU_FTR_SECTION_ELSE 510 b handle_page_fault 511ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 512 513 514EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 515 SET_SCRATCH0(r13) 516 EXCEPTION_PROLOG_0(PACA_EXSLB) 517 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) 518 mr r12,r3 /* save r3 */ 519 mfspr r3,SPRN_DAR 520 mfspr r11,SPRN_SRR1 521 crset 4*cr6+eq 522 BRANCH_TO_COMMON(r10, slb_miss_common) 523EXC_REAL_END(data_access_slb, 0x380, 0x80) 524 525EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 526 SET_SCRATCH0(r13) 527 EXCEPTION_PROLOG_0(PACA_EXSLB) 528 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) 529 mr r12,r3 /* save r3 */ 530 mfspr r3,SPRN_DAR 531 mfspr r11,SPRN_SRR1 532 crset 4*cr6+eq 533 BRANCH_TO_COMMON(r10, slb_miss_common) 534EXC_VIRT_END(data_access_slb, 0x4380, 0x80) 535TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 536 537 538EXC_REAL(instruction_access, 0x400, 0x80) 539EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 540TRAMP_KVM(PACA_EXGEN, 0x400) 541 542EXC_COMMON_BEGIN(instruction_access_common) 543 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 544 RECONCILE_IRQ_STATE(r10, r11) 545 ld r12,_MSR(r1) 546 ld r3,_NIP(r1) 547 andis. r4,r12,DSISR_SRR1_MATCH_64S@h 548 li r5,0x400 549 std r3,_DAR(r1) 550 std r4,_DSISR(r1) 551BEGIN_MMU_FTR_SECTION 552 b do_hash_page /* Try to handle as hpte fault */ 553MMU_FTR_SECTION_ELSE 554 b handle_page_fault 555ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 556 557 558EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) 559 SET_SCRATCH0(r13) 560 EXCEPTION_PROLOG_0(PACA_EXSLB) 561 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) 562 mr r12,r3 /* save r3 */ 563 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 564 mfspr r11,SPRN_SRR1 565 crclr 4*cr6+eq 566 BRANCH_TO_COMMON(r10, slb_miss_common) 567EXC_REAL_END(instruction_access_slb, 0x480, 0x80) 568 569EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) 570 SET_SCRATCH0(r13) 571 EXCEPTION_PROLOG_0(PACA_EXSLB) 572 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) 573 mr r12,r3 /* save r3 */ 574 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 575 mfspr r11,SPRN_SRR1 576 crclr 4*cr6+eq 577 BRANCH_TO_COMMON(r10, slb_miss_common) 578EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) 579TRAMP_KVM(PACA_EXSLB, 0x480) 580 581 582/* 583 * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as 584 * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled. 585 */ 586EXC_COMMON_BEGIN(slb_miss_common) 587 /* 588 * r13 points to the PACA, r9 contains the saved CR, 589 * r12 contains the saved r3, 590 * r11 contain the saved SRR1, SRR0 is still ready for return 591 * r3 has the faulting address 592 * r9 - r13 are saved in paca->exslb. 593 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss 594 * We assume we aren't going to take any exceptions during this 595 * procedure. 596 */ 597 mflr r10 598 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 599 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 600 601 /* 602 * Test MSR_RI before calling slb_allocate_realmode, because the 603 * MSR in r11 gets clobbered. However we still want to allocate 604 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in 605 * recursive SLB faults. So use cr5 for this, which is preserved. 606 */ 607 andi. r11,r11,MSR_RI /* check for unrecoverable exception */ 608 cmpdi cr5,r11,MSR_RI 609 610 crset 4*cr0+eq 611#ifdef CONFIG_PPC_BOOK3S_64 612BEGIN_MMU_FTR_SECTION 613 bl slb_allocate 614END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) 615#endif 616 617 ld r10,PACA_EXSLB+EX_LR(r13) 618 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 619 mtlr r10 620 621 beq- 8f /* if bad address, make full stack frame */ 622 623 bne- cr5,2f /* if unrecoverable exception, oops */ 624 625 /* All done -- return from exception. */ 626 627.machine push 628.machine "power4" 629 mtcrf 0x80,r9 630 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */ 631 mtcrf 0x02,r9 /* I/D indication is in cr6 */ 632 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 633.machine pop 634 635 RESTORE_CTR(r9, PACA_EXSLB) 636 RESTORE_PPR_PACA(PACA_EXSLB, r9) 637 mr r3,r12 638 ld r9,PACA_EXSLB+EX_R9(r13) 639 ld r10,PACA_EXSLB+EX_R10(r13) 640 ld r11,PACA_EXSLB+EX_R11(r13) 641 ld r12,PACA_EXSLB+EX_R12(r13) 642 ld r13,PACA_EXSLB+EX_R13(r13) 643 rfid 644 b . /* prevent speculative execution */ 645 6462: std r3,PACA_EXSLB+EX_DAR(r13) 647 mr r3,r12 648 mfspr r11,SPRN_SRR0 649 mfspr r12,SPRN_SRR1 650 LOAD_HANDLER(r10,unrecov_slb) 651 mtspr SPRN_SRR0,r10 652 ld r10,PACAKMSR(r13) 653 mtspr SPRN_SRR1,r10 654 rfid 655 b . 656 6578: std r3,PACA_EXSLB+EX_DAR(r13) 658 mr r3,r12 659 mfspr r11,SPRN_SRR0 660 mfspr r12,SPRN_SRR1 661 LOAD_HANDLER(r10,bad_addr_slb) 662 mtspr SPRN_SRR0,r10 663 ld r10,PACAKMSR(r13) 664 mtspr SPRN_SRR1,r10 665 rfid 666 b . 667 668EXC_COMMON_BEGIN(unrecov_slb) 669 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 670 RECONCILE_IRQ_STATE(r10, r11) 671 bl save_nvgprs 6721: addi r3,r1,STACK_FRAME_OVERHEAD 673 bl unrecoverable_exception 674 b 1b 675 676EXC_COMMON_BEGIN(bad_addr_slb) 677 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) 678 RECONCILE_IRQ_STATE(r10, r11) 679 ld r3, PACA_EXSLB+EX_DAR(r13) 680 std r3, _DAR(r1) 681 beq cr6, 2f 682 li r10, 0x480 /* fix trap number for I-SLB miss */ 683 std r10, _TRAP(r1) 6842: bl save_nvgprs 685 addi r3, r1, STACK_FRAME_OVERHEAD 686 bl slb_miss_bad_addr 687 b ret_from_except 688 689EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 690 .globl hardware_interrupt_hv; 691hardware_interrupt_hv: 692 BEGIN_FTR_SECTION 693 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 694 EXC_HV, SOFTEN_TEST_HV) 695 FTR_SECTION_ELSE 696 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 697 EXC_STD, SOFTEN_TEST_PR) 698 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 699EXC_REAL_END(hardware_interrupt, 0x500, 0x100) 700 701EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 702 .globl hardware_interrupt_relon_hv; 703hardware_interrupt_relon_hv: 704 BEGIN_FTR_SECTION 705 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) 706 FTR_SECTION_ELSE 707 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) 708 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 709EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 710 711TRAMP_KVM(PACA_EXGEN, 0x500) 712TRAMP_KVM_HV(PACA_EXGEN, 0x500) 713EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 714 715 716EXC_REAL(alignment, 0x600, 0x100) 717EXC_VIRT(alignment, 0x4600, 0x100, 0x600) 718TRAMP_KVM(PACA_EXGEN, 0x600) 719EXC_COMMON_BEGIN(alignment_common) 720 mfspr r10,SPRN_DAR 721 std r10,PACA_EXGEN+EX_DAR(r13) 722 mfspr r10,SPRN_DSISR 723 stw r10,PACA_EXGEN+EX_DSISR(r13) 724 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 725 ld r3,PACA_EXGEN+EX_DAR(r13) 726 lwz r4,PACA_EXGEN+EX_DSISR(r13) 727 std r3,_DAR(r1) 728 std r4,_DSISR(r1) 729 bl save_nvgprs 730 RECONCILE_IRQ_STATE(r10, r11) 731 addi r3,r1,STACK_FRAME_OVERHEAD 732 bl alignment_exception 733 b ret_from_except 734 735 736EXC_REAL(program_check, 0x700, 0x100) 737EXC_VIRT(program_check, 0x4700, 0x100, 0x700) 738TRAMP_KVM(PACA_EXGEN, 0x700) 739EXC_COMMON_BEGIN(program_check_common) 740 /* 741 * It's possible to receive a TM Bad Thing type program check with 742 * userspace register values (in particular r1), but with SRR1 reporting 743 * that we came from the kernel. Normally that would confuse the bad 744 * stack logic, and we would report a bad kernel stack pointer. Instead 745 * we switch to the emergency stack if we're taking a TM Bad Thing from 746 * the kernel. 747 */ 748 li r10,MSR_PR /* Build a mask of MSR_PR .. */ 749 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ 750 and r10,r10,r12 /* Mask SRR1 with that. */ 751 srdi r10,r10,8 /* Shift it so we can compare */ 752 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ 753 bne 1f /* If != go to normal path. */ 754 755 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ 756 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ 757 /* 3 in EXCEPTION_PROLOG_COMMON */ 758 mr r10,r1 /* Save r1 */ 759 ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 760 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 761 b 3f /* Jump into the macro !! */ 7621: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 763 bl save_nvgprs 764 RECONCILE_IRQ_STATE(r10, r11) 765 addi r3,r1,STACK_FRAME_OVERHEAD 766 bl program_check_exception 767 b ret_from_except 768 769 770EXC_REAL(fp_unavailable, 0x800, 0x100) 771EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 772TRAMP_KVM(PACA_EXGEN, 0x800) 773EXC_COMMON_BEGIN(fp_unavailable_common) 774 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 775 bne 1f /* if from user, just load it up */ 776 bl save_nvgprs 777 RECONCILE_IRQ_STATE(r10, r11) 778 addi r3,r1,STACK_FRAME_OVERHEAD 779 bl kernel_fp_unavailable_exception 780 BUG_OPCODE 7811: 782#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 783BEGIN_FTR_SECTION 784 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 785 * transaction), go do TM stuff 786 */ 787 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 788 bne- 2f 789END_FTR_SECTION_IFSET(CPU_FTR_TM) 790#endif 791 bl load_up_fpu 792 b fast_exception_return 793#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 7942: /* User process was in a transaction */ 795 bl save_nvgprs 796 RECONCILE_IRQ_STATE(r10, r11) 797 addi r3,r1,STACK_FRAME_OVERHEAD 798 bl fp_unavailable_tm 799 b ret_from_except 800#endif 801 802 803EXC_REAL_MASKABLE(decrementer, 0x900, 0x80) 804EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900) 805TRAMP_KVM(PACA_EXGEN, 0x900) 806EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 807 808 809EXC_REAL_HV(hdecrementer, 0x980, 0x80) 810EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 811TRAMP_KVM_HV(PACA_EXGEN, 0x980) 812EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 813 814 815EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100) 816EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00) 817TRAMP_KVM(PACA_EXGEN, 0xa00) 818#ifdef CONFIG_PPC_DOORBELL 819EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 820#else 821EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 822#endif 823 824 825EXC_REAL(trap_0b, 0xb00, 0x100) 826EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 827TRAMP_KVM(PACA_EXGEN, 0xb00) 828EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 829 830/* 831 * system call / hypercall (0xc00, 0x4c00) 832 * 833 * The system call exception is invoked with "sc 0" and does not alter HV bit. 834 * There is support for kernel code to invoke system calls but there are no 835 * in-tree users. 836 * 837 * The hypercall is invoked with "sc 1" and sets HV=1. 838 * 839 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 840 * 0x4c00 virtual mode. 841 * 842 * Call convention: 843 * 844 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt 845 * 846 * For hypercalls, the register convention is as follows: 847 * r0 volatile 848 * r1-2 nonvolatile 849 * r3 volatile parameter and return value for status 850 * r4-r10 volatile input and output value 851 * r11 volatile hypercall number and output value 852 * r12 volatile input and output value 853 * r13-r31 nonvolatile 854 * LR nonvolatile 855 * CTR volatile 856 * XER volatile 857 * CR0-1 CR5-7 volatile 858 * CR2-4 nonvolatile 859 * Other registers nonvolatile 860 * 861 * The intersection of volatile registers that don't contain possible 862 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 863 * without saving, though xer is not a good idea to use, as hardware may 864 * interpret some bits so it may be costly to change them. 865 */ 866#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 867 /* 868 * There is a little bit of juggling to get syscall and hcall 869 * working well. Save r13 in ctr to avoid using SPRG scratch 870 * register. 871 * 872 * Userspace syscalls have already saved the PPR, hcalls must save 873 * it before setting HMT_MEDIUM. 874 */ 875#define SYSCALL_KVMTEST \ 876 mtctr r13; \ 877 GET_PACA(r13); \ 878 std r10,PACA_EXGEN+EX_R10(r13); \ 879 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \ 880 HMT_MEDIUM; \ 881 mfctr r9; 882 883#else 884#define SYSCALL_KVMTEST \ 885 HMT_MEDIUM; \ 886 mr r9,r13; \ 887 GET_PACA(r13); 888#endif 889 890#define LOAD_SYSCALL_HANDLER(reg) \ 891 __LOAD_HANDLER(reg, system_call_common) 892 893/* 894 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, 895 * and HMT_MEDIUM. 896 */ 897#define SYSCALL_REAL \ 898 mfspr r11,SPRN_SRR0 ; \ 899 mfspr r12,SPRN_SRR1 ; \ 900 LOAD_SYSCALL_HANDLER(r10) ; \ 901 mtspr SPRN_SRR0,r10 ; \ 902 ld r10,PACAKMSR(r13) ; \ 903 mtspr SPRN_SRR1,r10 ; \ 904 rfid ; \ 905 b . ; /* prevent speculative execution */ 906 907#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 908#define SYSCALL_FASTENDIAN_TEST \ 909BEGIN_FTR_SECTION \ 910 cmpdi r0,0x1ebe ; \ 911 beq- 1f ; \ 912END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 913 914#define SYSCALL_FASTENDIAN \ 915 /* Fast LE/BE switch system call */ \ 9161: mfspr r12,SPRN_SRR1 ; \ 917 xori r12,r12,MSR_LE ; \ 918 mtspr SPRN_SRR1,r12 ; \ 919 mr r13,r9 ; \ 920 rfid ; /* return to userspace */ \ 921 b . ; /* prevent speculative execution */ 922#else 923#define SYSCALL_FASTENDIAN_TEST 924#define SYSCALL_FASTENDIAN 925#endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */ 926 927#if defined(CONFIG_RELOCATABLE) 928 /* 929 * We can't branch directly so we do it via the CTR which 930 * is volatile across system calls. 931 */ 932#define SYSCALL_VIRT \ 933 LOAD_SYSCALL_HANDLER(r10) ; \ 934 mtctr r10 ; \ 935 mfspr r11,SPRN_SRR0 ; \ 936 mfspr r12,SPRN_SRR1 ; \ 937 li r10,MSR_RI ; \ 938 mtmsrd r10,1 ; \ 939 bctr ; 940#else 941 /* We can branch directly */ 942#define SYSCALL_VIRT \ 943 mfspr r11,SPRN_SRR0 ; \ 944 mfspr r12,SPRN_SRR1 ; \ 945 li r10,MSR_RI ; \ 946 mtmsrd r10,1 ; /* Set RI (EE=0) */ \ 947 b system_call_common ; 948#endif 949 950EXC_REAL_BEGIN(system_call, 0xc00, 0x100) 951 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 952 SYSCALL_FASTENDIAN_TEST 953 SYSCALL_REAL 954 SYSCALL_FASTENDIAN 955EXC_REAL_END(system_call, 0xc00, 0x100) 956 957EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 958 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 959 SYSCALL_FASTENDIAN_TEST 960 SYSCALL_VIRT 961 SYSCALL_FASTENDIAN 962EXC_VIRT_END(system_call, 0x4c00, 0x100) 963 964#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 965 /* 966 * This is a hcall, so register convention is as above, with these 967 * differences: 968 * r13 = PACA 969 * ctr = orig r13 970 * orig r10 saved in PACA 971 */ 972TRAMP_KVM_BEGIN(do_kvm_0xc00) 973 /* 974 * Save the PPR (on systems that support it) before changing to 975 * HMT_MEDIUM. That allows the KVM code to save that value into the 976 * guest state (it is the guest's PPR value). 977 */ 978 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) 979 HMT_MEDIUM 980 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) 981 mfctr r10 982 SET_SCRATCH0(r10) 983 std r9,PACA_EXGEN+EX_R9(r13) 984 mfcr r9 985 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) 986#endif 987 988 989EXC_REAL(single_step, 0xd00, 0x100) 990EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 991TRAMP_KVM(PACA_EXGEN, 0xd00) 992EXC_COMMON(single_step_common, 0xd00, single_step_exception) 993 994EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 995EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 996TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 997EXC_COMMON_BEGIN(h_data_storage_common) 998 mfspr r10,SPRN_HDAR 999 std r10,PACA_EXGEN+EX_DAR(r13) 1000 mfspr r10,SPRN_HDSISR 1001 stw r10,PACA_EXGEN+EX_DSISR(r13) 1002 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) 1003 bl save_nvgprs 1004 RECONCILE_IRQ_STATE(r10, r11) 1005 addi r3,r1,STACK_FRAME_OVERHEAD 1006 bl unknown_exception 1007 b ret_from_except 1008 1009 1010EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 1011EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 1012TRAMP_KVM_HV(PACA_EXGEN, 0xe20) 1013EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 1014 1015 1016EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 1017EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 1018TRAMP_KVM_HV(PACA_EXGEN, 0xe40) 1019EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 1020 1021 1022/* 1023 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 1024 * first, and then eventaully from there to the trampoline to get into virtual 1025 * mode. 1026 */ 1027__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) 1028__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) 1029EXC_VIRT_NONE(0x4e60, 0x20) 1030TRAMP_KVM_HV(PACA_EXGEN, 0xe60) 1031TRAMP_REAL_BEGIN(hmi_exception_early) 1032 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) 1033 mr r10,r1 /* Save r1 */ 1034 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 1035 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1036 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 1037 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ 1038 EXCEPTION_PROLOG_COMMON_1() 1039 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 1040 EXCEPTION_PROLOG_COMMON_3(0xe60) 1041 addi r3,r1,STACK_FRAME_OVERHEAD 1042 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */ 1043 cmpdi cr0,r3,0 1044 1045 /* Windup the stack. */ 1046 /* Move original HSRR0 and HSRR1 into the respective regs */ 1047 ld r9,_MSR(r1) 1048 mtspr SPRN_HSRR1,r9 1049 ld r3,_NIP(r1) 1050 mtspr SPRN_HSRR0,r3 1051 ld r9,_CTR(r1) 1052 mtctr r9 1053 ld r9,_XER(r1) 1054 mtxer r9 1055 ld r9,_LINK(r1) 1056 mtlr r9 1057 REST_GPR(0, r1) 1058 REST_8GPRS(2, r1) 1059 REST_GPR(10, r1) 1060 ld r11,_CCR(r1) 1061 REST_2GPRS(12, r1) 1062 bne 1f 1063 mtcr r11 1064 REST_GPR(11, r1) 1065 ld r1,GPR1(r1) 1066 hrfid 1067 10681: mtcr r11 1069 REST_GPR(11, r1) 1070 ld r1,GPR1(r1) 1071 1072 /* 1073 * Go to virtual mode and pull the HMI event information from 1074 * firmware. 1075 */ 1076 .globl hmi_exception_after_realmode 1077hmi_exception_after_realmode: 1078 SET_SCRATCH0(r13) 1079 EXCEPTION_PROLOG_0(PACA_EXGEN) 1080 b tramp_real_hmi_exception 1081 1082EXC_COMMON_BEGIN(hmi_exception_common) 1083EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception, 1084 ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON) 1085 1086EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20) 1087EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80) 1088TRAMP_KVM_HV(PACA_EXGEN, 0xe80) 1089#ifdef CONFIG_PPC_DOORBELL 1090EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 1091#else 1092EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 1093#endif 1094 1095 1096EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20) 1097EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0) 1098TRAMP_KVM_HV(PACA_EXGEN, 0xea0) 1099EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 1100 1101 1102EXC_REAL_NONE(0xec0, 0x20) 1103EXC_VIRT_NONE(0x4ec0, 0x20) 1104EXC_REAL_NONE(0xee0, 0x20) 1105EXC_VIRT_NONE(0x4ee0, 0x20) 1106 1107 1108EXC_REAL_OOL(performance_monitor, 0xf00, 0x20) 1109EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00) 1110TRAMP_KVM(PACA_EXGEN, 0xf00) 1111EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1112 1113 1114EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 1115EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1116TRAMP_KVM(PACA_EXGEN, 0xf20) 1117EXC_COMMON_BEGIN(altivec_unavailable_common) 1118 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1119#ifdef CONFIG_ALTIVEC 1120BEGIN_FTR_SECTION 1121 beq 1f 1122#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1123 BEGIN_FTR_SECTION_NESTED(69) 1124 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1125 * transaction), go do TM stuff 1126 */ 1127 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1128 bne- 2f 1129 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1130#endif 1131 bl load_up_altivec 1132 b fast_exception_return 1133#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 11342: /* User process was in a transaction */ 1135 bl save_nvgprs 1136 RECONCILE_IRQ_STATE(r10, r11) 1137 addi r3,r1,STACK_FRAME_OVERHEAD 1138 bl altivec_unavailable_tm 1139 b ret_from_except 1140#endif 11411: 1142END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1143#endif 1144 bl save_nvgprs 1145 RECONCILE_IRQ_STATE(r10, r11) 1146 addi r3,r1,STACK_FRAME_OVERHEAD 1147 bl altivec_unavailable_exception 1148 b ret_from_except 1149 1150 1151EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 1152EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1153TRAMP_KVM(PACA_EXGEN, 0xf40) 1154EXC_COMMON_BEGIN(vsx_unavailable_common) 1155 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 1156#ifdef CONFIG_VSX 1157BEGIN_FTR_SECTION 1158 beq 1f 1159#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1160 BEGIN_FTR_SECTION_NESTED(69) 1161 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1162 * transaction), go do TM stuff 1163 */ 1164 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1165 bne- 2f 1166 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1167#endif 1168 b load_up_vsx 1169#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 11702: /* User process was in a transaction */ 1171 bl save_nvgprs 1172 RECONCILE_IRQ_STATE(r10, r11) 1173 addi r3,r1,STACK_FRAME_OVERHEAD 1174 bl vsx_unavailable_tm 1175 b ret_from_except 1176#endif 11771: 1178END_FTR_SECTION_IFSET(CPU_FTR_VSX) 1179#endif 1180 bl save_nvgprs 1181 RECONCILE_IRQ_STATE(r10, r11) 1182 addi r3,r1,STACK_FRAME_OVERHEAD 1183 bl vsx_unavailable_exception 1184 b ret_from_except 1185 1186 1187EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 1188EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 1189TRAMP_KVM(PACA_EXGEN, 0xf60) 1190EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 1191 1192 1193EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 1194EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 1195TRAMP_KVM_HV(PACA_EXGEN, 0xf80) 1196EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 1197 1198 1199EXC_REAL_NONE(0xfa0, 0x20) 1200EXC_VIRT_NONE(0x4fa0, 0x20) 1201EXC_REAL_NONE(0xfc0, 0x20) 1202EXC_VIRT_NONE(0x4fc0, 0x20) 1203EXC_REAL_NONE(0xfe0, 0x20) 1204EXC_VIRT_NONE(0x4fe0, 0x20) 1205 1206EXC_REAL_NONE(0x1000, 0x100) 1207EXC_VIRT_NONE(0x5000, 0x100) 1208EXC_REAL_NONE(0x1100, 0x100) 1209EXC_VIRT_NONE(0x5100, 0x100) 1210 1211#ifdef CONFIG_CBE_RAS 1212EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 1213EXC_VIRT_NONE(0x5200, 0x100) 1214TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1215EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1216#else /* CONFIG_CBE_RAS */ 1217EXC_REAL_NONE(0x1200, 0x100) 1218EXC_VIRT_NONE(0x5200, 0x100) 1219#endif 1220 1221 1222EXC_REAL(instruction_breakpoint, 0x1300, 0x100) 1223EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1224TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 1225EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 1226 1227EXC_REAL_NONE(0x1400, 0x100) 1228EXC_VIRT_NONE(0x5400, 0x100) 1229 1230EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 1231 mtspr SPRN_SPRG_HSCRATCH0,r13 1232 EXCEPTION_PROLOG_0(PACA_EXGEN) 1233 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) 1234 1235#ifdef CONFIG_PPC_DENORMALISATION 1236 mfspr r10,SPRN_HSRR1 1237 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 1238 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1239 addi r11,r11,-4 /* HSRR0 is next instruction */ 1240 bne+ denorm_assist 1241#endif 1242 1243 KVMTEST_PR(0x1500) 1244 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) 1245EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1246 1247#ifdef CONFIG_PPC_DENORMALISATION 1248EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1249 b exc_real_0x1500_denorm_exception_hv 1250EXC_VIRT_END(denorm_exception, 0x5500, 0x100) 1251#else 1252EXC_VIRT_NONE(0x5500, 0x100) 1253#endif 1254 1255TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) 1256 1257#ifdef CONFIG_PPC_DENORMALISATION 1258TRAMP_REAL_BEGIN(denorm_assist) 1259BEGIN_FTR_SECTION 1260/* 1261 * To denormalise we need to move a copy of the register to itself. 1262 * For POWER6 do that here for all FP regs. 1263 */ 1264 mfmsr r10 1265 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1266 xori r10,r10,(MSR_FE0|MSR_FE1) 1267 mtmsrd r10 1268 sync 1269 1270#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 1271#define FMR4(n) FMR2(n) ; FMR2(n+2) 1272#define FMR8(n) FMR4(n) ; FMR4(n+4) 1273#define FMR16(n) FMR8(n) ; FMR8(n+8) 1274#define FMR32(n) FMR16(n) ; FMR16(n+16) 1275 FMR32(0) 1276 1277FTR_SECTION_ELSE 1278/* 1279 * To denormalise we need to move a copy of the register to itself. 1280 * For POWER7 do that here for the first 32 VSX registers only. 1281 */ 1282 mfmsr r10 1283 oris r10,r10,MSR_VSX@h 1284 mtmsrd r10 1285 sync 1286 1287#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) 1288#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) 1289#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) 1290#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) 1291#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) 1292 XVCPSGNDP32(0) 1293 1294ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1295 1296BEGIN_FTR_SECTION 1297 b denorm_done 1298END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1299/* 1300 * To denormalise we need to move a copy of the register to itself. 1301 * For POWER8 we need to do that for all 64 VSX registers 1302 */ 1303 XVCPSGNDP32(32) 1304denorm_done: 1305 mtspr SPRN_HSRR0,r11 1306 mtcrf 0x80,r9 1307 ld r9,PACA_EXGEN+EX_R9(r13) 1308 RESTORE_PPR_PACA(PACA_EXGEN, r10) 1309BEGIN_FTR_SECTION 1310 ld r10,PACA_EXGEN+EX_CFAR(r13) 1311 mtspr SPRN_CFAR,r10 1312END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1313 ld r10,PACA_EXGEN+EX_R10(r13) 1314 ld r11,PACA_EXGEN+EX_R11(r13) 1315 ld r12,PACA_EXGEN+EX_R12(r13) 1316 ld r13,PACA_EXGEN+EX_R13(r13) 1317 HRFID 1318 b . 1319#endif 1320 1321EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) 1322 1323 1324#ifdef CONFIG_CBE_RAS 1325EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 1326EXC_VIRT_NONE(0x5600, 0x100) 1327TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 1328EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1329#else /* CONFIG_CBE_RAS */ 1330EXC_REAL_NONE(0x1600, 0x100) 1331EXC_VIRT_NONE(0x5600, 0x100) 1332#endif 1333 1334 1335EXC_REAL(altivec_assist, 0x1700, 0x100) 1336EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 1337TRAMP_KVM(PACA_EXGEN, 0x1700) 1338#ifdef CONFIG_ALTIVEC 1339EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 1340#else 1341EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 1342#endif 1343 1344 1345#ifdef CONFIG_CBE_RAS 1346EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 1347EXC_VIRT_NONE(0x5800, 0x100) 1348TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 1349EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 1350#else /* CONFIG_CBE_RAS */ 1351EXC_REAL_NONE(0x1800, 0x100) 1352EXC_VIRT_NONE(0x5800, 0x100) 1353#endif 1354 1355#ifdef CONFIG_PPC_WATCHDOG 1356 1357#define MASKED_DEC_HANDLER_LABEL 3f 1358 1359#define MASKED_DEC_HANDLER(_H) \ 13603: /* soft-nmi */ \ 1361 std r12,PACA_EXGEN+EX_R12(r13); \ 1362 GET_SCRATCH0(r10); \ 1363 std r10,PACA_EXGEN+EX_R13(r13); \ 1364 EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H) 1365 1366/* 1367 * Branch to soft_nmi_interrupt using the emergency stack. The emergency 1368 * stack is one that is usable by maskable interrupts so long as MSR_EE 1369 * remains off. It is used for recovery when something has corrupted the 1370 * normal kernel stack, for example. The "soft NMI" must not use the process 1371 * stack because we want irq disabled sections to avoid touching the stack 1372 * at all (other than PMU interrupts), so use the emergency stack for this, 1373 * and run it entirely with interrupts hard disabled. 1374 */ 1375EXC_COMMON_BEGIN(soft_nmi_common) 1376 mr r10,r1 1377 ld r1,PACAEMERGSP(r13) 1378 subi r1,r1,INT_FRAME_SIZE 1379 EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, 1380 system_reset, soft_nmi_interrupt, 1381 ADD_NVGPRS;ADD_RECONCILE) 1382 b ret_from_except 1383 1384#else /* CONFIG_PPC_WATCHDOG */ 1385#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ 1386#define MASKED_DEC_HANDLER(_H) 1387#endif /* CONFIG_PPC_WATCHDOG */ 1388 1389/* 1390 * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 1391 * - If it was a decrementer interrupt, we bump the dec to max and and return. 1392 * - If it was a doorbell we return immediately since doorbells are edge 1393 * triggered and won't automatically refire. 1394 * - If it was a HMI we return immediately since we handled it in realmode 1395 * and it won't refire. 1396 * - else we hard disable and return. 1397 * This is called with r10 containing the value to OR to the paca field. 1398 */ 1399#define MASKED_INTERRUPT(_H) \ 1400masked_##_H##interrupt: \ 1401 std r11,PACA_EXGEN+EX_R11(r13); \ 1402 lbz r11,PACAIRQHAPPENED(r13); \ 1403 or r11,r11,r10; \ 1404 stb r11,PACAIRQHAPPENED(r13); \ 1405 cmpwi r10,PACA_IRQ_DEC; \ 1406 bne 1f; \ 1407 lis r10,0x7fff; \ 1408 ori r10,r10,0xffff; \ 1409 mtspr SPRN_DEC,r10; \ 1410 b MASKED_DEC_HANDLER_LABEL; \ 14111: andi. r10,r10,(PACA_IRQ_DBELL|PACA_IRQ_HMI); \ 1412 bne 2f; \ 1413 mfspr r10,SPRN_##_H##SRR1; \ 1414 xori r10,r10,MSR_EE; /* clear MSR_EE */ \ 1415 mtspr SPRN_##_H##SRR1,r10; \ 14162: mtcrf 0x80,r9; \ 1417 ld r9,PACA_EXGEN+EX_R9(r13); \ 1418 ld r10,PACA_EXGEN+EX_R10(r13); \ 1419 ld r11,PACA_EXGEN+EX_R11(r13); \ 1420 /* returns to kernel where r13 must be set up, so don't restore it */ \ 1421 ##_H##rfid; \ 1422 b .; \ 1423 MASKED_DEC_HANDLER(_H) 1424 1425/* 1426 * Real mode exceptions actually use this too, but alternate 1427 * instruction code patches (which end up in the common .text area) 1428 * cannot reach these if they are put there. 1429 */ 1430USE_FIXED_SECTION(virt_trampolines) 1431 MASKED_INTERRUPT() 1432 MASKED_INTERRUPT(H) 1433 1434#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1435TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 1436 /* 1437 * Here all GPRs are unchanged from when the interrupt happened 1438 * except for r13, which is saved in SPRG_SCRATCH0. 1439 */ 1440 mfspr r13, SPRN_SRR0 1441 addi r13, r13, 4 1442 mtspr SPRN_SRR0, r13 1443 GET_SCRATCH0(r13) 1444 rfid 1445 b . 1446 1447TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 1448 /* 1449 * Here all GPRs are unchanged from when the interrupt happened 1450 * except for r13, which is saved in SPRG_SCRATCH0. 1451 */ 1452 mfspr r13, SPRN_HSRR0 1453 addi r13, r13, 4 1454 mtspr SPRN_HSRR0, r13 1455 GET_SCRATCH0(r13) 1456 hrfid 1457 b . 1458#endif 1459 1460/* 1461 * Ensure that any handlers that get invoked from the exception prologs 1462 * above are below the first 64KB (0x10000) of the kernel image because 1463 * the prologs assemble the addresses of these handlers using the 1464 * LOAD_HANDLER macro, which uses an ori instruction. 1465 */ 1466 1467/*** Common interrupt handlers ***/ 1468 1469 1470 /* 1471 * Relocation-on interrupts: A subset of the interrupts can be delivered 1472 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 1473 * it. Addresses are the same as the original interrupt addresses, but 1474 * offset by 0xc000000000004000. 1475 * It's impossible to receive interrupts below 0x300 via this mechanism. 1476 * KVM: None of these traps are from the guest ; anything that escalated 1477 * to HV=1 from HV=0 is delivered via real mode handlers. 1478 */ 1479 1480 /* 1481 * This uses the standard macro, since the original 0x300 vector 1482 * only has extra guff for STAB-based processors -- which never 1483 * come here. 1484 */ 1485 1486EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 1487 b __ppc64_runlatch_on 1488 1489USE_FIXED_SECTION(virt_trampolines) 1490 /* 1491 * The __end_interrupts marker must be past the out-of-line (OOL) 1492 * handlers, so that they are copied to real address 0x100 when running 1493 * a relocatable kernel. This ensures they can be reached from the short 1494 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 1495 * directly, without using LOAD_HANDLER(). 1496 */ 1497 .align 7 1498 .globl __end_interrupts 1499__end_interrupts: 1500DEFINE_FIXED_SYMBOL(__end_interrupts) 1501 1502#ifdef CONFIG_PPC_970_NAP 1503EXC_COMMON_BEGIN(power4_fixup_nap) 1504 andc r9,r9,r10 1505 std r9,TI_LOCAL_FLAGS(r11) 1506 ld r10,_LINK(r1) /* make idle task do the */ 1507 std r10,_NIP(r1) /* equivalent of a blr */ 1508 blr 1509#endif 1510 1511CLOSE_FIXED_SECTION(real_vectors); 1512CLOSE_FIXED_SECTION(real_trampolines); 1513CLOSE_FIXED_SECTION(virt_vectors); 1514CLOSE_FIXED_SECTION(virt_trampolines); 1515 1516USE_TEXT_SECTION() 1517 1518/* 1519 * Hash table stuff 1520 */ 1521 .balign IFETCH_ALIGN_BYTES 1522do_hash_page: 1523#ifdef CONFIG_PPC_BOOK3S_64 1524 lis r0,(DSISR_BAD_FAULT_64S|DSISR_DABRMATCH)@h 1525 ori r0,r0,DSISR_BAD_FAULT_64S@l 1526 and. r0,r4,r0 /* weird error? */ 1527 bne- handle_page_fault /* if not, try to insert a HPTE */ 1528 CURRENT_THREAD_INFO(r11, r1) 1529 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 1530 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 1531 bne 77f /* then don't call hash_page now */ 1532 1533 /* 1534 * r3 contains the faulting address 1535 * r4 msr 1536 * r5 contains the trap number 1537 * r6 contains dsisr 1538 * 1539 * at return r3 = 0 for success, 1 for page fault, negative for error 1540 */ 1541 mr r4,r12 1542 ld r6,_DSISR(r1) 1543 bl __hash_page /* build HPTE if possible */ 1544 cmpdi r3,0 /* see if __hash_page succeeded */ 1545 1546 /* Success */ 1547 beq fast_exc_return_irq /* Return from exception on success */ 1548 1549 /* Error */ 1550 blt- 13f 1551 1552 /* Reload DSISR into r4 for the DABR check below */ 1553 ld r4,_DSISR(r1) 1554#endif /* CONFIG_PPC_BOOK3S_64 */ 1555 1556/* Here we have a page fault that hash_page can't handle. */ 1557handle_page_fault: 155811: andis. r0,r4,DSISR_DABRMATCH@h 1559 bne- handle_dabr_fault 1560 ld r4,_DAR(r1) 1561 ld r5,_DSISR(r1) 1562 addi r3,r1,STACK_FRAME_OVERHEAD 1563 bl do_page_fault 1564 cmpdi r3,0 1565 beq+ 12f 1566 bl save_nvgprs 1567 mr r5,r3 1568 addi r3,r1,STACK_FRAME_OVERHEAD 1569 lwz r4,_DAR(r1) 1570 bl bad_page_fault 1571 b ret_from_except 1572 1573/* We have a data breakpoint exception - handle it */ 1574handle_dabr_fault: 1575 bl save_nvgprs 1576 ld r4,_DAR(r1) 1577 ld r5,_DSISR(r1) 1578 addi r3,r1,STACK_FRAME_OVERHEAD 1579 bl do_break 158012: b ret_from_except_lite 1581 1582 1583#ifdef CONFIG_PPC_BOOK3S_64 1584/* We have a page fault that hash_page could handle but HV refused 1585 * the PTE insertion 1586 */ 158713: bl save_nvgprs 1588 mr r5,r3 1589 addi r3,r1,STACK_FRAME_OVERHEAD 1590 ld r4,_DAR(r1) 1591 bl low_hash_fault 1592 b ret_from_except 1593#endif 1594 1595/* 1596 * We come here as a result of a DSI at a point where we don't want 1597 * to call hash_page, such as when we are accessing memory (possibly 1598 * user memory) inside a PMU interrupt that occurred while interrupts 1599 * were soft-disabled. We want to invoke the exception handler for 1600 * the access, or panic if there isn't a handler. 1601 */ 160277: bl save_nvgprs 1603 mr r4,r3 1604 addi r3,r1,STACK_FRAME_OVERHEAD 1605 li r5,SIGSEGV 1606 bl bad_page_fault 1607 b ret_from_except 1608 1609/* 1610 * Here we have detected that the kernel stack pointer is bad. 1611 * R9 contains the saved CR, r13 points to the paca, 1612 * r10 contains the (bad) kernel stack pointer, 1613 * r11 and r12 contain the saved SRR0 and SRR1. 1614 * We switch to using an emergency stack, save the registers there, 1615 * and call kernel_bad_stack(), which panics. 1616 */ 1617bad_stack: 1618 ld r1,PACAEMERGSP(r13) 1619 subi r1,r1,64+INT_FRAME_SIZE 1620 std r9,_CCR(r1) 1621 std r10,GPR1(r1) 1622 std r11,_NIP(r1) 1623 std r12,_MSR(r1) 1624 mfspr r11,SPRN_DAR 1625 mfspr r12,SPRN_DSISR 1626 std r11,_DAR(r1) 1627 std r12,_DSISR(r1) 1628 mflr r10 1629 mfctr r11 1630 mfxer r12 1631 std r10,_LINK(r1) 1632 std r11,_CTR(r1) 1633 std r12,_XER(r1) 1634 SAVE_GPR(0,r1) 1635 SAVE_GPR(2,r1) 1636 ld r10,EX_R3(r3) 1637 std r10,GPR3(r1) 1638 SAVE_GPR(4,r1) 1639 SAVE_4GPRS(5,r1) 1640 ld r9,EX_R9(r3) 1641 ld r10,EX_R10(r3) 1642 SAVE_2GPRS(9,r1) 1643 ld r9,EX_R11(r3) 1644 ld r10,EX_R12(r3) 1645 ld r11,EX_R13(r3) 1646 std r9,GPR11(r1) 1647 std r10,GPR12(r1) 1648 std r11,GPR13(r1) 1649BEGIN_FTR_SECTION 1650 ld r10,EX_CFAR(r3) 1651 std r10,ORIG_GPR3(r1) 1652END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1653 SAVE_8GPRS(14,r1) 1654 SAVE_10GPRS(22,r1) 1655 lhz r12,PACA_TRAP_SAVE(r13) 1656 std r12,_TRAP(r1) 1657 addi r11,r1,INT_FRAME_SIZE 1658 std r11,0(r1) 1659 li r12,0 1660 std r12,0(r11) 1661 ld r2,PACATOC(r13) 1662 ld r11,exception_marker@toc(r2) 1663 std r12,RESULT(r1) 1664 std r11,STACK_FRAME_OVERHEAD-16(r1) 16651: addi r3,r1,STACK_FRAME_OVERHEAD 1666 bl kernel_bad_stack 1667 b 1b 1668_ASM_NOKPROBE_SYMBOL(bad_stack); 1669 1670/* 1671 * When doorbell is triggered from system reset wakeup, the message is 1672 * not cleared, so it would fire again when EE is enabled. 1673 * 1674 * When coming from local_irq_enable, there may be the same problem if 1675 * we were hard disabled. 1676 * 1677 * Execute msgclr to clear pending exceptions before handling it. 1678 */ 1679h_doorbell_common_msgclr: 1680 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1681 PPC_MSGCLR(3) 1682 b h_doorbell_common 1683 1684doorbell_super_common_msgclr: 1685 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1686 PPC_MSGCLRP(3) 1687 b doorbell_super_common 1688 1689/* 1690 * Called from arch_local_irq_enable when an interrupt needs 1691 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 1692 * which kind of interrupt. MSR:EE is already off. We generate a 1693 * stackframe like if a real interrupt had happened. 1694 * 1695 * Note: While MSR:EE is off, we need to make sure that _MSR 1696 * in the generated frame has EE set to 1 or the exception 1697 * handler will not properly re-enable them. 1698 * 1699 * Note that we don't specify LR as the NIP (return address) for 1700 * the interrupt because that would unbalance the return branch 1701 * predictor. 1702 */ 1703_GLOBAL(__replay_interrupt) 1704 /* We are going to jump to the exception common code which 1705 * will retrieve various register values from the PACA which 1706 * we don't give a damn about, so we don't bother storing them. 1707 */ 1708 mfmsr r12 1709 LOAD_REG_ADDR(r11, replay_interrupt_return) 1710 mfcr r9 1711 ori r12,r12,MSR_EE 1712 cmpwi r3,0x900 1713 beq decrementer_common 1714 cmpwi r3,0x500 1715BEGIN_FTR_SECTION 1716 beq h_virt_irq_common 1717FTR_SECTION_ELSE 1718 beq hardware_interrupt_common 1719ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) 1720BEGIN_FTR_SECTION 1721 cmpwi r3,0xa00 1722 beq h_doorbell_common_msgclr 1723 cmpwi r3,0xe60 1724 beq hmi_exception_common 1725FTR_SECTION_ELSE 1726 cmpwi r3,0xa00 1727 beq doorbell_super_common_msgclr 1728ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1729replay_interrupt_return: 1730 blr 1731 1732_ASM_NOKPROBE_SYMBOL(__replay_interrupt) 1733