1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
7 *
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
10 *
11 * Most of this originates from head_64.S and thus has the same
12 * copyright history.
13 *
14 */
15
16#include <asm/hw_irq.h>
17#include <asm/exception-64s.h>
18#include <asm/ptrace.h>
19#include <asm/cpuidle.h>
20#include <asm/head-64.h>
21#include <asm/feature-fixups.h>
22#include <asm/kup.h>
23
24/* PACA save area offsets (exgen, exmc, etc) */
25#define EX_R9		0
26#define EX_R10		8
27#define EX_R11		16
28#define EX_R12		24
29#define EX_R13		32
30#define EX_DAR		40
31#define EX_DSISR	48
32#define EX_CCR		52
33#define EX_CFAR		56
34#define EX_PPR		64
35#if defined(CONFIG_RELOCATABLE)
36#define EX_CTR		72
37.if EX_SIZE != 10
38	.error "EX_SIZE is wrong"
39.endif
40#else
41.if EX_SIZE != 9
42	.error "EX_SIZE is wrong"
43.endif
44#endif
45
46/*
47 * Following are fixed section helper macros.
48 *
49 * EXC_REAL_BEGIN/END  - real, unrelocated exception vectors
50 * EXC_VIRT_BEGIN/END  - virt (AIL), unrelocated exception vectors
51 * TRAMP_REAL_BEGIN    - real, unrelocated helpers (virt may call these)
52 * TRAMP_VIRT_BEGIN    - virt, unreloc helpers (in practice, real can use)
53 * TRAMP_KVM_BEGIN     - KVM handlers, these are put into real, unrelocated
54 * EXC_COMMON          - After switching to virtual, relocated mode.
55 */
56
57#define EXC_REAL_BEGIN(name, start, size)			\
58	FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
59
60#define EXC_REAL_END(name, start, size)				\
61	FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
62
63#define EXC_VIRT_BEGIN(name, start, size)			\
64	FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
65
66#define EXC_VIRT_END(name, start, size)				\
67	FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
68
69#define EXC_COMMON_BEGIN(name)					\
70	USE_TEXT_SECTION();					\
71	.balign IFETCH_ALIGN_BYTES;				\
72	.global name;						\
73	_ASM_NOKPROBE_SYMBOL(name);				\
74	DEFINE_FIXED_SYMBOL(name);				\
75name:
76
77#define TRAMP_REAL_BEGIN(name)					\
78	FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name)
79
80#define TRAMP_VIRT_BEGIN(name)					\
81	FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name)
82
83#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
84#define TRAMP_KVM_BEGIN(name)					\
85	TRAMP_VIRT_BEGIN(name)
86#else
87#define TRAMP_KVM_BEGIN(name)
88#endif
89
90#define EXC_REAL_NONE(start, size)				\
91	FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \
92	FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size)
93
94#define EXC_VIRT_NONE(start, size)				\
95	FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \
96	FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size)
97
98/*
99 * We're short on space and time in the exception prolog, so we can't
100 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
101 * Instead we get the base of the kernel from paca->kernelbase and or in the low
102 * part of label. This requires that the label be within 64KB of kernelbase, and
103 * that kernelbase be 64K aligned.
104 */
105#define LOAD_HANDLER(reg, label)					\
106	ld	reg,PACAKBASE(r13);	/* get high part of &label */	\
107	ori	reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
108
109#define __LOAD_HANDLER(reg, label)					\
110	ld	reg,PACAKBASE(r13);					\
111	ori	reg,reg,(ABS_ADDR(label))@l
112
113/*
114 * Branches from unrelocated code (e.g., interrupts) to labels outside
115 * head-y require >64K offsets.
116 */
117#define __LOAD_FAR_HANDLER(reg, label)					\
118	ld	reg,PACAKBASE(r13);					\
119	ori	reg,reg,(ABS_ADDR(label))@l;				\
120	addis	reg,reg,(ABS_ADDR(label))@h
121
122/* Exception register prefixes */
123#define EXC_HV_OR_STD	2 /* depends on HVMODE */
124#define EXC_HV		1
125#define EXC_STD		0
126
127#if defined(CONFIG_RELOCATABLE)
128/*
129 * If we support interrupts with relocation on AND we're a relocatable kernel,
130 * we need to use CTR to get to the 2nd level handler.  So, save/restore it
131 * when required.
132 */
133#define SAVE_CTR(reg, area)	mfctr	reg ; 	std	reg,area+EX_CTR(r13)
134#define GET_CTR(reg, area) 			ld	reg,area+EX_CTR(r13)
135#define RESTORE_CTR(reg, area)	ld	reg,area+EX_CTR(r13) ; mtctr reg
136#else
137/* ...else CTR is unused and in register. */
138#define SAVE_CTR(reg, area)
139#define GET_CTR(reg, area) 	mfctr	reg
140#define RESTORE_CTR(reg, area)
141#endif
142
143/*
144 * PPR save/restore macros used in exceptions-64s.S
145 * Used for P7 or later processors
146 */
147#define SAVE_PPR(area, ra)						\
148BEGIN_FTR_SECTION_NESTED(940)						\
149	ld	ra,area+EX_PPR(r13);	/* Read PPR from paca */	\
150	std	ra,_PPR(r1);						\
151END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
152
153#define RESTORE_PPR_PACA(area, ra)					\
154BEGIN_FTR_SECTION_NESTED(941)						\
155	ld	ra,area+EX_PPR(r13);					\
156	mtspr	SPRN_PPR,ra;						\
157END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
158
159/*
160 * Get an SPR into a register if the CPU has the given feature
161 */
162#define OPT_GET_SPR(ra, spr, ftr)					\
163BEGIN_FTR_SECTION_NESTED(943)						\
164	mfspr	ra,spr;							\
165END_FTR_SECTION_NESTED(ftr,ftr,943)
166
167/*
168 * Set an SPR from a register if the CPU has the given feature
169 */
170#define OPT_SET_SPR(ra, spr, ftr)					\
171BEGIN_FTR_SECTION_NESTED(943)						\
172	mtspr	spr,ra;							\
173END_FTR_SECTION_NESTED(ftr,ftr,943)
174
175/*
176 * Save a register to the PACA if the CPU has the given feature
177 */
178#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr)				\
179BEGIN_FTR_SECTION_NESTED(943)						\
180	std	ra,offset(r13);						\
181END_FTR_SECTION_NESTED(ftr,ftr,943)
182
183/*
184 * Branch to label using its 0xC000 address. This results in instruction
185 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
186 * on using mtmsr rather than rfid.
187 *
188 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
189 * load KBASE for a slight optimisation.
190 */
191#define BRANCH_TO_C000(reg, label)					\
192	__LOAD_FAR_HANDLER(reg, label);					\
193	mtctr	reg;							\
194	bctr
195
196.macro INT_KVM_HANDLER name, vec, hsrr, area, skip
197	TRAMP_KVM_BEGIN(\name\()_kvm)
198	KVM_HANDLER \vec, \hsrr, \area, \skip
199.endm
200
201#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
202#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
203/*
204 * If hv is possible, interrupts come into to the hv version
205 * of the kvmppc_interrupt code, which then jumps to the PR handler,
206 * kvmppc_interrupt_pr, if the guest is a PR guest.
207 */
208#define kvmppc_interrupt kvmppc_interrupt_hv
209#else
210#define kvmppc_interrupt kvmppc_interrupt_pr
211#endif
212
213.macro KVMTEST name, hsrr, n
214	lbz	r10,HSTATE_IN_GUEST(r13)
215	cmpwi	r10,0
216	bne	\name\()_kvm
217.endm
218
219.macro KVM_HANDLER vec, hsrr, area, skip
220	.if \skip
221	cmpwi	r10,KVM_GUEST_MODE_SKIP
222	beq	89f
223	.else
224BEGIN_FTR_SECTION_NESTED(947)
225	ld	r10,\area+EX_CFAR(r13)
226	std	r10,HSTATE_CFAR(r13)
227END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947)
228	.endif
229
230BEGIN_FTR_SECTION_NESTED(948)
231	ld	r10,\area+EX_PPR(r13)
232	std	r10,HSTATE_PPR(r13)
233END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
234	ld	r10,\area+EX_R10(r13)
235	std	r12,HSTATE_SCRATCH0(r13)
236	sldi	r12,r9,32
237	/* HSRR variants have the 0x2 bit added to their trap number */
238	.if \hsrr == EXC_HV_OR_STD
239	BEGIN_FTR_SECTION
240	ori	r12,r12,(\vec + 0x2)
241	FTR_SECTION_ELSE
242	ori	r12,r12,(\vec)
243	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
244	.elseif \hsrr
245	ori	r12,r12,(\vec + 0x2)
246	.else
247	ori	r12,r12,(\vec)
248	.endif
249
250#ifdef CONFIG_RELOCATABLE
251	/*
252	 * KVM requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives
253	 * outside the head section. CONFIG_RELOCATABLE KVM expects CTR
254	 * to be saved in HSTATE_SCRATCH1.
255	 */
256	mfctr	r9
257	std	r9,HSTATE_SCRATCH1(r13)
258	__LOAD_FAR_HANDLER(r9, kvmppc_interrupt)
259	mtctr	r9
260	ld	r9,\area+EX_R9(r13)
261	bctr
262#else
263	ld	r9,\area+EX_R9(r13)
264	b	kvmppc_interrupt
265#endif
266
267
268	.if \skip
26989:	mtocrf	0x80,r9
270	ld	r9,\area+EX_R9(r13)
271	ld	r10,\area+EX_R10(r13)
272	.if \hsrr == EXC_HV_OR_STD
273	BEGIN_FTR_SECTION
274	b	kvmppc_skip_Hinterrupt
275	FTR_SECTION_ELSE
276	b	kvmppc_skip_interrupt
277	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
278	.elseif \hsrr
279	b	kvmppc_skip_Hinterrupt
280	.else
281	b	kvmppc_skip_interrupt
282	.endif
283	.endif
284.endm
285
286#else
287.macro KVMTEST name, hsrr, n
288.endm
289.macro KVM_HANDLER name, vec, hsrr, area, skip
290.endm
291#endif
292
293.macro INT_SAVE_SRR_AND_JUMP label, hsrr, set_ri
294	ld	r10,PACAKMSR(r13)	/* get MSR value for kernel */
295	.if ! \set_ri
296	xori	r10,r10,MSR_RI		/* Clear MSR_RI */
297	.endif
298	.if \hsrr == EXC_HV_OR_STD
299	BEGIN_FTR_SECTION
300	mfspr	r11,SPRN_HSRR0		/* save HSRR0 */
301	mfspr	r12,SPRN_HSRR1		/* and HSRR1 */
302	mtspr	SPRN_HSRR1,r10
303	FTR_SECTION_ELSE
304	mfspr	r11,SPRN_SRR0		/* save SRR0 */
305	mfspr	r12,SPRN_SRR1		/* and SRR1 */
306	mtspr	SPRN_SRR1,r10
307	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
308	.elseif \hsrr
309	mfspr	r11,SPRN_HSRR0		/* save HSRR0 */
310	mfspr	r12,SPRN_HSRR1		/* and HSRR1 */
311	mtspr	SPRN_HSRR1,r10
312	.else
313	mfspr	r11,SPRN_SRR0		/* save SRR0 */
314	mfspr	r12,SPRN_SRR1		/* and SRR1 */
315	mtspr	SPRN_SRR1,r10
316	.endif
317	LOAD_HANDLER(r10, \label\())
318	.if \hsrr == EXC_HV_OR_STD
319	BEGIN_FTR_SECTION
320	mtspr	SPRN_HSRR0,r10
321	HRFI_TO_KERNEL
322	FTR_SECTION_ELSE
323	mtspr	SPRN_SRR0,r10
324	RFI_TO_KERNEL
325	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
326	.elseif \hsrr
327	mtspr	SPRN_HSRR0,r10
328	HRFI_TO_KERNEL
329	.else
330	mtspr	SPRN_SRR0,r10
331	RFI_TO_KERNEL
332	.endif
333	b	.	/* prevent speculative execution */
334.endm
335
336/* INT_SAVE_SRR_AND_JUMP works for real or virt, this is faster but virt only */
337.macro INT_VIRT_SAVE_SRR_AND_JUMP label, hsrr
338#ifdef CONFIG_RELOCATABLE
339	.if \hsrr == EXC_HV_OR_STD
340	BEGIN_FTR_SECTION
341	mfspr	r11,SPRN_HSRR0	/* save HSRR0 */
342	FTR_SECTION_ELSE
343	mfspr	r11,SPRN_SRR0	/* save SRR0 */
344	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
345	.elseif \hsrr
346	mfspr	r11,SPRN_HSRR0	/* save HSRR0 */
347	.else
348	mfspr	r11,SPRN_SRR0	/* save SRR0 */
349	.endif
350	LOAD_HANDLER(r12, \label\())
351	mtctr	r12
352	.if \hsrr == EXC_HV_OR_STD
353	BEGIN_FTR_SECTION
354	mfspr	r12,SPRN_HSRR1	/* and HSRR1 */
355	FTR_SECTION_ELSE
356	mfspr	r12,SPRN_SRR1	/* and HSRR1 */
357	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
358	.elseif \hsrr
359	mfspr	r12,SPRN_HSRR1	/* and HSRR1 */
360	.else
361	mfspr	r12,SPRN_SRR1	/* and HSRR1 */
362	.endif
363	li	r10,MSR_RI
364	mtmsrd 	r10,1		/* Set RI (EE=0) */
365	bctr
366#else
367	.if \hsrr == EXC_HV_OR_STD
368	BEGIN_FTR_SECTION
369	mfspr	r11,SPRN_HSRR0		/* save HSRR0 */
370	mfspr	r12,SPRN_HSRR1		/* and HSRR1 */
371	FTR_SECTION_ELSE
372	mfspr	r11,SPRN_SRR0		/* save SRR0 */
373	mfspr	r12,SPRN_SRR1		/* and SRR1 */
374	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
375	.elseif \hsrr
376	mfspr	r11,SPRN_HSRR0		/* save HSRR0 */
377	mfspr	r12,SPRN_HSRR1		/* and HSRR1 */
378	.else
379	mfspr	r11,SPRN_SRR0		/* save SRR0 */
380	mfspr	r12,SPRN_SRR1		/* and SRR1 */
381	.endif
382	li	r10,MSR_RI
383	mtmsrd 	r10,1			/* Set RI (EE=0) */
384	b	\label
385#endif
386.endm
387
388/*
389 * This is the BOOK3S interrupt entry code macro.
390 *
391 * This can result in one of several things happening:
392 * - Branch to the _common handler, relocated, in virtual mode.
393 *   These are normal interrupts (synchronous and asynchronous) handled by
394 *   the kernel.
395 * - Branch to KVM, relocated but real mode interrupts remain in real mode.
396 *   These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
397 *   / intended for host or guest kernel, but KVM must always be involved
398 *   because the machine state is set for guest execution.
399 * - Branch to the masked handler, unrelocated.
400 *   These occur when maskable asynchronous interrupts are taken with the
401 *   irq_soft_mask set.
402 * - Branch to an "early" handler in real mode but relocated.
403 *   This is done if early=1. MCE and HMI use these to handle errors in real
404 *   mode.
405 * - Fall through and continue executing in real, unrelocated mode.
406 *   This is done if early=2.
407 */
408.macro INT_HANDLER name, vec, ool=0, early=0, virt=0, hsrr=0, area=PACA_EXGEN, ri=1, dar=0, dsisr=0, bitmask=0, kvm=0
409	SET_SCRATCH0(r13)			/* save r13 */
410	GET_PACA(r13)
411	std	r9,\area\()+EX_R9(r13)		/* save r9 */
412	OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
413	HMT_MEDIUM
414	std	r10,\area\()+EX_R10(r13)	/* save r10 - r12 */
415	OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
416	.if \ool
417	.if !\virt
418	b	tramp_real_\name
419	.pushsection .text
420	TRAMP_REAL_BEGIN(tramp_real_\name)
421	.else
422	b	tramp_virt_\name
423	.pushsection .text
424	TRAMP_VIRT_BEGIN(tramp_virt_\name)
425	.endif
426	.endif
427
428	OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
429	OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
430	INTERRUPT_TO_KERNEL
431	SAVE_CTR(r10, \area\())
432	mfcr	r9
433	.if \kvm
434		KVMTEST \name \hsrr \vec
435	.endif
436	.if \bitmask
437		lbz	r10,PACAIRQSOFTMASK(r13)
438		andi.	r10,r10,\bitmask
439		/* Associate vector numbers with bits in paca->irq_happened */
440		.if \vec == 0x500 || \vec == 0xea0
441		li	r10,PACA_IRQ_EE
442		.elseif \vec == 0x900
443		li	r10,PACA_IRQ_DEC
444		.elseif \vec == 0xa00 || \vec == 0xe80
445		li	r10,PACA_IRQ_DBELL
446		.elseif \vec == 0xe60
447		li	r10,PACA_IRQ_HMI
448		.elseif \vec == 0xf00
449		li	r10,PACA_IRQ_PMI
450		.else
451		.abort "Bad maskable vector"
452		.endif
453
454		.if \hsrr == EXC_HV_OR_STD
455		BEGIN_FTR_SECTION
456		bne	masked_Hinterrupt
457		FTR_SECTION_ELSE
458		bne	masked_interrupt
459		ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
460		.elseif \hsrr
461		bne	masked_Hinterrupt
462		.else
463		bne	masked_interrupt
464		.endif
465	.endif
466
467	std	r11,\area\()+EX_R11(r13)
468	std	r12,\area\()+EX_R12(r13)
469
470	/*
471	 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
472	 * because a d-side MCE will clobber those registers so is
473	 * not recoverable if they are live.
474	 */
475	GET_SCRATCH0(r10)
476	std	r10,\area\()+EX_R13(r13)
477	.if \dar
478	.if \hsrr
479	mfspr	r10,SPRN_HDAR
480	.else
481	mfspr	r10,SPRN_DAR
482	.endif
483	std	r10,\area\()+EX_DAR(r13)
484	.endif
485	.if \dsisr
486	.if \hsrr
487	mfspr	r10,SPRN_HDSISR
488	.else
489	mfspr	r10,SPRN_DSISR
490	.endif
491	stw	r10,\area\()+EX_DSISR(r13)
492	.endif
493
494	.if \early == 2
495	/* nothing more */
496	.elseif \early
497	mfctr	r10			/* save ctr, even for !RELOCATABLE */
498	BRANCH_TO_C000(r11, \name\()_early_common)
499	.elseif !\virt
500	INT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr, \ri
501	.else
502	INT_VIRT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr
503	.endif
504	.if \ool
505	.popsection
506	.endif
507.endm
508
509/*
510 * On entry r13 points to the paca, r9-r13 are saved in the paca,
511 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
512 * SRR1, and relocation is on.
513 *
514 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
515 * PPR save and CPU accounting is not done for the !stack case (XXX why not?)
516 */
517.macro INT_COMMON vec, area, stack, kuap, reconcile, dar, dsisr
518	.if \stack
519	andi.	r10,r12,MSR_PR		/* See if coming from user	*/
520	mr	r10,r1			/* Save r1			*/
521	subi	r1,r1,INT_FRAME_SIZE	/* alloc frame on kernel stack	*/
522	beq-	100f
523	ld	r1,PACAKSAVE(r13)	/* kernel stack to use		*/
524100:	tdgei	r1,-INT_FRAME_SIZE	/* trap if r1 is in userspace	*/
525	EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
526	.endif
527
528	std	r9,_CCR(r1)		/* save CR in stackframe	*/
529	std	r11,_NIP(r1)		/* save SRR0 in stackframe	*/
530	std	r12,_MSR(r1)		/* save SRR1 in stackframe	*/
531	std	r10,0(r1)		/* make stack chain pointer	*/
532	std	r0,GPR0(r1)		/* save r0 in stackframe	*/
533	std	r10,GPR1(r1)		/* save r1 in stackframe	*/
534
535	.if \stack
536	.if \kuap
537	kuap_save_amr_and_lock r9, r10, cr1, cr0
538	.endif
539	beq	101f			/* if from kernel mode		*/
540	ACCOUNT_CPU_USER_ENTRY(r13, r9, r10)
541	SAVE_PPR(\area, r9)
542101:
543	.else
544	.if \kuap
545	kuap_save_amr_and_lock r9, r10, cr1
546	.endif
547	.endif
548
549	/* Save original regs values from save area to stack frame. */
550	ld	r9,\area+EX_R9(r13)	/* move r9, r10 to stackframe	*/
551	ld	r10,\area+EX_R10(r13)
552	std	r9,GPR9(r1)
553	std	r10,GPR10(r1)
554	ld	r9,\area+EX_R11(r13)	/* move r11 - r13 to stackframe	*/
555	ld	r10,\area+EX_R12(r13)
556	ld	r11,\area+EX_R13(r13)
557	std	r9,GPR11(r1)
558	std	r10,GPR12(r1)
559	std	r11,GPR13(r1)
560	.if \dar
561	.if \dar == 2
562	ld	r10,_NIP(r1)
563	.else
564	ld	r10,\area+EX_DAR(r13)
565	.endif
566	std	r10,_DAR(r1)
567	.endif
568	.if \dsisr
569	.if \dsisr == 2
570	ld	r10,_MSR(r1)
571	lis	r11,DSISR_SRR1_MATCH_64S@h
572	and	r10,r10,r11
573	.else
574	lwz	r10,\area+EX_DSISR(r13)
575	.endif
576	std	r10,_DSISR(r1)
577	.endif
578BEGIN_FTR_SECTION_NESTED(66)
579	ld	r10,\area+EX_CFAR(r13)
580	std	r10,ORIG_GPR3(r1)
581END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66)
582	GET_CTR(r10, \area)
583	std	r10,_CTR(r1)
584	std	r2,GPR2(r1)		/* save r2 in stackframe	*/
585	SAVE_4GPRS(3, r1)		/* save r3 - r6 in stackframe   */
586	SAVE_2GPRS(7, r1)		/* save r7, r8 in stackframe	*/
587	mflr	r9			/* Get LR, later save to stack	*/
588	ld	r2,PACATOC(r13)		/* get kernel TOC into r2	*/
589	std	r9,_LINK(r1)
590	lbz	r10,PACAIRQSOFTMASK(r13)
591	mfspr	r11,SPRN_XER		/* save XER in stackframe	*/
592	std	r10,SOFTE(r1)
593	std	r11,_XER(r1)
594	li	r9,(\vec)+1
595	std	r9,_TRAP(r1)		/* set trap number		*/
596	li	r10,0
597	ld	r11,exception_marker@toc(r2)
598	std	r10,RESULT(r1)		/* clear regs->result		*/
599	std	r11,STACK_FRAME_OVERHEAD-16(r1) /* mark the frame	*/
600
601	.if \stack
602	ACCOUNT_STOLEN_TIME
603	.endif
604
605	.if \reconcile
606	RECONCILE_IRQ_STATE(r10, r11)
607	.endif
608.endm
609
610/*
611 * Restore all registers including H/SRR0/1 saved in a stack frame of a
612 * standard exception.
613 */
614.macro EXCEPTION_RESTORE_REGS hsrr
615	/* Move original SRR0 and SRR1 into the respective regs */
616	ld	r9,_MSR(r1)
617	.if \hsrr == EXC_HV_OR_STD
618	.error "EXC_HV_OR_STD Not implemented for EXCEPTION_RESTORE_REGS"
619	.endif
620	.if \hsrr
621	mtspr	SPRN_HSRR1,r9
622	.else
623	mtspr	SPRN_SRR1,r9
624	.endif
625	ld	r9,_NIP(r1)
626	.if \hsrr
627	mtspr	SPRN_HSRR0,r9
628	.else
629	mtspr	SPRN_SRR0,r9
630	.endif
631	ld	r9,_CTR(r1)
632	mtctr	r9
633	ld	r9,_XER(r1)
634	mtxer	r9
635	ld	r9,_LINK(r1)
636	mtlr	r9
637	ld	r9,_CCR(r1)
638	mtcr	r9
639	REST_8GPRS(2, r1)
640	REST_4GPRS(10, r1)
641	REST_GPR(0, r1)
642	/* restore original r1. */
643	ld	r1,GPR1(r1)
644.endm
645
646#define RUNLATCH_ON				\
647BEGIN_FTR_SECTION				\
648	ld	r3, PACA_THREAD_INFO(r13);	\
649	ld	r4,TI_LOCAL_FLAGS(r3);		\
650	andi.	r0,r4,_TLF_RUNLATCH;		\
651	beql	ppc64_runlatch_on_trampoline;	\
652END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
653
654/*
655 * When the idle code in power4_idle puts the CPU into NAP mode,
656 * it has to do so in a loop, and relies on the external interrupt
657 * and decrementer interrupt entry code to get it out of the loop.
658 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
659 * to signal that it is in the loop and needs help to get out.
660 */
661#ifdef CONFIG_PPC_970_NAP
662#define FINISH_NAP				\
663BEGIN_FTR_SECTION				\
664	ld	r11, PACA_THREAD_INFO(r13);	\
665	ld	r9,TI_LOCAL_FLAGS(r11);		\
666	andi.	r10,r9,_TLF_NAPPING;		\
667	bnel	power4_fixup_nap;		\
668END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
669#else
670#define FINISH_NAP
671#endif
672
673#define EXC_COMMON(name, realvec, hdlr)					\
674	EXC_COMMON_BEGIN(name);						\
675	INT_COMMON realvec, PACA_EXGEN, 1, 1, 1, 0, 0 ;			\
676	bl	save_nvgprs;						\
677	addi	r3,r1,STACK_FRAME_OVERHEAD;				\
678	bl	hdlr;							\
679	b	ret_from_except
680
681/*
682 * Like EXC_COMMON, but for exceptions that can occur in the idle task and
683 * therefore need the special idle handling (finish nap and runlatch)
684 */
685#define EXC_COMMON_ASYNC(name, realvec, hdlr)				\
686	EXC_COMMON_BEGIN(name);						\
687	INT_COMMON realvec, PACA_EXGEN, 1, 1, 1, 0, 0 ;			\
688	FINISH_NAP;							\
689	RUNLATCH_ON;							\
690	addi	r3,r1,STACK_FRAME_OVERHEAD;				\
691	bl	hdlr;							\
692	b	ret_from_except_lite
693
694
695/*
696 * There are a few constraints to be concerned with.
697 * - Real mode exceptions code/data must be located at their physical location.
698 * - Virtual mode exceptions must be mapped at their 0xc000... location.
699 * - Fixed location code must not call directly beyond the __end_interrupts
700 *   area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
701 *   must be used.
702 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
703 *   virtual 0xc00...
704 * - Conditional branch targets must be within +/-32K of caller.
705 *
706 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
707 * therefore don't have to run in physically located code or rfid to
708 * virtual mode kernel code. However on relocatable kernels they do have
709 * to branch to KERNELBASE offset because the rest of the kernel (outside
710 * the exception vectors) may be located elsewhere.
711 *
712 * Virtual exceptions correspond with physical, except their entry points
713 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
714 * offset applied. Virtual exceptions are enabled with the Alternate
715 * Interrupt Location (AIL) bit set in the LPCR. However this does not
716 * guarantee they will be delivered virtually. Some conditions (see the ISA)
717 * cause exceptions to be delivered in real mode.
718 *
719 * It's impossible to receive interrupts below 0x300 via AIL.
720 *
721 * KVM: None of the virtual exceptions are from the guest. Anything that
722 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
723 *
724 *
725 * We layout physical memory as follows:
726 * 0x0000 - 0x00ff : Secondary processor spin code
727 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
728 * 0x1900 - 0x3fff : Real mode trampolines
729 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
730 * 0x5900 - 0x6fff : Relon mode trampolines
731 * 0x7000 - 0x7fff : FWNMI data area
732 * 0x8000 -   .... : Common interrupt handlers, remaining early
733 *                   setup code, rest of kernel.
734 *
735 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
736 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
737 * vectors there.
738 */
739OPEN_FIXED_SECTION(real_vectors,        0x0100, 0x1900)
740OPEN_FIXED_SECTION(real_trampolines,    0x1900, 0x4000)
741OPEN_FIXED_SECTION(virt_vectors,        0x4000, 0x5900)
742OPEN_FIXED_SECTION(virt_trampolines,    0x5900, 0x7000)
743
744#ifdef CONFIG_PPC_POWERNV
745	.globl start_real_trampolines
746	.globl end_real_trampolines
747	.globl start_virt_trampolines
748	.globl end_virt_trampolines
749#endif
750
751#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
752/*
753 * Data area reserved for FWNMI option.
754 * This address (0x7000) is fixed by the RPA.
755 * pseries and powernv need to keep the whole page from
756 * 0x7000 to 0x8000 free for use by the firmware
757 */
758ZERO_FIXED_SECTION(fwnmi_page,          0x7000, 0x8000)
759OPEN_TEXT_SECTION(0x8000)
760#else
761OPEN_TEXT_SECTION(0x7000)
762#endif
763
764USE_FIXED_SECTION(real_vectors)
765
766/*
767 * This is the start of the interrupt handlers for pSeries
768 * This code runs with relocation off.
769 * Code from here to __end_interrupts gets copied down to real
770 * address 0x100 when we are running a relocatable kernel.
771 * Therefore any relative branches in this section must only
772 * branch to labels in this section.
773 */
774	.globl __start_interrupts
775__start_interrupts:
776
777/* No virt vectors corresponding with 0x0..0x100 */
778EXC_VIRT_NONE(0x4000, 0x100)
779
780
781EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
782#ifdef CONFIG_PPC_P7_NAP
783	/*
784	 * If running native on arch 2.06 or later, check if we are waking up
785	 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
786	 * bits 46:47. A non-0 value indicates that we are coming from a power
787	 * saving state. The idle wakeup handler initially runs in real mode,
788	 * but we branch to the 0xc000... address so we can turn on relocation
789	 * with mtmsrd later, after SPRs are restored.
790	 *
791	 * Careful to minimise cost for the fast path (idle wakeup) while
792	 * also avoiding clobbering CFAR for the debug path (non-idle).
793	 *
794	 * For the idle wake case volatile registers can be clobbered, which
795	 * is why we use those initially. If it turns out to not be an idle
796	 * wake, carefully put everything back the way it was, so we can use
797	 * common exception macros to handle it.
798	 */
799BEGIN_FTR_SECTION
800	SET_SCRATCH0(r13)
801	GET_PACA(r13)
802	std	r3,PACA_EXNMI+0*8(r13)
803	std	r4,PACA_EXNMI+1*8(r13)
804	std	r5,PACA_EXNMI+2*8(r13)
805	mfspr	r3,SPRN_SRR1
806	mfocrf	r4,0x80
807	rlwinm.	r5,r3,47-31,30,31
808	bne+	system_reset_idle_wake
809	/* Not powersave wakeup. Restore regs for regular interrupt handler. */
810	mtocrf	0x80,r4
811	ld	r3,PACA_EXNMI+0*8(r13)
812	ld	r4,PACA_EXNMI+1*8(r13)
813	ld	r5,PACA_EXNMI+2*8(r13)
814	GET_SCRATCH0(r13)
815END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
816#endif
817
818	INT_HANDLER system_reset, 0x100, area=PACA_EXNMI, ri=0, kvm=1
819	/*
820	 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
821	 * being used, so a nested NMI exception would corrupt it.
822	 *
823	 * In theory, we should not enable relocation here if it was disabled
824	 * in SRR1, because the MMU may not be configured to support it (e.g.,
825	 * SLB may have been cleared). In practice, there should only be a few
826	 * small windows where that's the case, and sreset is considered to
827	 * be dangerous anyway.
828	 */
829EXC_REAL_END(system_reset, 0x100, 0x100)
830EXC_VIRT_NONE(0x4100, 0x100)
831INT_KVM_HANDLER system_reset 0x100, EXC_STD, PACA_EXNMI, 0
832
833#ifdef CONFIG_PPC_P7_NAP
834TRAMP_REAL_BEGIN(system_reset_idle_wake)
835	/* We are waking up from idle, so may clobber any volatile register */
836	cmpwi	cr1,r5,2
837	bltlr	cr1	/* no state loss, return to idle caller with r3=SRR1 */
838	BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss))
839#endif
840
841#ifdef CONFIG_PPC_PSERIES
842/*
843 * Vectors for the FWNMI option.  Share common code.
844 */
845TRAMP_REAL_BEGIN(system_reset_fwnmi)
846	/* See comment at system_reset exception, don't turn on RI */
847	INT_HANDLER system_reset, 0x100, area=PACA_EXNMI, ri=0
848
849#endif /* CONFIG_PPC_PSERIES */
850
851EXC_COMMON_BEGIN(system_reset_common)
852	/*
853	 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
854	 * to recover, but nested NMI will notice in_nmi and not recover
855	 * because of the use of the NMI stack. in_nmi reentrancy is tested in
856	 * system_reset_exception.
857	 */
858	lhz	r10,PACA_IN_NMI(r13)
859	addi	r10,r10,1
860	sth	r10,PACA_IN_NMI(r13)
861	li	r10,MSR_RI
862	mtmsrd 	r10,1
863
864	mr	r10,r1
865	ld	r1,PACA_NMI_EMERG_SP(r13)
866	subi	r1,r1,INT_FRAME_SIZE
867	INT_COMMON 0x100, PACA_EXNMI, 0, 1, 0, 0, 0
868	bl	save_nvgprs
869	/*
870	 * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does
871	 * the right thing. We do not want to reconcile because that goes
872	 * through irq tracing which we don't want in NMI.
873	 *
874	 * Save PACAIRQHAPPENED because some code will do a hard disable
875	 * (e.g., xmon). So we want to restore this back to where it was
876	 * when we return. DAR is unused in the stack, so save it there.
877	 */
878	li	r10,IRQS_ALL_DISABLED
879	stb	r10,PACAIRQSOFTMASK(r13)
880	lbz	r10,PACAIRQHAPPENED(r13)
881	std	r10,_DAR(r1)
882
883	addi	r3,r1,STACK_FRAME_OVERHEAD
884	bl	system_reset_exception
885
886	/* Clear MSR_RI before setting SRR0 and SRR1. */
887	li	r9,0
888	mtmsrd	r9,1
889
890	/*
891	 * MSR_RI is clear, now we can decrement paca->in_nmi.
892	 */
893	lhz	r10,PACA_IN_NMI(r13)
894	subi	r10,r10,1
895	sth	r10,PACA_IN_NMI(r13)
896
897	/*
898	 * Restore soft mask settings.
899	 */
900	ld	r10,_DAR(r1)
901	stb	r10,PACAIRQHAPPENED(r13)
902	ld	r10,SOFTE(r1)
903	stb	r10,PACAIRQSOFTMASK(r13)
904
905	EXCEPTION_RESTORE_REGS EXC_STD
906	RFI_TO_USER_OR_KERNEL
907
908
909EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
910	INT_HANDLER machine_check, 0x200, early=1, area=PACA_EXMC, dar=1, dsisr=1
911	/*
912	 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
913	 * nested machine check corrupts it. machine_check_common enables
914	 * MSR_RI.
915	 */
916EXC_REAL_END(machine_check, 0x200, 0x100)
917EXC_VIRT_NONE(0x4200, 0x100)
918
919#ifdef CONFIG_PPC_PSERIES
920TRAMP_REAL_BEGIN(machine_check_fwnmi)
921	/* See comment at machine_check exception, don't turn on RI */
922	INT_HANDLER machine_check, 0x200, early=1, area=PACA_EXMC, dar=1, dsisr=1
923#endif
924
925INT_KVM_HANDLER machine_check 0x200, EXC_STD, PACA_EXMC, 1
926
927#define MACHINE_CHECK_HANDLER_WINDUP			\
928	/* Clear MSR_RI before setting SRR0 and SRR1. */\
929	li	r9,0;					\
930	mtmsrd	r9,1;		/* Clear MSR_RI */	\
931	/* Decrement paca->in_mce now RI is clear. */	\
932	lhz	r12,PACA_IN_MCE(r13);			\
933	subi	r12,r12,1;				\
934	sth	r12,PACA_IN_MCE(r13);			\
935	EXCEPTION_RESTORE_REGS EXC_STD
936
937EXC_COMMON_BEGIN(machine_check_early_common)
938	mtctr	r10			/* Restore ctr */
939	mfspr	r11,SPRN_SRR0
940	mfspr	r12,SPRN_SRR1
941
942	/*
943	 * Switch to mc_emergency stack and handle re-entrancy (we limit
944	 * the nested MCE upto level 4 to avoid stack overflow).
945	 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
946	 *
947	 * We use paca->in_mce to check whether this is the first entry or
948	 * nested machine check. We increment paca->in_mce to track nested
949	 * machine checks.
950	 *
951	 * If this is the first entry then set stack pointer to
952	 * paca->mc_emergency_sp, otherwise r1 is already pointing to
953	 * stack frame on mc_emergency stack.
954	 *
955	 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
956	 * checkstop if we get another machine check exception before we do
957	 * rfid with MSR_ME=1.
958	 *
959	 * This interrupt can wake directly from idle. If that is the case,
960	 * the machine check is handled then the idle wakeup code is called
961	 * to restore state.
962	 */
963	lhz	r10,PACA_IN_MCE(r13)
964	cmpwi	r10,0			/* Are we in nested machine check */
965	cmpwi	cr1,r10,MAX_MCE_DEPTH	/* Are we at maximum nesting */
966	addi	r10,r10,1		/* increment paca->in_mce */
967	sth	r10,PACA_IN_MCE(r13)
968
969	mr	r10,r1			/* Save r1 */
970	bne	1f
971	/* First machine check entry */
972	ld	r1,PACAMCEMERGSP(r13)	/* Use MC emergency stack */
9731:	/* Limit nested MCE to level 4 to avoid stack overflow */
974	bgt	cr1,unrecoverable_mce	/* Check if we hit limit of 4 */
975	subi	r1,r1,INT_FRAME_SIZE	/* alloc stack frame */
976
977	/* We don't touch AMR here, we never go to virtual mode */
978	INT_COMMON 0x200, PACA_EXMC, 0, 0, 0, 1, 1
979
980BEGIN_FTR_SECTION
981	bl	enable_machine_check
982END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
983	li	r10,MSR_RI
984	mtmsrd	r10,1
985
986	bl	save_nvgprs
987	addi	r3,r1,STACK_FRAME_OVERHEAD
988	bl	machine_check_early
989	std	r3,RESULT(r1)	/* Save result */
990	ld	r12,_MSR(r1)
991
992#ifdef CONFIG_PPC_P7_NAP
993	/*
994	 * Check if thread was in power saving mode. We come here when any
995	 * of the following is true:
996	 * a. thread wasn't in power saving mode
997	 * b. thread was in power saving mode with no state loss,
998	 *    supervisor state loss or hypervisor state loss.
999	 *
1000	 * Go back to nap/sleep/winkle mode again if (b) is true.
1001	 */
1002BEGIN_FTR_SECTION
1003	rlwinm.	r11,r12,47-31,30,31
1004	bne	machine_check_idle_common
1005END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1006#endif
1007
1008#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1009	/*
1010	 * Check if we are coming from guest. If yes, then run the normal
1011	 * exception handler which will take the
1012	 * machine_check_kvm->kvmppc_interrupt branch to deliver the MC event
1013	 * to guest.
1014	 */
1015	lbz	r11,HSTATE_IN_GUEST(r13)
1016	cmpwi	r11,0			/* Check if coming from guest */
1017	bne	mce_deliver		/* continue if we are. */
1018#endif
1019
1020	/*
1021	 * Check if we are coming from userspace. If yes, then run the normal
1022	 * exception handler which will deliver the MC event to this kernel.
1023	 */
1024	andi.	r11,r12,MSR_PR		/* See if coming from user. */
1025	bne	mce_deliver		/* continue in V mode if we are. */
1026
1027	/*
1028	 * At this point we are coming from kernel context.
1029	 * Queue up the MCE event and return from the interrupt.
1030	 * But before that, check if this is an un-recoverable exception.
1031	 * If yes, then stay on emergency stack and panic.
1032	 */
1033	andi.	r11,r12,MSR_RI
1034	beq	unrecoverable_mce
1035
1036	/*
1037	 * Check if we have successfully handled/recovered from error, if not
1038	 * then stay on emergency stack and panic.
1039	 */
1040	ld	r3,RESULT(r1)	/* Load result */
1041	cmpdi	r3,0		/* see if we handled MCE successfully */
1042	beq	unrecoverable_mce /* if !handled then panic */
1043
1044	/*
1045	 * Return from MC interrupt.
1046	 * Queue up the MCE event so that we can log it later, while
1047	 * returning from kernel or opal call.
1048	 */
1049	bl	machine_check_queue_event
1050	MACHINE_CHECK_HANDLER_WINDUP
1051	RFI_TO_KERNEL
1052
1053mce_deliver:
1054	/*
1055	 * This is a host user or guest MCE. Restore all registers, then
1056	 * run the "late" handler. For host user, this will run the
1057	 * machine_check_exception handler in virtual mode like a normal
1058	 * interrupt handler. For guest, this will trigger the KVM test
1059	 * and branch to the KVM interrupt similarly to other interrupts.
1060	 */
1061BEGIN_FTR_SECTION
1062	ld	r10,ORIG_GPR3(r1)
1063	mtspr	SPRN_CFAR,r10
1064END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1065	MACHINE_CHECK_HANDLER_WINDUP
1066	/* See comment at machine_check exception, don't turn on RI */
1067	INT_HANDLER machine_check, 0x200, area=PACA_EXMC, ri=0, dar=1, dsisr=1, kvm=1
1068
1069EXC_COMMON_BEGIN(machine_check_common)
1070	/*
1071	 * Machine check is different because we use a different
1072	 * save area: PACA_EXMC instead of PACA_EXGEN.
1073	 */
1074	INT_COMMON 0x200, PACA_EXMC, 1, 1, 1, 1, 1
1075	FINISH_NAP
1076	/* Enable MSR_RI when finished with PACA_EXMC */
1077	li	r10,MSR_RI
1078	mtmsrd 	r10,1
1079	bl	save_nvgprs
1080	addi	r3,r1,STACK_FRAME_OVERHEAD
1081	bl	machine_check_exception
1082	b	ret_from_except
1083
1084#ifdef CONFIG_PPC_P7_NAP
1085/*
1086 * This is an idle wakeup. Low level machine check has already been
1087 * done. Queue the event then call the idle code to do the wake up.
1088 */
1089EXC_COMMON_BEGIN(machine_check_idle_common)
1090	bl	machine_check_queue_event
1091
1092	/*
1093	 * We have not used any non-volatile GPRs here, and as a rule
1094	 * most exception code including machine check does not.
1095	 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
1096	 * wakeup will restore volatile registers.
1097	 *
1098	 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
1099	 *
1100	 * Then decrement MCE nesting after finishing with the stack.
1101	 */
1102	ld	r3,_MSR(r1)
1103	ld	r4,_LINK(r1)
1104
1105	lhz	r11,PACA_IN_MCE(r13)
1106	subi	r11,r11,1
1107	sth	r11,PACA_IN_MCE(r13)
1108
1109	mtlr	r4
1110	rlwinm	r10,r3,47-31,30,31
1111	cmpwi	cr1,r10,2
1112	bltlr	cr1	/* no state loss, return to idle caller */
1113	b	idle_return_gpr_loss
1114#endif
1115
1116EXC_COMMON_BEGIN(unrecoverable_mce)
1117	/*
1118	 * We are going down. But there are chances that we might get hit by
1119	 * another MCE during panic path and we may run into unstable state
1120	 * with no way out. Hence, turn ME bit off while going down, so that
1121	 * when another MCE is hit during panic path, system will checkstop
1122	 * and hypervisor will get restarted cleanly by SP.
1123	 */
1124BEGIN_FTR_SECTION
1125	li	r10,0 /* clear MSR_RI */
1126	mtmsrd	r10,1
1127	bl	disable_machine_check
1128END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1129	ld	r10,PACAKMSR(r13)
1130	li	r3,MSR_ME
1131	andc	r10,r10,r3
1132	mtmsrd	r10
1133
1134	/* Invoke machine_check_exception to print MCE event and panic. */
1135	addi	r3,r1,STACK_FRAME_OVERHEAD
1136	bl	machine_check_exception
1137
1138	/*
1139	 * We will not reach here. Even if we did, there is no way out.
1140	 * Call unrecoverable_exception and die.
1141	 */
1142	addi	r3,r1,STACK_FRAME_OVERHEAD
1143	bl	unrecoverable_exception
1144	b	.
1145
1146
1147EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1148	INT_HANDLER data_access, 0x300, ool=1, dar=1, dsisr=1, kvm=1
1149EXC_REAL_END(data_access, 0x300, 0x80)
1150EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1151	INT_HANDLER data_access, 0x300, virt=1, dar=1, dsisr=1
1152EXC_VIRT_END(data_access, 0x4300, 0x80)
1153INT_KVM_HANDLER data_access, 0x300, EXC_STD, PACA_EXGEN, 1
1154EXC_COMMON_BEGIN(data_access_common)
1155	/*
1156	 * Here r13 points to the paca, r9 contains the saved CR,
1157	 * SRR0 and SRR1 are saved in r11 and r12,
1158	 * r9 - r13 are saved in paca->exgen.
1159	 * EX_DAR and EX_DSISR have saved DAR/DSISR
1160	 */
1161	INT_COMMON 0x300, PACA_EXGEN, 1, 1, 1, 1, 1
1162	ld	r4,_DAR(r1)
1163	ld	r5,_DSISR(r1)
1164BEGIN_MMU_FTR_SECTION
1165	ld	r6,_MSR(r1)
1166	li	r3,0x300
1167	b	do_hash_page		/* Try to handle as hpte fault */
1168MMU_FTR_SECTION_ELSE
1169	b	handle_page_fault
1170ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1171
1172
1173EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1174	INT_HANDLER data_access_slb, 0x380, ool=1, area=PACA_EXSLB, dar=1, kvm=1
1175EXC_REAL_END(data_access_slb, 0x380, 0x80)
1176EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1177	INT_HANDLER data_access_slb, 0x380, virt=1, area=PACA_EXSLB, dar=1
1178EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1179INT_KVM_HANDLER data_access_slb, 0x380, EXC_STD, PACA_EXSLB, 1
1180EXC_COMMON_BEGIN(data_access_slb_common)
1181	INT_COMMON 0x380, PACA_EXSLB, 1, 1, 0, 1, 0
1182	ld	r4,_DAR(r1)
1183	addi	r3,r1,STACK_FRAME_OVERHEAD
1184BEGIN_MMU_FTR_SECTION
1185	/* HPT case, do SLB fault */
1186	bl	do_slb_fault
1187	cmpdi	r3,0
1188	bne-	1f
1189	b	fast_exception_return
11901:	/* Error case */
1191MMU_FTR_SECTION_ELSE
1192	/* Radix case, access is outside page table range */
1193	li	r3,-EFAULT
1194ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1195	std	r3,RESULT(r1)
1196	bl	save_nvgprs
1197	RECONCILE_IRQ_STATE(r10, r11)
1198	ld	r4,_DAR(r1)
1199	ld	r5,RESULT(r1)
1200	addi	r3,r1,STACK_FRAME_OVERHEAD
1201	bl	do_bad_slb_fault
1202	b	ret_from_except
1203
1204
1205EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1206	INT_HANDLER instruction_access, 0x400, kvm=1
1207EXC_REAL_END(instruction_access, 0x400, 0x80)
1208EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1209	INT_HANDLER instruction_access, 0x400, virt=1
1210EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1211INT_KVM_HANDLER instruction_access, 0x400, EXC_STD, PACA_EXGEN, 0
1212EXC_COMMON_BEGIN(instruction_access_common)
1213	INT_COMMON 0x400, PACA_EXGEN, 1, 1, 1, 2, 2
1214	ld	r4,_DAR(r1)
1215	ld	r5,_DSISR(r1)
1216BEGIN_MMU_FTR_SECTION
1217	ld      r6,_MSR(r1)
1218	li	r3,0x400
1219	b	do_hash_page		/* Try to handle as hpte fault */
1220MMU_FTR_SECTION_ELSE
1221	b	handle_page_fault
1222ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1223
1224
1225EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1226	INT_HANDLER instruction_access_slb, 0x480, area=PACA_EXSLB, kvm=1
1227EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1228EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1229	INT_HANDLER instruction_access_slb, 0x480, virt=1, area=PACA_EXSLB
1230EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1231INT_KVM_HANDLER instruction_access_slb, 0x480, EXC_STD, PACA_EXSLB, 0
1232EXC_COMMON_BEGIN(instruction_access_slb_common)
1233	INT_COMMON 0x480, PACA_EXSLB, 1, 1, 0, 2, 0
1234	ld	r4,_DAR(r1)
1235	addi	r3,r1,STACK_FRAME_OVERHEAD
1236BEGIN_MMU_FTR_SECTION
1237	/* HPT case, do SLB fault */
1238	bl	do_slb_fault
1239	cmpdi	r3,0
1240	bne-	1f
1241	b	fast_exception_return
12421:	/* Error case */
1243MMU_FTR_SECTION_ELSE
1244	/* Radix case, access is outside page table range */
1245	li	r3,-EFAULT
1246ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1247	std	r3,RESULT(r1)
1248	bl	save_nvgprs
1249	RECONCILE_IRQ_STATE(r10, r11)
1250	ld	r4,_DAR(r1)
1251	ld	r5,RESULT(r1)
1252	addi	r3,r1,STACK_FRAME_OVERHEAD
1253	bl	do_bad_slb_fault
1254	b	ret_from_except
1255
1256EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1257	INT_HANDLER hardware_interrupt, 0x500, hsrr=EXC_HV_OR_STD, bitmask=IRQS_DISABLED, kvm=1
1258EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1259EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1260	INT_HANDLER hardware_interrupt, 0x500, virt=1, hsrr=EXC_HV_OR_STD, bitmask=IRQS_DISABLED, kvm=1
1261EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1262INT_KVM_HANDLER hardware_interrupt, 0x500, EXC_HV_OR_STD, PACA_EXGEN, 0
1263EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
1264
1265
1266EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1267	INT_HANDLER alignment, 0x600, dar=1, dsisr=1, kvm=1
1268EXC_REAL_END(alignment, 0x600, 0x100)
1269EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1270	INT_HANDLER alignment, 0x600, virt=1, dar=1, dsisr=1
1271EXC_VIRT_END(alignment, 0x4600, 0x100)
1272INT_KVM_HANDLER alignment, 0x600, EXC_STD, PACA_EXGEN, 0
1273EXC_COMMON_BEGIN(alignment_common)
1274	INT_COMMON 0x600, PACA_EXGEN, 1, 1, 1, 1, 1
1275	bl	save_nvgprs
1276	addi	r3,r1,STACK_FRAME_OVERHEAD
1277	bl	alignment_exception
1278	b	ret_from_except
1279
1280
1281EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1282	INT_HANDLER program_check, 0x700, kvm=1
1283EXC_REAL_END(program_check, 0x700, 0x100)
1284EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1285	INT_HANDLER program_check, 0x700, virt=1
1286EXC_VIRT_END(program_check, 0x4700, 0x100)
1287INT_KVM_HANDLER program_check, 0x700, EXC_STD, PACA_EXGEN, 0
1288EXC_COMMON_BEGIN(program_check_common)
1289	/*
1290	 * It's possible to receive a TM Bad Thing type program check with
1291	 * userspace register values (in particular r1), but with SRR1 reporting
1292	 * that we came from the kernel. Normally that would confuse the bad
1293	 * stack logic, and we would report a bad kernel stack pointer. Instead
1294	 * we switch to the emergency stack if we're taking a TM Bad Thing from
1295	 * the kernel.
1296	 */
1297
1298	andi.	r10,r12,MSR_PR
1299	bne	2f			/* If userspace, go normal path */
1300
1301	andis.	r10,r12,(SRR1_PROGTM)@h
1302	bne	1f			/* If TM, emergency		*/
1303
1304	cmpdi	r1,-INT_FRAME_SIZE	/* check if r1 is in userspace	*/
1305	blt	2f			/* normal path if not		*/
1306
1307	/* Use the emergency stack					*/
13081:	andi.	r10,r12,MSR_PR		/* Set CR0 correctly for label	*/
1309					/* 3 in EXCEPTION_PROLOG_COMMON	*/
1310	mr	r10,r1			/* Save r1			*/
1311	ld	r1,PACAEMERGSP(r13)	/* Use emergency stack		*/
1312	subi	r1,r1,INT_FRAME_SIZE	/* alloc stack frame		*/
1313	INT_COMMON 0x700, PACA_EXGEN, 0, 1, 1, 0, 0
1314	b 3f
13152:
1316	INT_COMMON 0x700, PACA_EXGEN, 1, 1, 1, 0, 0
13173:
1318	bl	save_nvgprs
1319	addi	r3,r1,STACK_FRAME_OVERHEAD
1320	bl	program_check_exception
1321	b	ret_from_except
1322
1323
1324EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1325	INT_HANDLER fp_unavailable, 0x800, kvm=1
1326EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1327EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1328	INT_HANDLER fp_unavailable, 0x800, virt=1
1329EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1330INT_KVM_HANDLER fp_unavailable, 0x800, EXC_STD, PACA_EXGEN, 0
1331EXC_COMMON_BEGIN(fp_unavailable_common)
1332	INT_COMMON 0x800, PACA_EXGEN, 1, 1, 0, 0, 0
1333	bne	1f			/* if from user, just load it up */
1334	bl	save_nvgprs
1335	RECONCILE_IRQ_STATE(r10, r11)
1336	addi	r3,r1,STACK_FRAME_OVERHEAD
1337	bl	kernel_fp_unavailable_exception
13380:	trap
1339	EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
13401:
1341#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1342BEGIN_FTR_SECTION
1343	/* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1344	 * transaction), go do TM stuff
1345	 */
1346	rldicl.	r0, r12, (64-MSR_TS_LG), (64-2)
1347	bne-	2f
1348END_FTR_SECTION_IFSET(CPU_FTR_TM)
1349#endif
1350	bl	load_up_fpu
1351	b	fast_exception_return
1352#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
13532:	/* User process was in a transaction */
1354	bl	save_nvgprs
1355	RECONCILE_IRQ_STATE(r10, r11)
1356	addi	r3,r1,STACK_FRAME_OVERHEAD
1357	bl	fp_unavailable_tm
1358	b	ret_from_except
1359#endif
1360
1361
1362EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1363	INT_HANDLER decrementer, 0x900, ool=1, bitmask=IRQS_DISABLED, kvm=1
1364EXC_REAL_END(decrementer, 0x900, 0x80)
1365EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1366	INT_HANDLER decrementer, 0x900, virt=1, bitmask=IRQS_DISABLED
1367EXC_VIRT_END(decrementer, 0x4900, 0x80)
1368INT_KVM_HANDLER decrementer, 0x900, EXC_STD, PACA_EXGEN, 0
1369EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
1370
1371
1372EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1373	INT_HANDLER hdecrementer, 0x980, hsrr=EXC_HV, kvm=1
1374EXC_REAL_END(hdecrementer, 0x980, 0x80)
1375EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1376	INT_HANDLER hdecrementer, 0x980, virt=1, hsrr=EXC_HV, kvm=1
1377EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1378INT_KVM_HANDLER hdecrementer, 0x980, EXC_HV, PACA_EXGEN, 0
1379EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
1380
1381
1382EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1383	INT_HANDLER doorbell_super, 0xa00, bitmask=IRQS_DISABLED, kvm=1
1384EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1385EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1386	INT_HANDLER doorbell_super, 0xa00, virt=1, bitmask=IRQS_DISABLED
1387EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1388INT_KVM_HANDLER doorbell_super, 0xa00, EXC_STD, PACA_EXGEN, 0
1389#ifdef CONFIG_PPC_DOORBELL
1390EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
1391#else
1392EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
1393#endif
1394
1395
1396EXC_REAL_NONE(0xb00, 0x100)
1397EXC_VIRT_NONE(0x4b00, 0x100)
1398
1399/*
1400 * system call / hypercall (0xc00, 0x4c00)
1401 *
1402 * The system call exception is invoked with "sc 0" and does not alter HV bit.
1403 *
1404 * The hypercall is invoked with "sc 1" and sets HV=1.
1405 *
1406 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1407 * 0x4c00 virtual mode.
1408 *
1409 * Call convention:
1410 *
1411 * syscall and hypercalls register conventions are documented in
1412 * Documentation/powerpc/syscall64-abi.rst and
1413 * Documentation/powerpc/papr_hcalls.rst respectively.
1414 *
1415 * The intersection of volatile registers that don't contain possible
1416 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1417 * without saving, though xer is not a good idea to use, as hardware may
1418 * interpret some bits so it may be costly to change them.
1419 */
1420.macro SYSTEM_CALL virt
1421#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1422	/*
1423	 * There is a little bit of juggling to get syscall and hcall
1424	 * working well. Save r13 in ctr to avoid using SPRG scratch
1425	 * register.
1426	 *
1427	 * Userspace syscalls have already saved the PPR, hcalls must save
1428	 * it before setting HMT_MEDIUM.
1429	 */
1430	mtctr	r13
1431	GET_PACA(r13)
1432	std	r10,PACA_EXGEN+EX_R10(r13)
1433	INTERRUPT_TO_KERNEL
1434	KVMTEST system_call EXC_STD 0xc00 /* uses r10, branch to system_call_kvm */
1435	mfctr	r9
1436#else
1437	mr	r9,r13
1438	GET_PACA(r13)
1439	INTERRUPT_TO_KERNEL
1440#endif
1441
1442#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1443BEGIN_FTR_SECTION
1444	cmpdi	r0,0x1ebe
1445	beq-	1f
1446END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1447#endif
1448
1449	/* We reach here with PACA in r13, r13 in r9. */
1450	mfspr	r11,SPRN_SRR0
1451	mfspr	r12,SPRN_SRR1
1452
1453	HMT_MEDIUM
1454
1455	.if ! \virt
1456	__LOAD_HANDLER(r10, system_call_common)
1457	mtspr	SPRN_SRR0,r10
1458	ld	r10,PACAKMSR(r13)
1459	mtspr	SPRN_SRR1,r10
1460	RFI_TO_KERNEL
1461	b	.	/* prevent speculative execution */
1462	.else
1463	li	r10,MSR_RI
1464	mtmsrd 	r10,1			/* Set RI (EE=0) */
1465#ifdef CONFIG_RELOCATABLE
1466	__LOAD_HANDLER(r10, system_call_common)
1467	mtctr	r10
1468	bctr
1469#else
1470	b	system_call_common
1471#endif
1472	.endif
1473
1474#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1475	/* Fast LE/BE switch system call */
14761:	mfspr	r12,SPRN_SRR1
1477	xori	r12,r12,MSR_LE
1478	mtspr	SPRN_SRR1,r12
1479	mr	r13,r9
1480	RFI_TO_USER	/* return to userspace */
1481	b	.	/* prevent speculative execution */
1482#endif
1483.endm
1484
1485EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1486	SYSTEM_CALL 0
1487EXC_REAL_END(system_call, 0xc00, 0x100)
1488EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
1489	SYSTEM_CALL 1
1490EXC_VIRT_END(system_call, 0x4c00, 0x100)
1491
1492#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1493	/*
1494	 * This is a hcall, so register convention is as above, with these
1495	 * differences:
1496	 * r13 = PACA
1497	 * ctr = orig r13
1498	 * orig r10 saved in PACA
1499	 */
1500TRAMP_KVM_BEGIN(system_call_kvm)
1501	 /*
1502	  * Save the PPR (on systems that support it) before changing to
1503	  * HMT_MEDIUM. That allows the KVM code to save that value into the
1504	  * guest state (it is the guest's PPR value).
1505	  */
1506	OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
1507	HMT_MEDIUM
1508	OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
1509	mfctr	r10
1510	SET_SCRATCH0(r10)
1511	std	r9,PACA_EXGEN+EX_R9(r13)
1512	mfcr	r9
1513	KVM_HANDLER 0xc00, EXC_STD, PACA_EXGEN, 0
1514#endif
1515
1516
1517EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
1518	INT_HANDLER single_step, 0xd00, kvm=1
1519EXC_REAL_END(single_step, 0xd00, 0x100)
1520EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
1521	INT_HANDLER single_step, 0xd00, virt=1
1522EXC_VIRT_END(single_step, 0x4d00, 0x100)
1523INT_KVM_HANDLER single_step, 0xd00, EXC_STD, PACA_EXGEN, 0
1524EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1525
1526
1527EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
1528	INT_HANDLER h_data_storage, 0xe00, ool=1, hsrr=EXC_HV, dar=1, dsisr=1, kvm=1
1529EXC_REAL_END(h_data_storage, 0xe00, 0x20)
1530EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
1531	INT_HANDLER h_data_storage, 0xe00, ool=1, virt=1, hsrr=EXC_HV, dar=1, dsisr=1, kvm=1
1532EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
1533INT_KVM_HANDLER h_data_storage, 0xe00, EXC_HV, PACA_EXGEN, 1
1534EXC_COMMON_BEGIN(h_data_storage_common)
1535	INT_COMMON 0xe00, PACA_EXGEN, 1, 1, 1, 1, 1
1536	bl      save_nvgprs
1537	addi    r3,r1,STACK_FRAME_OVERHEAD
1538BEGIN_MMU_FTR_SECTION
1539	ld	r4,_DAR(r1)
1540	li	r5,SIGSEGV
1541	bl      bad_page_fault
1542MMU_FTR_SECTION_ELSE
1543	bl      unknown_exception
1544ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
1545	b       ret_from_except
1546
1547
1548EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
1549	INT_HANDLER h_instr_storage, 0xe20, ool=1, hsrr=EXC_HV, kvm=1
1550EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
1551EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
1552	INT_HANDLER h_instr_storage, 0xe20, ool=1, virt=1, hsrr=EXC_HV, kvm=1
1553EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
1554INT_KVM_HANDLER h_instr_storage, 0xe20, EXC_HV, PACA_EXGEN, 0
1555EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1556
1557
1558EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
1559	INT_HANDLER emulation_assist, 0xe40, ool=1, hsrr=EXC_HV, kvm=1
1560EXC_REAL_END(emulation_assist, 0xe40, 0x20)
1561EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
1562	INT_HANDLER emulation_assist, 0xe40, ool=1, virt=1, hsrr=EXC_HV, kvm=1
1563EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
1564INT_KVM_HANDLER emulation_assist, 0xe40, EXC_HV, PACA_EXGEN, 0
1565EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1566
1567
1568/*
1569 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1570 * first, and then eventaully from there to the trampoline to get into virtual
1571 * mode.
1572 */
1573EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
1574	INT_HANDLER hmi_exception, 0xe60, ool=1, early=1, hsrr=EXC_HV, ri=0, kvm=1
1575EXC_REAL_END(hmi_exception, 0xe60, 0x20)
1576EXC_VIRT_NONE(0x4e60, 0x20)
1577INT_KVM_HANDLER hmi_exception, 0xe60, EXC_HV, PACA_EXGEN, 0
1578EXC_COMMON_BEGIN(hmi_exception_early_common)
1579	mtctr	r10			/* Restore ctr */
1580	mfspr	r11,SPRN_HSRR0		/* Save HSRR0 */
1581	mfspr	r12,SPRN_HSRR1		/* Save HSRR1 */
1582	mr	r10,r1			/* Save r1 */
1583	ld	r1,PACAEMERGSP(r13)	/* Use emergency stack for realmode */
1584	subi	r1,r1,INT_FRAME_SIZE	/* alloc stack frame		*/
1585
1586	/* We don't touch AMR here, we never go to virtual mode */
1587	INT_COMMON 0xe60, PACA_EXGEN, 0, 0, 0, 0, 0
1588
1589	addi	r3,r1,STACK_FRAME_OVERHEAD
1590	bl	hmi_exception_realmode
1591	cmpdi	cr0,r3,0
1592	bne	1f
1593
1594	EXCEPTION_RESTORE_REGS EXC_HV
1595	HRFI_TO_USER_OR_KERNEL
1596
15971:
1598	/*
1599	 * Go to virtual mode and pull the HMI event information from
1600	 * firmware.
1601	 */
1602	EXCEPTION_RESTORE_REGS EXC_HV
1603	INT_HANDLER hmi_exception, 0xe60, hsrr=EXC_HV, bitmask=IRQS_DISABLED, kvm=1
1604
1605EXC_COMMON_BEGIN(hmi_exception_common)
1606	INT_COMMON 0xe60, PACA_EXGEN, 1, 1, 1, 0, 0
1607	FINISH_NAP
1608	RUNLATCH_ON
1609	bl	save_nvgprs
1610	addi	r3,r1,STACK_FRAME_OVERHEAD
1611	bl	handle_hmi_exception
1612	b	ret_from_except
1613
1614
1615EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
1616	INT_HANDLER h_doorbell, 0xe80, ool=1, hsrr=EXC_HV, bitmask=IRQS_DISABLED, kvm=1
1617EXC_REAL_END(h_doorbell, 0xe80, 0x20)
1618EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
1619	INT_HANDLER h_doorbell, 0xe80, ool=1, virt=1, hsrr=EXC_HV, bitmask=IRQS_DISABLED, kvm=1
1620EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
1621INT_KVM_HANDLER h_doorbell, 0xe80, EXC_HV, PACA_EXGEN, 0
1622#ifdef CONFIG_PPC_DOORBELL
1623EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1624#else
1625EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1626#endif
1627
1628
1629EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
1630	INT_HANDLER h_virt_irq, 0xea0, ool=1, hsrr=EXC_HV, bitmask=IRQS_DISABLED, kvm=1
1631EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
1632EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
1633	INT_HANDLER h_virt_irq, 0xea0, ool=1, virt=1, hsrr=EXC_HV, bitmask=IRQS_DISABLED, kvm=1
1634EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
1635INT_KVM_HANDLER h_virt_irq, 0xea0, EXC_HV, PACA_EXGEN, 0
1636EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1637
1638
1639EXC_REAL_NONE(0xec0, 0x20)
1640EXC_VIRT_NONE(0x4ec0, 0x20)
1641EXC_REAL_NONE(0xee0, 0x20)
1642EXC_VIRT_NONE(0x4ee0, 0x20)
1643
1644
1645EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
1646	INT_HANDLER performance_monitor, 0xf00, ool=1, bitmask=IRQS_PMI_DISABLED, kvm=1
1647EXC_REAL_END(performance_monitor, 0xf00, 0x20)
1648EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
1649	INT_HANDLER performance_monitor, 0xf00, ool=1, virt=1, bitmask=IRQS_PMI_DISABLED
1650EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
1651INT_KVM_HANDLER performance_monitor, 0xf00, EXC_STD, PACA_EXGEN, 0
1652EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1653
1654
1655EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
1656	INT_HANDLER altivec_unavailable, 0xf20, ool=1, kvm=1
1657EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
1658EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
1659	INT_HANDLER altivec_unavailable, 0xf20, ool=1, virt=1
1660EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
1661INT_KVM_HANDLER altivec_unavailable, 0xf20, EXC_STD, PACA_EXGEN, 0
1662EXC_COMMON_BEGIN(altivec_unavailable_common)
1663	INT_COMMON 0xf20, PACA_EXGEN, 1, 1, 0, 0, 0
1664#ifdef CONFIG_ALTIVEC
1665BEGIN_FTR_SECTION
1666	beq	1f
1667#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1668  BEGIN_FTR_SECTION_NESTED(69)
1669	/* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1670	 * transaction), go do TM stuff
1671	 */
1672	rldicl.	r0, r12, (64-MSR_TS_LG), (64-2)
1673	bne-	2f
1674  END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1675#endif
1676	bl	load_up_altivec
1677	b	fast_exception_return
1678#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
16792:	/* User process was in a transaction */
1680	bl	save_nvgprs
1681	RECONCILE_IRQ_STATE(r10, r11)
1682	addi	r3,r1,STACK_FRAME_OVERHEAD
1683	bl	altivec_unavailable_tm
1684	b	ret_from_except
1685#endif
16861:
1687END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1688#endif
1689	bl	save_nvgprs
1690	RECONCILE_IRQ_STATE(r10, r11)
1691	addi	r3,r1,STACK_FRAME_OVERHEAD
1692	bl	altivec_unavailable_exception
1693	b	ret_from_except
1694
1695
1696EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
1697	INT_HANDLER vsx_unavailable, 0xf40, ool=1, kvm=1
1698EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
1699EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
1700	INT_HANDLER vsx_unavailable, 0xf40, ool=1, virt=1
1701EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
1702INT_KVM_HANDLER vsx_unavailable, 0xf40, EXC_STD, PACA_EXGEN, 0
1703EXC_COMMON_BEGIN(vsx_unavailable_common)
1704	INT_COMMON 0xf40, PACA_EXGEN, 1, 1, 0, 0, 0
1705#ifdef CONFIG_VSX
1706BEGIN_FTR_SECTION
1707	beq	1f
1708#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1709  BEGIN_FTR_SECTION_NESTED(69)
1710	/* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1711	 * transaction), go do TM stuff
1712	 */
1713	rldicl.	r0, r12, (64-MSR_TS_LG), (64-2)
1714	bne-	2f
1715  END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1716#endif
1717	b	load_up_vsx
1718#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
17192:	/* User process was in a transaction */
1720	bl	save_nvgprs
1721	RECONCILE_IRQ_STATE(r10, r11)
1722	addi	r3,r1,STACK_FRAME_OVERHEAD
1723	bl	vsx_unavailable_tm
1724	b	ret_from_except
1725#endif
17261:
1727END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1728#endif
1729	bl	save_nvgprs
1730	RECONCILE_IRQ_STATE(r10, r11)
1731	addi	r3,r1,STACK_FRAME_OVERHEAD
1732	bl	vsx_unavailable_exception
1733	b	ret_from_except
1734
1735
1736EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
1737	INT_HANDLER facility_unavailable, 0xf60, ool=1, kvm=1
1738EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
1739EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
1740	INT_HANDLER facility_unavailable, 0xf60, ool=1, virt=1
1741EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
1742INT_KVM_HANDLER facility_unavailable, 0xf60, EXC_STD, PACA_EXGEN, 0
1743EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1744
1745
1746EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
1747	INT_HANDLER h_facility_unavailable, 0xf80, ool=1, hsrr=EXC_HV, kvm=1
1748EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
1749EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
1750	INT_HANDLER h_facility_unavailable, 0xf80, ool=1, virt=1, hsrr=EXC_HV, kvm=1
1751EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
1752INT_KVM_HANDLER h_facility_unavailable, 0xf80, EXC_HV, PACA_EXGEN, 0
1753EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1754
1755
1756EXC_REAL_NONE(0xfa0, 0x20)
1757EXC_VIRT_NONE(0x4fa0, 0x20)
1758EXC_REAL_NONE(0xfc0, 0x20)
1759EXC_VIRT_NONE(0x4fc0, 0x20)
1760EXC_REAL_NONE(0xfe0, 0x20)
1761EXC_VIRT_NONE(0x4fe0, 0x20)
1762
1763EXC_REAL_NONE(0x1000, 0x100)
1764EXC_VIRT_NONE(0x5000, 0x100)
1765EXC_REAL_NONE(0x1100, 0x100)
1766EXC_VIRT_NONE(0x5100, 0x100)
1767
1768#ifdef CONFIG_CBE_RAS
1769EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
1770	INT_HANDLER cbe_system_error, 0x1200, ool=1, hsrr=EXC_HV, kvm=1
1771EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
1772EXC_VIRT_NONE(0x5200, 0x100)
1773INT_KVM_HANDLER cbe_system_error, 0x1200, EXC_HV, PACA_EXGEN, 1
1774EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1775#else /* CONFIG_CBE_RAS */
1776EXC_REAL_NONE(0x1200, 0x100)
1777EXC_VIRT_NONE(0x5200, 0x100)
1778#endif
1779
1780
1781EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
1782	INT_HANDLER instruction_breakpoint, 0x1300, kvm=1
1783EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
1784EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
1785	INT_HANDLER instruction_breakpoint, 0x1300, virt=1
1786EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
1787INT_KVM_HANDLER instruction_breakpoint, 0x1300, EXC_STD, PACA_EXGEN, 1
1788EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1789
1790
1791EXC_REAL_NONE(0x1400, 0x100)
1792EXC_VIRT_NONE(0x5400, 0x100)
1793
1794EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1795	INT_HANDLER denorm_exception_hv, 0x1500, early=2, hsrr=EXC_HV
1796#ifdef CONFIG_PPC_DENORMALISATION
1797	mfspr	r10,SPRN_HSRR1
1798	andis.	r10,r10,(HSRR1_DENORM)@h /* denorm? */
1799	bne+	denorm_assist
1800#endif
1801	KVMTEST denorm_exception_hv, EXC_HV 0x1500
1802	INT_SAVE_SRR_AND_JUMP denorm_common, EXC_HV, 1
1803EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1804
1805#ifdef CONFIG_PPC_DENORMALISATION
1806EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1807	INT_HANDLER denorm_exception, 0x1500, 0, 2, 1, EXC_HV, PACA_EXGEN, 1, 0, 0, 0, 0
1808	mfspr	r10,SPRN_HSRR1
1809	andis.	r10,r10,(HSRR1_DENORM)@h /* denorm? */
1810	bne+	denorm_assist
1811	INT_VIRT_SAVE_SRR_AND_JUMP denorm_common, EXC_HV
1812EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1813#else
1814EXC_VIRT_NONE(0x5500, 0x100)
1815#endif
1816
1817INT_KVM_HANDLER denorm_exception_hv, 0x1500, EXC_HV, PACA_EXGEN, 0
1818
1819#ifdef CONFIG_PPC_DENORMALISATION
1820TRAMP_REAL_BEGIN(denorm_assist)
1821BEGIN_FTR_SECTION
1822/*
1823 * To denormalise we need to move a copy of the register to itself.
1824 * For POWER6 do that here for all FP regs.
1825 */
1826	mfmsr	r10
1827	ori	r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1828	xori	r10,r10,(MSR_FE0|MSR_FE1)
1829	mtmsrd	r10
1830	sync
1831
1832	.Lreg=0
1833	.rept 32
1834	fmr	.Lreg,.Lreg
1835	.Lreg=.Lreg+1
1836	.endr
1837
1838FTR_SECTION_ELSE
1839/*
1840 * To denormalise we need to move a copy of the register to itself.
1841 * For POWER7 do that here for the first 32 VSX registers only.
1842 */
1843	mfmsr	r10
1844	oris	r10,r10,MSR_VSX@h
1845	mtmsrd	r10
1846	sync
1847
1848	.Lreg=0
1849	.rept 32
1850	XVCPSGNDP(.Lreg,.Lreg,.Lreg)
1851	.Lreg=.Lreg+1
1852	.endr
1853
1854ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1855
1856BEGIN_FTR_SECTION
1857	b	denorm_done
1858END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1859/*
1860 * To denormalise we need to move a copy of the register to itself.
1861 * For POWER8 we need to do that for all 64 VSX registers
1862 */
1863	.Lreg=32
1864	.rept 32
1865	XVCPSGNDP(.Lreg,.Lreg,.Lreg)
1866	.Lreg=.Lreg+1
1867	.endr
1868
1869denorm_done:
1870	mfspr	r11,SPRN_HSRR0
1871	subi	r11,r11,4
1872	mtspr	SPRN_HSRR0,r11
1873	mtcrf	0x80,r9
1874	ld	r9,PACA_EXGEN+EX_R9(r13)
1875	RESTORE_PPR_PACA(PACA_EXGEN, r10)
1876BEGIN_FTR_SECTION
1877	ld	r10,PACA_EXGEN+EX_CFAR(r13)
1878	mtspr	SPRN_CFAR,r10
1879END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1880	ld	r10,PACA_EXGEN+EX_R10(r13)
1881	ld	r11,PACA_EXGEN+EX_R11(r13)
1882	ld	r12,PACA_EXGEN+EX_R12(r13)
1883	ld	r13,PACA_EXGEN+EX_R13(r13)
1884	HRFI_TO_UNKNOWN
1885	b	.
1886#endif
1887
1888EXC_COMMON(denorm_common, 0x1500, unknown_exception)
1889
1890
1891#ifdef CONFIG_CBE_RAS
1892EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
1893	INT_HANDLER cbe_maintenance, 0x1600, ool=1, hsrr=EXC_HV, kvm=1
1894EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
1895EXC_VIRT_NONE(0x5600, 0x100)
1896INT_KVM_HANDLER cbe_maintenance, 0x1600, EXC_HV, PACA_EXGEN, 1
1897EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1898#else /* CONFIG_CBE_RAS */
1899EXC_REAL_NONE(0x1600, 0x100)
1900EXC_VIRT_NONE(0x5600, 0x100)
1901#endif
1902
1903
1904EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
1905	INT_HANDLER altivec_assist, 0x1700, kvm=1
1906EXC_REAL_END(altivec_assist, 0x1700, 0x100)
1907EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
1908	INT_HANDLER altivec_assist, 0x1700, virt=1
1909EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
1910INT_KVM_HANDLER altivec_assist, 0x1700, EXC_STD, PACA_EXGEN, 0
1911#ifdef CONFIG_ALTIVEC
1912EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1913#else
1914EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1915#endif
1916
1917
1918#ifdef CONFIG_CBE_RAS
1919EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
1920	INT_HANDLER cbe_thermal, 0x1800, ool=1, hsrr=EXC_HV, kvm=1
1921EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
1922EXC_VIRT_NONE(0x5800, 0x100)
1923INT_KVM_HANDLER cbe_thermal, 0x1800, EXC_HV, PACA_EXGEN, 1
1924EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1925#else /* CONFIG_CBE_RAS */
1926EXC_REAL_NONE(0x1800, 0x100)
1927EXC_VIRT_NONE(0x5800, 0x100)
1928#endif
1929
1930
1931#ifdef CONFIG_PPC_WATCHDOG
1932
1933#define MASKED_DEC_HANDLER_LABEL 3f
1934
1935#define MASKED_DEC_HANDLER(_H)				\
19363: /* soft-nmi */					\
1937	std	r12,PACA_EXGEN+EX_R12(r13);		\
1938	GET_SCRATCH0(r10);				\
1939	std	r10,PACA_EXGEN+EX_R13(r13);		\
1940	INT_SAVE_SRR_AND_JUMP soft_nmi_common, _H, 1
1941
1942/*
1943 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
1944 * stack is one that is usable by maskable interrupts so long as MSR_EE
1945 * remains off. It is used for recovery when something has corrupted the
1946 * normal kernel stack, for example. The "soft NMI" must not use the process
1947 * stack because we want irq disabled sections to avoid touching the stack
1948 * at all (other than PMU interrupts), so use the emergency stack for this,
1949 * and run it entirely with interrupts hard disabled.
1950 */
1951EXC_COMMON_BEGIN(soft_nmi_common)
1952	mr	r10,r1
1953	ld	r1,PACAEMERGSP(r13)
1954	subi	r1,r1,INT_FRAME_SIZE
1955	INT_COMMON 0x900, PACA_EXGEN, 0, 1, 1, 0, 0
1956	bl	save_nvgprs
1957	addi	r3,r1,STACK_FRAME_OVERHEAD
1958	bl	soft_nmi_interrupt
1959	b	ret_from_except
1960
1961#else /* CONFIG_PPC_WATCHDOG */
1962#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1963#define MASKED_DEC_HANDLER(_H)
1964#endif /* CONFIG_PPC_WATCHDOG */
1965
1966/*
1967 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1968 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1969 * - If it was a doorbell we return immediately since doorbells are edge
1970 *   triggered and won't automatically refire.
1971 * - If it was a HMI we return immediately since we handled it in realmode
1972 *   and it won't refire.
1973 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
1974 * This is called with r10 containing the value to OR to the paca field.
1975 */
1976.macro MASKED_INTERRUPT hsrr
1977	.if \hsrr
1978masked_Hinterrupt:
1979	.else
1980masked_interrupt:
1981	.endif
1982	std	r11,PACA_EXGEN+EX_R11(r13)
1983	lbz	r11,PACAIRQHAPPENED(r13)
1984	or	r11,r11,r10
1985	stb	r11,PACAIRQHAPPENED(r13)
1986	cmpwi	r10,PACA_IRQ_DEC
1987	bne	1f
1988	lis	r10,0x7fff
1989	ori	r10,r10,0xffff
1990	mtspr	SPRN_DEC,r10
1991	b	MASKED_DEC_HANDLER_LABEL
19921:	andi.	r10,r10,PACA_IRQ_MUST_HARD_MASK
1993	beq	2f
1994	.if \hsrr
1995	mfspr	r10,SPRN_HSRR1
1996	xori	r10,r10,MSR_EE	/* clear MSR_EE */
1997	mtspr	SPRN_HSRR1,r10
1998	.else
1999	mfspr	r10,SPRN_SRR1
2000	xori	r10,r10,MSR_EE	/* clear MSR_EE */
2001	mtspr	SPRN_SRR1,r10
2002	.endif
2003	ori	r11,r11,PACA_IRQ_HARD_DIS
2004	stb	r11,PACAIRQHAPPENED(r13)
20052:	/* done */
2006	mtcrf	0x80,r9
2007	std	r1,PACAR1(r13)
2008	ld	r9,PACA_EXGEN+EX_R9(r13)
2009	ld	r10,PACA_EXGEN+EX_R10(r13)
2010	ld	r11,PACA_EXGEN+EX_R11(r13)
2011	/* returns to kernel where r13 must be set up, so don't restore it */
2012	.if \hsrr
2013	HRFI_TO_KERNEL
2014	.else
2015	RFI_TO_KERNEL
2016	.endif
2017	b	.
2018	MASKED_DEC_HANDLER(\hsrr\())
2019.endm
2020
2021TRAMP_REAL_BEGIN(stf_barrier_fallback)
2022	std	r9,PACA_EXRFI+EX_R9(r13)
2023	std	r10,PACA_EXRFI+EX_R10(r13)
2024	sync
2025	ld	r9,PACA_EXRFI+EX_R9(r13)
2026	ld	r10,PACA_EXRFI+EX_R10(r13)
2027	ori	31,31,0
2028	.rept 14
2029	b	1f
20301:
2031	.endr
2032	blr
2033
2034TRAMP_REAL_BEGIN(rfi_flush_fallback)
2035	SET_SCRATCH0(r13);
2036	GET_PACA(r13);
2037	std	r1,PACA_EXRFI+EX_R12(r13)
2038	ld	r1,PACAKSAVE(r13)
2039	std	r9,PACA_EXRFI+EX_R9(r13)
2040	std	r10,PACA_EXRFI+EX_R10(r13)
2041	std	r11,PACA_EXRFI+EX_R11(r13)
2042	mfctr	r9
2043	ld	r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2044	ld	r11,PACA_L1D_FLUSH_SIZE(r13)
2045	srdi	r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2046	mtctr	r11
2047	DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2048
2049	/* order ld/st prior to dcbt stop all streams with flushing */
2050	sync
2051
2052	/*
2053	 * The load adresses are at staggered offsets within cachelines,
2054	 * which suits some pipelines better (on others it should not
2055	 * hurt).
2056	 */
20571:
2058	ld	r11,(0x80 + 8)*0(r10)
2059	ld	r11,(0x80 + 8)*1(r10)
2060	ld	r11,(0x80 + 8)*2(r10)
2061	ld	r11,(0x80 + 8)*3(r10)
2062	ld	r11,(0x80 + 8)*4(r10)
2063	ld	r11,(0x80 + 8)*5(r10)
2064	ld	r11,(0x80 + 8)*6(r10)
2065	ld	r11,(0x80 + 8)*7(r10)
2066	addi	r10,r10,0x80*8
2067	bdnz	1b
2068
2069	mtctr	r9
2070	ld	r9,PACA_EXRFI+EX_R9(r13)
2071	ld	r10,PACA_EXRFI+EX_R10(r13)
2072	ld	r11,PACA_EXRFI+EX_R11(r13)
2073	ld	r1,PACA_EXRFI+EX_R12(r13)
2074	GET_SCRATCH0(r13);
2075	rfid
2076
2077TRAMP_REAL_BEGIN(hrfi_flush_fallback)
2078	SET_SCRATCH0(r13);
2079	GET_PACA(r13);
2080	std	r1,PACA_EXRFI+EX_R12(r13)
2081	ld	r1,PACAKSAVE(r13)
2082	std	r9,PACA_EXRFI+EX_R9(r13)
2083	std	r10,PACA_EXRFI+EX_R10(r13)
2084	std	r11,PACA_EXRFI+EX_R11(r13)
2085	mfctr	r9
2086	ld	r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2087	ld	r11,PACA_L1D_FLUSH_SIZE(r13)
2088	srdi	r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2089	mtctr	r11
2090	DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2091
2092	/* order ld/st prior to dcbt stop all streams with flushing */
2093	sync
2094
2095	/*
2096	 * The load adresses are at staggered offsets within cachelines,
2097	 * which suits some pipelines better (on others it should not
2098	 * hurt).
2099	 */
21001:
2101	ld	r11,(0x80 + 8)*0(r10)
2102	ld	r11,(0x80 + 8)*1(r10)
2103	ld	r11,(0x80 + 8)*2(r10)
2104	ld	r11,(0x80 + 8)*3(r10)
2105	ld	r11,(0x80 + 8)*4(r10)
2106	ld	r11,(0x80 + 8)*5(r10)
2107	ld	r11,(0x80 + 8)*6(r10)
2108	ld	r11,(0x80 + 8)*7(r10)
2109	addi	r10,r10,0x80*8
2110	bdnz	1b
2111
2112	mtctr	r9
2113	ld	r9,PACA_EXRFI+EX_R9(r13)
2114	ld	r10,PACA_EXRFI+EX_R10(r13)
2115	ld	r11,PACA_EXRFI+EX_R11(r13)
2116	ld	r1,PACA_EXRFI+EX_R12(r13)
2117	GET_SCRATCH0(r13);
2118	hrfid
2119
2120/*
2121 * Real mode exceptions actually use this too, but alternate
2122 * instruction code patches (which end up in the common .text area)
2123 * cannot reach these if they are put there.
2124 */
2125USE_FIXED_SECTION(virt_trampolines)
2126	MASKED_INTERRUPT EXC_STD
2127	MASKED_INTERRUPT EXC_HV
2128
2129#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2130TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
2131	/*
2132	 * Here all GPRs are unchanged from when the interrupt happened
2133	 * except for r13, which is saved in SPRG_SCRATCH0.
2134	 */
2135	mfspr	r13, SPRN_SRR0
2136	addi	r13, r13, 4
2137	mtspr	SPRN_SRR0, r13
2138	GET_SCRATCH0(r13)
2139	RFI_TO_KERNEL
2140	b	.
2141
2142TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
2143	/*
2144	 * Here all GPRs are unchanged from when the interrupt happened
2145	 * except for r13, which is saved in SPRG_SCRATCH0.
2146	 */
2147	mfspr	r13, SPRN_HSRR0
2148	addi	r13, r13, 4
2149	mtspr	SPRN_HSRR0, r13
2150	GET_SCRATCH0(r13)
2151	HRFI_TO_KERNEL
2152	b	.
2153#endif
2154
2155/*
2156 * Ensure that any handlers that get invoked from the exception prologs
2157 * above are below the first 64KB (0x10000) of the kernel image because
2158 * the prologs assemble the addresses of these handlers using the
2159 * LOAD_HANDLER macro, which uses an ori instruction.
2160 */
2161
2162/*** Common interrupt handlers ***/
2163
2164
2165	/*
2166	 * Relocation-on interrupts: A subset of the interrupts can be delivered
2167	 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
2168	 * it.  Addresses are the same as the original interrupt addresses, but
2169	 * offset by 0xc000000000004000.
2170	 * It's impossible to receive interrupts below 0x300 via this mechanism.
2171	 * KVM: None of these traps are from the guest ; anything that escalated
2172	 * to HV=1 from HV=0 is delivered via real mode handlers.
2173	 */
2174
2175	/*
2176	 * This uses the standard macro, since the original 0x300 vector
2177	 * only has extra guff for STAB-based processors -- which never
2178	 * come here.
2179	 */
2180
2181EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
2182	b	__ppc64_runlatch_on
2183
2184USE_FIXED_SECTION(virt_trampolines)
2185	/*
2186	 * The __end_interrupts marker must be past the out-of-line (OOL)
2187	 * handlers, so that they are copied to real address 0x100 when running
2188	 * a relocatable kernel. This ensures they can be reached from the short
2189	 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
2190	 * directly, without using LOAD_HANDLER().
2191	 */
2192	.align	7
2193	.globl	__end_interrupts
2194__end_interrupts:
2195DEFINE_FIXED_SYMBOL(__end_interrupts)
2196
2197#ifdef CONFIG_PPC_970_NAP
2198	/*
2199	 * Called by exception entry code if _TLF_NAPPING was set, this clears
2200	 * the NAPPING flag, and redirects the exception exit to
2201	 * power4_fixup_nap_return.
2202	 */
2203	.globl power4_fixup_nap
2204EXC_COMMON_BEGIN(power4_fixup_nap)
2205	andc	r9,r9,r10
2206	std	r9,TI_LOCAL_FLAGS(r11)
2207	LOAD_REG_ADDR(r10, power4_idle_nap_return)
2208	std	r10,_NIP(r1)
2209	blr
2210
2211power4_idle_nap_return:
2212	blr
2213#endif
2214
2215CLOSE_FIXED_SECTION(real_vectors);
2216CLOSE_FIXED_SECTION(real_trampolines);
2217CLOSE_FIXED_SECTION(virt_vectors);
2218CLOSE_FIXED_SECTION(virt_trampolines);
2219
2220USE_TEXT_SECTION()
2221
2222/* MSR[RI] should be clear because this uses SRR[01] */
2223enable_machine_check:
2224	mflr	r0
2225	bcl	20,31,$+4
22260:	mflr	r3
2227	addi	r3,r3,(1f - 0b)
2228	mtspr	SPRN_SRR0,r3
2229	mfmsr	r3
2230	ori	r3,r3,MSR_ME
2231	mtspr	SPRN_SRR1,r3
2232	RFI_TO_KERNEL
22331:	mtlr	r0
2234	blr
2235
2236/* MSR[RI] should be clear because this uses SRR[01] */
2237disable_machine_check:
2238	mflr	r0
2239	bcl	20,31,$+4
22400:	mflr	r3
2241	addi	r3,r3,(1f - 0b)
2242	mtspr	SPRN_SRR0,r3
2243	mfmsr	r3
2244	li	r4,MSR_ME
2245	andc	r3,r3,r4
2246	mtspr	SPRN_SRR1,r3
2247	RFI_TO_KERNEL
22481:	mtlr	r0
2249	blr
2250
2251/*
2252 * Hash table stuff
2253 */
2254	.balign	IFETCH_ALIGN_BYTES
2255do_hash_page:
2256#ifdef CONFIG_PPC_BOOK3S_64
2257	lis	r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
2258	ori	r0,r0,DSISR_BAD_FAULT_64S@l
2259	and.	r0,r5,r0		/* weird error? */
2260	bne-	handle_page_fault	/* if not, try to insert a HPTE */
2261	ld	r11, PACA_THREAD_INFO(r13)
2262	lwz	r0,TI_PREEMPT(r11)	/* If we're in an "NMI" */
2263	andis.	r0,r0,NMI_MASK@h	/* (i.e. an irq when soft-disabled) */
2264	bne	77f			/* then don't call hash_page now */
2265
2266	/*
2267	 * r3 contains the trap number
2268	 * r4 contains the faulting address
2269	 * r5 contains dsisr
2270	 * r6 msr
2271	 *
2272	 * at return r3 = 0 for success, 1 for page fault, negative for error
2273	 */
2274	bl	__hash_page		/* build HPTE if possible */
2275        cmpdi	r3,0			/* see if __hash_page succeeded */
2276
2277	/* Success */
2278	beq	fast_exc_return_irq	/* Return from exception on success */
2279
2280	/* Error */
2281	blt-	13f
2282
2283	/* Reload DAR/DSISR into r4/r5 for the DABR check below */
2284	ld	r4,_DAR(r1)
2285	ld      r5,_DSISR(r1)
2286#endif /* CONFIG_PPC_BOOK3S_64 */
2287
2288/* Here we have a page fault that hash_page can't handle. */
2289handle_page_fault:
229011:	andis.  r0,r5,DSISR_DABRMATCH@h
2291	bne-    handle_dabr_fault
2292	addi	r3,r1,STACK_FRAME_OVERHEAD
2293	bl	do_page_fault
2294	cmpdi	r3,0
2295	beq+	ret_from_except_lite
2296	bl	save_nvgprs
2297	mr	r5,r3
2298	addi	r3,r1,STACK_FRAME_OVERHEAD
2299	ld	r4,_DAR(r1)
2300	bl	bad_page_fault
2301	b	ret_from_except
2302
2303/* We have a data breakpoint exception - handle it */
2304handle_dabr_fault:
2305	bl	save_nvgprs
2306	ld      r4,_DAR(r1)
2307	ld      r5,_DSISR(r1)
2308	addi    r3,r1,STACK_FRAME_OVERHEAD
2309	bl      do_break
2310	/*
2311	 * do_break() may have changed the NV GPRS while handling a breakpoint.
2312	 * If so, we need to restore them with their updated values. Don't use
2313	 * ret_from_except_lite here.
2314	 */
2315	b       ret_from_except
2316
2317
2318#ifdef CONFIG_PPC_BOOK3S_64
2319/* We have a page fault that hash_page could handle but HV refused
2320 * the PTE insertion
2321 */
232213:	bl	save_nvgprs
2323	mr	r5,r3
2324	addi	r3,r1,STACK_FRAME_OVERHEAD
2325	ld	r4,_DAR(r1)
2326	bl	low_hash_fault
2327	b	ret_from_except
2328#endif
2329
2330/*
2331 * We come here as a result of a DSI at a point where we don't want
2332 * to call hash_page, such as when we are accessing memory (possibly
2333 * user memory) inside a PMU interrupt that occurred while interrupts
2334 * were soft-disabled.  We want to invoke the exception handler for
2335 * the access, or panic if there isn't a handler.
2336 */
233777:	bl	save_nvgprs
2338	addi	r3,r1,STACK_FRAME_OVERHEAD
2339	li	r5,SIGSEGV
2340	bl	bad_page_fault
2341	b	ret_from_except
2342
2343/*
2344 * When doorbell is triggered from system reset wakeup, the message is
2345 * not cleared, so it would fire again when EE is enabled.
2346 *
2347 * When coming from local_irq_enable, there may be the same problem if
2348 * we were hard disabled.
2349 *
2350 * Execute msgclr to clear pending exceptions before handling it.
2351 */
2352h_doorbell_common_msgclr:
2353	LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
2354	PPC_MSGCLR(3)
2355	b 	h_doorbell_common
2356
2357doorbell_super_common_msgclr:
2358	LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
2359	PPC_MSGCLRP(3)
2360	b 	doorbell_super_common
2361
2362/*
2363 * Called from arch_local_irq_enable when an interrupt needs
2364 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
2365 * which kind of interrupt. MSR:EE is already off. We generate a
2366 * stackframe like if a real interrupt had happened.
2367 *
2368 * Note: While MSR:EE is off, we need to make sure that _MSR
2369 * in the generated frame has EE set to 1 or the exception
2370 * handler will not properly re-enable them.
2371 *
2372 * Note that we don't specify LR as the NIP (return address) for
2373 * the interrupt because that would unbalance the return branch
2374 * predictor.
2375 */
2376_GLOBAL(__replay_interrupt)
2377	/* We are going to jump to the exception common code which
2378	 * will retrieve various register values from the PACA which
2379	 * we don't give a damn about, so we don't bother storing them.
2380	 */
2381	mfmsr	r12
2382	LOAD_REG_ADDR(r11, replay_interrupt_return)
2383	mfcr	r9
2384	ori	r12,r12,MSR_EE
2385	cmpwi	r3,0x900
2386	beq	decrementer_common
2387	cmpwi	r3,0x500
2388BEGIN_FTR_SECTION
2389	beq	h_virt_irq_common
2390FTR_SECTION_ELSE
2391	beq	hardware_interrupt_common
2392ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
2393	cmpwi	r3,0xf00
2394	beq	performance_monitor_common
2395BEGIN_FTR_SECTION
2396	cmpwi	r3,0xa00
2397	beq	h_doorbell_common_msgclr
2398	cmpwi	r3,0xe60
2399	beq	hmi_exception_common
2400FTR_SECTION_ELSE
2401	cmpwi	r3,0xa00
2402	beq	doorbell_super_common_msgclr
2403ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
2404replay_interrupt_return:
2405	blr
2406
2407_ASM_NOKPROBE_SYMBOL(__replay_interrupt)
2408