1/* 2 * This file contains the 64-bit "server" PowerPC variant 3 * of the low level exception handling including exception 4 * vectors, exception return, part of the slb and stab 5 * handling and other fixed offset specific things. 6 * 7 * This file is meant to be #included from head_64.S due to 8 * position dependent assembly. 9 * 10 * Most of this originates from head_64.S and thus has the same 11 * copyright history. 12 * 13 */ 14 15#include <asm/hw_irq.h> 16#include <asm/exception-64s.h> 17#include <asm/ptrace.h> 18#include <asm/cpuidle.h> 19#include <asm/head-64.h> 20 21/* 22 * There are a few constraints to be concerned with. 23 * - Real mode exceptions code/data must be located at their physical location. 24 * - Virtual mode exceptions must be mapped at their 0xc000... location. 25 * - Fixed location code must not call directly beyond the __end_interrupts 26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 27 * must be used. 28 * - LOAD_HANDLER targets must be within first 64K of physical 0 / 29 * virtual 0xc00... 30 * - Conditional branch targets must be within +/-32K of caller. 31 * 32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 33 * therefore don't have to run in physically located code or rfid to 34 * virtual mode kernel code. However on relocatable kernels they do have 35 * to branch to KERNELBASE offset because the rest of the kernel (outside 36 * the exception vectors) may be located elsewhere. 37 * 38 * Virtual exceptions correspond with physical, except their entry points 39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000 40 * offset applied. Virtual exceptions are enabled with the Alternate 41 * Interrupt Location (AIL) bit set in the LPCR. However this does not 42 * guarantee they will be delivered virtually. Some conditions (see the ISA) 43 * cause exceptions to be delivered in real mode. 44 * 45 * It's impossible to receive interrupts below 0x300 via AIL. 46 * 47 * KVM: None of the virtual exceptions are from the guest. Anything that 48 * escalated to HV=1 from HV=0 is delivered via real mode handlers. 49 * 50 * 51 * We layout physical memory as follows: 52 * 0x0000 - 0x00ff : Secondary processor spin code 53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 54 * 0x1900 - 0x3fff : Real mode trampolines 55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 56 * 0x5900 - 0x6fff : Relon mode trampolines 57 * 0x7000 - 0x7fff : FWNMI data area 58 * 0x8000 - .... : Common interrupt handlers, remaining early 59 * setup code, rest of kernel. 60 * 61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 63 * vectors there. 64 */ 65OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 66OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 67OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 68OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 69#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 70/* 71 * Data area reserved for FWNMI option. 72 * This address (0x7000) is fixed by the RPA. 73 * pseries and powernv need to keep the whole page from 74 * 0x7000 to 0x8000 free for use by the firmware 75 */ 76ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 77OPEN_TEXT_SECTION(0x8000) 78#else 79OPEN_TEXT_SECTION(0x7000) 80#endif 81 82USE_FIXED_SECTION(real_vectors) 83 84/* 85 * This is the start of the interrupt handlers for pSeries 86 * This code runs with relocation off. 87 * Code from here to __end_interrupts gets copied down to real 88 * address 0x100 when we are running a relocatable kernel. 89 * Therefore any relative branches in this section must only 90 * branch to labels in this section. 91 */ 92 .globl __start_interrupts 93__start_interrupts: 94 95/* No virt vectors corresponding with 0x0..0x100 */ 96EXC_VIRT_NONE(0x4000, 0x100) 97 98 99#ifdef CONFIG_PPC_P7_NAP 100 /* 101 * If running native on arch 2.06 or later, check if we are waking up 102 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 103 * bits 46:47. A non-0 value indicates that we are coming from a power 104 * saving state. The idle wakeup handler initially runs in real mode, 105 * but we branch to the 0xc000... address so we can turn on relocation 106 * with mtmsr. 107 */ 108#define IDLETEST(n) \ 109 BEGIN_FTR_SECTION ; \ 110 mfspr r10,SPRN_SRR1 ; \ 111 rlwinm. r10,r10,47-31,30,31 ; \ 112 beq- 1f ; \ 113 cmpwi cr3,r10,2 ; \ 114 BRANCH_TO_C000(r10, system_reset_idle_common) ; \ 1151: \ 116 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 117#else 118#define IDLETEST NOTEST 119#endif 120 121EXC_REAL_BEGIN(system_reset, 0x100, 0x100) 122 SET_SCRATCH0(r13) 123 /* 124 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 125 * being used, so a nested NMI exception would corrupt it. 126 */ 127 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD, 128 IDLETEST, 0x100) 129 130EXC_REAL_END(system_reset, 0x100, 0x100) 131EXC_VIRT_NONE(0x4100, 0x100) 132 133#ifdef CONFIG_PPC_P7_NAP 134EXC_COMMON_BEGIN(system_reset_idle_common) 135 mfspr r12,SPRN_SRR1 136 b pnv_powersave_wakeup 137#endif 138 139EXC_COMMON_BEGIN(system_reset_common) 140 /* 141 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 142 * to recover, but nested NMI will notice in_nmi and not recover 143 * because of the use of the NMI stack. in_nmi reentrancy is tested in 144 * system_reset_exception. 145 */ 146 lhz r10,PACA_IN_NMI(r13) 147 addi r10,r10,1 148 sth r10,PACA_IN_NMI(r13) 149 li r10,MSR_RI 150 mtmsrd r10,1 151 152 mr r10,r1 153 ld r1,PACA_NMI_EMERG_SP(r13) 154 subi r1,r1,INT_FRAME_SIZE 155 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, 156 system_reset, system_reset_exception, 157 ADD_NVGPRS;ADD_RECONCILE) 158 159 /* 160 * The stack is no longer in use, decrement in_nmi. 161 */ 162 lhz r10,PACA_IN_NMI(r13) 163 subi r10,r10,1 164 sth r10,PACA_IN_NMI(r13) 165 166 b ret_from_except 167 168#ifdef CONFIG_PPC_PSERIES 169/* 170 * Vectors for the FWNMI option. Share common code. 171 */ 172TRAMP_REAL_BEGIN(system_reset_fwnmi) 173 SET_SCRATCH0(r13) /* save r13 */ 174 /* See comment at system_reset exception */ 175 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, 176 EXC_STD, NOTEST, 0x100) 177#endif /* CONFIG_PPC_PSERIES */ 178 179 180EXC_REAL_BEGIN(machine_check, 0x200, 0x100) 181 /* This is moved out of line as it can be patched by FW, but 182 * some code path might still want to branch into the original 183 * vector 184 */ 185 SET_SCRATCH0(r13) /* save r13 */ 186 EXCEPTION_PROLOG_0(PACA_EXMC) 187BEGIN_FTR_SECTION 188 b machine_check_powernv_early 189FTR_SECTION_ELSE 190 b machine_check_pSeries_0 191ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 192EXC_REAL_END(machine_check, 0x200, 0x100) 193EXC_VIRT_NONE(0x4200, 0x100) 194TRAMP_REAL_BEGIN(machine_check_powernv_early) 195BEGIN_FTR_SECTION 196 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) 197 /* 198 * Register contents: 199 * R13 = PACA 200 * R9 = CR 201 * Original R9 to R13 is saved on PACA_EXMC 202 * 203 * Switch to mc_emergency stack and handle re-entrancy (we limit 204 * the nested MCE upto level 4 to avoid stack overflow). 205 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 206 * 207 * We use paca->in_mce to check whether this is the first entry or 208 * nested machine check. We increment paca->in_mce to track nested 209 * machine checks. 210 * 211 * If this is the first entry then set stack pointer to 212 * paca->mc_emergency_sp, otherwise r1 is already pointing to 213 * stack frame on mc_emergency stack. 214 * 215 * NOTE: We are here with MSR_ME=0 (off), which means we risk a 216 * checkstop if we get another machine check exception before we do 217 * rfid with MSR_ME=1. 218 * 219 * This interrupt can wake directly from idle. If that is the case, 220 * the machine check is handled then the idle wakeup code is called 221 * to restore state. In that case, the POWER9 DD1 idle PACA workaround 222 * is not applied in the early machine check code, which will cause 223 * bugs. 224 */ 225 mr r11,r1 /* Save r1 */ 226 lhz r10,PACA_IN_MCE(r13) 227 cmpwi r10,0 /* Are we in nested machine check */ 228 bne 0f /* Yes, we are. */ 229 /* First machine check entry */ 230 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 2310: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 232 addi r10,r10,1 /* increment paca->in_mce */ 233 sth r10,PACA_IN_MCE(r13) 234 /* Limit nested MCE to level 4 to avoid stack overflow */ 235 cmpwi r10,4 236 bgt 2f /* Check if we hit limit of 4 */ 237 std r11,GPR1(r1) /* Save r1 on the stack. */ 238 std r11,0(r1) /* make stack chain pointer */ 239 mfspr r11,SPRN_SRR0 /* Save SRR0 */ 240 std r11,_NIP(r1) 241 mfspr r11,SPRN_SRR1 /* Save SRR1 */ 242 std r11,_MSR(r1) 243 mfspr r11,SPRN_DAR /* Save DAR */ 244 std r11,_DAR(r1) 245 mfspr r11,SPRN_DSISR /* Save DSISR */ 246 std r11,_DSISR(r1) 247 std r9,_CCR(r1) /* Save CR in stackframe */ 248 /* Save r9 through r13 from EXMC save area to stack frame. */ 249 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 250 mfmsr r11 /* get MSR value */ 251 ori r11,r11,MSR_ME /* turn on ME bit */ 252 ori r11,r11,MSR_RI /* turn on RI bit */ 253 LOAD_HANDLER(r12, machine_check_handle_early) 2541: mtspr SPRN_SRR0,r12 255 mtspr SPRN_SRR1,r11 256 rfid 257 b . /* prevent speculative execution */ 2582: 259 /* Stack overflow. Stay on emergency stack and panic. 260 * Keep the ME bit off while panic-ing, so that if we hit 261 * another machine check we checkstop. 262 */ 263 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 264 ld r11,PACAKMSR(r13) 265 LOAD_HANDLER(r12, unrecover_mce) 266 li r10,MSR_ME 267 andc r11,r11,r10 /* Turn off MSR_ME */ 268 b 1b 269 b . /* prevent speculative execution */ 270END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 271 272TRAMP_REAL_BEGIN(machine_check_pSeries) 273 .globl machine_check_fwnmi 274machine_check_fwnmi: 275 SET_SCRATCH0(r13) /* save r13 */ 276 EXCEPTION_PROLOG_0(PACA_EXMC) 277machine_check_pSeries_0: 278 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) 279 /* 280 * MSR_RI is not enabled, because PACA_EXMC is being used, so a 281 * nested machine check corrupts it. machine_check_common enables 282 * MSR_RI. 283 */ 284 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD) 285 286TRAMP_KVM_SKIP(PACA_EXMC, 0x200) 287 288EXC_COMMON_BEGIN(machine_check_common) 289 /* 290 * Machine check is different because we use a different 291 * save area: PACA_EXMC instead of PACA_EXGEN. 292 */ 293 mfspr r10,SPRN_DAR 294 std r10,PACA_EXMC+EX_DAR(r13) 295 mfspr r10,SPRN_DSISR 296 stw r10,PACA_EXMC+EX_DSISR(r13) 297 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 298 FINISH_NAP 299 RECONCILE_IRQ_STATE(r10, r11) 300 ld r3,PACA_EXMC+EX_DAR(r13) 301 lwz r4,PACA_EXMC+EX_DSISR(r13) 302 /* Enable MSR_RI when finished with PACA_EXMC */ 303 li r10,MSR_RI 304 mtmsrd r10,1 305 std r3,_DAR(r1) 306 std r4,_DSISR(r1) 307 bl save_nvgprs 308 addi r3,r1,STACK_FRAME_OVERHEAD 309 bl machine_check_exception 310 b ret_from_except 311 312#define MACHINE_CHECK_HANDLER_WINDUP \ 313 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 314 li r0,MSR_RI; \ 315 mfmsr r9; /* get MSR value */ \ 316 andc r9,r9,r0; \ 317 mtmsrd r9,1; /* Clear MSR_RI */ \ 318 /* Move original SRR0 and SRR1 into the respective regs */ \ 319 ld r9,_MSR(r1); \ 320 mtspr SPRN_SRR1,r9; \ 321 ld r3,_NIP(r1); \ 322 mtspr SPRN_SRR0,r3; \ 323 ld r9,_CTR(r1); \ 324 mtctr r9; \ 325 ld r9,_XER(r1); \ 326 mtxer r9; \ 327 ld r9,_LINK(r1); \ 328 mtlr r9; \ 329 REST_GPR(0, r1); \ 330 REST_8GPRS(2, r1); \ 331 REST_GPR(10, r1); \ 332 ld r11,_CCR(r1); \ 333 mtcr r11; \ 334 /* Decrement paca->in_mce. */ \ 335 lhz r12,PACA_IN_MCE(r13); \ 336 subi r12,r12,1; \ 337 sth r12,PACA_IN_MCE(r13); \ 338 REST_GPR(11, r1); \ 339 REST_2GPRS(12, r1); \ 340 /* restore original r1. */ \ 341 ld r1,GPR1(r1) 342 343#ifdef CONFIG_PPC_P7_NAP 344/* 345 * This is an idle wakeup. Low level machine check has already been 346 * done. Queue the event then call the idle code to do the wake up. 347 */ 348EXC_COMMON_BEGIN(machine_check_idle_common) 349 bl machine_check_queue_event 350 351 /* 352 * We have not used any non-volatile GPRs here, and as a rule 353 * most exception code including machine check does not. 354 * Therefore PACA_NAPSTATELOST does not need to be set. Idle 355 * wakeup will restore volatile registers. 356 * 357 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. 358 * 359 * Then decrement MCE nesting after finishing with the stack. 360 */ 361 ld r3,_MSR(r1) 362 363 lhz r11,PACA_IN_MCE(r13) 364 subi r11,r11,1 365 sth r11,PACA_IN_MCE(r13) 366 367 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ 368 /* Recoverability could be improved by reducing the use of SRR1. */ 369 li r11,0 370 mtmsrd r11,1 371 372 b pnv_powersave_wakeup_mce 373#endif 374 /* 375 * Handle machine check early in real mode. We come here with 376 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 377 */ 378EXC_COMMON_BEGIN(machine_check_handle_early) 379 std r0,GPR0(r1) /* Save r0 */ 380 EXCEPTION_PROLOG_COMMON_3(0x200) 381 bl save_nvgprs 382 addi r3,r1,STACK_FRAME_OVERHEAD 383 bl machine_check_early 384 std r3,RESULT(r1) /* Save result */ 385 ld r12,_MSR(r1) 386 387#ifdef CONFIG_PPC_P7_NAP 388 /* 389 * Check if thread was in power saving mode. We come here when any 390 * of the following is true: 391 * a. thread wasn't in power saving mode 392 * b. thread was in power saving mode with no state loss, 393 * supervisor state loss or hypervisor state loss. 394 * 395 * Go back to nap/sleep/winkle mode again if (b) is true. 396 */ 397 BEGIN_FTR_SECTION 398 rlwinm. r11,r12,47-31,30,31 399 bne machine_check_idle_common 400 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 401#endif 402 403 /* 404 * Check if we are coming from hypervisor userspace. If yes then we 405 * continue in host kernel in V mode to deliver the MC event. 406 */ 407 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 408 beq 5f 409 andi. r11,r12,MSR_PR /* See if coming from user. */ 410 bne 9f /* continue in V mode if we are. */ 411 4125: 413#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 414 /* 415 * We are coming from kernel context. Check if we are coming from 416 * guest. if yes, then we can continue. We will fall through 417 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 418 */ 419 lbz r11,HSTATE_IN_GUEST(r13) 420 cmpwi r11,0 /* Check if coming from guest */ 421 bne 9f /* continue if we are. */ 422#endif 423 /* 424 * At this point we are not sure about what context we come from. 425 * Queue up the MCE event and return from the interrupt. 426 * But before that, check if this is an un-recoverable exception. 427 * If yes, then stay on emergency stack and panic. 428 */ 429 andi. r11,r12,MSR_RI 430 bne 2f 4311: mfspr r11,SPRN_SRR0 432 LOAD_HANDLER(r10,unrecover_mce) 433 mtspr SPRN_SRR0,r10 434 ld r10,PACAKMSR(r13) 435 /* 436 * We are going down. But there are chances that we might get hit by 437 * another MCE during panic path and we may run into unstable state 438 * with no way out. Hence, turn ME bit off while going down, so that 439 * when another MCE is hit during panic path, system will checkstop 440 * and hypervisor will get restarted cleanly by SP. 441 */ 442 li r3,MSR_ME 443 andc r10,r10,r3 /* Turn off MSR_ME */ 444 mtspr SPRN_SRR1,r10 445 rfid 446 b . 4472: 448 /* 449 * Check if we have successfully handled/recovered from error, if not 450 * then stay on emergency stack and panic. 451 */ 452 ld r3,RESULT(r1) /* Load result */ 453 cmpdi r3,0 /* see if we handled MCE successfully */ 454 455 beq 1b /* if !handled then panic */ 456 /* 457 * Return from MC interrupt. 458 * Queue up the MCE event so that we can log it later, while 459 * returning from kernel or opal call. 460 */ 461 bl machine_check_queue_event 462 MACHINE_CHECK_HANDLER_WINDUP 463 rfid 4649: 465 /* Deliver the machine check to host kernel in V mode. */ 466 MACHINE_CHECK_HANDLER_WINDUP 467 b machine_check_pSeries 468 469EXC_COMMON_BEGIN(unrecover_mce) 470 /* Invoke machine_check_exception to print MCE event and panic. */ 471 addi r3,r1,STACK_FRAME_OVERHEAD 472 bl machine_check_exception 473 /* 474 * We will not reach here. Even if we did, there is no way out. Call 475 * unrecoverable_exception and die. 476 */ 4771: addi r3,r1,STACK_FRAME_OVERHEAD 478 bl unrecoverable_exception 479 b 1b 480 481 482EXC_REAL(data_access, 0x300, 0x80) 483EXC_VIRT(data_access, 0x4300, 0x80, 0x300) 484TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 485 486EXC_COMMON_BEGIN(data_access_common) 487 /* 488 * Here r13 points to the paca, r9 contains the saved CR, 489 * SRR0 and SRR1 are saved in r11 and r12, 490 * r9 - r13 are saved in paca->exgen. 491 */ 492 mfspr r10,SPRN_DAR 493 std r10,PACA_EXGEN+EX_DAR(r13) 494 mfspr r10,SPRN_DSISR 495 stw r10,PACA_EXGEN+EX_DSISR(r13) 496 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 497 RECONCILE_IRQ_STATE(r10, r11) 498 ld r12,_MSR(r1) 499 ld r3,PACA_EXGEN+EX_DAR(r13) 500 lwz r4,PACA_EXGEN+EX_DSISR(r13) 501 li r5,0x300 502 std r3,_DAR(r1) 503 std r4,_DSISR(r1) 504BEGIN_MMU_FTR_SECTION 505 b do_hash_page /* Try to handle as hpte fault */ 506MMU_FTR_SECTION_ELSE 507 b handle_page_fault 508ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 509 510 511EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 512 SET_SCRATCH0(r13) 513 EXCEPTION_PROLOG_0(PACA_EXSLB) 514 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) 515 mr r12,r3 /* save r3 */ 516 mfspr r3,SPRN_DAR 517 mfspr r11,SPRN_SRR1 518 crset 4*cr6+eq 519 BRANCH_TO_COMMON(r10, slb_miss_common) 520EXC_REAL_END(data_access_slb, 0x380, 0x80) 521 522EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 523 SET_SCRATCH0(r13) 524 EXCEPTION_PROLOG_0(PACA_EXSLB) 525 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) 526 mr r12,r3 /* save r3 */ 527 mfspr r3,SPRN_DAR 528 mfspr r11,SPRN_SRR1 529 crset 4*cr6+eq 530 BRANCH_TO_COMMON(r10, slb_miss_common) 531EXC_VIRT_END(data_access_slb, 0x4380, 0x80) 532TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 533 534 535EXC_REAL(instruction_access, 0x400, 0x80) 536EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 537TRAMP_KVM(PACA_EXGEN, 0x400) 538 539EXC_COMMON_BEGIN(instruction_access_common) 540 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 541 RECONCILE_IRQ_STATE(r10, r11) 542 ld r12,_MSR(r1) 543 ld r3,_NIP(r1) 544 andis. r4,r12,0x5820 545 li r5,0x400 546 std r3,_DAR(r1) 547 std r4,_DSISR(r1) 548BEGIN_MMU_FTR_SECTION 549 b do_hash_page /* Try to handle as hpte fault */ 550MMU_FTR_SECTION_ELSE 551 b handle_page_fault 552ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 553 554 555EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) 556 SET_SCRATCH0(r13) 557 EXCEPTION_PROLOG_0(PACA_EXSLB) 558 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) 559 mr r12,r3 /* save r3 */ 560 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 561 mfspr r11,SPRN_SRR1 562 crclr 4*cr6+eq 563 BRANCH_TO_COMMON(r10, slb_miss_common) 564EXC_REAL_END(instruction_access_slb, 0x480, 0x80) 565 566EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) 567 SET_SCRATCH0(r13) 568 EXCEPTION_PROLOG_0(PACA_EXSLB) 569 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) 570 mr r12,r3 /* save r3 */ 571 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 572 mfspr r11,SPRN_SRR1 573 crclr 4*cr6+eq 574 BRANCH_TO_COMMON(r10, slb_miss_common) 575EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) 576TRAMP_KVM(PACA_EXSLB, 0x480) 577 578 579/* 580 * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as 581 * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled. 582 */ 583EXC_COMMON_BEGIN(slb_miss_common) 584 /* 585 * r13 points to the PACA, r9 contains the saved CR, 586 * r12 contains the saved r3, 587 * r11 contain the saved SRR1, SRR0 is still ready for return 588 * r3 has the faulting address 589 * r9 - r13 are saved in paca->exslb. 590 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss 591 * We assume we aren't going to take any exceptions during this 592 * procedure. 593 */ 594 mflr r10 595 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 596 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 597 598 /* 599 * Test MSR_RI before calling slb_allocate_realmode, because the 600 * MSR in r11 gets clobbered. However we still want to allocate 601 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in 602 * recursive SLB faults. So use cr5 for this, which is preserved. 603 */ 604 andi. r11,r11,MSR_RI /* check for unrecoverable exception */ 605 cmpdi cr5,r11,MSR_RI 606 607 crset 4*cr0+eq 608#ifdef CONFIG_PPC_STD_MMU_64 609BEGIN_MMU_FTR_SECTION 610 bl slb_allocate 611END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) 612#endif 613 614 ld r10,PACA_EXSLB+EX_LR(r13) 615 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 616 mtlr r10 617 618 beq- 8f /* if bad address, make full stack frame */ 619 620 bne- cr5,2f /* if unrecoverable exception, oops */ 621 622 /* All done -- return from exception. */ 623 624.machine push 625.machine "power4" 626 mtcrf 0x80,r9 627 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */ 628 mtcrf 0x02,r9 /* I/D indication is in cr6 */ 629 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 630.machine pop 631 632 RESTORE_CTR(r9, PACA_EXSLB) 633 RESTORE_PPR_PACA(PACA_EXSLB, r9) 634 mr r3,r12 635 ld r9,PACA_EXSLB+EX_R9(r13) 636 ld r10,PACA_EXSLB+EX_R10(r13) 637 ld r11,PACA_EXSLB+EX_R11(r13) 638 ld r12,PACA_EXSLB+EX_R12(r13) 639 ld r13,PACA_EXSLB+EX_R13(r13) 640 rfid 641 b . /* prevent speculative execution */ 642 6432: std r3,PACA_EXSLB+EX_DAR(r13) 644 mr r3,r12 645 mfspr r11,SPRN_SRR0 646 mfspr r12,SPRN_SRR1 647 LOAD_HANDLER(r10,unrecov_slb) 648 mtspr SPRN_SRR0,r10 649 ld r10,PACAKMSR(r13) 650 mtspr SPRN_SRR1,r10 651 rfid 652 b . 653 6548: std r3,PACA_EXSLB+EX_DAR(r13) 655 mr r3,r12 656 mfspr r11,SPRN_SRR0 657 mfspr r12,SPRN_SRR1 658 LOAD_HANDLER(r10,bad_addr_slb) 659 mtspr SPRN_SRR0,r10 660 ld r10,PACAKMSR(r13) 661 mtspr SPRN_SRR1,r10 662 rfid 663 b . 664 665EXC_COMMON_BEGIN(unrecov_slb) 666 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 667 RECONCILE_IRQ_STATE(r10, r11) 668 bl save_nvgprs 6691: addi r3,r1,STACK_FRAME_OVERHEAD 670 bl unrecoverable_exception 671 b 1b 672 673EXC_COMMON_BEGIN(bad_addr_slb) 674 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) 675 RECONCILE_IRQ_STATE(r10, r11) 676 ld r3, PACA_EXSLB+EX_DAR(r13) 677 std r3, _DAR(r1) 678 beq cr6, 2f 679 li r10, 0x480 /* fix trap number for I-SLB miss */ 680 std r10, _TRAP(r1) 6812: bl save_nvgprs 682 addi r3, r1, STACK_FRAME_OVERHEAD 683 bl slb_miss_bad_addr 684 b ret_from_except 685 686EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 687 .globl hardware_interrupt_hv; 688hardware_interrupt_hv: 689 BEGIN_FTR_SECTION 690 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 691 EXC_HV, SOFTEN_TEST_HV) 692 FTR_SECTION_ELSE 693 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 694 EXC_STD, SOFTEN_TEST_PR) 695 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 696EXC_REAL_END(hardware_interrupt, 0x500, 0x100) 697 698EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 699 .globl hardware_interrupt_relon_hv; 700hardware_interrupt_relon_hv: 701 BEGIN_FTR_SECTION 702 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) 703 FTR_SECTION_ELSE 704 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) 705 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 706EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 707 708TRAMP_KVM(PACA_EXGEN, 0x500) 709TRAMP_KVM_HV(PACA_EXGEN, 0x500) 710EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 711 712 713EXC_REAL(alignment, 0x600, 0x100) 714EXC_VIRT(alignment, 0x4600, 0x100, 0x600) 715TRAMP_KVM(PACA_EXGEN, 0x600) 716EXC_COMMON_BEGIN(alignment_common) 717 mfspr r10,SPRN_DAR 718 std r10,PACA_EXGEN+EX_DAR(r13) 719 mfspr r10,SPRN_DSISR 720 stw r10,PACA_EXGEN+EX_DSISR(r13) 721 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 722 ld r3,PACA_EXGEN+EX_DAR(r13) 723 lwz r4,PACA_EXGEN+EX_DSISR(r13) 724 std r3,_DAR(r1) 725 std r4,_DSISR(r1) 726 bl save_nvgprs 727 RECONCILE_IRQ_STATE(r10, r11) 728 addi r3,r1,STACK_FRAME_OVERHEAD 729 bl alignment_exception 730 b ret_from_except 731 732 733EXC_REAL(program_check, 0x700, 0x100) 734EXC_VIRT(program_check, 0x4700, 0x100, 0x700) 735TRAMP_KVM(PACA_EXGEN, 0x700) 736EXC_COMMON_BEGIN(program_check_common) 737 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 738 bl save_nvgprs 739 RECONCILE_IRQ_STATE(r10, r11) 740 addi r3,r1,STACK_FRAME_OVERHEAD 741 bl program_check_exception 742 b ret_from_except 743 744 745EXC_REAL(fp_unavailable, 0x800, 0x100) 746EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 747TRAMP_KVM(PACA_EXGEN, 0x800) 748EXC_COMMON_BEGIN(fp_unavailable_common) 749 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 750 bne 1f /* if from user, just load it up */ 751 bl save_nvgprs 752 RECONCILE_IRQ_STATE(r10, r11) 753 addi r3,r1,STACK_FRAME_OVERHEAD 754 bl kernel_fp_unavailable_exception 755 BUG_OPCODE 7561: 757#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 758BEGIN_FTR_SECTION 759 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 760 * transaction), go do TM stuff 761 */ 762 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 763 bne- 2f 764END_FTR_SECTION_IFSET(CPU_FTR_TM) 765#endif 766 bl load_up_fpu 767 b fast_exception_return 768#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 7692: /* User process was in a transaction */ 770 bl save_nvgprs 771 RECONCILE_IRQ_STATE(r10, r11) 772 addi r3,r1,STACK_FRAME_OVERHEAD 773 bl fp_unavailable_tm 774 b ret_from_except 775#endif 776 777 778EXC_REAL_MASKABLE(decrementer, 0x900, 0x80) 779EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900) 780TRAMP_KVM(PACA_EXGEN, 0x900) 781EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 782 783 784EXC_REAL_HV(hdecrementer, 0x980, 0x80) 785EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 786TRAMP_KVM_HV(PACA_EXGEN, 0x980) 787EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 788 789 790EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100) 791EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00) 792TRAMP_KVM(PACA_EXGEN, 0xa00) 793#ifdef CONFIG_PPC_DOORBELL 794EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 795#else 796EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 797#endif 798 799 800EXC_REAL(trap_0b, 0xb00, 0x100) 801EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 802TRAMP_KVM(PACA_EXGEN, 0xb00) 803EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 804 805/* 806 * system call / hypercall (0xc00, 0x4c00) 807 * 808 * The system call exception is invoked with "sc 0" and does not alter HV bit. 809 * There is support for kernel code to invoke system calls but there are no 810 * in-tree users. 811 * 812 * The hypercall is invoked with "sc 1" and sets HV=1. 813 * 814 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 815 * 0x4c00 virtual mode. 816 * 817 * Call convention: 818 * 819 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt 820 * 821 * For hypercalls, the register convention is as follows: 822 * r0 volatile 823 * r1-2 nonvolatile 824 * r3 volatile parameter and return value for status 825 * r4-r10 volatile input and output value 826 * r11 volatile hypercall number and output value 827 * r12 volatile input and output value 828 * r13-r31 nonvolatile 829 * LR nonvolatile 830 * CTR volatile 831 * XER volatile 832 * CR0-1 CR5-7 volatile 833 * CR2-4 nonvolatile 834 * Other registers nonvolatile 835 * 836 * The intersection of volatile registers that don't contain possible 837 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 838 * without saving, though xer is not a good idea to use, as hardware may 839 * interpret some bits so it may be costly to change them. 840 */ 841#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 842 /* 843 * There is a little bit of juggling to get syscall and hcall 844 * working well. Save r13 in ctr to avoid using SPRG scratch 845 * register. 846 * 847 * Userspace syscalls have already saved the PPR, hcalls must save 848 * it before setting HMT_MEDIUM. 849 */ 850#define SYSCALL_KVMTEST \ 851 mtctr r13; \ 852 GET_PACA(r13); \ 853 std r10,PACA_EXGEN+EX_R10(r13); \ 854 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \ 855 HMT_MEDIUM; \ 856 mfctr r9; 857 858#else 859#define SYSCALL_KVMTEST \ 860 HMT_MEDIUM; \ 861 mr r9,r13; \ 862 GET_PACA(r13); 863#endif 864 865#define LOAD_SYSCALL_HANDLER(reg) \ 866 __LOAD_HANDLER(reg, system_call_common) 867 868#define SYSCALL_FASTENDIAN_TEST \ 869BEGIN_FTR_SECTION \ 870 cmpdi r0,0x1ebe ; \ 871 beq- 1f ; \ 872END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 873 874/* 875 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, 876 * and HMT_MEDIUM. 877 */ 878#define SYSCALL_REAL \ 879 mfspr r11,SPRN_SRR0 ; \ 880 mfspr r12,SPRN_SRR1 ; \ 881 LOAD_SYSCALL_HANDLER(r10) ; \ 882 mtspr SPRN_SRR0,r10 ; \ 883 ld r10,PACAKMSR(r13) ; \ 884 mtspr SPRN_SRR1,r10 ; \ 885 rfid ; \ 886 b . ; /* prevent speculative execution */ 887 888#define SYSCALL_FASTENDIAN \ 889 /* Fast LE/BE switch system call */ \ 8901: mfspr r12,SPRN_SRR1 ; \ 891 xori r12,r12,MSR_LE ; \ 892 mtspr SPRN_SRR1,r12 ; \ 893 mr r13,r9 ; \ 894 rfid ; /* return to userspace */ \ 895 b . ; /* prevent speculative execution */ 896 897#if defined(CONFIG_RELOCATABLE) 898 /* 899 * We can't branch directly so we do it via the CTR which 900 * is volatile across system calls. 901 */ 902#define SYSCALL_VIRT \ 903 LOAD_SYSCALL_HANDLER(r10) ; \ 904 mtctr r10 ; \ 905 mfspr r11,SPRN_SRR0 ; \ 906 mfspr r12,SPRN_SRR1 ; \ 907 li r10,MSR_RI ; \ 908 mtmsrd r10,1 ; \ 909 bctr ; 910#else 911 /* We can branch directly */ 912#define SYSCALL_VIRT \ 913 mfspr r11,SPRN_SRR0 ; \ 914 mfspr r12,SPRN_SRR1 ; \ 915 li r10,MSR_RI ; \ 916 mtmsrd r10,1 ; /* Set RI (EE=0) */ \ 917 b system_call_common ; 918#endif 919 920EXC_REAL_BEGIN(system_call, 0xc00, 0x100) 921 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 922 SYSCALL_FASTENDIAN_TEST 923 SYSCALL_REAL 924 SYSCALL_FASTENDIAN 925EXC_REAL_END(system_call, 0xc00, 0x100) 926 927EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 928 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 929 SYSCALL_FASTENDIAN_TEST 930 SYSCALL_VIRT 931 SYSCALL_FASTENDIAN 932EXC_VIRT_END(system_call, 0x4c00, 0x100) 933 934#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 935 /* 936 * This is a hcall, so register convention is as above, with these 937 * differences: 938 * r13 = PACA 939 * ctr = orig r13 940 * orig r10 saved in PACA 941 */ 942TRAMP_KVM_BEGIN(do_kvm_0xc00) 943 /* 944 * Save the PPR (on systems that support it) before changing to 945 * HMT_MEDIUM. That allows the KVM code to save that value into the 946 * guest state (it is the guest's PPR value). 947 */ 948 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) 949 HMT_MEDIUM 950 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) 951 mfctr r10 952 SET_SCRATCH0(r10) 953 std r9,PACA_EXGEN+EX_R9(r13) 954 mfcr r9 955 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) 956#endif 957 958 959EXC_REAL(single_step, 0xd00, 0x100) 960EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 961TRAMP_KVM(PACA_EXGEN, 0xd00) 962EXC_COMMON(single_step_common, 0xd00, single_step_exception) 963 964EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 965EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 966TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 967EXC_COMMON_BEGIN(h_data_storage_common) 968 mfspr r10,SPRN_HDAR 969 std r10,PACA_EXGEN+EX_DAR(r13) 970 mfspr r10,SPRN_HDSISR 971 stw r10,PACA_EXGEN+EX_DSISR(r13) 972 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) 973 bl save_nvgprs 974 RECONCILE_IRQ_STATE(r10, r11) 975 addi r3,r1,STACK_FRAME_OVERHEAD 976 bl unknown_exception 977 b ret_from_except 978 979 980EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 981EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 982TRAMP_KVM_HV(PACA_EXGEN, 0xe20) 983EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 984 985 986EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 987EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 988TRAMP_KVM_HV(PACA_EXGEN, 0xe40) 989EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 990 991 992/* 993 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 994 * first, and then eventaully from there to the trampoline to get into virtual 995 * mode. 996 */ 997__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) 998__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) 999EXC_VIRT_NONE(0x4e60, 0x20) 1000TRAMP_KVM_HV(PACA_EXGEN, 0xe60) 1001TRAMP_REAL_BEGIN(hmi_exception_early) 1002 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) 1003 mr r10,r1 /* Save r1 */ 1004 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 1005 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1006 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 1007 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ 1008 EXCEPTION_PROLOG_COMMON_1() 1009 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 1010 EXCEPTION_PROLOG_COMMON_3(0xe60) 1011 addi r3,r1,STACK_FRAME_OVERHEAD 1012 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */ 1013 /* Windup the stack. */ 1014 /* Move original HSRR0 and HSRR1 into the respective regs */ 1015 ld r9,_MSR(r1) 1016 mtspr SPRN_HSRR1,r9 1017 ld r3,_NIP(r1) 1018 mtspr SPRN_HSRR0,r3 1019 ld r9,_CTR(r1) 1020 mtctr r9 1021 ld r9,_XER(r1) 1022 mtxer r9 1023 ld r9,_LINK(r1) 1024 mtlr r9 1025 REST_GPR(0, r1) 1026 REST_8GPRS(2, r1) 1027 REST_GPR(10, r1) 1028 ld r11,_CCR(r1) 1029 mtcr r11 1030 REST_GPR(11, r1) 1031 REST_2GPRS(12, r1) 1032 /* restore original r1. */ 1033 ld r1,GPR1(r1) 1034 1035 /* 1036 * Go to virtual mode and pull the HMI event information from 1037 * firmware. 1038 */ 1039 .globl hmi_exception_after_realmode 1040hmi_exception_after_realmode: 1041 SET_SCRATCH0(r13) 1042 EXCEPTION_PROLOG_0(PACA_EXGEN) 1043 b tramp_real_hmi_exception 1044 1045EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) 1046 1047 1048EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20) 1049EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80) 1050TRAMP_KVM_HV(PACA_EXGEN, 0xe80) 1051#ifdef CONFIG_PPC_DOORBELL 1052EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 1053#else 1054EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 1055#endif 1056 1057 1058EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20) 1059EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0) 1060TRAMP_KVM_HV(PACA_EXGEN, 0xea0) 1061EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 1062 1063 1064EXC_REAL_NONE(0xec0, 0x20) 1065EXC_VIRT_NONE(0x4ec0, 0x20) 1066EXC_REAL_NONE(0xee0, 0x20) 1067EXC_VIRT_NONE(0x4ee0, 0x20) 1068 1069 1070EXC_REAL_OOL(performance_monitor, 0xf00, 0x20) 1071EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00) 1072TRAMP_KVM(PACA_EXGEN, 0xf00) 1073EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1074 1075 1076EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 1077EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1078TRAMP_KVM(PACA_EXGEN, 0xf20) 1079EXC_COMMON_BEGIN(altivec_unavailable_common) 1080 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1081#ifdef CONFIG_ALTIVEC 1082BEGIN_FTR_SECTION 1083 beq 1f 1084#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1085 BEGIN_FTR_SECTION_NESTED(69) 1086 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1087 * transaction), go do TM stuff 1088 */ 1089 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1090 bne- 2f 1091 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1092#endif 1093 bl load_up_altivec 1094 b fast_exception_return 1095#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 10962: /* User process was in a transaction */ 1097 bl save_nvgprs 1098 RECONCILE_IRQ_STATE(r10, r11) 1099 addi r3,r1,STACK_FRAME_OVERHEAD 1100 bl altivec_unavailable_tm 1101 b ret_from_except 1102#endif 11031: 1104END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1105#endif 1106 bl save_nvgprs 1107 RECONCILE_IRQ_STATE(r10, r11) 1108 addi r3,r1,STACK_FRAME_OVERHEAD 1109 bl altivec_unavailable_exception 1110 b ret_from_except 1111 1112 1113EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 1114EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1115TRAMP_KVM(PACA_EXGEN, 0xf40) 1116EXC_COMMON_BEGIN(vsx_unavailable_common) 1117 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 1118#ifdef CONFIG_VSX 1119BEGIN_FTR_SECTION 1120 beq 1f 1121#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1122 BEGIN_FTR_SECTION_NESTED(69) 1123 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1124 * transaction), go do TM stuff 1125 */ 1126 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1127 bne- 2f 1128 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1129#endif 1130 b load_up_vsx 1131#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 11322: /* User process was in a transaction */ 1133 bl save_nvgprs 1134 RECONCILE_IRQ_STATE(r10, r11) 1135 addi r3,r1,STACK_FRAME_OVERHEAD 1136 bl vsx_unavailable_tm 1137 b ret_from_except 1138#endif 11391: 1140END_FTR_SECTION_IFSET(CPU_FTR_VSX) 1141#endif 1142 bl save_nvgprs 1143 RECONCILE_IRQ_STATE(r10, r11) 1144 addi r3,r1,STACK_FRAME_OVERHEAD 1145 bl vsx_unavailable_exception 1146 b ret_from_except 1147 1148 1149EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 1150EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 1151TRAMP_KVM(PACA_EXGEN, 0xf60) 1152EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 1153 1154 1155EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 1156EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 1157TRAMP_KVM_HV(PACA_EXGEN, 0xf80) 1158EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 1159 1160 1161EXC_REAL_NONE(0xfa0, 0x20) 1162EXC_VIRT_NONE(0x4fa0, 0x20) 1163EXC_REAL_NONE(0xfc0, 0x20) 1164EXC_VIRT_NONE(0x4fc0, 0x20) 1165EXC_REAL_NONE(0xfe0, 0x20) 1166EXC_VIRT_NONE(0x4fe0, 0x20) 1167 1168EXC_REAL_NONE(0x1000, 0x100) 1169EXC_VIRT_NONE(0x5000, 0x100) 1170EXC_REAL_NONE(0x1100, 0x100) 1171EXC_VIRT_NONE(0x5100, 0x100) 1172 1173#ifdef CONFIG_CBE_RAS 1174EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 1175EXC_VIRT_NONE(0x5200, 0x100) 1176TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1177EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1178#else /* CONFIG_CBE_RAS */ 1179EXC_REAL_NONE(0x1200, 0x100) 1180EXC_VIRT_NONE(0x5200, 0x100) 1181#endif 1182 1183 1184EXC_REAL(instruction_breakpoint, 0x1300, 0x100) 1185EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1186TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 1187EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 1188 1189EXC_REAL_NONE(0x1400, 0x100) 1190EXC_VIRT_NONE(0x5400, 0x100) 1191 1192EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 1193 mtspr SPRN_SPRG_HSCRATCH0,r13 1194 EXCEPTION_PROLOG_0(PACA_EXGEN) 1195 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) 1196 1197#ifdef CONFIG_PPC_DENORMALISATION 1198 mfspr r10,SPRN_HSRR1 1199 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 1200 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1201 addi r11,r11,-4 /* HSRR0 is next instruction */ 1202 bne+ denorm_assist 1203#endif 1204 1205 KVMTEST_PR(0x1500) 1206 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) 1207EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1208 1209#ifdef CONFIG_PPC_DENORMALISATION 1210EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1211 b exc_real_0x1500_denorm_exception_hv 1212EXC_VIRT_END(denorm_exception, 0x5500, 0x100) 1213#else 1214EXC_VIRT_NONE(0x5500, 0x100) 1215#endif 1216 1217TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) 1218 1219#ifdef CONFIG_PPC_DENORMALISATION 1220TRAMP_REAL_BEGIN(denorm_assist) 1221BEGIN_FTR_SECTION 1222/* 1223 * To denormalise we need to move a copy of the register to itself. 1224 * For POWER6 do that here for all FP regs. 1225 */ 1226 mfmsr r10 1227 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1228 xori r10,r10,(MSR_FE0|MSR_FE1) 1229 mtmsrd r10 1230 sync 1231 1232#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 1233#define FMR4(n) FMR2(n) ; FMR2(n+2) 1234#define FMR8(n) FMR4(n) ; FMR4(n+4) 1235#define FMR16(n) FMR8(n) ; FMR8(n+8) 1236#define FMR32(n) FMR16(n) ; FMR16(n+16) 1237 FMR32(0) 1238 1239FTR_SECTION_ELSE 1240/* 1241 * To denormalise we need to move a copy of the register to itself. 1242 * For POWER7 do that here for the first 32 VSX registers only. 1243 */ 1244 mfmsr r10 1245 oris r10,r10,MSR_VSX@h 1246 mtmsrd r10 1247 sync 1248 1249#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) 1250#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) 1251#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) 1252#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) 1253#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) 1254 XVCPSGNDP32(0) 1255 1256ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1257 1258BEGIN_FTR_SECTION 1259 b denorm_done 1260END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1261/* 1262 * To denormalise we need to move a copy of the register to itself. 1263 * For POWER8 we need to do that for all 64 VSX registers 1264 */ 1265 XVCPSGNDP32(32) 1266denorm_done: 1267 mtspr SPRN_HSRR0,r11 1268 mtcrf 0x80,r9 1269 ld r9,PACA_EXGEN+EX_R9(r13) 1270 RESTORE_PPR_PACA(PACA_EXGEN, r10) 1271BEGIN_FTR_SECTION 1272 ld r10,PACA_EXGEN+EX_CFAR(r13) 1273 mtspr SPRN_CFAR,r10 1274END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1275 ld r10,PACA_EXGEN+EX_R10(r13) 1276 ld r11,PACA_EXGEN+EX_R11(r13) 1277 ld r12,PACA_EXGEN+EX_R12(r13) 1278 ld r13,PACA_EXGEN+EX_R13(r13) 1279 HRFID 1280 b . 1281#endif 1282 1283EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) 1284 1285 1286#ifdef CONFIG_CBE_RAS 1287EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 1288EXC_VIRT_NONE(0x5600, 0x100) 1289TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 1290EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1291#else /* CONFIG_CBE_RAS */ 1292EXC_REAL_NONE(0x1600, 0x100) 1293EXC_VIRT_NONE(0x5600, 0x100) 1294#endif 1295 1296 1297EXC_REAL(altivec_assist, 0x1700, 0x100) 1298EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 1299TRAMP_KVM(PACA_EXGEN, 0x1700) 1300#ifdef CONFIG_ALTIVEC 1301EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 1302#else 1303EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 1304#endif 1305 1306 1307#ifdef CONFIG_CBE_RAS 1308EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 1309EXC_VIRT_NONE(0x5800, 0x100) 1310TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 1311EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 1312#else /* CONFIG_CBE_RAS */ 1313EXC_REAL_NONE(0x1800, 0x100) 1314EXC_VIRT_NONE(0x5800, 0x100) 1315#endif 1316 1317#if defined(CONFIG_HARDLOCKUP_DETECTOR) && defined(CONFIG_HAVE_HARDLOCKUP_DETECTOR_ARCH) 1318 1319#define MASKED_DEC_HANDLER_LABEL 3f 1320 1321#define MASKED_DEC_HANDLER(_H) \ 13223: /* soft-nmi */ \ 1323 std r12,PACA_EXGEN+EX_R12(r13); \ 1324 GET_SCRATCH0(r10); \ 1325 std r10,PACA_EXGEN+EX_R13(r13); \ 1326 EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H) 1327 1328/* 1329 * Branch to soft_nmi_interrupt using the emergency stack. The emergency 1330 * stack is one that is usable by maskable interrupts so long as MSR_EE 1331 * remains off. It is used for recovery when something has corrupted the 1332 * normal kernel stack, for example. The "soft NMI" must not use the process 1333 * stack because we want irq disabled sections to avoid touching the stack 1334 * at all (other than PMU interrupts), so use the emergency stack for this, 1335 * and run it entirely with interrupts hard disabled. 1336 */ 1337EXC_COMMON_BEGIN(soft_nmi_common) 1338 mr r10,r1 1339 ld r1,PACAEMERGSP(r13) 1340 subi r1,r1,INT_FRAME_SIZE 1341 EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, 1342 system_reset, soft_nmi_interrupt, 1343 ADD_NVGPRS;ADD_RECONCILE) 1344 b ret_from_except 1345 1346#else 1347#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ 1348#define MASKED_DEC_HANDLER(_H) 1349#endif 1350 1351/* 1352 * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 1353 * - If it was a decrementer interrupt, we bump the dec to max and and return. 1354 * - If it was a doorbell we return immediately since doorbells are edge 1355 * triggered and won't automatically refire. 1356 * - If it was a HMI we return immediately since we handled it in realmode 1357 * and it won't refire. 1358 * - else we hard disable and return. 1359 * This is called with r10 containing the value to OR to the paca field. 1360 */ 1361#define MASKED_INTERRUPT(_H) \ 1362masked_##_H##interrupt: \ 1363 std r11,PACA_EXGEN+EX_R11(r13); \ 1364 lbz r11,PACAIRQHAPPENED(r13); \ 1365 or r11,r11,r10; \ 1366 stb r11,PACAIRQHAPPENED(r13); \ 1367 cmpwi r10,PACA_IRQ_DEC; \ 1368 bne 1f; \ 1369 lis r10,0x7fff; \ 1370 ori r10,r10,0xffff; \ 1371 mtspr SPRN_DEC,r10; \ 1372 b MASKED_DEC_HANDLER_LABEL; \ 13731: cmpwi r10,PACA_IRQ_DBELL; \ 1374 beq 2f; \ 1375 cmpwi r10,PACA_IRQ_HMI; \ 1376 beq 2f; \ 1377 mfspr r10,SPRN_##_H##SRR1; \ 1378 rldicl r10,r10,48,1; /* clear MSR_EE */ \ 1379 rotldi r10,r10,16; \ 1380 mtspr SPRN_##_H##SRR1,r10; \ 13812: mtcrf 0x80,r9; \ 1382 ld r9,PACA_EXGEN+EX_R9(r13); \ 1383 ld r10,PACA_EXGEN+EX_R10(r13); \ 1384 ld r11,PACA_EXGEN+EX_R11(r13); \ 1385 GET_SCRATCH0(r13); \ 1386 ##_H##rfid; \ 1387 b .; \ 1388 MASKED_DEC_HANDLER(_H) 1389 1390/* 1391 * Real mode exceptions actually use this too, but alternate 1392 * instruction code patches (which end up in the common .text area) 1393 * cannot reach these if they are put there. 1394 */ 1395USE_FIXED_SECTION(virt_trampolines) 1396 MASKED_INTERRUPT() 1397 MASKED_INTERRUPT(H) 1398 1399#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1400TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 1401 /* 1402 * Here all GPRs are unchanged from when the interrupt happened 1403 * except for r13, which is saved in SPRG_SCRATCH0. 1404 */ 1405 mfspr r13, SPRN_SRR0 1406 addi r13, r13, 4 1407 mtspr SPRN_SRR0, r13 1408 GET_SCRATCH0(r13) 1409 rfid 1410 b . 1411 1412TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 1413 /* 1414 * Here all GPRs are unchanged from when the interrupt happened 1415 * except for r13, which is saved in SPRG_SCRATCH0. 1416 */ 1417 mfspr r13, SPRN_HSRR0 1418 addi r13, r13, 4 1419 mtspr SPRN_HSRR0, r13 1420 GET_SCRATCH0(r13) 1421 hrfid 1422 b . 1423#endif 1424 1425/* 1426 * Ensure that any handlers that get invoked from the exception prologs 1427 * above are below the first 64KB (0x10000) of the kernel image because 1428 * the prologs assemble the addresses of these handlers using the 1429 * LOAD_HANDLER macro, which uses an ori instruction. 1430 */ 1431 1432/*** Common interrupt handlers ***/ 1433 1434 1435 /* 1436 * Relocation-on interrupts: A subset of the interrupts can be delivered 1437 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 1438 * it. Addresses are the same as the original interrupt addresses, but 1439 * offset by 0xc000000000004000. 1440 * It's impossible to receive interrupts below 0x300 via this mechanism. 1441 * KVM: None of these traps are from the guest ; anything that escalated 1442 * to HV=1 from HV=0 is delivered via real mode handlers. 1443 */ 1444 1445 /* 1446 * This uses the standard macro, since the original 0x300 vector 1447 * only has extra guff for STAB-based processors -- which never 1448 * come here. 1449 */ 1450 1451EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 1452 b __ppc64_runlatch_on 1453 1454USE_FIXED_SECTION(virt_trampolines) 1455 /* 1456 * The __end_interrupts marker must be past the out-of-line (OOL) 1457 * handlers, so that they are copied to real address 0x100 when running 1458 * a relocatable kernel. This ensures they can be reached from the short 1459 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 1460 * directly, without using LOAD_HANDLER(). 1461 */ 1462 .align 7 1463 .globl __end_interrupts 1464__end_interrupts: 1465DEFINE_FIXED_SYMBOL(__end_interrupts) 1466 1467#ifdef CONFIG_PPC_970_NAP 1468EXC_COMMON_BEGIN(power4_fixup_nap) 1469 andc r9,r9,r10 1470 std r9,TI_LOCAL_FLAGS(r11) 1471 ld r10,_LINK(r1) /* make idle task do the */ 1472 std r10,_NIP(r1) /* equivalent of a blr */ 1473 blr 1474#endif 1475 1476CLOSE_FIXED_SECTION(real_vectors); 1477CLOSE_FIXED_SECTION(real_trampolines); 1478CLOSE_FIXED_SECTION(virt_vectors); 1479CLOSE_FIXED_SECTION(virt_trampolines); 1480 1481USE_TEXT_SECTION() 1482 1483/* 1484 * Hash table stuff 1485 */ 1486 .balign IFETCH_ALIGN_BYTES 1487do_hash_page: 1488#ifdef CONFIG_PPC_STD_MMU_64 1489 andis. r0,r4,0xa450 /* weird error? */ 1490 bne- handle_page_fault /* if not, try to insert a HPTE */ 1491 CURRENT_THREAD_INFO(r11, r1) 1492 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 1493 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 1494 bne 77f /* then don't call hash_page now */ 1495 1496 /* 1497 * r3 contains the faulting address 1498 * r4 msr 1499 * r5 contains the trap number 1500 * r6 contains dsisr 1501 * 1502 * at return r3 = 0 for success, 1 for page fault, negative for error 1503 */ 1504 mr r4,r12 1505 ld r6,_DSISR(r1) 1506 bl __hash_page /* build HPTE if possible */ 1507 cmpdi r3,0 /* see if __hash_page succeeded */ 1508 1509 /* Success */ 1510 beq fast_exc_return_irq /* Return from exception on success */ 1511 1512 /* Error */ 1513 blt- 13f 1514 1515 /* Reload DSISR into r4 for the DABR check below */ 1516 ld r4,_DSISR(r1) 1517#endif /* CONFIG_PPC_STD_MMU_64 */ 1518 1519/* Here we have a page fault that hash_page can't handle. */ 1520handle_page_fault: 152111: andis. r0,r4,DSISR_DABRMATCH@h 1522 bne- handle_dabr_fault 1523 ld r4,_DAR(r1) 1524 ld r5,_DSISR(r1) 1525 addi r3,r1,STACK_FRAME_OVERHEAD 1526 bl do_page_fault 1527 cmpdi r3,0 1528 beq+ 12f 1529 bl save_nvgprs 1530 mr r5,r3 1531 addi r3,r1,STACK_FRAME_OVERHEAD 1532 lwz r4,_DAR(r1) 1533 bl bad_page_fault 1534 b ret_from_except 1535 1536/* We have a data breakpoint exception - handle it */ 1537handle_dabr_fault: 1538 bl save_nvgprs 1539 ld r4,_DAR(r1) 1540 ld r5,_DSISR(r1) 1541 addi r3,r1,STACK_FRAME_OVERHEAD 1542 bl do_break 154312: b ret_from_except_lite 1544 1545 1546#ifdef CONFIG_PPC_STD_MMU_64 1547/* We have a page fault that hash_page could handle but HV refused 1548 * the PTE insertion 1549 */ 155013: bl save_nvgprs 1551 mr r5,r3 1552 addi r3,r1,STACK_FRAME_OVERHEAD 1553 ld r4,_DAR(r1) 1554 bl low_hash_fault 1555 b ret_from_except 1556#endif 1557 1558/* 1559 * We come here as a result of a DSI at a point where we don't want 1560 * to call hash_page, such as when we are accessing memory (possibly 1561 * user memory) inside a PMU interrupt that occurred while interrupts 1562 * were soft-disabled. We want to invoke the exception handler for 1563 * the access, or panic if there isn't a handler. 1564 */ 156577: bl save_nvgprs 1566 mr r4,r3 1567 addi r3,r1,STACK_FRAME_OVERHEAD 1568 li r5,SIGSEGV 1569 bl bad_page_fault 1570 b ret_from_except 1571 1572/* 1573 * Here we have detected that the kernel stack pointer is bad. 1574 * R9 contains the saved CR, r13 points to the paca, 1575 * r10 contains the (bad) kernel stack pointer, 1576 * r11 and r12 contain the saved SRR0 and SRR1. 1577 * We switch to using an emergency stack, save the registers there, 1578 * and call kernel_bad_stack(), which panics. 1579 */ 1580bad_stack: 1581 ld r1,PACAEMERGSP(r13) 1582 subi r1,r1,64+INT_FRAME_SIZE 1583 std r9,_CCR(r1) 1584 std r10,GPR1(r1) 1585 std r11,_NIP(r1) 1586 std r12,_MSR(r1) 1587 mfspr r11,SPRN_DAR 1588 mfspr r12,SPRN_DSISR 1589 std r11,_DAR(r1) 1590 std r12,_DSISR(r1) 1591 mflr r10 1592 mfctr r11 1593 mfxer r12 1594 std r10,_LINK(r1) 1595 std r11,_CTR(r1) 1596 std r12,_XER(r1) 1597 SAVE_GPR(0,r1) 1598 SAVE_GPR(2,r1) 1599 ld r10,EX_R3(r3) 1600 std r10,GPR3(r1) 1601 SAVE_GPR(4,r1) 1602 SAVE_4GPRS(5,r1) 1603 ld r9,EX_R9(r3) 1604 ld r10,EX_R10(r3) 1605 SAVE_2GPRS(9,r1) 1606 ld r9,EX_R11(r3) 1607 ld r10,EX_R12(r3) 1608 ld r11,EX_R13(r3) 1609 std r9,GPR11(r1) 1610 std r10,GPR12(r1) 1611 std r11,GPR13(r1) 1612BEGIN_FTR_SECTION 1613 ld r10,EX_CFAR(r3) 1614 std r10,ORIG_GPR3(r1) 1615END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1616 SAVE_8GPRS(14,r1) 1617 SAVE_10GPRS(22,r1) 1618 lhz r12,PACA_TRAP_SAVE(r13) 1619 std r12,_TRAP(r1) 1620 addi r11,r1,INT_FRAME_SIZE 1621 std r11,0(r1) 1622 li r12,0 1623 std r12,0(r11) 1624 ld r2,PACATOC(r13) 1625 ld r11,exception_marker@toc(r2) 1626 std r12,RESULT(r1) 1627 std r11,STACK_FRAME_OVERHEAD-16(r1) 16281: addi r3,r1,STACK_FRAME_OVERHEAD 1629 bl kernel_bad_stack 1630 b 1b 1631_ASM_NOKPROBE_SYMBOL(bad_stack); 1632 1633/* 1634 * When doorbell is triggered from system reset wakeup, the message is 1635 * not cleared, so it would fire again when EE is enabled. 1636 * 1637 * When coming from local_irq_enable, there may be the same problem if 1638 * we were hard disabled. 1639 * 1640 * Execute msgclr to clear pending exceptions before handling it. 1641 */ 1642h_doorbell_common_msgclr: 1643 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1644 PPC_MSGCLR(3) 1645 b h_doorbell_common 1646 1647doorbell_super_common_msgclr: 1648 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1649 PPC_MSGCLRP(3) 1650 b doorbell_super_common 1651 1652/* 1653 * Called from arch_local_irq_enable when an interrupt needs 1654 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 1655 * which kind of interrupt. MSR:EE is already off. We generate a 1656 * stackframe like if a real interrupt had happened. 1657 * 1658 * Note: While MSR:EE is off, we need to make sure that _MSR 1659 * in the generated frame has EE set to 1 or the exception 1660 * handler will not properly re-enable them. 1661 * 1662 * Note that we don't specify LR as the NIP (return address) for 1663 * the interrupt because that would unbalance the return branch 1664 * predictor. 1665 */ 1666_GLOBAL(__replay_interrupt) 1667 /* We are going to jump to the exception common code which 1668 * will retrieve various register values from the PACA which 1669 * we don't give a damn about, so we don't bother storing them. 1670 */ 1671 mfmsr r12 1672 LOAD_REG_ADDR(r11, 1f) 1673 mfcr r9 1674 ori r12,r12,MSR_EE 1675 cmpwi r3,0x900 1676 beq decrementer_common 1677 cmpwi r3,0x500 1678 beq hardware_interrupt_common 1679BEGIN_FTR_SECTION 1680 cmpwi r3,0xe80 1681 beq h_doorbell_common_msgclr 1682 cmpwi r3,0xea0 1683 beq h_virt_irq_common 1684 cmpwi r3,0xe60 1685 beq hmi_exception_common 1686FTR_SECTION_ELSE 1687 cmpwi r3,0xa00 1688 beq doorbell_super_common_msgclr 1689ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 16901: 1691 blr 1692 1693_ASM_NOKPROBE_SYMBOL(__replay_interrupt) 1694