1/* 2 * This file contains the 64-bit "server" PowerPC variant 3 * of the low level exception handling including exception 4 * vectors, exception return, part of the slb and stab 5 * handling and other fixed offset specific things. 6 * 7 * This file is meant to be #included from head_64.S due to 8 * position dependent assembly. 9 * 10 * Most of this originates from head_64.S and thus has the same 11 * copyright history. 12 * 13 */ 14 15#include <asm/hw_irq.h> 16#include <asm/exception-64s.h> 17#include <asm/ptrace.h> 18#include <asm/cpuidle.h> 19#include <asm/head-64.h> 20 21/* 22 * There are a few constraints to be concerned with. 23 * - Real mode exceptions code/data must be located at their physical location. 24 * - Virtual mode exceptions must be mapped at their 0xc000... location. 25 * - Fixed location code must not call directly beyond the __end_interrupts 26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 27 * must be used. 28 * - LOAD_HANDLER targets must be within first 64K of physical 0 / 29 * virtual 0xc00... 30 * - Conditional branch targets must be within +/-32K of caller. 31 * 32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 33 * therefore don't have to run in physically located code or rfid to 34 * virtual mode kernel code. However on relocatable kernels they do have 35 * to branch to KERNELBASE offset because the rest of the kernel (outside 36 * the exception vectors) may be located elsewhere. 37 * 38 * Virtual exceptions correspond with physical, except their entry points 39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000 40 * offset applied. Virtual exceptions are enabled with the Alternate 41 * Interrupt Location (AIL) bit set in the LPCR. However this does not 42 * guarantee they will be delivered virtually. Some conditions (see the ISA) 43 * cause exceptions to be delivered in real mode. 44 * 45 * It's impossible to receive interrupts below 0x300 via AIL. 46 * 47 * KVM: None of the virtual exceptions are from the guest. Anything that 48 * escalated to HV=1 from HV=0 is delivered via real mode handlers. 49 * 50 * 51 * We layout physical memory as follows: 52 * 0x0000 - 0x00ff : Secondary processor spin code 53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 54 * 0x1900 - 0x3fff : Real mode trampolines 55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 56 * 0x5900 - 0x6fff : Relon mode trampolines 57 * 0x7000 - 0x7fff : FWNMI data area 58 * 0x8000 - .... : Common interrupt handlers, remaining early 59 * setup code, rest of kernel. 60 * 61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 63 * vectors there. 64 */ 65OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 66OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 67OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 68OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 69#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 70/* 71 * Data area reserved for FWNMI option. 72 * This address (0x7000) is fixed by the RPA. 73 * pseries and powernv need to keep the whole page from 74 * 0x7000 to 0x8000 free for use by the firmware 75 */ 76ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 77OPEN_TEXT_SECTION(0x8000) 78#else 79OPEN_TEXT_SECTION(0x7000) 80#endif 81 82USE_FIXED_SECTION(real_vectors) 83 84/* 85 * This is the start of the interrupt handlers for pSeries 86 * This code runs with relocation off. 87 * Code from here to __end_interrupts gets copied down to real 88 * address 0x100 when we are running a relocatable kernel. 89 * Therefore any relative branches in this section must only 90 * branch to labels in this section. 91 */ 92 .globl __start_interrupts 93__start_interrupts: 94 95/* No virt vectors corresponding with 0x0..0x100 */ 96EXC_VIRT_NONE(0x4000, 0x100) 97 98 99#ifdef CONFIG_PPC_P7_NAP 100 /* 101 * If running native on arch 2.06 or later, check if we are waking up 102 * from nap/sleep/winkle, and branch to idle handler. 103 */ 104#define IDLETEST(n) \ 105 BEGIN_FTR_SECTION ; \ 106 mfspr r10,SPRN_SRR1 ; \ 107 rlwinm. r10,r10,47-31,30,31 ; \ 108 beq- 1f ; \ 109 cmpwi cr3,r10,2 ; \ 110 BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \ 1111: \ 112 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 113#else 114#define IDLETEST NOTEST 115#endif 116 117EXC_REAL_BEGIN(system_reset, 0x100, 0x100) 118 SET_SCRATCH0(r13) 119 GET_PACA(r13) 120 clrrdi r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */ 121 EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD, 122 IDLETEST, 0x100) 123 124EXC_REAL_END(system_reset, 0x100, 0x100) 125EXC_VIRT_NONE(0x4100, 0x100) 126 127#ifdef CONFIG_PPC_P7_NAP 128EXC_COMMON_BEGIN(system_reset_idle_common) 129BEGIN_FTR_SECTION 130 GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */ 131END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) 132 bl pnv_restore_hyp_resource 133 134 li r0,PNV_THREAD_RUNNING 135 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ 136 137#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 138 li r0,KVM_HWTHREAD_IN_KERNEL 139 stb r0,HSTATE_HWTHREAD_STATE(r13) 140 /* Order setting hwthread_state vs. testing hwthread_req */ 141 sync 142 lbz r0,HSTATE_HWTHREAD_REQ(r13) 143 cmpwi r0,0 144 beq 1f 145 BRANCH_TO_KVM(r10, kvm_start_guest) 1461: 147#endif 148 149 /* Return SRR1 from power7_nap() */ 150 mfspr r3,SPRN_SRR1 151 blt cr3,2f 152 b pnv_wakeup_loss 1532: b pnv_wakeup_noloss 154#endif 155 156EXC_COMMON(system_reset_common, 0x100, system_reset_exception) 157 158#ifdef CONFIG_PPC_PSERIES 159/* 160 * Vectors for the FWNMI option. Share common code. 161 */ 162TRAMP_REAL_BEGIN(system_reset_fwnmi) 163 SET_SCRATCH0(r13) /* save r13 */ 164 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, 165 NOTEST, 0x100) 166#endif /* CONFIG_PPC_PSERIES */ 167 168 169EXC_REAL_BEGIN(machine_check, 0x200, 0x100) 170 /* This is moved out of line as it can be patched by FW, but 171 * some code path might still want to branch into the original 172 * vector 173 */ 174 SET_SCRATCH0(r13) /* save r13 */ 175 /* 176 * Running native on arch 2.06 or later, we may wakeup from winkle 177 * inside machine check. If yes, then last bit of HSPRG0 would be set 178 * to 1. Hence clear it unconditionally. 179 */ 180 GET_PACA(r13) 181 clrrdi r13,r13,1 182 SET_PACA(r13) 183 EXCEPTION_PROLOG_0(PACA_EXMC) 184BEGIN_FTR_SECTION 185 b machine_check_powernv_early 186FTR_SECTION_ELSE 187 b machine_check_pSeries_0 188ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 189EXC_REAL_END(machine_check, 0x200, 0x100) 190EXC_VIRT_NONE(0x4200, 0x100) 191TRAMP_REAL_BEGIN(machine_check_powernv_early) 192BEGIN_FTR_SECTION 193 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) 194 /* 195 * Register contents: 196 * R13 = PACA 197 * R9 = CR 198 * Original R9 to R13 is saved on PACA_EXMC 199 * 200 * Switch to mc_emergency stack and handle re-entrancy (we limit 201 * the nested MCE upto level 4 to avoid stack overflow). 202 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 203 * 204 * We use paca->in_mce to check whether this is the first entry or 205 * nested machine check. We increment paca->in_mce to track nested 206 * machine checks. 207 * 208 * If this is the first entry then set stack pointer to 209 * paca->mc_emergency_sp, otherwise r1 is already pointing to 210 * stack frame on mc_emergency stack. 211 * 212 * NOTE: We are here with MSR_ME=0 (off), which means we risk a 213 * checkstop if we get another machine check exception before we do 214 * rfid with MSR_ME=1. 215 */ 216 mr r11,r1 /* Save r1 */ 217 lhz r10,PACA_IN_MCE(r13) 218 cmpwi r10,0 /* Are we in nested machine check */ 219 bne 0f /* Yes, we are. */ 220 /* First machine check entry */ 221 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 2220: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 223 addi r10,r10,1 /* increment paca->in_mce */ 224 sth r10,PACA_IN_MCE(r13) 225 /* Limit nested MCE to level 4 to avoid stack overflow */ 226 cmpwi r10,4 227 bgt 2f /* Check if we hit limit of 4 */ 228 std r11,GPR1(r1) /* Save r1 on the stack. */ 229 std r11,0(r1) /* make stack chain pointer */ 230 mfspr r11,SPRN_SRR0 /* Save SRR0 */ 231 std r11,_NIP(r1) 232 mfspr r11,SPRN_SRR1 /* Save SRR1 */ 233 std r11,_MSR(r1) 234 mfspr r11,SPRN_DAR /* Save DAR */ 235 std r11,_DAR(r1) 236 mfspr r11,SPRN_DSISR /* Save DSISR */ 237 std r11,_DSISR(r1) 238 std r9,_CCR(r1) /* Save CR in stackframe */ 239 /* Save r9 through r13 from EXMC save area to stack frame. */ 240 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 241 mfmsr r11 /* get MSR value */ 242 ori r11,r11,MSR_ME /* turn on ME bit */ 243 ori r11,r11,MSR_RI /* turn on RI bit */ 244 LOAD_HANDLER(r12, machine_check_handle_early) 2451: mtspr SPRN_SRR0,r12 246 mtspr SPRN_SRR1,r11 247 rfid 248 b . /* prevent speculative execution */ 2492: 250 /* Stack overflow. Stay on emergency stack and panic. 251 * Keep the ME bit off while panic-ing, so that if we hit 252 * another machine check we checkstop. 253 */ 254 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 255 ld r11,PACAKMSR(r13) 256 LOAD_HANDLER(r12, unrecover_mce) 257 li r10,MSR_ME 258 andc r11,r11,r10 /* Turn off MSR_ME */ 259 b 1b 260 b . /* prevent speculative execution */ 261END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 262 263TRAMP_REAL_BEGIN(machine_check_pSeries) 264 .globl machine_check_fwnmi 265machine_check_fwnmi: 266 SET_SCRATCH0(r13) /* save r13 */ 267 EXCEPTION_PROLOG_0(PACA_EXMC) 268machine_check_pSeries_0: 269 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) 270 /* 271 * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the 272 * difference that MSR_RI is not enabled, because PACA_EXMC is being 273 * used, so nested machine check corrupts it. machine_check_common 274 * enables MSR_RI. 275 */ 276 ld r10,PACAKMSR(r13) 277 xori r10,r10,MSR_RI 278 mfspr r11,SPRN_SRR0 279 LOAD_HANDLER(r12, machine_check_common) 280 mtspr SPRN_SRR0,r12 281 mfspr r12,SPRN_SRR1 282 mtspr SPRN_SRR1,r10 283 rfid 284 b . /* prevent speculative execution */ 285 286TRAMP_KVM_SKIP(PACA_EXMC, 0x200) 287 288EXC_COMMON_BEGIN(machine_check_common) 289 /* 290 * Machine check is different because we use a different 291 * save area: PACA_EXMC instead of PACA_EXGEN. 292 */ 293 mfspr r10,SPRN_DAR 294 std r10,PACA_EXMC+EX_DAR(r13) 295 mfspr r10,SPRN_DSISR 296 stw r10,PACA_EXMC+EX_DSISR(r13) 297 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 298 FINISH_NAP 299 RECONCILE_IRQ_STATE(r10, r11) 300 ld r3,PACA_EXMC+EX_DAR(r13) 301 lwz r4,PACA_EXMC+EX_DSISR(r13) 302 /* Enable MSR_RI when finished with PACA_EXMC */ 303 li r10,MSR_RI 304 mtmsrd r10,1 305 std r3,_DAR(r1) 306 std r4,_DSISR(r1) 307 bl save_nvgprs 308 addi r3,r1,STACK_FRAME_OVERHEAD 309 bl machine_check_exception 310 b ret_from_except 311 312#define MACHINE_CHECK_HANDLER_WINDUP \ 313 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 314 li r0,MSR_RI; \ 315 mfmsr r9; /* get MSR value */ \ 316 andc r9,r9,r0; \ 317 mtmsrd r9,1; /* Clear MSR_RI */ \ 318 /* Move original SRR0 and SRR1 into the respective regs */ \ 319 ld r9,_MSR(r1); \ 320 mtspr SPRN_SRR1,r9; \ 321 ld r3,_NIP(r1); \ 322 mtspr SPRN_SRR0,r3; \ 323 ld r9,_CTR(r1); \ 324 mtctr r9; \ 325 ld r9,_XER(r1); \ 326 mtxer r9; \ 327 ld r9,_LINK(r1); \ 328 mtlr r9; \ 329 REST_GPR(0, r1); \ 330 REST_8GPRS(2, r1); \ 331 REST_GPR(10, r1); \ 332 ld r11,_CCR(r1); \ 333 mtcr r11; \ 334 /* Decrement paca->in_mce. */ \ 335 lhz r12,PACA_IN_MCE(r13); \ 336 subi r12,r12,1; \ 337 sth r12,PACA_IN_MCE(r13); \ 338 REST_GPR(11, r1); \ 339 REST_2GPRS(12, r1); \ 340 /* restore original r1. */ \ 341 ld r1,GPR1(r1) 342 343 /* 344 * Handle machine check early in real mode. We come here with 345 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 346 */ 347EXC_COMMON_BEGIN(machine_check_handle_early) 348 std r0,GPR0(r1) /* Save r0 */ 349 EXCEPTION_PROLOG_COMMON_3(0x200) 350 bl save_nvgprs 351 addi r3,r1,STACK_FRAME_OVERHEAD 352 bl machine_check_early 353 std r3,RESULT(r1) /* Save result */ 354 ld r12,_MSR(r1) 355#ifdef CONFIG_PPC_P7_NAP 356 /* 357 * Check if thread was in power saving mode. We come here when any 358 * of the following is true: 359 * a. thread wasn't in power saving mode 360 * b. thread was in power saving mode with no state loss, 361 * supervisor state loss or hypervisor state loss. 362 * 363 * Go back to nap/sleep/winkle mode again if (b) is true. 364 */ 365 rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ 366 beq 4f /* No, it wasn;t */ 367 /* Thread was in power saving mode. Go back to nap again. */ 368 cmpwi r11,2 369 blt 3f 370 /* Supervisor/Hypervisor state loss */ 371 li r0,1 372 stb r0,PACA_NAPSTATELOST(r13) 3733: bl machine_check_queue_event 374 MACHINE_CHECK_HANDLER_WINDUP 375 GET_PACA(r13) 376 ld r1,PACAR1(r13) 377 /* 378 * Check what idle state this CPU was in and go back to same mode 379 * again. 380 */ 381 lbz r3,PACA_THREAD_IDLE_STATE(r13) 382 cmpwi r3,PNV_THREAD_NAP 383 bgt 10f 384 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP) 385 /* No return */ 38610: 387 cmpwi r3,PNV_THREAD_SLEEP 388 bgt 2f 389 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP) 390 /* No return */ 391 3922: 393 /* 394 * Go back to winkle. Please note that this thread was woken up in 395 * machine check from winkle and have not restored the per-subcore 396 * state. Hence before going back to winkle, set last bit of HSPRG0 397 * to 1. This will make sure that if this thread gets woken up 398 * again at reset vector 0x100 then it will get chance to restore 399 * the subcore state. 400 */ 401 ori r13,r13,1 402 SET_PACA(r13) 403 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE) 404 /* No return */ 4054: 406#endif 407 /* 408 * Check if we are coming from hypervisor userspace. If yes then we 409 * continue in host kernel in V mode to deliver the MC event. 410 */ 411 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 412 beq 5f 413 andi. r11,r12,MSR_PR /* See if coming from user. */ 414 bne 9f /* continue in V mode if we are. */ 415 4165: 417#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 418 /* 419 * We are coming from kernel context. Check if we are coming from 420 * guest. if yes, then we can continue. We will fall through 421 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 422 */ 423 lbz r11,HSTATE_IN_GUEST(r13) 424 cmpwi r11,0 /* Check if coming from guest */ 425 bne 9f /* continue if we are. */ 426#endif 427 /* 428 * At this point we are not sure about what context we come from. 429 * Queue up the MCE event and return from the interrupt. 430 * But before that, check if this is an un-recoverable exception. 431 * If yes, then stay on emergency stack and panic. 432 */ 433 andi. r11,r12,MSR_RI 434 bne 2f 4351: mfspr r11,SPRN_SRR0 436 LOAD_HANDLER(r10,unrecover_mce) 437 mtspr SPRN_SRR0,r10 438 ld r10,PACAKMSR(r13) 439 /* 440 * We are going down. But there are chances that we might get hit by 441 * another MCE during panic path and we may run into unstable state 442 * with no way out. Hence, turn ME bit off while going down, so that 443 * when another MCE is hit during panic path, system will checkstop 444 * and hypervisor will get restarted cleanly by SP. 445 */ 446 li r3,MSR_ME 447 andc r10,r10,r3 /* Turn off MSR_ME */ 448 mtspr SPRN_SRR1,r10 449 rfid 450 b . 4512: 452 /* 453 * Check if we have successfully handled/recovered from error, if not 454 * then stay on emergency stack and panic. 455 */ 456 ld r3,RESULT(r1) /* Load result */ 457 cmpdi r3,0 /* see if we handled MCE successfully */ 458 459 beq 1b /* if !handled then panic */ 460 /* 461 * Return from MC interrupt. 462 * Queue up the MCE event so that we can log it later, while 463 * returning from kernel or opal call. 464 */ 465 bl machine_check_queue_event 466 MACHINE_CHECK_HANDLER_WINDUP 467 rfid 4689: 469 /* Deliver the machine check to host kernel in V mode. */ 470 MACHINE_CHECK_HANDLER_WINDUP 471 b machine_check_pSeries 472 473EXC_COMMON_BEGIN(unrecover_mce) 474 /* Invoke machine_check_exception to print MCE event and panic. */ 475 addi r3,r1,STACK_FRAME_OVERHEAD 476 bl machine_check_exception 477 /* 478 * We will not reach here. Even if we did, there is no way out. Call 479 * unrecoverable_exception and die. 480 */ 4811: addi r3,r1,STACK_FRAME_OVERHEAD 482 bl unrecoverable_exception 483 b 1b 484 485 486EXC_REAL(data_access, 0x300, 0x80) 487EXC_VIRT(data_access, 0x4300, 0x80, 0x300) 488TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 489 490EXC_COMMON_BEGIN(data_access_common) 491 /* 492 * Here r13 points to the paca, r9 contains the saved CR, 493 * SRR0 and SRR1 are saved in r11 and r12, 494 * r9 - r13 are saved in paca->exgen. 495 */ 496 mfspr r10,SPRN_DAR 497 std r10,PACA_EXGEN+EX_DAR(r13) 498 mfspr r10,SPRN_DSISR 499 stw r10,PACA_EXGEN+EX_DSISR(r13) 500 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 501 RECONCILE_IRQ_STATE(r10, r11) 502 ld r12,_MSR(r1) 503 ld r3,PACA_EXGEN+EX_DAR(r13) 504 lwz r4,PACA_EXGEN+EX_DSISR(r13) 505 li r5,0x300 506 std r3,_DAR(r1) 507 std r4,_DSISR(r1) 508BEGIN_MMU_FTR_SECTION 509 b do_hash_page /* Try to handle as hpte fault */ 510MMU_FTR_SECTION_ELSE 511 b handle_page_fault 512ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 513 514 515EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 516 SET_SCRATCH0(r13) 517 EXCEPTION_PROLOG_0(PACA_EXSLB) 518 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) 519 std r3,PACA_EXSLB+EX_R3(r13) 520 mfspr r3,SPRN_DAR 521 mfspr r12,SPRN_SRR1 522 crset 4*cr6+eq 523#ifndef CONFIG_RELOCATABLE 524 b slb_miss_realmode 525#else 526 /* 527 * We can't just use a direct branch to slb_miss_realmode 528 * because the distance from here to there depends on where 529 * the kernel ends up being put. 530 */ 531 mfctr r11 532 LOAD_HANDLER(r10, slb_miss_realmode) 533 mtctr r10 534 bctr 535#endif 536EXC_REAL_END(data_access_slb, 0x380, 0x80) 537 538EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 539 SET_SCRATCH0(r13) 540 EXCEPTION_PROLOG_0(PACA_EXSLB) 541 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) 542 std r3,PACA_EXSLB+EX_R3(r13) 543 mfspr r3,SPRN_DAR 544 mfspr r12,SPRN_SRR1 545 crset 4*cr6+eq 546#ifndef CONFIG_RELOCATABLE 547 b slb_miss_realmode 548#else 549 /* 550 * We can't just use a direct branch to slb_miss_realmode 551 * because the distance from here to there depends on where 552 * the kernel ends up being put. 553 */ 554 mfctr r11 555 LOAD_HANDLER(r10, slb_miss_realmode) 556 mtctr r10 557 bctr 558#endif 559EXC_VIRT_END(data_access_slb, 0x4380, 0x80) 560TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 561 562 563EXC_REAL(instruction_access, 0x400, 0x80) 564EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 565TRAMP_KVM(PACA_EXGEN, 0x400) 566 567EXC_COMMON_BEGIN(instruction_access_common) 568 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 569 RECONCILE_IRQ_STATE(r10, r11) 570 ld r12,_MSR(r1) 571 ld r3,_NIP(r1) 572 andis. r4,r12,0x5820 573 li r5,0x400 574 std r3,_DAR(r1) 575 std r4,_DSISR(r1) 576BEGIN_MMU_FTR_SECTION 577 b do_hash_page /* Try to handle as hpte fault */ 578MMU_FTR_SECTION_ELSE 579 b handle_page_fault 580ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 581 582 583EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) 584 SET_SCRATCH0(r13) 585 EXCEPTION_PROLOG_0(PACA_EXSLB) 586 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) 587 std r3,PACA_EXSLB+EX_R3(r13) 588 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 589 mfspr r12,SPRN_SRR1 590 crclr 4*cr6+eq 591#ifndef CONFIG_RELOCATABLE 592 b slb_miss_realmode 593#else 594 mfctr r11 595 LOAD_HANDLER(r10, slb_miss_realmode) 596 mtctr r10 597 bctr 598#endif 599EXC_REAL_END(instruction_access_slb, 0x480, 0x80) 600 601EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) 602 SET_SCRATCH0(r13) 603 EXCEPTION_PROLOG_0(PACA_EXSLB) 604 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) 605 std r3,PACA_EXSLB+EX_R3(r13) 606 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 607 mfspr r12,SPRN_SRR1 608 crclr 4*cr6+eq 609#ifndef CONFIG_RELOCATABLE 610 b slb_miss_realmode 611#else 612 mfctr r11 613 LOAD_HANDLER(r10, slb_miss_realmode) 614 mtctr r10 615 bctr 616#endif 617EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) 618TRAMP_KVM(PACA_EXSLB, 0x480) 619 620 621/* This handler is used by both 0x380 and 0x480 slb miss interrupts */ 622EXC_COMMON_BEGIN(slb_miss_realmode) 623 /* 624 * r13 points to the PACA, r9 contains the saved CR, 625 * r12 contain the saved SRR1, SRR0 is still ready for return 626 * r3 has the faulting address 627 * r9 - r13 are saved in paca->exslb. 628 * r3 is saved in paca->slb_r3 629 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss 630 * We assume we aren't going to take any exceptions during this 631 * procedure. 632 */ 633 mflr r10 634#ifdef CONFIG_RELOCATABLE 635 mtctr r11 636#endif 637 638 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 639 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 640 std r3,PACA_EXSLB+EX_DAR(r13) 641 642 crset 4*cr0+eq 643#ifdef CONFIG_PPC_STD_MMU_64 644BEGIN_MMU_FTR_SECTION 645 bl slb_allocate_realmode 646END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) 647#endif 648 649 ld r10,PACA_EXSLB+EX_LR(r13) 650 ld r3,PACA_EXSLB+EX_R3(r13) 651 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 652 mtlr r10 653 654 beq 8f /* if bad address, make full stack frame */ 655 656 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 657 beq- 2f 658 659 /* All done -- return from exception. */ 660 661.machine push 662.machine "power4" 663 mtcrf 0x80,r9 664 mtcrf 0x02,r9 /* I/D indication is in cr6 */ 665 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 666.machine pop 667 668 RESTORE_PPR_PACA(PACA_EXSLB, r9) 669 ld r9,PACA_EXSLB+EX_R9(r13) 670 ld r10,PACA_EXSLB+EX_R10(r13) 671 ld r11,PACA_EXSLB+EX_R11(r13) 672 ld r12,PACA_EXSLB+EX_R12(r13) 673 ld r13,PACA_EXSLB+EX_R13(r13) 674 rfid 675 b . /* prevent speculative execution */ 676 6772: mfspr r11,SPRN_SRR0 678 LOAD_HANDLER(r10,unrecov_slb) 679 mtspr SPRN_SRR0,r10 680 ld r10,PACAKMSR(r13) 681 mtspr SPRN_SRR1,r10 682 rfid 683 b . 684 6858: mfspr r11,SPRN_SRR0 686 LOAD_HANDLER(r10,bad_addr_slb) 687 mtspr SPRN_SRR0,r10 688 ld r10,PACAKMSR(r13) 689 mtspr SPRN_SRR1,r10 690 rfid 691 b . 692 693EXC_COMMON_BEGIN(unrecov_slb) 694 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 695 RECONCILE_IRQ_STATE(r10, r11) 696 bl save_nvgprs 6971: addi r3,r1,STACK_FRAME_OVERHEAD 698 bl unrecoverable_exception 699 b 1b 700 701EXC_COMMON_BEGIN(bad_addr_slb) 702 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) 703 RECONCILE_IRQ_STATE(r10, r11) 704 ld r3, PACA_EXSLB+EX_DAR(r13) 705 std r3, _DAR(r1) 706 beq cr6, 2f 707 li r10, 0x480 /* fix trap number for I-SLB miss */ 708 std r10, _TRAP(r1) 7092: bl save_nvgprs 710 addi r3, r1, STACK_FRAME_OVERHEAD 711 bl slb_miss_bad_addr 712 b ret_from_except 713 714EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 715 .globl hardware_interrupt_hv; 716hardware_interrupt_hv: 717 BEGIN_FTR_SECTION 718 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 719 EXC_HV, SOFTEN_TEST_HV) 720 FTR_SECTION_ELSE 721 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 722 EXC_STD, SOFTEN_TEST_PR) 723 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 724EXC_REAL_END(hardware_interrupt, 0x500, 0x100) 725 726EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 727 .globl hardware_interrupt_relon_hv; 728hardware_interrupt_relon_hv: 729 BEGIN_FTR_SECTION 730 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) 731 FTR_SECTION_ELSE 732 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) 733 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 734EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 735 736TRAMP_KVM(PACA_EXGEN, 0x500) 737TRAMP_KVM_HV(PACA_EXGEN, 0x500) 738EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 739 740 741EXC_REAL(alignment, 0x600, 0x100) 742EXC_VIRT(alignment, 0x4600, 0x100, 0x600) 743TRAMP_KVM(PACA_EXGEN, 0x600) 744EXC_COMMON_BEGIN(alignment_common) 745 mfspr r10,SPRN_DAR 746 std r10,PACA_EXGEN+EX_DAR(r13) 747 mfspr r10,SPRN_DSISR 748 stw r10,PACA_EXGEN+EX_DSISR(r13) 749 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 750 ld r3,PACA_EXGEN+EX_DAR(r13) 751 lwz r4,PACA_EXGEN+EX_DSISR(r13) 752 std r3,_DAR(r1) 753 std r4,_DSISR(r1) 754 bl save_nvgprs 755 RECONCILE_IRQ_STATE(r10, r11) 756 addi r3,r1,STACK_FRAME_OVERHEAD 757 bl alignment_exception 758 b ret_from_except 759 760 761EXC_REAL(program_check, 0x700, 0x100) 762EXC_VIRT(program_check, 0x4700, 0x100, 0x700) 763TRAMP_KVM(PACA_EXGEN, 0x700) 764EXC_COMMON_BEGIN(program_check_common) 765 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 766 bl save_nvgprs 767 RECONCILE_IRQ_STATE(r10, r11) 768 addi r3,r1,STACK_FRAME_OVERHEAD 769 bl program_check_exception 770 b ret_from_except 771 772 773EXC_REAL(fp_unavailable, 0x800, 0x100) 774EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 775TRAMP_KVM(PACA_EXGEN, 0x800) 776EXC_COMMON_BEGIN(fp_unavailable_common) 777 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 778 bne 1f /* if from user, just load it up */ 779 bl save_nvgprs 780 RECONCILE_IRQ_STATE(r10, r11) 781 addi r3,r1,STACK_FRAME_OVERHEAD 782 bl kernel_fp_unavailable_exception 783 BUG_OPCODE 7841: 785#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 786BEGIN_FTR_SECTION 787 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 788 * transaction), go do TM stuff 789 */ 790 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 791 bne- 2f 792END_FTR_SECTION_IFSET(CPU_FTR_TM) 793#endif 794 bl load_up_fpu 795 b fast_exception_return 796#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 7972: /* User process was in a transaction */ 798 bl save_nvgprs 799 RECONCILE_IRQ_STATE(r10, r11) 800 addi r3,r1,STACK_FRAME_OVERHEAD 801 bl fp_unavailable_tm 802 b ret_from_except 803#endif 804 805 806EXC_REAL_MASKABLE(decrementer, 0x900, 0x80) 807EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900) 808TRAMP_KVM(PACA_EXGEN, 0x900) 809EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 810 811 812EXC_REAL_HV(hdecrementer, 0x980, 0x80) 813EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 814TRAMP_KVM_HV(PACA_EXGEN, 0x980) 815EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 816 817 818EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100) 819EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00) 820TRAMP_KVM(PACA_EXGEN, 0xa00) 821#ifdef CONFIG_PPC_DOORBELL 822EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 823#else 824EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 825#endif 826 827 828EXC_REAL(trap_0b, 0xb00, 0x100) 829EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 830TRAMP_KVM(PACA_EXGEN, 0xb00) 831EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 832 833#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 834 /* 835 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems 836 * that support it) before changing to HMT_MEDIUM. That allows the KVM 837 * code to save that value into the guest state (it is the guest's PPR 838 * value). Otherwise just change to HMT_MEDIUM as userspace has 839 * already saved the PPR. 840 */ 841#define SYSCALL_KVMTEST \ 842 SET_SCRATCH0(r13); \ 843 GET_PACA(r13); \ 844 std r9,PACA_EXGEN+EX_R9(r13); \ 845 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 846 HMT_MEDIUM; \ 847 std r10,PACA_EXGEN+EX_R10(r13); \ 848 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 849 mfcr r9; \ 850 KVMTEST_PR(0xc00); \ 851 GET_SCRATCH0(r13) 852 853#else 854#define SYSCALL_KVMTEST \ 855 HMT_MEDIUM 856#endif 857 858#define LOAD_SYSCALL_HANDLER(reg) \ 859 __LOAD_HANDLER(reg, system_call_common) 860 861/* Syscall routine is used twice, in reloc-off and reloc-on paths */ 862#define SYSCALL_PSERIES_1 \ 863BEGIN_FTR_SECTION \ 864 cmpdi r0,0x1ebe ; \ 865 beq- 1f ; \ 866END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 867 mr r9,r13 ; \ 868 GET_PACA(r13) ; \ 869 mfspr r11,SPRN_SRR0 ; \ 8700: 871 872#define SYSCALL_PSERIES_2_RFID \ 873 mfspr r12,SPRN_SRR1 ; \ 874 LOAD_SYSCALL_HANDLER(r10) ; \ 875 mtspr SPRN_SRR0,r10 ; \ 876 ld r10,PACAKMSR(r13) ; \ 877 mtspr SPRN_SRR1,r10 ; \ 878 rfid ; \ 879 b . ; /* prevent speculative execution */ 880 881#define SYSCALL_PSERIES_3 \ 882 /* Fast LE/BE switch system call */ \ 8831: mfspr r12,SPRN_SRR1 ; \ 884 xori r12,r12,MSR_LE ; \ 885 mtspr SPRN_SRR1,r12 ; \ 886 rfid ; /* return to userspace */ \ 887 b . ; /* prevent speculative execution */ 888 889#if defined(CONFIG_RELOCATABLE) 890 /* 891 * We can't branch directly so we do it via the CTR which 892 * is volatile across system calls. 893 */ 894#define SYSCALL_PSERIES_2_DIRECT \ 895 LOAD_SYSCALL_HANDLER(r12) ; \ 896 mtctr r12 ; \ 897 mfspr r12,SPRN_SRR1 ; \ 898 li r10,MSR_RI ; \ 899 mtmsrd r10,1 ; \ 900 bctr ; 901#else 902 /* We can branch directly */ 903#define SYSCALL_PSERIES_2_DIRECT \ 904 mfspr r12,SPRN_SRR1 ; \ 905 li r10,MSR_RI ; \ 906 mtmsrd r10,1 ; /* Set RI (EE=0) */ \ 907 b system_call_common ; 908#endif 909 910EXC_REAL_BEGIN(system_call, 0xc00, 0x100) 911 SYSCALL_KVMTEST 912 SYSCALL_PSERIES_1 913 SYSCALL_PSERIES_2_RFID 914 SYSCALL_PSERIES_3 915EXC_REAL_END(system_call, 0xc00, 0x100) 916 917EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 918 SYSCALL_KVMTEST 919 SYSCALL_PSERIES_1 920 SYSCALL_PSERIES_2_DIRECT 921 SYSCALL_PSERIES_3 922EXC_VIRT_END(system_call, 0x4c00, 0x100) 923 924TRAMP_KVM(PACA_EXGEN, 0xc00) 925 926 927EXC_REAL(single_step, 0xd00, 0x100) 928EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 929TRAMP_KVM(PACA_EXGEN, 0xd00) 930EXC_COMMON(single_step_common, 0xd00, single_step_exception) 931 932EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 933EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 934TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 935EXC_COMMON_BEGIN(h_data_storage_common) 936 mfspr r10,SPRN_HDAR 937 std r10,PACA_EXGEN+EX_DAR(r13) 938 mfspr r10,SPRN_HDSISR 939 stw r10,PACA_EXGEN+EX_DSISR(r13) 940 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) 941 bl save_nvgprs 942 RECONCILE_IRQ_STATE(r10, r11) 943 addi r3,r1,STACK_FRAME_OVERHEAD 944 bl unknown_exception 945 b ret_from_except 946 947 948EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 949EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 950TRAMP_KVM_HV(PACA_EXGEN, 0xe20) 951EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 952 953 954EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 955EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 956TRAMP_KVM_HV(PACA_EXGEN, 0xe40) 957EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 958 959 960/* 961 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 962 * first, and then eventaully from there to the trampoline to get into virtual 963 * mode. 964 */ 965__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) 966__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) 967EXC_VIRT_NONE(0x4e60, 0x20) 968TRAMP_KVM_HV(PACA_EXGEN, 0xe60) 969TRAMP_REAL_BEGIN(hmi_exception_early) 970 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) 971 mr r10,r1 /* Save r1 */ 972 ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 973 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 974 std r9,_CCR(r1) /* save CR in stackframe */ 975 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 976 std r11,_NIP(r1) /* save HSRR0 in stackframe */ 977 mfspr r12,SPRN_HSRR1 /* Save SRR1 */ 978 std r12,_MSR(r1) /* save SRR1 in stackframe */ 979 std r10,0(r1) /* make stack chain pointer */ 980 std r0,GPR0(r1) /* save r0 in stackframe */ 981 std r10,GPR1(r1) /* save r1 in stackframe */ 982 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 983 EXCEPTION_PROLOG_COMMON_3(0xe60) 984 addi r3,r1,STACK_FRAME_OVERHEAD 985 BRANCH_LINK_TO_FAR(r4, hmi_exception_realmode) 986 /* Windup the stack. */ 987 /* Move original HSRR0 and HSRR1 into the respective regs */ 988 ld r9,_MSR(r1) 989 mtspr SPRN_HSRR1,r9 990 ld r3,_NIP(r1) 991 mtspr SPRN_HSRR0,r3 992 ld r9,_CTR(r1) 993 mtctr r9 994 ld r9,_XER(r1) 995 mtxer r9 996 ld r9,_LINK(r1) 997 mtlr r9 998 REST_GPR(0, r1) 999 REST_8GPRS(2, r1) 1000 REST_GPR(10, r1) 1001 ld r11,_CCR(r1) 1002 mtcr r11 1003 REST_GPR(11, r1) 1004 REST_2GPRS(12, r1) 1005 /* restore original r1. */ 1006 ld r1,GPR1(r1) 1007 1008 /* 1009 * Go to virtual mode and pull the HMI event information from 1010 * firmware. 1011 */ 1012 .globl hmi_exception_after_realmode 1013hmi_exception_after_realmode: 1014 SET_SCRATCH0(r13) 1015 EXCEPTION_PROLOG_0(PACA_EXGEN) 1016 b tramp_real_hmi_exception 1017 1018EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) 1019 1020 1021EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20) 1022EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80) 1023TRAMP_KVM_HV(PACA_EXGEN, 0xe80) 1024#ifdef CONFIG_PPC_DOORBELL 1025EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 1026#else 1027EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 1028#endif 1029 1030 1031EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20) 1032EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0) 1033TRAMP_KVM_HV(PACA_EXGEN, 0xea0) 1034EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 1035 1036 1037EXC_REAL_NONE(0xec0, 0x20) 1038EXC_VIRT_NONE(0x4ec0, 0x20) 1039EXC_REAL_NONE(0xee0, 0x20) 1040EXC_VIRT_NONE(0x4ee0, 0x20) 1041 1042 1043EXC_REAL_OOL(performance_monitor, 0xf00, 0x20) 1044EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00) 1045TRAMP_KVM(PACA_EXGEN, 0xf00) 1046EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1047 1048 1049EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 1050EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1051TRAMP_KVM(PACA_EXGEN, 0xf20) 1052EXC_COMMON_BEGIN(altivec_unavailable_common) 1053 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1054#ifdef CONFIG_ALTIVEC 1055BEGIN_FTR_SECTION 1056 beq 1f 1057#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1058 BEGIN_FTR_SECTION_NESTED(69) 1059 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1060 * transaction), go do TM stuff 1061 */ 1062 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1063 bne- 2f 1064 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1065#endif 1066 bl load_up_altivec 1067 b fast_exception_return 1068#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 10692: /* User process was in a transaction */ 1070 bl save_nvgprs 1071 RECONCILE_IRQ_STATE(r10, r11) 1072 addi r3,r1,STACK_FRAME_OVERHEAD 1073 bl altivec_unavailable_tm 1074 b ret_from_except 1075#endif 10761: 1077END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1078#endif 1079 bl save_nvgprs 1080 RECONCILE_IRQ_STATE(r10, r11) 1081 addi r3,r1,STACK_FRAME_OVERHEAD 1082 bl altivec_unavailable_exception 1083 b ret_from_except 1084 1085 1086EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 1087EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1088TRAMP_KVM(PACA_EXGEN, 0xf40) 1089EXC_COMMON_BEGIN(vsx_unavailable_common) 1090 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 1091#ifdef CONFIG_VSX 1092BEGIN_FTR_SECTION 1093 beq 1f 1094#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1095 BEGIN_FTR_SECTION_NESTED(69) 1096 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1097 * transaction), go do TM stuff 1098 */ 1099 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1100 bne- 2f 1101 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1102#endif 1103 b load_up_vsx 1104#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 11052: /* User process was in a transaction */ 1106 bl save_nvgprs 1107 RECONCILE_IRQ_STATE(r10, r11) 1108 addi r3,r1,STACK_FRAME_OVERHEAD 1109 bl vsx_unavailable_tm 1110 b ret_from_except 1111#endif 11121: 1113END_FTR_SECTION_IFSET(CPU_FTR_VSX) 1114#endif 1115 bl save_nvgprs 1116 RECONCILE_IRQ_STATE(r10, r11) 1117 addi r3,r1,STACK_FRAME_OVERHEAD 1118 bl vsx_unavailable_exception 1119 b ret_from_except 1120 1121 1122EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 1123EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 1124TRAMP_KVM(PACA_EXGEN, 0xf60) 1125EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 1126 1127 1128EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 1129EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 1130TRAMP_KVM_HV(PACA_EXGEN, 0xf80) 1131EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 1132 1133 1134EXC_REAL_NONE(0xfa0, 0x20) 1135EXC_VIRT_NONE(0x4fa0, 0x20) 1136EXC_REAL_NONE(0xfc0, 0x20) 1137EXC_VIRT_NONE(0x4fc0, 0x20) 1138EXC_REAL_NONE(0xfe0, 0x20) 1139EXC_VIRT_NONE(0x4fe0, 0x20) 1140 1141EXC_REAL_NONE(0x1000, 0x100) 1142EXC_VIRT_NONE(0x5000, 0x100) 1143EXC_REAL_NONE(0x1100, 0x100) 1144EXC_VIRT_NONE(0x5100, 0x100) 1145 1146#ifdef CONFIG_CBE_RAS 1147EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 1148EXC_VIRT_NONE(0x5200, 0x100) 1149TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1150EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1151#else /* CONFIG_CBE_RAS */ 1152EXC_REAL_NONE(0x1200, 0x100) 1153EXC_VIRT_NONE(0x5200, 0x100) 1154#endif 1155 1156 1157EXC_REAL(instruction_breakpoint, 0x1300, 0x100) 1158EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1159TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 1160EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 1161 1162EXC_REAL_NONE(0x1400, 0x100) 1163EXC_VIRT_NONE(0x5400, 0x100) 1164 1165EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 1166 mtspr SPRN_SPRG_HSCRATCH0,r13 1167 EXCEPTION_PROLOG_0(PACA_EXGEN) 1168 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) 1169 1170#ifdef CONFIG_PPC_DENORMALISATION 1171 mfspr r10,SPRN_HSRR1 1172 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 1173 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1174 addi r11,r11,-4 /* HSRR0 is next instruction */ 1175 bne+ denorm_assist 1176#endif 1177 1178 KVMTEST_PR(0x1500) 1179 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) 1180EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1181 1182#ifdef CONFIG_PPC_DENORMALISATION 1183EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1184 b exc_real_0x1500_denorm_exception_hv 1185EXC_VIRT_END(denorm_exception, 0x5500, 0x100) 1186#else 1187EXC_VIRT_NONE(0x5500, 0x100) 1188#endif 1189 1190TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) 1191 1192#ifdef CONFIG_PPC_DENORMALISATION 1193TRAMP_REAL_BEGIN(denorm_assist) 1194BEGIN_FTR_SECTION 1195/* 1196 * To denormalise we need to move a copy of the register to itself. 1197 * For POWER6 do that here for all FP regs. 1198 */ 1199 mfmsr r10 1200 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1201 xori r10,r10,(MSR_FE0|MSR_FE1) 1202 mtmsrd r10 1203 sync 1204 1205#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 1206#define FMR4(n) FMR2(n) ; FMR2(n+2) 1207#define FMR8(n) FMR4(n) ; FMR4(n+4) 1208#define FMR16(n) FMR8(n) ; FMR8(n+8) 1209#define FMR32(n) FMR16(n) ; FMR16(n+16) 1210 FMR32(0) 1211 1212FTR_SECTION_ELSE 1213/* 1214 * To denormalise we need to move a copy of the register to itself. 1215 * For POWER7 do that here for the first 32 VSX registers only. 1216 */ 1217 mfmsr r10 1218 oris r10,r10,MSR_VSX@h 1219 mtmsrd r10 1220 sync 1221 1222#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) 1223#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) 1224#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) 1225#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) 1226#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) 1227 XVCPSGNDP32(0) 1228 1229ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1230 1231BEGIN_FTR_SECTION 1232 b denorm_done 1233END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1234/* 1235 * To denormalise we need to move a copy of the register to itself. 1236 * For POWER8 we need to do that for all 64 VSX registers 1237 */ 1238 XVCPSGNDP32(32) 1239denorm_done: 1240 mtspr SPRN_HSRR0,r11 1241 mtcrf 0x80,r9 1242 ld r9,PACA_EXGEN+EX_R9(r13) 1243 RESTORE_PPR_PACA(PACA_EXGEN, r10) 1244BEGIN_FTR_SECTION 1245 ld r10,PACA_EXGEN+EX_CFAR(r13) 1246 mtspr SPRN_CFAR,r10 1247END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1248 ld r10,PACA_EXGEN+EX_R10(r13) 1249 ld r11,PACA_EXGEN+EX_R11(r13) 1250 ld r12,PACA_EXGEN+EX_R12(r13) 1251 ld r13,PACA_EXGEN+EX_R13(r13) 1252 HRFID 1253 b . 1254#endif 1255 1256EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) 1257 1258 1259#ifdef CONFIG_CBE_RAS 1260EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 1261EXC_VIRT_NONE(0x5600, 0x100) 1262TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 1263EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1264#else /* CONFIG_CBE_RAS */ 1265EXC_REAL_NONE(0x1600, 0x100) 1266EXC_VIRT_NONE(0x5600, 0x100) 1267#endif 1268 1269 1270EXC_REAL(altivec_assist, 0x1700, 0x100) 1271EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 1272TRAMP_KVM(PACA_EXGEN, 0x1700) 1273#ifdef CONFIG_ALTIVEC 1274EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 1275#else 1276EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 1277#endif 1278 1279 1280#ifdef CONFIG_CBE_RAS 1281EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 1282EXC_VIRT_NONE(0x5800, 0x100) 1283TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 1284EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 1285#else /* CONFIG_CBE_RAS */ 1286EXC_REAL_NONE(0x1800, 0x100) 1287EXC_VIRT_NONE(0x5800, 0x100) 1288#endif 1289 1290 1291/* 1292 * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 1293 * - If it was a decrementer interrupt, we bump the dec to max and and return. 1294 * - If it was a doorbell we return immediately since doorbells are edge 1295 * triggered and won't automatically refire. 1296 * - If it was a HMI we return immediately since we handled it in realmode 1297 * and it won't refire. 1298 * - else we hard disable and return. 1299 * This is called with r10 containing the value to OR to the paca field. 1300 */ 1301#define MASKED_INTERRUPT(_H) \ 1302masked_##_H##interrupt: \ 1303 std r11,PACA_EXGEN+EX_R11(r13); \ 1304 lbz r11,PACAIRQHAPPENED(r13); \ 1305 or r11,r11,r10; \ 1306 stb r11,PACAIRQHAPPENED(r13); \ 1307 cmpwi r10,PACA_IRQ_DEC; \ 1308 bne 1f; \ 1309 lis r10,0x7fff; \ 1310 ori r10,r10,0xffff; \ 1311 mtspr SPRN_DEC,r10; \ 1312 b 2f; \ 13131: cmpwi r10,PACA_IRQ_DBELL; \ 1314 beq 2f; \ 1315 cmpwi r10,PACA_IRQ_HMI; \ 1316 beq 2f; \ 1317 mfspr r10,SPRN_##_H##SRR1; \ 1318 rldicl r10,r10,48,1; /* clear MSR_EE */ \ 1319 rotldi r10,r10,16; \ 1320 mtspr SPRN_##_H##SRR1,r10; \ 13212: mtcrf 0x80,r9; \ 1322 ld r9,PACA_EXGEN+EX_R9(r13); \ 1323 ld r10,PACA_EXGEN+EX_R10(r13); \ 1324 ld r11,PACA_EXGEN+EX_R11(r13); \ 1325 GET_SCRATCH0(r13); \ 1326 ##_H##rfid; \ 1327 b . 1328 1329/* 1330 * Real mode exceptions actually use this too, but alternate 1331 * instruction code patches (which end up in the common .text area) 1332 * cannot reach these if they are put there. 1333 */ 1334USE_FIXED_SECTION(virt_trampolines) 1335 MASKED_INTERRUPT() 1336 MASKED_INTERRUPT(H) 1337 1338#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1339TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 1340 /* 1341 * Here all GPRs are unchanged from when the interrupt happened 1342 * except for r13, which is saved in SPRG_SCRATCH0. 1343 */ 1344 mfspr r13, SPRN_SRR0 1345 addi r13, r13, 4 1346 mtspr SPRN_SRR0, r13 1347 GET_SCRATCH0(r13) 1348 rfid 1349 b . 1350 1351TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 1352 /* 1353 * Here all GPRs are unchanged from when the interrupt happened 1354 * except for r13, which is saved in SPRG_SCRATCH0. 1355 */ 1356 mfspr r13, SPRN_HSRR0 1357 addi r13, r13, 4 1358 mtspr SPRN_HSRR0, r13 1359 GET_SCRATCH0(r13) 1360 hrfid 1361 b . 1362#endif 1363 1364/* 1365 * Ensure that any handlers that get invoked from the exception prologs 1366 * above are below the first 64KB (0x10000) of the kernel image because 1367 * the prologs assemble the addresses of these handlers using the 1368 * LOAD_HANDLER macro, which uses an ori instruction. 1369 */ 1370 1371/*** Common interrupt handlers ***/ 1372 1373 1374 /* 1375 * Relocation-on interrupts: A subset of the interrupts can be delivered 1376 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 1377 * it. Addresses are the same as the original interrupt addresses, but 1378 * offset by 0xc000000000004000. 1379 * It's impossible to receive interrupts below 0x300 via this mechanism. 1380 * KVM: None of these traps are from the guest ; anything that escalated 1381 * to HV=1 from HV=0 is delivered via real mode handlers. 1382 */ 1383 1384 /* 1385 * This uses the standard macro, since the original 0x300 vector 1386 * only has extra guff for STAB-based processors -- which never 1387 * come here. 1388 */ 1389 1390EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 1391 b __ppc64_runlatch_on 1392 1393USE_FIXED_SECTION(virt_trampolines) 1394 /* 1395 * The __end_interrupts marker must be past the out-of-line (OOL) 1396 * handlers, so that they are copied to real address 0x100 when running 1397 * a relocatable kernel. This ensures they can be reached from the short 1398 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 1399 * directly, without using LOAD_HANDLER(). 1400 */ 1401 .align 7 1402 .globl __end_interrupts 1403__end_interrupts: 1404DEFINE_FIXED_SYMBOL(__end_interrupts) 1405 1406#ifdef CONFIG_PPC_970_NAP 1407EXC_COMMON_BEGIN(power4_fixup_nap) 1408 andc r9,r9,r10 1409 std r9,TI_LOCAL_FLAGS(r11) 1410 ld r10,_LINK(r1) /* make idle task do the */ 1411 std r10,_NIP(r1) /* equivalent of a blr */ 1412 blr 1413#endif 1414 1415CLOSE_FIXED_SECTION(real_vectors); 1416CLOSE_FIXED_SECTION(real_trampolines); 1417CLOSE_FIXED_SECTION(virt_vectors); 1418CLOSE_FIXED_SECTION(virt_trampolines); 1419 1420USE_TEXT_SECTION() 1421 1422/* 1423 * Hash table stuff 1424 */ 1425 .balign IFETCH_ALIGN_BYTES 1426do_hash_page: 1427#ifdef CONFIG_PPC_STD_MMU_64 1428 andis. r0,r4,0xa410 /* weird error? */ 1429 bne- handle_page_fault /* if not, try to insert a HPTE */ 1430 andis. r0,r4,DSISR_DABRMATCH@h 1431 bne- handle_dabr_fault 1432 CURRENT_THREAD_INFO(r11, r1) 1433 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 1434 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 1435 bne 77f /* then don't call hash_page now */ 1436 1437 /* 1438 * r3 contains the faulting address 1439 * r4 msr 1440 * r5 contains the trap number 1441 * r6 contains dsisr 1442 * 1443 * at return r3 = 0 for success, 1 for page fault, negative for error 1444 */ 1445 mr r4,r12 1446 ld r6,_DSISR(r1) 1447 bl __hash_page /* build HPTE if possible */ 1448 cmpdi r3,0 /* see if __hash_page succeeded */ 1449 1450 /* Success */ 1451 beq fast_exc_return_irq /* Return from exception on success */ 1452 1453 /* Error */ 1454 blt- 13f 1455#endif /* CONFIG_PPC_STD_MMU_64 */ 1456 1457/* Here we have a page fault that hash_page can't handle. */ 1458handle_page_fault: 145911: ld r4,_DAR(r1) 1460 ld r5,_DSISR(r1) 1461 addi r3,r1,STACK_FRAME_OVERHEAD 1462 bl do_page_fault 1463 cmpdi r3,0 1464 beq+ 12f 1465 bl save_nvgprs 1466 mr r5,r3 1467 addi r3,r1,STACK_FRAME_OVERHEAD 1468 lwz r4,_DAR(r1) 1469 bl bad_page_fault 1470 b ret_from_except 1471 1472/* We have a data breakpoint exception - handle it */ 1473handle_dabr_fault: 1474 bl save_nvgprs 1475 ld r4,_DAR(r1) 1476 ld r5,_DSISR(r1) 1477 addi r3,r1,STACK_FRAME_OVERHEAD 1478 bl do_break 147912: b ret_from_except_lite 1480 1481 1482#ifdef CONFIG_PPC_STD_MMU_64 1483/* We have a page fault that hash_page could handle but HV refused 1484 * the PTE insertion 1485 */ 148613: bl save_nvgprs 1487 mr r5,r3 1488 addi r3,r1,STACK_FRAME_OVERHEAD 1489 ld r4,_DAR(r1) 1490 bl low_hash_fault 1491 b ret_from_except 1492#endif 1493 1494/* 1495 * We come here as a result of a DSI at a point where we don't want 1496 * to call hash_page, such as when we are accessing memory (possibly 1497 * user memory) inside a PMU interrupt that occurred while interrupts 1498 * were soft-disabled. We want to invoke the exception handler for 1499 * the access, or panic if there isn't a handler. 1500 */ 150177: bl save_nvgprs 1502 mr r4,r3 1503 addi r3,r1,STACK_FRAME_OVERHEAD 1504 li r5,SIGSEGV 1505 bl bad_page_fault 1506 b ret_from_except 1507 1508/* 1509 * Here we have detected that the kernel stack pointer is bad. 1510 * R9 contains the saved CR, r13 points to the paca, 1511 * r10 contains the (bad) kernel stack pointer, 1512 * r11 and r12 contain the saved SRR0 and SRR1. 1513 * We switch to using an emergency stack, save the registers there, 1514 * and call kernel_bad_stack(), which panics. 1515 */ 1516bad_stack: 1517 ld r1,PACAEMERGSP(r13) 1518 subi r1,r1,64+INT_FRAME_SIZE 1519 std r9,_CCR(r1) 1520 std r10,GPR1(r1) 1521 std r11,_NIP(r1) 1522 std r12,_MSR(r1) 1523 mfspr r11,SPRN_DAR 1524 mfspr r12,SPRN_DSISR 1525 std r11,_DAR(r1) 1526 std r12,_DSISR(r1) 1527 mflr r10 1528 mfctr r11 1529 mfxer r12 1530 std r10,_LINK(r1) 1531 std r11,_CTR(r1) 1532 std r12,_XER(r1) 1533 SAVE_GPR(0,r1) 1534 SAVE_GPR(2,r1) 1535 ld r10,EX_R3(r3) 1536 std r10,GPR3(r1) 1537 SAVE_GPR(4,r1) 1538 SAVE_4GPRS(5,r1) 1539 ld r9,EX_R9(r3) 1540 ld r10,EX_R10(r3) 1541 SAVE_2GPRS(9,r1) 1542 ld r9,EX_R11(r3) 1543 ld r10,EX_R12(r3) 1544 ld r11,EX_R13(r3) 1545 std r9,GPR11(r1) 1546 std r10,GPR12(r1) 1547 std r11,GPR13(r1) 1548BEGIN_FTR_SECTION 1549 ld r10,EX_CFAR(r3) 1550 std r10,ORIG_GPR3(r1) 1551END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1552 SAVE_8GPRS(14,r1) 1553 SAVE_10GPRS(22,r1) 1554 lhz r12,PACA_TRAP_SAVE(r13) 1555 std r12,_TRAP(r1) 1556 addi r11,r1,INT_FRAME_SIZE 1557 std r11,0(r1) 1558 li r12,0 1559 std r12,0(r11) 1560 ld r2,PACATOC(r13) 1561 ld r11,exception_marker@toc(r2) 1562 std r12,RESULT(r1) 1563 std r11,STACK_FRAME_OVERHEAD-16(r1) 15641: addi r3,r1,STACK_FRAME_OVERHEAD 1565 bl kernel_bad_stack 1566 b 1b 1567 1568/* 1569 * Called from arch_local_irq_enable when an interrupt needs 1570 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 1571 * which kind of interrupt. MSR:EE is already off. We generate a 1572 * stackframe like if a real interrupt had happened. 1573 * 1574 * Note: While MSR:EE is off, we need to make sure that _MSR 1575 * in the generated frame has EE set to 1 or the exception 1576 * handler will not properly re-enable them. 1577 */ 1578_GLOBAL(__replay_interrupt) 1579 /* We are going to jump to the exception common code which 1580 * will retrieve various register values from the PACA which 1581 * we don't give a damn about, so we don't bother storing them. 1582 */ 1583 mfmsr r12 1584 mflr r11 1585 mfcr r9 1586 ori r12,r12,MSR_EE 1587 cmpwi r3,0x900 1588 beq decrementer_common 1589 cmpwi r3,0x500 1590 beq hardware_interrupt_common 1591BEGIN_FTR_SECTION 1592 cmpwi r3,0xe80 1593 beq h_doorbell_common 1594 cmpwi r3,0xea0 1595 beq h_virt_irq_common 1596 cmpwi r3,0xe60 1597 beq hmi_exception_common 1598FTR_SECTION_ELSE 1599 cmpwi r3,0xa00 1600 beq doorbell_super_common 1601ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1602 blr 1603