1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This file contains the 64-bit "server" PowerPC variant 4 * of the low level exception handling including exception 5 * vectors, exception return, part of the slb and stab 6 * handling and other fixed offset specific things. 7 * 8 * This file is meant to be #included from head_64.S due to 9 * position dependent assembly. 10 * 11 * Most of this originates from head_64.S and thus has the same 12 * copyright history. 13 * 14 */ 15 16#include <asm/hw_irq.h> 17#include <asm/exception-64s.h> 18#include <asm/ptrace.h> 19#include <asm/cpuidle.h> 20#include <asm/head-64.h> 21#include <asm/feature-fixups.h> 22#include <asm/kup.h> 23 24/* 25 * Following are fixed section helper macros. 26 * 27 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors 28 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors 29 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these) 30 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use) 31 * EXC_COMMON - After switching to virtual, relocated mode. 32 */ 33 34#define EXC_REAL_BEGIN(name, start, size) \ 35 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size) 36 37#define EXC_REAL_END(name, start, size) \ 38 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size) 39 40#define EXC_VIRT_BEGIN(name, start, size) \ 41 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size) 42 43#define EXC_VIRT_END(name, start, size) \ 44 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size) 45 46#define EXC_COMMON_BEGIN(name) \ 47 USE_TEXT_SECTION(); \ 48 .balign IFETCH_ALIGN_BYTES; \ 49 .global name; \ 50 _ASM_NOKPROBE_SYMBOL(name); \ 51 DEFINE_FIXED_SYMBOL(name); \ 52name: 53 54#define TRAMP_REAL_BEGIN(name) \ 55 FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name) 56 57#define TRAMP_VIRT_BEGIN(name) \ 58 FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name) 59 60#define EXC_REAL_NONE(start, size) \ 61 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \ 62 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size) 63 64#define EXC_VIRT_NONE(start, size) \ 65 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \ 66 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size) 67 68/* 69 * We're short on space and time in the exception prolog, so we can't 70 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 71 * Instead we get the base of the kernel from paca->kernelbase and or in the low 72 * part of label. This requires that the label be within 64KB of kernelbase, and 73 * that kernelbase be 64K aligned. 74 */ 75#define LOAD_HANDLER(reg, label) \ 76 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 77 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) 78 79#define __LOAD_HANDLER(reg, label) \ 80 ld reg,PACAKBASE(r13); \ 81 ori reg,reg,(ABS_ADDR(label))@l 82 83/* 84 * Branches from unrelocated code (e.g., interrupts) to labels outside 85 * head-y require >64K offsets. 86 */ 87#define __LOAD_FAR_HANDLER(reg, label) \ 88 ld reg,PACAKBASE(r13); \ 89 ori reg,reg,(ABS_ADDR(label))@l; \ 90 addis reg,reg,(ABS_ADDR(label))@h 91 92/* 93 * Branch to label using its 0xC000 address. This results in instruction 94 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 95 * on using mtmsr rather than rfid. 96 * 97 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 98 * load KBASE for a slight optimisation. 99 */ 100#define BRANCH_TO_C000(reg, label) \ 101 __LOAD_FAR_HANDLER(reg, label); \ 102 mtctr reg; \ 103 bctr 104 105/* 106 * Interrupt code generation macros 107 */ 108#define IVEC .L_IVEC_\name\() /* Interrupt vector address */ 109#define IHSRR .L_IHSRR_\name\() /* Sets SRR or HSRR registers */ 110#define IHSRR_IF_HVMODE .L_IHSRR_IF_HVMODE_\name\() /* HSRR if HV else SRR */ 111#define IAREA .L_IAREA_\name\() /* PACA save area */ 112#define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point */ 113#define IISIDE .L_IISIDE_\name\() /* Uses SRR0/1 not DAR/DSISR */ 114#define IDAR .L_IDAR_\name\() /* Uses DAR (or SRR0) */ 115#define IDSISR .L_IDSISR_\name\() /* Uses DSISR (or SRR1) */ 116#define ISET_RI .L_ISET_RI_\name\() /* Run common code w/ MSR[RI]=1 */ 117#define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */ 118#define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */ 119#define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */ 120#define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */ 121#define __IKVM_REAL(name) .L_IKVM_REAL_ ## name 122#define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */ 123#define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */ 124#define __ISTACK(name) .L_ISTACK_ ## name 125#define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */ 126 127#define INT_DEFINE_BEGIN(n) \ 128.macro int_define_ ## n name 129 130#define INT_DEFINE_END(n) \ 131.endm ; \ 132int_define_ ## n n ; \ 133do_define_int n 134 135.macro do_define_int name 136 .ifndef IVEC 137 .error "IVEC not defined" 138 .endif 139 .ifndef IHSRR 140 IHSRR=0 141 .endif 142 .ifndef IHSRR_IF_HVMODE 143 IHSRR_IF_HVMODE=0 144 .endif 145 .ifndef IAREA 146 IAREA=PACA_EXGEN 147 .endif 148 .ifndef IVIRT 149 IVIRT=1 150 .endif 151 .ifndef IISIDE 152 IISIDE=0 153 .endif 154 .ifndef IDAR 155 IDAR=0 156 .endif 157 .ifndef IDSISR 158 IDSISR=0 159 .endif 160 .ifndef ISET_RI 161 ISET_RI=1 162 .endif 163 .ifndef IBRANCH_TO_COMMON 164 IBRANCH_TO_COMMON=1 165 .endif 166 .ifndef IREALMODE_COMMON 167 IREALMODE_COMMON=0 168 .else 169 .if ! IBRANCH_TO_COMMON 170 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0" 171 .endif 172 .endif 173 .ifndef IMASK 174 IMASK=0 175 .endif 176 .ifndef IKVM_REAL 177 IKVM_REAL=0 178 .endif 179 .ifndef IKVM_VIRT 180 IKVM_VIRT=0 181 .endif 182 .ifndef ISTACK 183 ISTACK=1 184 .endif 185 .ifndef IKUAP 186 IKUAP=1 187 .endif 188.endm 189 190/* 191 * All interrupts which set HSRR registers, as well as SRESET and MCE and 192 * syscall when invoked with "sc 1" switch to MSR[HV]=1 (HVMODE) to be taken, 193 * so they all generally need to test whether they were taken in guest context. 194 * 195 * Note: SRESET and MCE may also be sent to the guest by the hypervisor, and be 196 * taken with MSR[HV]=0. 197 * 198 * Interrupts which set SRR registers (with the above exceptions) do not 199 * elevate to MSR[HV]=1 mode, though most can be taken when running with 200 * MSR[HV]=1 (e.g., bare metal kernel and userspace). So these interrupts do 201 * not need to test whether a guest is running because they get delivered to 202 * the guest directly, including nested HV KVM guests. 203 * 204 * The exception is PR KVM, where the guest runs with MSR[PR]=1 and the host 205 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the 206 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be 207 * delivered to the real-mode entry point, therefore such interrupts only test 208 * KVM in their real mode handlers, and only when PR KVM is possible. 209 * 210 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always 211 * delivered in real-mode when the MMU is in hash mode because the MMU 212 * registers are not set appropriately to translate host addresses. In nested 213 * radix mode these can be delivered in virt-mode as the host translations are 214 * used implicitly (see: effective LPID, effective PID). 215 */ 216 217/* 218 * If an interrupt is taken while a guest is running, it is immediately routed 219 * to KVM to handle. 220 */ 221 222.macro KVMTEST name handler 223#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 224 lbz r10,HSTATE_IN_GUEST(r13) 225 cmpwi r10,0 226 /* HSRR variants have the 0x2 bit added to their trap number */ 227 .if IHSRR_IF_HVMODE 228 BEGIN_FTR_SECTION 229 li r10,(IVEC + 0x2) 230 FTR_SECTION_ELSE 231 li r10,(IVEC) 232 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 233 .elseif IHSRR 234 li r10,(IVEC + 0x2) 235 .else 236 li r10,(IVEC) 237 .endif 238 bne \handler 239#endif 240.endm 241 242/* 243 * This is the BOOK3S interrupt entry code macro. 244 * 245 * This can result in one of several things happening: 246 * - Branch to the _common handler, relocated, in virtual mode. 247 * These are normal interrupts (synchronous and asynchronous) handled by 248 * the kernel. 249 * - Branch to KVM, relocated but real mode interrupts remain in real mode. 250 * These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by 251 * / intended for host or guest kernel, but KVM must always be involved 252 * because the machine state is set for guest execution. 253 * - Branch to the masked handler, unrelocated. 254 * These occur when maskable asynchronous interrupts are taken with the 255 * irq_soft_mask set. 256 * - Branch to an "early" handler in real mode but relocated. 257 * This is done if early=1. MCE and HMI use these to handle errors in real 258 * mode. 259 * - Fall through and continue executing in real, unrelocated mode. 260 * This is done if early=2. 261 */ 262 263.macro GEN_BRANCH_TO_COMMON name, virt 264 .if IREALMODE_COMMON 265 LOAD_HANDLER(r10, \name\()_common) 266 mtctr r10 267 bctr 268 .else 269 .if \virt 270#ifndef CONFIG_RELOCATABLE 271 b \name\()_common_virt 272#else 273 LOAD_HANDLER(r10, \name\()_common_virt) 274 mtctr r10 275 bctr 276#endif 277 .else 278 LOAD_HANDLER(r10, \name\()_common_real) 279 mtctr r10 280 bctr 281 .endif 282 .endif 283.endm 284 285.macro GEN_INT_ENTRY name, virt, ool=0 286 SET_SCRATCH0(r13) /* save r13 */ 287 GET_PACA(r13) 288 std r9,IAREA+EX_R9(r13) /* save r9 */ 289BEGIN_FTR_SECTION 290 mfspr r9,SPRN_PPR 291END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 292 HMT_MEDIUM 293 std r10,IAREA+EX_R10(r13) /* save r10 - r12 */ 294BEGIN_FTR_SECTION 295 mfspr r10,SPRN_CFAR 296END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 297 .if \ool 298 .if !\virt 299 b tramp_real_\name 300 .pushsection .text 301 TRAMP_REAL_BEGIN(tramp_real_\name) 302 .else 303 b tramp_virt_\name 304 .pushsection .text 305 TRAMP_VIRT_BEGIN(tramp_virt_\name) 306 .endif 307 .endif 308 309BEGIN_FTR_SECTION 310 std r9,IAREA+EX_PPR(r13) 311END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 312BEGIN_FTR_SECTION 313 std r10,IAREA+EX_CFAR(r13) 314END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 315 INTERRUPT_TO_KERNEL 316 mfctr r10 317 std r10,IAREA+EX_CTR(r13) 318 mfcr r9 319 std r11,IAREA+EX_R11(r13) 320 std r12,IAREA+EX_R12(r13) 321 322 /* 323 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI], 324 * because a d-side MCE will clobber those registers so is 325 * not recoverable if they are live. 326 */ 327 GET_SCRATCH0(r10) 328 std r10,IAREA+EX_R13(r13) 329 .if IDAR && !IISIDE 330 .if IHSRR 331 mfspr r10,SPRN_HDAR 332 .else 333 mfspr r10,SPRN_DAR 334 .endif 335 std r10,IAREA+EX_DAR(r13) 336 .endif 337 .if IDSISR && !IISIDE 338 .if IHSRR 339 mfspr r10,SPRN_HDSISR 340 .else 341 mfspr r10,SPRN_DSISR 342 .endif 343 stw r10,IAREA+EX_DSISR(r13) 344 .endif 345 346 .if IHSRR_IF_HVMODE 347 BEGIN_FTR_SECTION 348 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 349 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 350 FTR_SECTION_ELSE 351 mfspr r11,SPRN_SRR0 /* save SRR0 */ 352 mfspr r12,SPRN_SRR1 /* and SRR1 */ 353 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 354 .elseif IHSRR 355 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 356 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 357 .else 358 mfspr r11,SPRN_SRR0 /* save SRR0 */ 359 mfspr r12,SPRN_SRR1 /* and SRR1 */ 360 .endif 361 362 .if IBRANCH_TO_COMMON 363 GEN_BRANCH_TO_COMMON \name \virt 364 .endif 365 366 .if \ool 367 .popsection 368 .endif 369.endm 370 371/* 372 * __GEN_COMMON_ENTRY is required to receive the branch from interrupt 373 * entry, except in the case of the real-mode handlers which require 374 * __GEN_REALMODE_COMMON_ENTRY. 375 * 376 * This switches to virtual mode and sets MSR[RI]. 377 */ 378.macro __GEN_COMMON_ENTRY name 379DEFINE_FIXED_SYMBOL(\name\()_common_real) 380\name\()_common_real: 381 .if IKVM_REAL 382 KVMTEST \name kvm_interrupt 383 .endif 384 385 ld r10,PACAKMSR(r13) /* get MSR value for kernel */ 386 /* MSR[RI] is clear iff using SRR regs */ 387 .if IHSRR_IF_HVMODE 388 BEGIN_FTR_SECTION 389 xori r10,r10,MSR_RI 390 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 391 .elseif ! IHSRR 392 xori r10,r10,MSR_RI 393 .endif 394 mtmsrd r10 395 396 .if IVIRT 397 .if IKVM_VIRT 398 b 1f /* skip the virt test coming from real */ 399 .endif 400 401 .balign IFETCH_ALIGN_BYTES 402DEFINE_FIXED_SYMBOL(\name\()_common_virt) 403\name\()_common_virt: 404 .if IKVM_VIRT 405 KVMTEST \name kvm_interrupt 4061: 407 .endif 408 .endif /* IVIRT */ 409.endm 410 411/* 412 * Don't switch to virt mode. Used for early MCE and HMI handlers that 413 * want to run in real mode. 414 */ 415.macro __GEN_REALMODE_COMMON_ENTRY name 416DEFINE_FIXED_SYMBOL(\name\()_common_real) 417\name\()_common_real: 418 .if IKVM_REAL 419 KVMTEST \name kvm_interrupt 420 .endif 421.endm 422 423.macro __GEN_COMMON_BODY name 424 .if IMASK 425 .if ! ISTACK 426 .error "No support for masked interrupt to use custom stack" 427 .endif 428 429 /* If coming from user, skip soft-mask tests. */ 430 andi. r10,r12,MSR_PR 431 bne 2f 432 433 /* Kernel code running below __end_interrupts is implicitly 434 * soft-masked */ 435 LOAD_HANDLER(r10, __end_interrupts) 436 cmpld r11,r10 437 li r10,IMASK 438 blt- 1f 439 440 /* Test the soft mask state against our interrupt's bit */ 441 lbz r10,PACAIRQSOFTMASK(r13) 4421: andi. r10,r10,IMASK 443 /* Associate vector numbers with bits in paca->irq_happened */ 444 .if IVEC == 0x500 || IVEC == 0xea0 445 li r10,PACA_IRQ_EE 446 .elseif IVEC == 0x900 447 li r10,PACA_IRQ_DEC 448 .elseif IVEC == 0xa00 || IVEC == 0xe80 449 li r10,PACA_IRQ_DBELL 450 .elseif IVEC == 0xe60 451 li r10,PACA_IRQ_HMI 452 .elseif IVEC == 0xf00 453 li r10,PACA_IRQ_PMI 454 .else 455 .abort "Bad maskable vector" 456 .endif 457 458 .if IHSRR_IF_HVMODE 459 BEGIN_FTR_SECTION 460 bne masked_Hinterrupt 461 FTR_SECTION_ELSE 462 bne masked_interrupt 463 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 464 .elseif IHSRR 465 bne masked_Hinterrupt 466 .else 467 bne masked_interrupt 468 .endif 469 .endif 470 471 .if ISTACK 472 andi. r10,r12,MSR_PR /* See if coming from user */ 4732: mr r10,r1 /* Save r1 */ 474 subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */ 475 beq- 100f 476 ld r1,PACAKSAVE(r13) /* kernel stack to use */ 477100: tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */ 478 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0 479 .endif 480 481 std r9,_CCR(r1) /* save CR in stackframe */ 482 std r11,_NIP(r1) /* save SRR0 in stackframe */ 483 std r12,_MSR(r1) /* save SRR1 in stackframe */ 484 std r10,0(r1) /* make stack chain pointer */ 485 std r0,GPR0(r1) /* save r0 in stackframe */ 486 std r10,GPR1(r1) /* save r1 in stackframe */ 487 488 .if ISET_RI 489 li r10,MSR_RI 490 mtmsrd r10,1 /* Set MSR_RI */ 491 .endif 492 493 .if ISTACK 494 .if IKUAP 495 kuap_save_amr_and_lock r9, r10, cr1, cr0 496 .endif 497 beq 101f /* if from kernel mode */ 498BEGIN_FTR_SECTION 499 ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */ 500 std r9,_PPR(r1) 501END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 502101: 503 .else 504 .if IKUAP 505 kuap_save_amr_and_lock r9, r10, cr1 506 .endif 507 .endif 508 509 /* Save original regs values from save area to stack frame. */ 510 ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */ 511 ld r10,IAREA+EX_R10(r13) 512 std r9,GPR9(r1) 513 std r10,GPR10(r1) 514 ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */ 515 ld r10,IAREA+EX_R12(r13) 516 ld r11,IAREA+EX_R13(r13) 517 std r9,GPR11(r1) 518 std r10,GPR12(r1) 519 std r11,GPR13(r1) 520 521 SAVE_NVGPRS(r1) 522 523 .if IDAR 524 .if IISIDE 525 ld r10,_NIP(r1) 526 .else 527 ld r10,IAREA+EX_DAR(r13) 528 .endif 529 std r10,_DAR(r1) 530 .endif 531 532 .if IDSISR 533 .if IISIDE 534 ld r10,_MSR(r1) 535 lis r11,DSISR_SRR1_MATCH_64S@h 536 and r10,r10,r11 537 .else 538 lwz r10,IAREA+EX_DSISR(r13) 539 .endif 540 std r10,_DSISR(r1) 541 .endif 542 543BEGIN_FTR_SECTION 544 ld r10,IAREA+EX_CFAR(r13) 545 std r10,ORIG_GPR3(r1) 546END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 547 ld r10,IAREA+EX_CTR(r13) 548 std r10,_CTR(r1) 549 std r2,GPR2(r1) /* save r2 in stackframe */ 550 SAVE_4GPRS(3, r1) /* save r3 - r6 in stackframe */ 551 SAVE_2GPRS(7, r1) /* save r7, r8 in stackframe */ 552 mflr r9 /* Get LR, later save to stack */ 553 ld r2,PACATOC(r13) /* get kernel TOC into r2 */ 554 std r9,_LINK(r1) 555 lbz r10,PACAIRQSOFTMASK(r13) 556 mfspr r11,SPRN_XER /* save XER in stackframe */ 557 std r10,SOFTE(r1) 558 std r11,_XER(r1) 559 li r9,IVEC 560 std r9,_TRAP(r1) /* set trap number */ 561 li r10,0 562 ld r11,exception_marker@toc(r2) 563 std r10,RESULT(r1) /* clear regs->result */ 564 std r11,STACK_FRAME_OVERHEAD-16(r1) /* mark the frame */ 565.endm 566 567/* 568 * On entry r13 points to the paca, r9-r13 are saved in the paca, 569 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 570 * SRR1, and relocation is on. 571 * 572 * If stack=0, then the stack is already set in r1, and r1 is saved in r10. 573 * PPR save and CPU accounting is not done for the !stack case (XXX why not?) 574 */ 575.macro GEN_COMMON name 576 __GEN_COMMON_ENTRY \name 577 __GEN_COMMON_BODY \name 578.endm 579 580/* 581 * Restore all registers including H/SRR0/1 saved in a stack frame of a 582 * standard exception. 583 */ 584.macro EXCEPTION_RESTORE_REGS hsrr=0 585 /* Move original SRR0 and SRR1 into the respective regs */ 586 ld r9,_MSR(r1) 587 .if \hsrr 588 mtspr SPRN_HSRR1,r9 589 .else 590 mtspr SPRN_SRR1,r9 591 .endif 592 ld r9,_NIP(r1) 593 .if \hsrr 594 mtspr SPRN_HSRR0,r9 595 .else 596 mtspr SPRN_SRR0,r9 597 .endif 598 ld r9,_CTR(r1) 599 mtctr r9 600 ld r9,_XER(r1) 601 mtxer r9 602 ld r9,_LINK(r1) 603 mtlr r9 604 ld r9,_CCR(r1) 605 mtcr r9 606 REST_8GPRS(2, r1) 607 REST_4GPRS(10, r1) 608 REST_GPR(0, r1) 609 /* restore original r1. */ 610 ld r1,GPR1(r1) 611.endm 612 613/* 614 * There are a few constraints to be concerned with. 615 * - Real mode exceptions code/data must be located at their physical location. 616 * - Virtual mode exceptions must be mapped at their 0xc000... location. 617 * - Fixed location code must not call directly beyond the __end_interrupts 618 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 619 * must be used. 620 * - LOAD_HANDLER targets must be within first 64K of physical 0 / 621 * virtual 0xc00... 622 * - Conditional branch targets must be within +/-32K of caller. 623 * 624 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 625 * therefore don't have to run in physically located code or rfid to 626 * virtual mode kernel code. However on relocatable kernels they do have 627 * to branch to KERNELBASE offset because the rest of the kernel (outside 628 * the exception vectors) may be located elsewhere. 629 * 630 * Virtual exceptions correspond with physical, except their entry points 631 * are offset by 0xc000000000000000 and also tend to get an added 0x4000 632 * offset applied. Virtual exceptions are enabled with the Alternate 633 * Interrupt Location (AIL) bit set in the LPCR. However this does not 634 * guarantee they will be delivered virtually. Some conditions (see the ISA) 635 * cause exceptions to be delivered in real mode. 636 * 637 * The scv instructions are a special case. They get a 0x3000 offset applied. 638 * scv exceptions have unique reentrancy properties, see below. 639 * 640 * It's impossible to receive interrupts below 0x300 via AIL. 641 * 642 * KVM: None of the virtual exceptions are from the guest. Anything that 643 * escalated to HV=1 from HV=0 is delivered via real mode handlers. 644 * 645 * 646 * We layout physical memory as follows: 647 * 0x0000 - 0x00ff : Secondary processor spin code 648 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 649 * 0x1900 - 0x2fff : Real mode trampolines 650 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 651 * 0x5900 - 0x6fff : Relon mode trampolines 652 * 0x7000 - 0x7fff : FWNMI data area 653 * 0x8000 - .... : Common interrupt handlers, remaining early 654 * setup code, rest of kernel. 655 * 656 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 657 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 658 * vectors there. 659 */ 660OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 661OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000) 662OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900) 663OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 664 665#ifdef CONFIG_PPC_POWERNV 666 .globl start_real_trampolines 667 .globl end_real_trampolines 668 .globl start_virt_trampolines 669 .globl end_virt_trampolines 670#endif 671 672#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 673/* 674 * Data area reserved for FWNMI option. 675 * This address (0x7000) is fixed by the RPA. 676 * pseries and powernv need to keep the whole page from 677 * 0x7000 to 0x8000 free for use by the firmware 678 */ 679ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 680OPEN_TEXT_SECTION(0x8000) 681#else 682OPEN_TEXT_SECTION(0x7000) 683#endif 684 685USE_FIXED_SECTION(real_vectors) 686 687/* 688 * This is the start of the interrupt handlers for pSeries 689 * This code runs with relocation off. 690 * Code from here to __end_interrupts gets copied down to real 691 * address 0x100 when we are running a relocatable kernel. 692 * Therefore any relative branches in this section must only 693 * branch to labels in this section. 694 */ 695 .globl __start_interrupts 696__start_interrupts: 697 698/** 699 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall). 700 * This is a synchronous interrupt invoked with the "scv" instruction. The 701 * system call does not alter the HV bit, so it is directed to the OS. 702 * 703 * Handling: 704 * scv instructions enter the kernel without changing EE, RI, ME, or HV. 705 * In particular, this means we can take a maskable interrupt at any point 706 * in the scv handler, which is unlike any other interrupt. This is solved 707 * by treating the instruction addresses below __end_interrupts as being 708 * soft-masked. 709 * 710 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and 711 * ensure scv is never executed with relocation off, which means AIL-0 712 * should never happen. 713 * 714 * Before leaving the below __end_interrupts text, at least of the following 715 * must be true: 716 * - MSR[PR]=1 (i.e., return to userspace) 717 * - MSR_EE|MSR_RI is set (no reentrant exceptions) 718 * - Standard kernel environment is set up (stack, paca, etc) 719 * 720 * Call convention: 721 * 722 * syscall register convention is in Documentation/powerpc/syscall64-abi.rst 723 */ 724EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000) 725 /* SCV 0 */ 726 mr r9,r13 727 GET_PACA(r13) 728 mflr r11 729 mfctr r12 730 li r10,IRQS_ALL_DISABLED 731 stb r10,PACAIRQSOFTMASK(r13) 732#ifdef CONFIG_RELOCATABLE 733 b system_call_vectored_tramp 734#else 735 b system_call_vectored_common 736#endif 737 nop 738 739 /* SCV 1 - 127 */ 740 .rept 127 741 mr r9,r13 742 GET_PACA(r13) 743 mflr r11 744 mfctr r12 745 li r10,IRQS_ALL_DISABLED 746 stb r10,PACAIRQSOFTMASK(r13) 747 li r0,-1 /* cause failure */ 748#ifdef CONFIG_RELOCATABLE 749 b system_call_vectored_sigill_tramp 750#else 751 b system_call_vectored_sigill 752#endif 753 .endr 754EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000) 755 756#ifdef CONFIG_RELOCATABLE 757TRAMP_VIRT_BEGIN(system_call_vectored_tramp) 758 __LOAD_HANDLER(r10, system_call_vectored_common) 759 mtctr r10 760 bctr 761 762TRAMP_VIRT_BEGIN(system_call_vectored_sigill_tramp) 763 __LOAD_HANDLER(r10, system_call_vectored_sigill) 764 mtctr r10 765 bctr 766#endif 767 768 769/* No virt vectors corresponding with 0x0..0x100 */ 770EXC_VIRT_NONE(0x4000, 0x100) 771 772 773/** 774 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI). 775 * This is a non-maskable, asynchronous interrupt always taken in real-mode. 776 * It is caused by: 777 * - Wake from power-saving state, on powernv. 778 * - An NMI from another CPU, triggered by firmware or hypercall. 779 * - As crash/debug signal injected from BMC, firmware or hypervisor. 780 * 781 * Handling: 782 * Power-save wakeup is the only performance critical path, so this is 783 * determined quickly as possible first. In this case volatile registers 784 * can be discarded and SPRs like CFAR don't need to be read. 785 * 786 * If not a powersave wakeup, then it's run as a regular interrupt, however 787 * it uses its own stack and PACA save area to preserve the regular kernel 788 * environment for debugging. 789 * 790 * This interrupt is not maskable, so triggering it when MSR[RI] is clear, 791 * or SCRATCH0 is in use, etc. may cause a crash. It's also not entirely 792 * correct to switch to virtual mode to run the regular interrupt handler 793 * because it might be interrupted when the MMU is in a bad state (e.g., SLB 794 * is clear). 795 * 796 * FWNMI: 797 * PAPR specifies a "fwnmi" facility which sends the sreset to a different 798 * entry point with a different register set up. Some hypervisors will 799 * send the sreset to 0x100 in the guest if it is not fwnmi capable. 800 * 801 * KVM: 802 * Unlike most SRR interrupts, this may be taken by the host while executing 803 * in a guest, so a KVM test is required. KVM will pull the CPU out of guest 804 * mode and then raise the sreset. 805 */ 806INT_DEFINE_BEGIN(system_reset) 807 IVEC=0x100 808 IAREA=PACA_EXNMI 809 IVIRT=0 /* no virt entry point */ 810 /* 811 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 812 * being used, so a nested NMI exception would corrupt it. 813 */ 814 ISET_RI=0 815 ISTACK=0 816 IKVM_REAL=1 817INT_DEFINE_END(system_reset) 818 819EXC_REAL_BEGIN(system_reset, 0x100, 0x100) 820#ifdef CONFIG_PPC_P7_NAP 821 /* 822 * If running native on arch 2.06 or later, check if we are waking up 823 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 824 * bits 46:47. A non-0 value indicates that we are coming from a power 825 * saving state. The idle wakeup handler initially runs in real mode, 826 * but we branch to the 0xc000... address so we can turn on relocation 827 * with mtmsrd later, after SPRs are restored. 828 * 829 * Careful to minimise cost for the fast path (idle wakeup) while 830 * also avoiding clobbering CFAR for the debug path (non-idle). 831 * 832 * For the idle wake case volatile registers can be clobbered, which 833 * is why we use those initially. If it turns out to not be an idle 834 * wake, carefully put everything back the way it was, so we can use 835 * common exception macros to handle it. 836 */ 837BEGIN_FTR_SECTION 838 SET_SCRATCH0(r13) 839 GET_PACA(r13) 840 std r3,PACA_EXNMI+0*8(r13) 841 std r4,PACA_EXNMI+1*8(r13) 842 std r5,PACA_EXNMI+2*8(r13) 843 mfspr r3,SPRN_SRR1 844 mfocrf r4,0x80 845 rlwinm. r5,r3,47-31,30,31 846 bne+ system_reset_idle_wake 847 /* Not powersave wakeup. Restore regs for regular interrupt handler. */ 848 mtocrf 0x80,r4 849 ld r3,PACA_EXNMI+0*8(r13) 850 ld r4,PACA_EXNMI+1*8(r13) 851 ld r5,PACA_EXNMI+2*8(r13) 852 GET_SCRATCH0(r13) 853END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 854#endif 855 856 GEN_INT_ENTRY system_reset, virt=0 857 /* 858 * In theory, we should not enable relocation here if it was disabled 859 * in SRR1, because the MMU may not be configured to support it (e.g., 860 * SLB may have been cleared). In practice, there should only be a few 861 * small windows where that's the case, and sreset is considered to 862 * be dangerous anyway. 863 */ 864EXC_REAL_END(system_reset, 0x100, 0x100) 865EXC_VIRT_NONE(0x4100, 0x100) 866 867#ifdef CONFIG_PPC_P7_NAP 868TRAMP_REAL_BEGIN(system_reset_idle_wake) 869 /* We are waking up from idle, so may clobber any volatile register */ 870 cmpwi cr1,r5,2 871 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */ 872 BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss)) 873#endif 874 875#ifdef CONFIG_PPC_PSERIES 876/* 877 * Vectors for the FWNMI option. Share common code. 878 */ 879TRAMP_REAL_BEGIN(system_reset_fwnmi) 880 GEN_INT_ENTRY system_reset, virt=0 881 882#endif /* CONFIG_PPC_PSERIES */ 883 884EXC_COMMON_BEGIN(system_reset_common) 885 __GEN_COMMON_ENTRY system_reset 886 /* 887 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 888 * to recover, but nested NMI will notice in_nmi and not recover 889 * because of the use of the NMI stack. in_nmi reentrancy is tested in 890 * system_reset_exception. 891 */ 892 lhz r10,PACA_IN_NMI(r13) 893 addi r10,r10,1 894 sth r10,PACA_IN_NMI(r13) 895 li r10,MSR_RI 896 mtmsrd r10,1 897 898 mr r10,r1 899 ld r1,PACA_NMI_EMERG_SP(r13) 900 subi r1,r1,INT_FRAME_SIZE 901 __GEN_COMMON_BODY system_reset 902 903 addi r3,r1,STACK_FRAME_OVERHEAD 904 bl system_reset_exception 905 906 /* Clear MSR_RI before setting SRR0 and SRR1. */ 907 li r9,0 908 mtmsrd r9,1 909 910 /* 911 * MSR_RI is clear, now we can decrement paca->in_nmi. 912 */ 913 lhz r10,PACA_IN_NMI(r13) 914 subi r10,r10,1 915 sth r10,PACA_IN_NMI(r13) 916 917 kuap_kernel_restore r9, r10 918 EXCEPTION_RESTORE_REGS 919 RFI_TO_USER_OR_KERNEL 920 921 922/** 923 * Interrupt 0x200 - Machine Check Interrupt (MCE). 924 * This is a non-maskable interrupt always taken in real-mode. It can be 925 * synchronous or asynchronous, caused by hardware or software, and it may be 926 * taken in a power-saving state. 927 * 928 * Handling: 929 * Similarly to system reset, this uses its own stack and PACA save area, 930 * the difference is re-entrancy is allowed on the machine check stack. 931 * 932 * machine_check_early is run in real mode, and carefully decodes the 933 * machine check and tries to handle it (e.g., flush the SLB if there was an 934 * error detected there), determines if it was recoverable and logs the 935 * event. 936 * 937 * This early code does not "reconcile" irq soft-mask state like SRESET or 938 * regular interrupts do, so irqs_disabled() among other things may not work 939 * properly (irq disable/enable already doesn't work because irq tracing can 940 * not work in real mode). 941 * 942 * Then, depending on the execution context when the interrupt is taken, there 943 * are 3 main actions: 944 * - Executing in kernel mode. The event is queued with irq_work, which means 945 * it is handled when it is next safe to do so (i.e., the kernel has enabled 946 * interrupts), which could be immediately when the interrupt returns. This 947 * avoids nasty issues like switching to virtual mode when the MMU is in a 948 * bad state, or when executing OPAL code. (SRESET is exposed to such issues, 949 * but it has different priorities). Check to see if the CPU was in power 950 * save, and return via the wake up code if it was. 951 * 952 * - Executing in user mode. machine_check_exception is run like a normal 953 * interrupt handler, which processes the data generated by the early handler. 954 * 955 * - Executing in guest mode. The interrupt is run with its KVM test, and 956 * branches to KVM to deal with. KVM may queue the event for the host 957 * to report later. 958 * 959 * This interrupt is not maskable, so if it triggers when MSR[RI] is clear, 960 * or SCRATCH0 is in use, it may cause a crash. 961 * 962 * KVM: 963 * See SRESET. 964 */ 965INT_DEFINE_BEGIN(machine_check_early) 966 IVEC=0x200 967 IAREA=PACA_EXMC 968 IVIRT=0 /* no virt entry point */ 969 IREALMODE_COMMON=1 970 /* 971 * MSR_RI is not enabled, because PACA_EXMC is being used, so a 972 * nested machine check corrupts it. machine_check_common enables 973 * MSR_RI. 974 */ 975 ISET_RI=0 976 ISTACK=0 977 IDAR=1 978 IDSISR=1 979 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */ 980INT_DEFINE_END(machine_check_early) 981 982INT_DEFINE_BEGIN(machine_check) 983 IVEC=0x200 984 IAREA=PACA_EXMC 985 IVIRT=0 /* no virt entry point */ 986 ISET_RI=0 987 IDAR=1 988 IDSISR=1 989 IKVM_REAL=1 990INT_DEFINE_END(machine_check) 991 992EXC_REAL_BEGIN(machine_check, 0x200, 0x100) 993 GEN_INT_ENTRY machine_check_early, virt=0 994EXC_REAL_END(machine_check, 0x200, 0x100) 995EXC_VIRT_NONE(0x4200, 0x100) 996 997#ifdef CONFIG_PPC_PSERIES 998TRAMP_REAL_BEGIN(machine_check_fwnmi) 999 /* See comment at machine_check exception, don't turn on RI */ 1000 GEN_INT_ENTRY machine_check_early, virt=0 1001#endif 1002 1003#define MACHINE_CHECK_HANDLER_WINDUP \ 1004 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 1005 li r9,0; \ 1006 mtmsrd r9,1; /* Clear MSR_RI */ \ 1007 /* Decrement paca->in_mce now RI is clear. */ \ 1008 lhz r12,PACA_IN_MCE(r13); \ 1009 subi r12,r12,1; \ 1010 sth r12,PACA_IN_MCE(r13); \ 1011 EXCEPTION_RESTORE_REGS 1012 1013EXC_COMMON_BEGIN(machine_check_early_common) 1014 __GEN_REALMODE_COMMON_ENTRY machine_check_early 1015 1016 /* 1017 * Switch to mc_emergency stack and handle re-entrancy (we limit 1018 * the nested MCE upto level 4 to avoid stack overflow). 1019 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 1020 * 1021 * We use paca->in_mce to check whether this is the first entry or 1022 * nested machine check. We increment paca->in_mce to track nested 1023 * machine checks. 1024 * 1025 * If this is the first entry then set stack pointer to 1026 * paca->mc_emergency_sp, otherwise r1 is already pointing to 1027 * stack frame on mc_emergency stack. 1028 * 1029 * NOTE: We are here with MSR_ME=0 (off), which means we risk a 1030 * checkstop if we get another machine check exception before we do 1031 * rfid with MSR_ME=1. 1032 * 1033 * This interrupt can wake directly from idle. If that is the case, 1034 * the machine check is handled then the idle wakeup code is called 1035 * to restore state. 1036 */ 1037 lhz r10,PACA_IN_MCE(r13) 1038 cmpwi r10,0 /* Are we in nested machine check */ 1039 cmpwi cr1,r10,MAX_MCE_DEPTH /* Are we at maximum nesting */ 1040 addi r10,r10,1 /* increment paca->in_mce */ 1041 sth r10,PACA_IN_MCE(r13) 1042 1043 mr r10,r1 /* Save r1 */ 1044 bne 1f 1045 /* First machine check entry */ 1046 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 10471: /* Limit nested MCE to level 4 to avoid stack overflow */ 1048 bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */ 1049 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1050 1051 __GEN_COMMON_BODY machine_check_early 1052 1053BEGIN_FTR_SECTION 1054 bl enable_machine_check 1055END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1056 li r10,MSR_RI 1057 mtmsrd r10,1 1058 1059 addi r3,r1,STACK_FRAME_OVERHEAD 1060 bl machine_check_early 1061 std r3,RESULT(r1) /* Save result */ 1062 ld r12,_MSR(r1) 1063 1064#ifdef CONFIG_PPC_P7_NAP 1065 /* 1066 * Check if thread was in power saving mode. We come here when any 1067 * of the following is true: 1068 * a. thread wasn't in power saving mode 1069 * b. thread was in power saving mode with no state loss, 1070 * supervisor state loss or hypervisor state loss. 1071 * 1072 * Go back to nap/sleep/winkle mode again if (b) is true. 1073 */ 1074BEGIN_FTR_SECTION 1075 rlwinm. r11,r12,47-31,30,31 1076 bne machine_check_idle_common 1077END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 1078#endif 1079 1080#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1081 /* 1082 * Check if we are coming from guest. If yes, then run the normal 1083 * exception handler which will take the 1084 * machine_check_kvm->kvm_interrupt branch to deliver the MC event 1085 * to guest. 1086 */ 1087 lbz r11,HSTATE_IN_GUEST(r13) 1088 cmpwi r11,0 /* Check if coming from guest */ 1089 bne mce_deliver /* continue if we are. */ 1090#endif 1091 1092 /* 1093 * Check if we are coming from userspace. If yes, then run the normal 1094 * exception handler which will deliver the MC event to this kernel. 1095 */ 1096 andi. r11,r12,MSR_PR /* See if coming from user. */ 1097 bne mce_deliver /* continue in V mode if we are. */ 1098 1099 /* 1100 * At this point we are coming from kernel context. 1101 * Queue up the MCE event and return from the interrupt. 1102 * But before that, check if this is an un-recoverable exception. 1103 * If yes, then stay on emergency stack and panic. 1104 */ 1105 andi. r11,r12,MSR_RI 1106 beq unrecoverable_mce 1107 1108 /* 1109 * Check if we have successfully handled/recovered from error, if not 1110 * then stay on emergency stack and panic. 1111 */ 1112 ld r3,RESULT(r1) /* Load result */ 1113 cmpdi r3,0 /* see if we handled MCE successfully */ 1114 beq unrecoverable_mce /* if !handled then panic */ 1115 1116 /* 1117 * Return from MC interrupt. 1118 * Queue up the MCE event so that we can log it later, while 1119 * returning from kernel or opal call. 1120 */ 1121 bl machine_check_queue_event 1122 MACHINE_CHECK_HANDLER_WINDUP 1123 RFI_TO_KERNEL 1124 1125mce_deliver: 1126 /* 1127 * This is a host user or guest MCE. Restore all registers, then 1128 * run the "late" handler. For host user, this will run the 1129 * machine_check_exception handler in virtual mode like a normal 1130 * interrupt handler. For guest, this will trigger the KVM test 1131 * and branch to the KVM interrupt similarly to other interrupts. 1132 */ 1133BEGIN_FTR_SECTION 1134 ld r10,ORIG_GPR3(r1) 1135 mtspr SPRN_CFAR,r10 1136END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1137 MACHINE_CHECK_HANDLER_WINDUP 1138 GEN_INT_ENTRY machine_check, virt=0 1139 1140EXC_COMMON_BEGIN(machine_check_common) 1141 /* 1142 * Machine check is different because we use a different 1143 * save area: PACA_EXMC instead of PACA_EXGEN. 1144 */ 1145 GEN_COMMON machine_check 1146 1147 /* Enable MSR_RI when finished with PACA_EXMC */ 1148 li r10,MSR_RI 1149 mtmsrd r10,1 1150 addi r3,r1,STACK_FRAME_OVERHEAD 1151 bl machine_check_exception 1152 b interrupt_return 1153 1154 1155#ifdef CONFIG_PPC_P7_NAP 1156/* 1157 * This is an idle wakeup. Low level machine check has already been 1158 * done. Queue the event then call the idle code to do the wake up. 1159 */ 1160EXC_COMMON_BEGIN(machine_check_idle_common) 1161 bl machine_check_queue_event 1162 1163 /* 1164 * GPR-loss wakeups are relatively straightforward, because the 1165 * idle sleep code has saved all non-volatile registers on its 1166 * own stack, and r1 in PACAR1. 1167 * 1168 * For no-loss wakeups the r1 and lr registers used by the 1169 * early machine check handler have to be restored first. r2 is 1170 * the kernel TOC, so no need to restore it. 1171 * 1172 * Then decrement MCE nesting after finishing with the stack. 1173 */ 1174 ld r3,_MSR(r1) 1175 ld r4,_LINK(r1) 1176 ld r1,GPR1(r1) 1177 1178 lhz r11,PACA_IN_MCE(r13) 1179 subi r11,r11,1 1180 sth r11,PACA_IN_MCE(r13) 1181 1182 mtlr r4 1183 rlwinm r10,r3,47-31,30,31 1184 cmpwi cr1,r10,2 1185 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */ 1186 b idle_return_gpr_loss 1187#endif 1188 1189EXC_COMMON_BEGIN(unrecoverable_mce) 1190 /* 1191 * We are going down. But there are chances that we might get hit by 1192 * another MCE during panic path and we may run into unstable state 1193 * with no way out. Hence, turn ME bit off while going down, so that 1194 * when another MCE is hit during panic path, system will checkstop 1195 * and hypervisor will get restarted cleanly by SP. 1196 */ 1197BEGIN_FTR_SECTION 1198 li r10,0 /* clear MSR_RI */ 1199 mtmsrd r10,1 1200 bl disable_machine_check 1201END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1202 ld r10,PACAKMSR(r13) 1203 li r3,MSR_ME 1204 andc r10,r10,r3 1205 mtmsrd r10 1206 1207 lhz r12,PACA_IN_MCE(r13) 1208 subi r12,r12,1 1209 sth r12,PACA_IN_MCE(r13) 1210 1211 /* Invoke machine_check_exception to print MCE event and panic. */ 1212 addi r3,r1,STACK_FRAME_OVERHEAD 1213 bl machine_check_exception 1214 1215 /* 1216 * We will not reach here. Even if we did, there is no way out. 1217 * Call unrecoverable_exception and die. 1218 */ 1219 addi r3,r1,STACK_FRAME_OVERHEAD 1220 bl unrecoverable_exception 1221 b . 1222 1223 1224/** 1225 * Interrupt 0x300 - Data Storage Interrupt (DSI). 1226 * This is a synchronous interrupt generated due to a data access exception, 1227 * e.g., a load orstore which does not have a valid page table entry with 1228 * permissions. DAWR matches also fault here, as do RC updates, and minor misc 1229 * errors e.g., copy/paste, AMO, certain invalid CI accesses, etc. 1230 * 1231 * Handling: 1232 * - Hash MMU 1233 * Go to do_hash_fault, which attempts to fill the HPT from an entry in the 1234 * Linux page table. Hash faults can hit in kernel mode in a fairly 1235 * arbitrary state (e.g., interrupts disabled, locks held) when accessing 1236 * "non-bolted" regions, e.g., vmalloc space. However these should always be 1237 * backed by Linux page table entries. 1238 * 1239 * If no entry is found the Linux page fault handler is invoked (by 1240 * do_hash_fault). Linux page faults can happen in kernel mode due to user 1241 * copy operations of course. 1242 * 1243 * KVM: The KVM HDSI handler may perform a load with MSR[DR]=1 in guest 1244 * MMU context, which may cause a DSI in the host, which must go to the 1245 * KVM handler. MSR[IR] is not enabled, so the real-mode handler will 1246 * always be used regardless of AIL setting. 1247 * 1248 * - Radix MMU 1249 * The hardware loads from the Linux page table directly, so a fault goes 1250 * immediately to Linux page fault. 1251 * 1252 * Conditions like DAWR match are handled on the way in to Linux page fault. 1253 */ 1254INT_DEFINE_BEGIN(data_access) 1255 IVEC=0x300 1256 IDAR=1 1257 IDSISR=1 1258 IKVM_REAL=1 1259INT_DEFINE_END(data_access) 1260 1261EXC_REAL_BEGIN(data_access, 0x300, 0x80) 1262 GEN_INT_ENTRY data_access, virt=0 1263EXC_REAL_END(data_access, 0x300, 0x80) 1264EXC_VIRT_BEGIN(data_access, 0x4300, 0x80) 1265 GEN_INT_ENTRY data_access, virt=1 1266EXC_VIRT_END(data_access, 0x4300, 0x80) 1267EXC_COMMON_BEGIN(data_access_common) 1268 GEN_COMMON data_access 1269 ld r4,_DSISR(r1) 1270 addi r3,r1,STACK_FRAME_OVERHEAD 1271 andis. r0,r4,DSISR_DABRMATCH@h 1272 bne- 1f 1273BEGIN_MMU_FTR_SECTION 1274 bl do_hash_fault 1275MMU_FTR_SECTION_ELSE 1276 bl do_page_fault 1277ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 1278 b interrupt_return 1279 12801: bl do_break 1281 /* 1282 * do_break() may have changed the NV GPRS while handling a breakpoint. 1283 * If so, we need to restore them with their updated values. 1284 */ 1285 REST_NVGPRS(r1) 1286 b interrupt_return 1287 1288 1289/** 1290 * Interrupt 0x380 - Data Segment Interrupt (DSLB). 1291 * This is a synchronous interrupt in response to an MMU fault missing SLB 1292 * entry for HPT, or an address outside RPT translation range. 1293 * 1294 * Handling: 1295 * - HPT: 1296 * This refills the SLB, or reports an access fault similarly to a bad page 1297 * fault. When coming from user-mode, the SLB handler may access any kernel 1298 * data, though it may itself take a DSLB. When coming from kernel mode, 1299 * recursive faults must be avoided so access is restricted to the kernel 1300 * image text/data, kernel stack, and any data allocated below 1301 * ppc64_bolted_size (first segment). The kernel handler must avoid stomping 1302 * on user-handler data structures. 1303 * 1304 * KVM: Same as 0x300, DSLB must test for KVM guest. 1305 */ 1306INT_DEFINE_BEGIN(data_access_slb) 1307 IVEC=0x380 1308 IDAR=1 1309 IKVM_REAL=1 1310INT_DEFINE_END(data_access_slb) 1311 1312EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 1313 GEN_INT_ENTRY data_access_slb, virt=0 1314EXC_REAL_END(data_access_slb, 0x380, 0x80) 1315EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 1316 GEN_INT_ENTRY data_access_slb, virt=1 1317EXC_VIRT_END(data_access_slb, 0x4380, 0x80) 1318EXC_COMMON_BEGIN(data_access_slb_common) 1319 GEN_COMMON data_access_slb 1320BEGIN_MMU_FTR_SECTION 1321 /* HPT case, do SLB fault */ 1322 addi r3,r1,STACK_FRAME_OVERHEAD 1323 bl do_slb_fault 1324 cmpdi r3,0 1325 bne- 1f 1326 b fast_interrupt_return 13271: /* Error case */ 1328MMU_FTR_SECTION_ELSE 1329 /* Radix case, access is outside page table range */ 1330 li r3,-EFAULT 1331ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 1332 std r3,RESULT(r1) 1333 addi r3,r1,STACK_FRAME_OVERHEAD 1334 bl do_bad_slb_fault 1335 b interrupt_return 1336 1337 1338/** 1339 * Interrupt 0x400 - Instruction Storage Interrupt (ISI). 1340 * This is a synchronous interrupt in response to an MMU fault due to an 1341 * instruction fetch. 1342 * 1343 * Handling: 1344 * Similar to DSI, though in response to fetch. The faulting address is found 1345 * in SRR0 (rather than DAR), and status in SRR1 (rather than DSISR). 1346 */ 1347INT_DEFINE_BEGIN(instruction_access) 1348 IVEC=0x400 1349 IISIDE=1 1350 IDAR=1 1351 IDSISR=1 1352#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1353 IKVM_REAL=1 1354#endif 1355INT_DEFINE_END(instruction_access) 1356 1357EXC_REAL_BEGIN(instruction_access, 0x400, 0x80) 1358 GEN_INT_ENTRY instruction_access, virt=0 1359EXC_REAL_END(instruction_access, 0x400, 0x80) 1360EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80) 1361 GEN_INT_ENTRY instruction_access, virt=1 1362EXC_VIRT_END(instruction_access, 0x4400, 0x80) 1363EXC_COMMON_BEGIN(instruction_access_common) 1364 GEN_COMMON instruction_access 1365 addi r3,r1,STACK_FRAME_OVERHEAD 1366BEGIN_MMU_FTR_SECTION 1367 bl do_hash_fault 1368MMU_FTR_SECTION_ELSE 1369 bl do_page_fault 1370ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 1371 b interrupt_return 1372 1373 1374/** 1375 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB). 1376 * This is a synchronous interrupt in response to an MMU fault due to an 1377 * instruction fetch. 1378 * 1379 * Handling: 1380 * Similar to DSLB, though in response to fetch. The faulting address is found 1381 * in SRR0 (rather than DAR). 1382 */ 1383INT_DEFINE_BEGIN(instruction_access_slb) 1384 IVEC=0x480 1385 IISIDE=1 1386 IDAR=1 1387#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1388 IKVM_REAL=1 1389#endif 1390INT_DEFINE_END(instruction_access_slb) 1391 1392EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) 1393 GEN_INT_ENTRY instruction_access_slb, virt=0 1394EXC_REAL_END(instruction_access_slb, 0x480, 0x80) 1395EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) 1396 GEN_INT_ENTRY instruction_access_slb, virt=1 1397EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) 1398EXC_COMMON_BEGIN(instruction_access_slb_common) 1399 GEN_COMMON instruction_access_slb 1400BEGIN_MMU_FTR_SECTION 1401 /* HPT case, do SLB fault */ 1402 addi r3,r1,STACK_FRAME_OVERHEAD 1403 bl do_slb_fault 1404 cmpdi r3,0 1405 bne- 1f 1406 b fast_interrupt_return 14071: /* Error case */ 1408MMU_FTR_SECTION_ELSE 1409 /* Radix case, access is outside page table range */ 1410 li r3,-EFAULT 1411ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 1412 std r3,RESULT(r1) 1413 addi r3,r1,STACK_FRAME_OVERHEAD 1414 bl do_bad_slb_fault 1415 b interrupt_return 1416 1417 1418/** 1419 * Interrupt 0x500 - External Interrupt. 1420 * This is an asynchronous maskable interrupt in response to an "external 1421 * exception" from the interrupt controller or hypervisor (e.g., device 1422 * interrupt). It is maskable in hardware by clearing MSR[EE], and 1423 * soft-maskable with IRQS_DISABLED mask (i.e., local_irq_disable()). 1424 * 1425 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that 1426 * interrupts are delivered with HSRR registers, guests use SRRs, which 1427 * reqiures IHSRR_IF_HVMODE. 1428 * 1429 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that 1430 * external interrupts are delivered as Hypervisor Virtualization Interrupts 1431 * rather than External Interrupts. 1432 * 1433 * Handling: 1434 * This calls into Linux IRQ handler. NVGPRs are not saved to reduce overhead, 1435 * because registers at the time of the interrupt are not so important as it is 1436 * asynchronous. 1437 * 1438 * If soft masked, the masked handler will note the pending interrupt for 1439 * replay, and clear MSR[EE] in the interrupted context. 1440 */ 1441INT_DEFINE_BEGIN(hardware_interrupt) 1442 IVEC=0x500 1443 IHSRR_IF_HVMODE=1 1444 IMASK=IRQS_DISABLED 1445 IKVM_REAL=1 1446 IKVM_VIRT=1 1447INT_DEFINE_END(hardware_interrupt) 1448 1449EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 1450 GEN_INT_ENTRY hardware_interrupt, virt=0 1451EXC_REAL_END(hardware_interrupt, 0x500, 0x100) 1452EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 1453 GEN_INT_ENTRY hardware_interrupt, virt=1 1454EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 1455EXC_COMMON_BEGIN(hardware_interrupt_common) 1456 GEN_COMMON hardware_interrupt 1457 addi r3,r1,STACK_FRAME_OVERHEAD 1458 bl do_IRQ 1459 b interrupt_return 1460 1461 1462/** 1463 * Interrupt 0x600 - Alignment Interrupt 1464 * This is a synchronous interrupt in response to data alignment fault. 1465 */ 1466INT_DEFINE_BEGIN(alignment) 1467 IVEC=0x600 1468 IDAR=1 1469 IDSISR=1 1470#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1471 IKVM_REAL=1 1472#endif 1473INT_DEFINE_END(alignment) 1474 1475EXC_REAL_BEGIN(alignment, 0x600, 0x100) 1476 GEN_INT_ENTRY alignment, virt=0 1477EXC_REAL_END(alignment, 0x600, 0x100) 1478EXC_VIRT_BEGIN(alignment, 0x4600, 0x100) 1479 GEN_INT_ENTRY alignment, virt=1 1480EXC_VIRT_END(alignment, 0x4600, 0x100) 1481EXC_COMMON_BEGIN(alignment_common) 1482 GEN_COMMON alignment 1483 addi r3,r1,STACK_FRAME_OVERHEAD 1484 bl alignment_exception 1485 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 1486 b interrupt_return 1487 1488 1489/** 1490 * Interrupt 0x700 - Program Interrupt (program check). 1491 * This is a synchronous interrupt in response to various instruction faults: 1492 * traps, privilege errors, TM errors, floating point exceptions. 1493 * 1494 * Handling: 1495 * This interrupt may use the "emergency stack" in some cases when being taken 1496 * from kernel context, which complicates handling. 1497 */ 1498INT_DEFINE_BEGIN(program_check) 1499 IVEC=0x700 1500#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1501 IKVM_REAL=1 1502#endif 1503INT_DEFINE_END(program_check) 1504 1505EXC_REAL_BEGIN(program_check, 0x700, 0x100) 1506 1507#ifdef CONFIG_CPU_LITTLE_ENDIAN 1508 /* 1509 * There's a short window during boot where although the kernel is 1510 * running little endian, any exceptions will cause the CPU to switch 1511 * back to big endian. For example a WARN() boils down to a trap 1512 * instruction, which will cause a program check, and we end up here but 1513 * with the CPU in big endian mode. The first instruction of the program 1514 * check handler (in GEN_INT_ENTRY below) is an mtsprg, which when 1515 * executed in the wrong endian is an lhzu with a ~3GB displacement from 1516 * r3. The content of r3 is random, so that is a load from some random 1517 * location, and depending on the system can easily lead to a checkstop, 1518 * or an infinitely recursive page fault. 1519 * 1520 * So to handle that case we have a trampoline here that can detect we 1521 * are in the wrong endian and flip us back to the correct endian. We 1522 * can't flip MSR[LE] using mtmsr, so we have to use rfid. That requires 1523 * backing up SRR0/1 as well as a GPR. To do that we use SPRG0/2/3, as 1524 * SPRG1 is already used for the paca. SPRG3 is user readable, but this 1525 * trampoline is only active very early in boot, and SPRG3 will be 1526 * reinitialised in vdso_getcpu_init() before userspace starts. 1527 */ 1528BEGIN_FTR_SECTION 1529 tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8 1530 b 1f // Skip trampoline if endian is correct 1531 .long 0xa643707d // mtsprg 0, r11 Backup r11 1532 .long 0xa6027a7d // mfsrr0 r11 1533 .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2 1534 .long 0xa6027b7d // mfsrr1 r11 1535 .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3 1536 .long 0xa600607d // mfmsr r11 1537 .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE] 1538 .long 0xa6037b7d // mtsrr1 r11 1539 .long 0x34076039 // li r11, 0x734 1540 .long 0xa6037a7d // mtsrr0 r11 1541 .long 0x2400004c // rfid 1542 mfsprg r11, 3 1543 mtsrr1 r11 // Restore SRR1 1544 mfsprg r11, 2 1545 mtsrr0 r11 // Restore SRR0 1546 mfsprg r11, 0 // Restore r11 15471: 1548END_FTR_SECTION(0, 1) // nop out after boot 1549#endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1550 1551 GEN_INT_ENTRY program_check, virt=0 1552EXC_REAL_END(program_check, 0x700, 0x100) 1553EXC_VIRT_BEGIN(program_check, 0x4700, 0x100) 1554 GEN_INT_ENTRY program_check, virt=1 1555EXC_VIRT_END(program_check, 0x4700, 0x100) 1556EXC_COMMON_BEGIN(program_check_common) 1557 __GEN_COMMON_ENTRY program_check 1558 1559 /* 1560 * It's possible to receive a TM Bad Thing type program check with 1561 * userspace register values (in particular r1), but with SRR1 reporting 1562 * that we came from the kernel. Normally that would confuse the bad 1563 * stack logic, and we would report a bad kernel stack pointer. Instead 1564 * we switch to the emergency stack if we're taking a TM Bad Thing from 1565 * the kernel. 1566 */ 1567 1568 andi. r10,r12,MSR_PR 1569 bne 2f /* If userspace, go normal path */ 1570 1571 andis. r10,r12,(SRR1_PROGTM)@h 1572 bne 1f /* If TM, emergency */ 1573 1574 cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */ 1575 blt 2f /* normal path if not */ 1576 1577 /* Use the emergency stack */ 15781: andi. r10,r12,MSR_PR /* Set CR0 correctly for label */ 1579 /* 3 in EXCEPTION_PROLOG_COMMON */ 1580 mr r10,r1 /* Save r1 */ 1581 ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 1582 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1583 __ISTACK(program_check)=0 1584 __GEN_COMMON_BODY program_check 1585 b 3f 15862: 1587 __ISTACK(program_check)=1 1588 __GEN_COMMON_BODY program_check 15893: 1590 addi r3,r1,STACK_FRAME_OVERHEAD 1591 bl program_check_exception 1592 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 1593 b interrupt_return 1594 1595 1596/* 1597 * Interrupt 0x800 - Floating-Point Unavailable Interrupt. 1598 * This is a synchronous interrupt in response to executing an fp instruction 1599 * with MSR[FP]=0. 1600 * 1601 * Handling: 1602 * This will load FP registers and enable the FP bit if coming from userspace, 1603 * otherwise report a bad kernel use of FP. 1604 */ 1605INT_DEFINE_BEGIN(fp_unavailable) 1606 IVEC=0x800 1607#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1608 IKVM_REAL=1 1609#endif 1610INT_DEFINE_END(fp_unavailable) 1611 1612EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100) 1613 GEN_INT_ENTRY fp_unavailable, virt=0 1614EXC_REAL_END(fp_unavailable, 0x800, 0x100) 1615EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100) 1616 GEN_INT_ENTRY fp_unavailable, virt=1 1617EXC_VIRT_END(fp_unavailable, 0x4800, 0x100) 1618EXC_COMMON_BEGIN(fp_unavailable_common) 1619 GEN_COMMON fp_unavailable 1620 bne 1f /* if from user, just load it up */ 1621 addi r3,r1,STACK_FRAME_OVERHEAD 1622 bl kernel_fp_unavailable_exception 16230: trap 1624 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 16251: 1626#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1627BEGIN_FTR_SECTION 1628 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1629 * transaction), go do TM stuff 1630 */ 1631 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1632 bne- 2f 1633END_FTR_SECTION_IFSET(CPU_FTR_TM) 1634#endif 1635 bl load_up_fpu 1636 b fast_interrupt_return 1637#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 16382: /* User process was in a transaction */ 1639 addi r3,r1,STACK_FRAME_OVERHEAD 1640 bl fp_unavailable_tm 1641 b interrupt_return 1642#endif 1643 1644 1645/** 1646 * Interrupt 0x900 - Decrementer Interrupt. 1647 * This is an asynchronous interrupt in response to a decrementer exception 1648 * (e.g., DEC has wrapped below zero). It is maskable in hardware by clearing 1649 * MSR[EE], and soft-maskable with IRQS_DISABLED mask (i.e., 1650 * local_irq_disable()). 1651 * 1652 * Handling: 1653 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500). 1654 * 1655 * If soft masked, the masked handler will note the pending interrupt for 1656 * replay, and bump the decrementer to a high value, leaving MSR[EE] enabled 1657 * in the interrupted context. 1658 * If PPC_WATCHDOG is configured, the soft masked handler will actually set 1659 * things back up to run soft_nmi_interrupt as a regular interrupt handler 1660 * on the emergency stack. 1661 */ 1662INT_DEFINE_BEGIN(decrementer) 1663 IVEC=0x900 1664 IMASK=IRQS_DISABLED 1665#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1666 IKVM_REAL=1 1667#endif 1668INT_DEFINE_END(decrementer) 1669 1670EXC_REAL_BEGIN(decrementer, 0x900, 0x80) 1671 GEN_INT_ENTRY decrementer, virt=0 1672EXC_REAL_END(decrementer, 0x900, 0x80) 1673EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80) 1674 GEN_INT_ENTRY decrementer, virt=1 1675EXC_VIRT_END(decrementer, 0x4900, 0x80) 1676EXC_COMMON_BEGIN(decrementer_common) 1677 GEN_COMMON decrementer 1678 addi r3,r1,STACK_FRAME_OVERHEAD 1679 bl timer_interrupt 1680 b interrupt_return 1681 1682 1683/** 1684 * Interrupt 0x980 - Hypervisor Decrementer Interrupt. 1685 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC 1686 * register. 1687 * 1688 * Handling: 1689 * Linux does not use this outside KVM where it's used to keep a host timer 1690 * while the guest is given control of DEC. It should normally be caught by 1691 * the KVM test and routed there. 1692 */ 1693INT_DEFINE_BEGIN(hdecrementer) 1694 IVEC=0x980 1695 IHSRR=1 1696 ISTACK=0 1697 IKVM_REAL=1 1698 IKVM_VIRT=1 1699INT_DEFINE_END(hdecrementer) 1700 1701EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80) 1702 GEN_INT_ENTRY hdecrementer, virt=0 1703EXC_REAL_END(hdecrementer, 0x980, 0x80) 1704EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80) 1705 GEN_INT_ENTRY hdecrementer, virt=1 1706EXC_VIRT_END(hdecrementer, 0x4980, 0x80) 1707EXC_COMMON_BEGIN(hdecrementer_common) 1708 __GEN_COMMON_ENTRY hdecrementer 1709 /* 1710 * Hypervisor decrementer interrupts not caught by the KVM test 1711 * shouldn't occur but are sometimes left pending on exit from a KVM 1712 * guest. We don't need to do anything to clear them, as they are 1713 * edge-triggered. 1714 * 1715 * Be careful to avoid touching the kernel stack. 1716 */ 1717 ld r10,PACA_EXGEN+EX_CTR(r13) 1718 mtctr r10 1719 mtcrf 0x80,r9 1720 ld r9,PACA_EXGEN+EX_R9(r13) 1721 ld r10,PACA_EXGEN+EX_R10(r13) 1722 ld r11,PACA_EXGEN+EX_R11(r13) 1723 ld r12,PACA_EXGEN+EX_R12(r13) 1724 ld r13,PACA_EXGEN+EX_R13(r13) 1725 HRFI_TO_KERNEL 1726 1727 1728/** 1729 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt. 1730 * This is an asynchronous interrupt in response to a msgsndp doorbell. 1731 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with 1732 * IRQS_DISABLED mask (i.e., local_irq_disable()). 1733 * 1734 * Handling: 1735 * Guests may use this for IPIs between threads in a core if the 1736 * hypervisor supports it. NVGPRS are not saved (see 0x500). 1737 * 1738 * If soft masked, the masked handler will note the pending interrupt for 1739 * replay, leaving MSR[EE] enabled in the interrupted context because the 1740 * doorbells are edge triggered. 1741 */ 1742INT_DEFINE_BEGIN(doorbell_super) 1743 IVEC=0xa00 1744 IMASK=IRQS_DISABLED 1745#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1746 IKVM_REAL=1 1747#endif 1748INT_DEFINE_END(doorbell_super) 1749 1750EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100) 1751 GEN_INT_ENTRY doorbell_super, virt=0 1752EXC_REAL_END(doorbell_super, 0xa00, 0x100) 1753EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100) 1754 GEN_INT_ENTRY doorbell_super, virt=1 1755EXC_VIRT_END(doorbell_super, 0x4a00, 0x100) 1756EXC_COMMON_BEGIN(doorbell_super_common) 1757 GEN_COMMON doorbell_super 1758 addi r3,r1,STACK_FRAME_OVERHEAD 1759#ifdef CONFIG_PPC_DOORBELL 1760 bl doorbell_exception 1761#else 1762 bl unknown_async_exception 1763#endif 1764 b interrupt_return 1765 1766 1767EXC_REAL_NONE(0xb00, 0x100) 1768EXC_VIRT_NONE(0x4b00, 0x100) 1769 1770/** 1771 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall). 1772 * This is a synchronous interrupt invoked with the "sc" instruction. The 1773 * system call is invoked with "sc 0" and does not alter the HV bit, so it 1774 * is directed to the currently running OS. The hypercall is invoked with 1775 * "sc 1" and it sets HV=1, so it elevates to hypervisor. 1776 * 1777 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 1778 * 0x4c00 virtual mode. 1779 * 1780 * Handling: 1781 * If the KVM test fires then it was due to a hypercall and is accordingly 1782 * routed to KVM. Otherwise this executes a normal Linux system call. 1783 * 1784 * Call convention: 1785 * 1786 * syscall and hypercalls register conventions are documented in 1787 * Documentation/powerpc/syscall64-abi.rst and 1788 * Documentation/powerpc/papr_hcalls.rst respectively. 1789 * 1790 * The intersection of volatile registers that don't contain possible 1791 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 1792 * without saving, though xer is not a good idea to use, as hardware may 1793 * interpret some bits so it may be costly to change them. 1794 */ 1795INT_DEFINE_BEGIN(system_call) 1796 IVEC=0xc00 1797 IKVM_REAL=1 1798 IKVM_VIRT=1 1799INT_DEFINE_END(system_call) 1800 1801.macro SYSTEM_CALL virt 1802#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1803 /* 1804 * There is a little bit of juggling to get syscall and hcall 1805 * working well. Save r13 in ctr to avoid using SPRG scratch 1806 * register. 1807 * 1808 * Userspace syscalls have already saved the PPR, hcalls must save 1809 * it before setting HMT_MEDIUM. 1810 */ 1811 mtctr r13 1812 GET_PACA(r13) 1813 std r10,PACA_EXGEN+EX_R10(r13) 1814 INTERRUPT_TO_KERNEL 1815 KVMTEST system_call kvm_hcall /* uses r10, branch to kvm_hcall */ 1816 mfctr r9 1817#else 1818 mr r9,r13 1819 GET_PACA(r13) 1820 INTERRUPT_TO_KERNEL 1821#endif 1822 1823#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 1824BEGIN_FTR_SECTION 1825 cmpdi r0,0x1ebe 1826 beq- 1f 1827END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) 1828#endif 1829 1830 /* We reach here with PACA in r13, r13 in r9. */ 1831 mfspr r11,SPRN_SRR0 1832 mfspr r12,SPRN_SRR1 1833 1834 HMT_MEDIUM 1835 1836 .if ! \virt 1837 __LOAD_HANDLER(r10, system_call_common_real) 1838 mtctr r10 1839 bctr 1840 .else 1841 li r10,MSR_RI 1842 mtmsrd r10,1 /* Set RI (EE=0) */ 1843#ifdef CONFIG_RELOCATABLE 1844 __LOAD_HANDLER(r10, system_call_common) 1845 mtctr r10 1846 bctr 1847#else 1848 b system_call_common 1849#endif 1850 .endif 1851 1852#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 1853 /* Fast LE/BE switch system call */ 18541: mfspr r12,SPRN_SRR1 1855 xori r12,r12,MSR_LE 1856 mtspr SPRN_SRR1,r12 1857 mr r13,r9 1858 RFI_TO_USER /* return to userspace */ 1859 b . /* prevent speculative execution */ 1860#endif 1861.endm 1862 1863EXC_REAL_BEGIN(system_call, 0xc00, 0x100) 1864 SYSTEM_CALL 0 1865EXC_REAL_END(system_call, 0xc00, 0x100) 1866EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 1867 SYSTEM_CALL 1 1868EXC_VIRT_END(system_call, 0x4c00, 0x100) 1869 1870#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1871TRAMP_REAL_BEGIN(kvm_hcall) 1872 std r9,PACA_EXGEN+EX_R9(r13) 1873 std r11,PACA_EXGEN+EX_R11(r13) 1874 std r12,PACA_EXGEN+EX_R12(r13) 1875 mfcr r9 1876 mfctr r10 1877 std r10,PACA_EXGEN+EX_R13(r13) 1878 li r10,0 1879 std r10,PACA_EXGEN+EX_CFAR(r13) 1880 std r10,PACA_EXGEN+EX_CTR(r13) 1881 /* 1882 * Save the PPR (on systems that support it) before changing to 1883 * HMT_MEDIUM. That allows the KVM code to save that value into the 1884 * guest state (it is the guest's PPR value). 1885 */ 1886BEGIN_FTR_SECTION 1887 mfspr r10,SPRN_PPR 1888 std r10,PACA_EXGEN+EX_PPR(r13) 1889END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 1890 1891 HMT_MEDIUM 1892 1893#ifdef CONFIG_RELOCATABLE 1894 /* 1895 * Requires __LOAD_FAR_HANDLER beause kvmppc_hcall lives 1896 * outside the head section. 1897 */ 1898 __LOAD_FAR_HANDLER(r10, kvmppc_hcall) 1899 mtctr r10 1900 bctr 1901#else 1902 b kvmppc_hcall 1903#endif 1904#endif 1905 1906/** 1907 * Interrupt 0xd00 - Trace Interrupt. 1908 * This is a synchronous interrupt in response to instruction step or 1909 * breakpoint faults. 1910 */ 1911INT_DEFINE_BEGIN(single_step) 1912 IVEC=0xd00 1913#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1914 IKVM_REAL=1 1915#endif 1916INT_DEFINE_END(single_step) 1917 1918EXC_REAL_BEGIN(single_step, 0xd00, 0x100) 1919 GEN_INT_ENTRY single_step, virt=0 1920EXC_REAL_END(single_step, 0xd00, 0x100) 1921EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100) 1922 GEN_INT_ENTRY single_step, virt=1 1923EXC_VIRT_END(single_step, 0x4d00, 0x100) 1924EXC_COMMON_BEGIN(single_step_common) 1925 GEN_COMMON single_step 1926 addi r3,r1,STACK_FRAME_OVERHEAD 1927 bl single_step_exception 1928 b interrupt_return 1929 1930 1931/** 1932 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI). 1933 * This is a synchronous interrupt in response to an MMU fault caused by a 1934 * guest data access. 1935 * 1936 * Handling: 1937 * This should always get routed to KVM. In radix MMU mode, this is caused 1938 * by a guest nested radix access that can't be performed due to the 1939 * partition scope page table. In hash mode, this can be caused by guests 1940 * running with translation disabled (virtual real mode) or with VPM enabled. 1941 * KVM will update the page table structures or disallow the access. 1942 */ 1943INT_DEFINE_BEGIN(h_data_storage) 1944 IVEC=0xe00 1945 IHSRR=1 1946 IDAR=1 1947 IDSISR=1 1948 IKVM_REAL=1 1949 IKVM_VIRT=1 1950INT_DEFINE_END(h_data_storage) 1951 1952EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20) 1953 GEN_INT_ENTRY h_data_storage, virt=0, ool=1 1954EXC_REAL_END(h_data_storage, 0xe00, 0x20) 1955EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20) 1956 GEN_INT_ENTRY h_data_storage, virt=1, ool=1 1957EXC_VIRT_END(h_data_storage, 0x4e00, 0x20) 1958EXC_COMMON_BEGIN(h_data_storage_common) 1959 GEN_COMMON h_data_storage 1960 addi r3,r1,STACK_FRAME_OVERHEAD 1961BEGIN_MMU_FTR_SECTION 1962 bl do_bad_page_fault_segv 1963MMU_FTR_SECTION_ELSE 1964 bl unknown_exception 1965ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) 1966 b interrupt_return 1967 1968 1969/** 1970 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI). 1971 * This is a synchronous interrupt in response to an MMU fault caused by a 1972 * guest instruction fetch, similar to HDSI. 1973 */ 1974INT_DEFINE_BEGIN(h_instr_storage) 1975 IVEC=0xe20 1976 IHSRR=1 1977 IKVM_REAL=1 1978 IKVM_VIRT=1 1979INT_DEFINE_END(h_instr_storage) 1980 1981EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20) 1982 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1 1983EXC_REAL_END(h_instr_storage, 0xe20, 0x20) 1984EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20) 1985 GEN_INT_ENTRY h_instr_storage, virt=1, ool=1 1986EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20) 1987EXC_COMMON_BEGIN(h_instr_storage_common) 1988 GEN_COMMON h_instr_storage 1989 addi r3,r1,STACK_FRAME_OVERHEAD 1990 bl unknown_exception 1991 b interrupt_return 1992 1993 1994/** 1995 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt. 1996 */ 1997INT_DEFINE_BEGIN(emulation_assist) 1998 IVEC=0xe40 1999 IHSRR=1 2000 IKVM_REAL=1 2001 IKVM_VIRT=1 2002INT_DEFINE_END(emulation_assist) 2003 2004EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20) 2005 GEN_INT_ENTRY emulation_assist, virt=0, ool=1 2006EXC_REAL_END(emulation_assist, 0xe40, 0x20) 2007EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20) 2008 GEN_INT_ENTRY emulation_assist, virt=1, ool=1 2009EXC_VIRT_END(emulation_assist, 0x4e40, 0x20) 2010EXC_COMMON_BEGIN(emulation_assist_common) 2011 GEN_COMMON emulation_assist 2012 addi r3,r1,STACK_FRAME_OVERHEAD 2013 bl emulation_assist_interrupt 2014 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 2015 b interrupt_return 2016 2017 2018/** 2019 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI). 2020 * This is an asynchronous interrupt caused by a Hypervisor Maintenance 2021 * Exception. It is always taken in real mode but uses HSRR registers 2022 * unlike SRESET and MCE. 2023 * 2024 * It is maskable in hardware by clearing MSR[EE], and partially soft-maskable 2025 * with IRQS_DISABLED mask (i.e., local_irq_disable()). 2026 * 2027 * Handling: 2028 * This is a special case, this is handled similarly to machine checks, with an 2029 * initial real mode handler that is not soft-masked, which attempts to fix the 2030 * problem. Then a regular handler which is soft-maskable and reports the 2031 * problem. 2032 * 2033 * The emergency stack is used for the early real mode handler. 2034 * 2035 * XXX: unclear why MCE and HMI schemes could not be made common, e.g., 2036 * either use soft-masking for the MCE, or use irq_work for the HMI. 2037 * 2038 * KVM: 2039 * Unlike MCE, this calls into KVM without calling the real mode handler 2040 * first. 2041 */ 2042INT_DEFINE_BEGIN(hmi_exception_early) 2043 IVEC=0xe60 2044 IHSRR=1 2045 IREALMODE_COMMON=1 2046 ISTACK=0 2047 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */ 2048 IKVM_REAL=1 2049INT_DEFINE_END(hmi_exception_early) 2050 2051INT_DEFINE_BEGIN(hmi_exception) 2052 IVEC=0xe60 2053 IHSRR=1 2054 IMASK=IRQS_DISABLED 2055 IKVM_REAL=1 2056INT_DEFINE_END(hmi_exception) 2057 2058EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20) 2059 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1 2060EXC_REAL_END(hmi_exception, 0xe60, 0x20) 2061EXC_VIRT_NONE(0x4e60, 0x20) 2062 2063EXC_COMMON_BEGIN(hmi_exception_early_common) 2064 __GEN_REALMODE_COMMON_ENTRY hmi_exception_early 2065 2066 mr r10,r1 /* Save r1 */ 2067 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 2068 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 2069 2070 __GEN_COMMON_BODY hmi_exception_early 2071 2072 addi r3,r1,STACK_FRAME_OVERHEAD 2073 bl hmi_exception_realmode 2074 cmpdi cr0,r3,0 2075 bne 1f 2076 2077 EXCEPTION_RESTORE_REGS hsrr=1 2078 HRFI_TO_USER_OR_KERNEL 2079 20801: 2081 /* 2082 * Go to virtual mode and pull the HMI event information from 2083 * firmware. 2084 */ 2085 EXCEPTION_RESTORE_REGS hsrr=1 2086 GEN_INT_ENTRY hmi_exception, virt=0 2087 2088EXC_COMMON_BEGIN(hmi_exception_common) 2089 GEN_COMMON hmi_exception 2090 addi r3,r1,STACK_FRAME_OVERHEAD 2091 bl handle_hmi_exception 2092 b interrupt_return 2093 2094 2095/** 2096 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt. 2097 * This is an asynchronous interrupt in response to a msgsnd doorbell. 2098 * Similar to the 0xa00 doorbell but for host rather than guest. 2099 */ 2100INT_DEFINE_BEGIN(h_doorbell) 2101 IVEC=0xe80 2102 IHSRR=1 2103 IMASK=IRQS_DISABLED 2104 IKVM_REAL=1 2105 IKVM_VIRT=1 2106INT_DEFINE_END(h_doorbell) 2107 2108EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20) 2109 GEN_INT_ENTRY h_doorbell, virt=0, ool=1 2110EXC_REAL_END(h_doorbell, 0xe80, 0x20) 2111EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20) 2112 GEN_INT_ENTRY h_doorbell, virt=1, ool=1 2113EXC_VIRT_END(h_doorbell, 0x4e80, 0x20) 2114EXC_COMMON_BEGIN(h_doorbell_common) 2115 GEN_COMMON h_doorbell 2116 addi r3,r1,STACK_FRAME_OVERHEAD 2117#ifdef CONFIG_PPC_DOORBELL 2118 bl doorbell_exception 2119#else 2120 bl unknown_async_exception 2121#endif 2122 b interrupt_return 2123 2124 2125/** 2126 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt. 2127 * This is an asynchronous interrupt in response to an "external exception". 2128 * Similar to 0x500 but for host only. 2129 */ 2130INT_DEFINE_BEGIN(h_virt_irq) 2131 IVEC=0xea0 2132 IHSRR=1 2133 IMASK=IRQS_DISABLED 2134 IKVM_REAL=1 2135 IKVM_VIRT=1 2136INT_DEFINE_END(h_virt_irq) 2137 2138EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20) 2139 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1 2140EXC_REAL_END(h_virt_irq, 0xea0, 0x20) 2141EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20) 2142 GEN_INT_ENTRY h_virt_irq, virt=1, ool=1 2143EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20) 2144EXC_COMMON_BEGIN(h_virt_irq_common) 2145 GEN_COMMON h_virt_irq 2146 addi r3,r1,STACK_FRAME_OVERHEAD 2147 bl do_IRQ 2148 b interrupt_return 2149 2150 2151EXC_REAL_NONE(0xec0, 0x20) 2152EXC_VIRT_NONE(0x4ec0, 0x20) 2153EXC_REAL_NONE(0xee0, 0x20) 2154EXC_VIRT_NONE(0x4ee0, 0x20) 2155 2156 2157/* 2158 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU). 2159 * This is an asynchronous interrupt in response to a PMU exception. 2160 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with 2161 * IRQS_PMI_DISABLED mask (NOTE: NOT local_irq_disable()). 2162 * 2163 * Handling: 2164 * This calls into the perf subsystem. 2165 * 2166 * Like the watchdog soft-nmi, it appears an NMI interrupt to Linux, in that it 2167 * runs under local_irq_disable. However it may be soft-masked in 2168 * powerpc-specific code. 2169 * 2170 * If soft masked, the masked handler will note the pending interrupt for 2171 * replay, and clear MSR[EE] in the interrupted context. 2172 */ 2173INT_DEFINE_BEGIN(performance_monitor) 2174 IVEC=0xf00 2175 IMASK=IRQS_PMI_DISABLED 2176#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2177 IKVM_REAL=1 2178#endif 2179INT_DEFINE_END(performance_monitor) 2180 2181EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20) 2182 GEN_INT_ENTRY performance_monitor, virt=0, ool=1 2183EXC_REAL_END(performance_monitor, 0xf00, 0x20) 2184EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20) 2185 GEN_INT_ENTRY performance_monitor, virt=1, ool=1 2186EXC_VIRT_END(performance_monitor, 0x4f00, 0x20) 2187EXC_COMMON_BEGIN(performance_monitor_common) 2188 GEN_COMMON performance_monitor 2189 addi r3,r1,STACK_FRAME_OVERHEAD 2190 bl performance_monitor_exception 2191 b interrupt_return 2192 2193 2194/** 2195 * Interrupt 0xf20 - Vector Unavailable Interrupt. 2196 * This is a synchronous interrupt in response to 2197 * executing a vector (or altivec) instruction with MSR[VEC]=0. 2198 * Similar to FP unavailable. 2199 */ 2200INT_DEFINE_BEGIN(altivec_unavailable) 2201 IVEC=0xf20 2202#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2203 IKVM_REAL=1 2204#endif 2205INT_DEFINE_END(altivec_unavailable) 2206 2207EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20) 2208 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1 2209EXC_REAL_END(altivec_unavailable, 0xf20, 0x20) 2210EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20) 2211 GEN_INT_ENTRY altivec_unavailable, virt=1, ool=1 2212EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20) 2213EXC_COMMON_BEGIN(altivec_unavailable_common) 2214 GEN_COMMON altivec_unavailable 2215#ifdef CONFIG_ALTIVEC 2216BEGIN_FTR_SECTION 2217 beq 1f 2218#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 2219 BEGIN_FTR_SECTION_NESTED(69) 2220 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 2221 * transaction), go do TM stuff 2222 */ 2223 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 2224 bne- 2f 2225 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 2226#endif 2227 bl load_up_altivec 2228 b fast_interrupt_return 2229#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 22302: /* User process was in a transaction */ 2231 addi r3,r1,STACK_FRAME_OVERHEAD 2232 bl altivec_unavailable_tm 2233 b interrupt_return 2234#endif 22351: 2236END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 2237#endif 2238 addi r3,r1,STACK_FRAME_OVERHEAD 2239 bl altivec_unavailable_exception 2240 b interrupt_return 2241 2242 2243/** 2244 * Interrupt 0xf40 - VSX Unavailable Interrupt. 2245 * This is a synchronous interrupt in response to 2246 * executing a VSX instruction with MSR[VSX]=0. 2247 * Similar to FP unavailable. 2248 */ 2249INT_DEFINE_BEGIN(vsx_unavailable) 2250 IVEC=0xf40 2251#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2252 IKVM_REAL=1 2253#endif 2254INT_DEFINE_END(vsx_unavailable) 2255 2256EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20) 2257 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1 2258EXC_REAL_END(vsx_unavailable, 0xf40, 0x20) 2259EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20) 2260 GEN_INT_ENTRY vsx_unavailable, virt=1, ool=1 2261EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20) 2262EXC_COMMON_BEGIN(vsx_unavailable_common) 2263 GEN_COMMON vsx_unavailable 2264#ifdef CONFIG_VSX 2265BEGIN_FTR_SECTION 2266 beq 1f 2267#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 2268 BEGIN_FTR_SECTION_NESTED(69) 2269 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 2270 * transaction), go do TM stuff 2271 */ 2272 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 2273 bne- 2f 2274 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 2275#endif 2276 b load_up_vsx 2277#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 22782: /* User process was in a transaction */ 2279 addi r3,r1,STACK_FRAME_OVERHEAD 2280 bl vsx_unavailable_tm 2281 b interrupt_return 2282#endif 22831: 2284END_FTR_SECTION_IFSET(CPU_FTR_VSX) 2285#endif 2286 addi r3,r1,STACK_FRAME_OVERHEAD 2287 bl vsx_unavailable_exception 2288 b interrupt_return 2289 2290 2291/** 2292 * Interrupt 0xf60 - Facility Unavailable Interrupt. 2293 * This is a synchronous interrupt in response to 2294 * executing an instruction without access to the facility that can be 2295 * resolved by the OS (e.g., FSCR, MSR). 2296 * Similar to FP unavailable. 2297 */ 2298INT_DEFINE_BEGIN(facility_unavailable) 2299 IVEC=0xf60 2300#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2301 IKVM_REAL=1 2302#endif 2303INT_DEFINE_END(facility_unavailable) 2304 2305EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20) 2306 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1 2307EXC_REAL_END(facility_unavailable, 0xf60, 0x20) 2308EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20) 2309 GEN_INT_ENTRY facility_unavailable, virt=1, ool=1 2310EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20) 2311EXC_COMMON_BEGIN(facility_unavailable_common) 2312 GEN_COMMON facility_unavailable 2313 addi r3,r1,STACK_FRAME_OVERHEAD 2314 bl facility_unavailable_exception 2315 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 2316 b interrupt_return 2317 2318 2319/** 2320 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt. 2321 * This is a synchronous interrupt in response to 2322 * executing an instruction without access to the facility that can only 2323 * be resolved in HV mode (e.g., HFSCR). 2324 * Similar to FP unavailable. 2325 */ 2326INT_DEFINE_BEGIN(h_facility_unavailable) 2327 IVEC=0xf80 2328 IHSRR=1 2329 IKVM_REAL=1 2330 IKVM_VIRT=1 2331INT_DEFINE_END(h_facility_unavailable) 2332 2333EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20) 2334 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1 2335EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20) 2336EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20) 2337 GEN_INT_ENTRY h_facility_unavailable, virt=1, ool=1 2338EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20) 2339EXC_COMMON_BEGIN(h_facility_unavailable_common) 2340 GEN_COMMON h_facility_unavailable 2341 addi r3,r1,STACK_FRAME_OVERHEAD 2342 bl facility_unavailable_exception 2343 REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */ 2344 b interrupt_return 2345 2346 2347EXC_REAL_NONE(0xfa0, 0x20) 2348EXC_VIRT_NONE(0x4fa0, 0x20) 2349EXC_REAL_NONE(0xfc0, 0x20) 2350EXC_VIRT_NONE(0x4fc0, 0x20) 2351EXC_REAL_NONE(0xfe0, 0x20) 2352EXC_VIRT_NONE(0x4fe0, 0x20) 2353 2354EXC_REAL_NONE(0x1000, 0x100) 2355EXC_VIRT_NONE(0x5000, 0x100) 2356EXC_REAL_NONE(0x1100, 0x100) 2357EXC_VIRT_NONE(0x5100, 0x100) 2358 2359#ifdef CONFIG_CBE_RAS 2360INT_DEFINE_BEGIN(cbe_system_error) 2361 IVEC=0x1200 2362 IHSRR=1 2363INT_DEFINE_END(cbe_system_error) 2364 2365EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100) 2366 GEN_INT_ENTRY cbe_system_error, virt=0 2367EXC_REAL_END(cbe_system_error, 0x1200, 0x100) 2368EXC_VIRT_NONE(0x5200, 0x100) 2369EXC_COMMON_BEGIN(cbe_system_error_common) 2370 GEN_COMMON cbe_system_error 2371 addi r3,r1,STACK_FRAME_OVERHEAD 2372 bl cbe_system_error_exception 2373 b interrupt_return 2374 2375#else /* CONFIG_CBE_RAS */ 2376EXC_REAL_NONE(0x1200, 0x100) 2377EXC_VIRT_NONE(0x5200, 0x100) 2378#endif 2379 2380/** 2381 * Interrupt 0x1300 - Instruction Address Breakpoint Interrupt. 2382 * This has been removed from the ISA before 2.01, which is the earliest 2383 * 64-bit BookS ISA supported, however the G5 / 970 implements this 2384 * interrupt with a non-architected feature available through the support 2385 * processor interface. 2386 */ 2387INT_DEFINE_BEGIN(instruction_breakpoint) 2388 IVEC=0x1300 2389#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2390 IKVM_REAL=1 2391#endif 2392INT_DEFINE_END(instruction_breakpoint) 2393 2394EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100) 2395 GEN_INT_ENTRY instruction_breakpoint, virt=0 2396EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100) 2397EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100) 2398 GEN_INT_ENTRY instruction_breakpoint, virt=1 2399EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100) 2400EXC_COMMON_BEGIN(instruction_breakpoint_common) 2401 GEN_COMMON instruction_breakpoint 2402 addi r3,r1,STACK_FRAME_OVERHEAD 2403 bl instruction_breakpoint_exception 2404 b interrupt_return 2405 2406 2407EXC_REAL_NONE(0x1400, 0x100) 2408EXC_VIRT_NONE(0x5400, 0x100) 2409 2410/** 2411 * Interrupt 0x1500 - Soft Patch Interrupt 2412 * 2413 * Handling: 2414 * This is an implementation specific interrupt which can be used for a 2415 * range of exceptions. 2416 * 2417 * This interrupt handler is unique in that it runs the denormal assist 2418 * code even for guests (and even in guest context) without going to KVM, 2419 * for speed. POWER9 does not raise denorm exceptions, so this special case 2420 * could be phased out in future to reduce special cases. 2421 */ 2422INT_DEFINE_BEGIN(denorm_exception) 2423 IVEC=0x1500 2424 IHSRR=1 2425 IBRANCH_TO_COMMON=0 2426 IKVM_REAL=1 2427INT_DEFINE_END(denorm_exception) 2428 2429EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100) 2430 GEN_INT_ENTRY denorm_exception, virt=0 2431#ifdef CONFIG_PPC_DENORMALISATION 2432 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */ 2433 bne+ denorm_assist 2434#endif 2435 GEN_BRANCH_TO_COMMON denorm_exception, virt=0 2436EXC_REAL_END(denorm_exception, 0x1500, 0x100) 2437#ifdef CONFIG_PPC_DENORMALISATION 2438EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 2439 GEN_INT_ENTRY denorm_exception, virt=1 2440 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */ 2441 bne+ denorm_assist 2442 GEN_BRANCH_TO_COMMON denorm_exception, virt=1 2443EXC_VIRT_END(denorm_exception, 0x5500, 0x100) 2444#else 2445EXC_VIRT_NONE(0x5500, 0x100) 2446#endif 2447 2448#ifdef CONFIG_PPC_DENORMALISATION 2449TRAMP_REAL_BEGIN(denorm_assist) 2450BEGIN_FTR_SECTION 2451/* 2452 * To denormalise we need to move a copy of the register to itself. 2453 * For POWER6 do that here for all FP regs. 2454 */ 2455 mfmsr r10 2456 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 2457 xori r10,r10,(MSR_FE0|MSR_FE1) 2458 mtmsrd r10 2459 sync 2460 2461 .Lreg=0 2462 .rept 32 2463 fmr .Lreg,.Lreg 2464 .Lreg=.Lreg+1 2465 .endr 2466 2467FTR_SECTION_ELSE 2468/* 2469 * To denormalise we need to move a copy of the register to itself. 2470 * For POWER7 do that here for the first 32 VSX registers only. 2471 */ 2472 mfmsr r10 2473 oris r10,r10,MSR_VSX@h 2474 mtmsrd r10 2475 sync 2476 2477 .Lreg=0 2478 .rept 32 2479 XVCPSGNDP(.Lreg,.Lreg,.Lreg) 2480 .Lreg=.Lreg+1 2481 .endr 2482 2483ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 2484 2485BEGIN_FTR_SECTION 2486 b denorm_done 2487END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 2488/* 2489 * To denormalise we need to move a copy of the register to itself. 2490 * For POWER8 we need to do that for all 64 VSX registers 2491 */ 2492 .Lreg=32 2493 .rept 32 2494 XVCPSGNDP(.Lreg,.Lreg,.Lreg) 2495 .Lreg=.Lreg+1 2496 .endr 2497 2498denorm_done: 2499 mfspr r11,SPRN_HSRR0 2500 subi r11,r11,4 2501 mtspr SPRN_HSRR0,r11 2502 mtcrf 0x80,r9 2503 ld r9,PACA_EXGEN+EX_R9(r13) 2504BEGIN_FTR_SECTION 2505 ld r10,PACA_EXGEN+EX_PPR(r13) 2506 mtspr SPRN_PPR,r10 2507END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 2508BEGIN_FTR_SECTION 2509 ld r10,PACA_EXGEN+EX_CFAR(r13) 2510 mtspr SPRN_CFAR,r10 2511END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 2512 ld r10,PACA_EXGEN+EX_R10(r13) 2513 ld r11,PACA_EXGEN+EX_R11(r13) 2514 ld r12,PACA_EXGEN+EX_R12(r13) 2515 ld r13,PACA_EXGEN+EX_R13(r13) 2516 HRFI_TO_UNKNOWN 2517 b . 2518#endif 2519 2520EXC_COMMON_BEGIN(denorm_exception_common) 2521 GEN_COMMON denorm_exception 2522 addi r3,r1,STACK_FRAME_OVERHEAD 2523 bl unknown_exception 2524 b interrupt_return 2525 2526 2527#ifdef CONFIG_CBE_RAS 2528INT_DEFINE_BEGIN(cbe_maintenance) 2529 IVEC=0x1600 2530 IHSRR=1 2531INT_DEFINE_END(cbe_maintenance) 2532 2533EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100) 2534 GEN_INT_ENTRY cbe_maintenance, virt=0 2535EXC_REAL_END(cbe_maintenance, 0x1600, 0x100) 2536EXC_VIRT_NONE(0x5600, 0x100) 2537EXC_COMMON_BEGIN(cbe_maintenance_common) 2538 GEN_COMMON cbe_maintenance 2539 addi r3,r1,STACK_FRAME_OVERHEAD 2540 bl cbe_maintenance_exception 2541 b interrupt_return 2542 2543#else /* CONFIG_CBE_RAS */ 2544EXC_REAL_NONE(0x1600, 0x100) 2545EXC_VIRT_NONE(0x5600, 0x100) 2546#endif 2547 2548 2549INT_DEFINE_BEGIN(altivec_assist) 2550 IVEC=0x1700 2551#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2552 IKVM_REAL=1 2553#endif 2554INT_DEFINE_END(altivec_assist) 2555 2556EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100) 2557 GEN_INT_ENTRY altivec_assist, virt=0 2558EXC_REAL_END(altivec_assist, 0x1700, 0x100) 2559EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100) 2560 GEN_INT_ENTRY altivec_assist, virt=1 2561EXC_VIRT_END(altivec_assist, 0x5700, 0x100) 2562EXC_COMMON_BEGIN(altivec_assist_common) 2563 GEN_COMMON altivec_assist 2564 addi r3,r1,STACK_FRAME_OVERHEAD 2565#ifdef CONFIG_ALTIVEC 2566 bl altivec_assist_exception 2567 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 2568#else 2569 bl unknown_exception 2570#endif 2571 b interrupt_return 2572 2573 2574#ifdef CONFIG_CBE_RAS 2575INT_DEFINE_BEGIN(cbe_thermal) 2576 IVEC=0x1800 2577 IHSRR=1 2578INT_DEFINE_END(cbe_thermal) 2579 2580EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100) 2581 GEN_INT_ENTRY cbe_thermal, virt=0 2582EXC_REAL_END(cbe_thermal, 0x1800, 0x100) 2583EXC_VIRT_NONE(0x5800, 0x100) 2584EXC_COMMON_BEGIN(cbe_thermal_common) 2585 GEN_COMMON cbe_thermal 2586 addi r3,r1,STACK_FRAME_OVERHEAD 2587 bl cbe_thermal_exception 2588 b interrupt_return 2589 2590#else /* CONFIG_CBE_RAS */ 2591EXC_REAL_NONE(0x1800, 0x100) 2592EXC_VIRT_NONE(0x5800, 0x100) 2593#endif 2594 2595 2596#ifdef CONFIG_PPC_WATCHDOG 2597 2598INT_DEFINE_BEGIN(soft_nmi) 2599 IVEC=0x900 2600 ISTACK=0 2601INT_DEFINE_END(soft_nmi) 2602 2603/* 2604 * Branch to soft_nmi_interrupt using the emergency stack. The emergency 2605 * stack is one that is usable by maskable interrupts so long as MSR_EE 2606 * remains off. It is used for recovery when something has corrupted the 2607 * normal kernel stack, for example. The "soft NMI" must not use the process 2608 * stack because we want irq disabled sections to avoid touching the stack 2609 * at all (other than PMU interrupts), so use the emergency stack for this, 2610 * and run it entirely with interrupts hard disabled. 2611 */ 2612EXC_COMMON_BEGIN(soft_nmi_common) 2613 mfspr r11,SPRN_SRR0 2614 mr r10,r1 2615 ld r1,PACAEMERGSP(r13) 2616 subi r1,r1,INT_FRAME_SIZE 2617 __GEN_COMMON_BODY soft_nmi 2618 2619 addi r3,r1,STACK_FRAME_OVERHEAD 2620 bl soft_nmi_interrupt 2621 2622 /* Clear MSR_RI before setting SRR0 and SRR1. */ 2623 li r9,0 2624 mtmsrd r9,1 2625 2626 kuap_kernel_restore r9, r10 2627 EXCEPTION_RESTORE_REGS hsrr=0 2628 RFI_TO_KERNEL 2629 2630#endif /* CONFIG_PPC_WATCHDOG */ 2631 2632/* 2633 * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 2634 * - If it was a decrementer interrupt, we bump the dec to max and and return. 2635 * - If it was a doorbell we return immediately since doorbells are edge 2636 * triggered and won't automatically refire. 2637 * - If it was a HMI we return immediately since we handled it in realmode 2638 * and it won't refire. 2639 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. 2640 * This is called with r10 containing the value to OR to the paca field. 2641 */ 2642.macro MASKED_INTERRUPT hsrr=0 2643 .if \hsrr 2644masked_Hinterrupt: 2645 .else 2646masked_interrupt: 2647 .endif 2648 lbz r11,PACAIRQHAPPENED(r13) 2649 or r11,r11,r10 2650 stb r11,PACAIRQHAPPENED(r13) 2651 cmpwi r10,PACA_IRQ_DEC 2652 bne 1f 2653 lis r10,0x7fff 2654 ori r10,r10,0xffff 2655 mtspr SPRN_DEC,r10 2656#ifdef CONFIG_PPC_WATCHDOG 2657 b soft_nmi_common 2658#else 2659 b 2f 2660#endif 26611: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK 2662 beq 2f 2663 xori r12,r12,MSR_EE /* clear MSR_EE */ 2664 .if \hsrr 2665 mtspr SPRN_HSRR1,r12 2666 .else 2667 mtspr SPRN_SRR1,r12 2668 .endif 2669 ori r11,r11,PACA_IRQ_HARD_DIS 2670 stb r11,PACAIRQHAPPENED(r13) 26712: /* done */ 2672 ld r10,PACA_EXGEN+EX_CTR(r13) 2673 mtctr r10 2674 mtcrf 0x80,r9 2675 std r1,PACAR1(r13) 2676 ld r9,PACA_EXGEN+EX_R9(r13) 2677 ld r10,PACA_EXGEN+EX_R10(r13) 2678 ld r11,PACA_EXGEN+EX_R11(r13) 2679 ld r12,PACA_EXGEN+EX_R12(r13) 2680 ld r13,PACA_EXGEN+EX_R13(r13) 2681 /* May return to masked low address where r13 is not set up */ 2682 .if \hsrr 2683 HRFI_TO_KERNEL 2684 .else 2685 RFI_TO_KERNEL 2686 .endif 2687 b . 2688.endm 2689 2690TRAMP_REAL_BEGIN(stf_barrier_fallback) 2691 std r9,PACA_EXRFI+EX_R9(r13) 2692 std r10,PACA_EXRFI+EX_R10(r13) 2693 sync 2694 ld r9,PACA_EXRFI+EX_R9(r13) 2695 ld r10,PACA_EXRFI+EX_R10(r13) 2696 ori 31,31,0 2697 .rept 14 2698 b 1f 26991: 2700 .endr 2701 blr 2702 2703/* Clobbers r10, r11, ctr */ 2704.macro L1D_DISPLACEMENT_FLUSH 2705 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2706 ld r11,PACA_L1D_FLUSH_SIZE(r13) 2707 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2708 mtctr r11 2709 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2710 2711 /* order ld/st prior to dcbt stop all streams with flushing */ 2712 sync 2713 2714 /* 2715 * The load addresses are at staggered offsets within cachelines, 2716 * which suits some pipelines better (on others it should not 2717 * hurt). 2718 */ 27191: 2720 ld r11,(0x80 + 8)*0(r10) 2721 ld r11,(0x80 + 8)*1(r10) 2722 ld r11,(0x80 + 8)*2(r10) 2723 ld r11,(0x80 + 8)*3(r10) 2724 ld r11,(0x80 + 8)*4(r10) 2725 ld r11,(0x80 + 8)*5(r10) 2726 ld r11,(0x80 + 8)*6(r10) 2727 ld r11,(0x80 + 8)*7(r10) 2728 addi r10,r10,0x80*8 2729 bdnz 1b 2730.endm 2731 2732TRAMP_REAL_BEGIN(entry_flush_fallback) 2733 std r9,PACA_EXRFI+EX_R9(r13) 2734 std r10,PACA_EXRFI+EX_R10(r13) 2735 std r11,PACA_EXRFI+EX_R11(r13) 2736 mfctr r9 2737 L1D_DISPLACEMENT_FLUSH 2738 mtctr r9 2739 ld r9,PACA_EXRFI+EX_R9(r13) 2740 ld r10,PACA_EXRFI+EX_R10(r13) 2741 ld r11,PACA_EXRFI+EX_R11(r13) 2742 blr 2743 2744/* 2745 * The SCV entry flush happens with interrupts enabled, so it must disable 2746 * to prevent EXRFI being clobbered by NMIs (e.g., soft_nmi_common). r10 2747 * (containing LR) does not need to be preserved here because scv entry 2748 * puts 0 in the pt_regs, CTR can be clobbered for the same reason. 2749 */ 2750TRAMP_REAL_BEGIN(scv_entry_flush_fallback) 2751 li r10,0 2752 mtmsrd r10,1 2753 lbz r10,PACAIRQHAPPENED(r13) 2754 ori r10,r10,PACA_IRQ_HARD_DIS 2755 stb r10,PACAIRQHAPPENED(r13) 2756 std r11,PACA_EXRFI+EX_R11(r13) 2757 L1D_DISPLACEMENT_FLUSH 2758 ld r11,PACA_EXRFI+EX_R11(r13) 2759 li r10,MSR_RI 2760 mtmsrd r10,1 2761 blr 2762 2763TRAMP_REAL_BEGIN(rfi_flush_fallback) 2764 SET_SCRATCH0(r13); 2765 GET_PACA(r13); 2766 std r1,PACA_EXRFI+EX_R12(r13) 2767 ld r1,PACAKSAVE(r13) 2768 std r9,PACA_EXRFI+EX_R9(r13) 2769 std r10,PACA_EXRFI+EX_R10(r13) 2770 std r11,PACA_EXRFI+EX_R11(r13) 2771 mfctr r9 2772 L1D_DISPLACEMENT_FLUSH 2773 mtctr r9 2774 ld r9,PACA_EXRFI+EX_R9(r13) 2775 ld r10,PACA_EXRFI+EX_R10(r13) 2776 ld r11,PACA_EXRFI+EX_R11(r13) 2777 ld r1,PACA_EXRFI+EX_R12(r13) 2778 GET_SCRATCH0(r13); 2779 rfid 2780 2781TRAMP_REAL_BEGIN(hrfi_flush_fallback) 2782 SET_SCRATCH0(r13); 2783 GET_PACA(r13); 2784 std r1,PACA_EXRFI+EX_R12(r13) 2785 ld r1,PACAKSAVE(r13) 2786 std r9,PACA_EXRFI+EX_R9(r13) 2787 std r10,PACA_EXRFI+EX_R10(r13) 2788 std r11,PACA_EXRFI+EX_R11(r13) 2789 mfctr r9 2790 L1D_DISPLACEMENT_FLUSH 2791 mtctr r9 2792 ld r9,PACA_EXRFI+EX_R9(r13) 2793 ld r10,PACA_EXRFI+EX_R10(r13) 2794 ld r11,PACA_EXRFI+EX_R11(r13) 2795 ld r1,PACA_EXRFI+EX_R12(r13) 2796 GET_SCRATCH0(r13); 2797 hrfid 2798 2799TRAMP_REAL_BEGIN(rfscv_flush_fallback) 2800 /* system call volatile */ 2801 mr r7,r13 2802 GET_PACA(r13); 2803 mr r8,r1 2804 ld r1,PACAKSAVE(r13) 2805 mfctr r9 2806 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2807 ld r11,PACA_L1D_FLUSH_SIZE(r13) 2808 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2809 mtctr r11 2810 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2811 2812 /* order ld/st prior to dcbt stop all streams with flushing */ 2813 sync 2814 2815 /* 2816 * The load adresses are at staggered offsets within cachelines, 2817 * which suits some pipelines better (on others it should not 2818 * hurt). 2819 */ 28201: 2821 ld r11,(0x80 + 8)*0(r10) 2822 ld r11,(0x80 + 8)*1(r10) 2823 ld r11,(0x80 + 8)*2(r10) 2824 ld r11,(0x80 + 8)*3(r10) 2825 ld r11,(0x80 + 8)*4(r10) 2826 ld r11,(0x80 + 8)*5(r10) 2827 ld r11,(0x80 + 8)*6(r10) 2828 ld r11,(0x80 + 8)*7(r10) 2829 addi r10,r10,0x80*8 2830 bdnz 1b 2831 2832 mtctr r9 2833 li r9,0 2834 li r10,0 2835 li r11,0 2836 mr r1,r8 2837 mr r13,r7 2838 RFSCV 2839 2840USE_TEXT_SECTION() 2841 2842#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 2843kvm_interrupt: 2844 /* 2845 * The conditional branch in KVMTEST can't reach all the way, 2846 * make a stub. 2847 */ 2848 b kvmppc_interrupt 2849#endif 2850 2851_GLOBAL(do_uaccess_flush) 2852 UACCESS_FLUSH_FIXUP_SECTION 2853 nop 2854 nop 2855 nop 2856 blr 2857 L1D_DISPLACEMENT_FLUSH 2858 blr 2859_ASM_NOKPROBE_SYMBOL(do_uaccess_flush) 2860EXPORT_SYMBOL(do_uaccess_flush) 2861 2862 2863MASKED_INTERRUPT 2864MASKED_INTERRUPT hsrr=1 2865 2866 /* 2867 * Relocation-on interrupts: A subset of the interrupts can be delivered 2868 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 2869 * it. Addresses are the same as the original interrupt addresses, but 2870 * offset by 0xc000000000004000. 2871 * It's impossible to receive interrupts below 0x300 via this mechanism. 2872 * KVM: None of these traps are from the guest ; anything that escalated 2873 * to HV=1 from HV=0 is delivered via real mode handlers. 2874 */ 2875 2876 /* 2877 * This uses the standard macro, since the original 0x300 vector 2878 * only has extra guff for STAB-based processors -- which never 2879 * come here. 2880 */ 2881 2882USE_FIXED_SECTION(virt_trampolines) 2883 /* 2884 * All code below __end_interrupts is treated as soft-masked. If 2885 * any code runs here with MSR[EE]=1, it must then cope with pending 2886 * soft interrupt being raised (i.e., by ensuring it is replayed). 2887 * 2888 * The __end_interrupts marker must be past the out-of-line (OOL) 2889 * handlers, so that they are copied to real address 0x100 when running 2890 * a relocatable kernel. This ensures they can be reached from the short 2891 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 2892 * directly, without using LOAD_HANDLER(). 2893 */ 2894 .align 7 2895 .globl __end_interrupts 2896__end_interrupts: 2897DEFINE_FIXED_SYMBOL(__end_interrupts) 2898 2899CLOSE_FIXED_SECTION(real_vectors); 2900CLOSE_FIXED_SECTION(real_trampolines); 2901CLOSE_FIXED_SECTION(virt_vectors); 2902CLOSE_FIXED_SECTION(virt_trampolines); 2903 2904USE_TEXT_SECTION() 2905 2906/* MSR[RI] should be clear because this uses SRR[01] */ 2907enable_machine_check: 2908 mflr r0 2909 bcl 20,31,$+4 29100: mflr r3 2911 addi r3,r3,(1f - 0b) 2912 mtspr SPRN_SRR0,r3 2913 mfmsr r3 2914 ori r3,r3,MSR_ME 2915 mtspr SPRN_SRR1,r3 2916 RFI_TO_KERNEL 29171: mtlr r0 2918 blr 2919 2920/* MSR[RI] should be clear because this uses SRR[01] */ 2921disable_machine_check: 2922 mflr r0 2923 bcl 20,31,$+4 29240: mflr r3 2925 addi r3,r3,(1f - 0b) 2926 mtspr SPRN_SRR0,r3 2927 mfmsr r3 2928 li r4,MSR_ME 2929 andc r3,r3,r4 2930 mtspr SPRN_SRR1,r3 2931 RFI_TO_KERNEL 29321: mtlr r0 2933 blr 2934