1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This file contains the 64-bit "server" PowerPC variant 4 * of the low level exception handling including exception 5 * vectors, exception return, part of the slb and stab 6 * handling and other fixed offset specific things. 7 * 8 * This file is meant to be #included from head_64.S due to 9 * position dependent assembly. 10 * 11 * Most of this originates from head_64.S and thus has the same 12 * copyright history. 13 * 14 */ 15 16#include <asm/hw_irq.h> 17#include <asm/exception-64s.h> 18#include <asm/ptrace.h> 19#include <asm/cpuidle.h> 20#include <asm/head-64.h> 21#include <asm/feature-fixups.h> 22 23/* 24 * There are a few constraints to be concerned with. 25 * - Real mode exceptions code/data must be located at their physical location. 26 * - Virtual mode exceptions must be mapped at their 0xc000... location. 27 * - Fixed location code must not call directly beyond the __end_interrupts 28 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 29 * must be used. 30 * - LOAD_HANDLER targets must be within first 64K of physical 0 / 31 * virtual 0xc00... 32 * - Conditional branch targets must be within +/-32K of caller. 33 * 34 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 35 * therefore don't have to run in physically located code or rfid to 36 * virtual mode kernel code. However on relocatable kernels they do have 37 * to branch to KERNELBASE offset because the rest of the kernel (outside 38 * the exception vectors) may be located elsewhere. 39 * 40 * Virtual exceptions correspond with physical, except their entry points 41 * are offset by 0xc000000000000000 and also tend to get an added 0x4000 42 * offset applied. Virtual exceptions are enabled with the Alternate 43 * Interrupt Location (AIL) bit set in the LPCR. However this does not 44 * guarantee they will be delivered virtually. Some conditions (see the ISA) 45 * cause exceptions to be delivered in real mode. 46 * 47 * It's impossible to receive interrupts below 0x300 via AIL. 48 * 49 * KVM: None of the virtual exceptions are from the guest. Anything that 50 * escalated to HV=1 from HV=0 is delivered via real mode handlers. 51 * 52 * 53 * We layout physical memory as follows: 54 * 0x0000 - 0x00ff : Secondary processor spin code 55 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 56 * 0x1900 - 0x3fff : Real mode trampolines 57 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 58 * 0x5900 - 0x6fff : Relon mode trampolines 59 * 0x7000 - 0x7fff : FWNMI data area 60 * 0x8000 - .... : Common interrupt handlers, remaining early 61 * setup code, rest of kernel. 62 * 63 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 64 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 65 * vectors there. 66 */ 67OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 68OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 69OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 70OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 71#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 72/* 73 * Data area reserved for FWNMI option. 74 * This address (0x7000) is fixed by the RPA. 75 * pseries and powernv need to keep the whole page from 76 * 0x7000 to 0x8000 free for use by the firmware 77 */ 78ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 79OPEN_TEXT_SECTION(0x8000) 80#else 81OPEN_TEXT_SECTION(0x7000) 82#endif 83 84USE_FIXED_SECTION(real_vectors) 85 86/* 87 * This is the start of the interrupt handlers for pSeries 88 * This code runs with relocation off. 89 * Code from here to __end_interrupts gets copied down to real 90 * address 0x100 when we are running a relocatable kernel. 91 * Therefore any relative branches in this section must only 92 * branch to labels in this section. 93 */ 94 .globl __start_interrupts 95__start_interrupts: 96 97/* No virt vectors corresponding with 0x0..0x100 */ 98EXC_VIRT_NONE(0x4000, 0x100) 99 100 101#ifdef CONFIG_PPC_P7_NAP 102 /* 103 * If running native on arch 2.06 or later, check if we are waking up 104 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 105 * bits 46:47. A non-0 value indicates that we are coming from a power 106 * saving state. The idle wakeup handler initially runs in real mode, 107 * but we branch to the 0xc000... address so we can turn on relocation 108 * with mtmsr. 109 */ 110#define IDLETEST(n) \ 111 BEGIN_FTR_SECTION ; \ 112 mfspr r10,SPRN_SRR1 ; \ 113 rlwinm. r10,r10,47-31,30,31 ; \ 114 beq- 1f ; \ 115 cmpwi cr3,r10,2 ; \ 116 BRANCH_TO_C000(r10, system_reset_idle_common) ; \ 1171: \ 118 KVMTEST_PR(n) ; \ 119 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 120#else 121#define IDLETEST NOTEST 122#endif 123 124EXC_REAL_BEGIN(system_reset, 0x100, 0x100) 125 SET_SCRATCH0(r13) 126 /* 127 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 128 * being used, so a nested NMI exception would corrupt it. 129 */ 130 EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, 131 IDLETEST, 0x100) 132 133EXC_REAL_END(system_reset, 0x100, 0x100) 134EXC_VIRT_NONE(0x4100, 0x100) 135TRAMP_KVM(PACA_EXNMI, 0x100) 136 137#ifdef CONFIG_PPC_P7_NAP 138EXC_COMMON_BEGIN(system_reset_idle_common) 139 mfspr r12,SPRN_SRR1 140 b pnv_powersave_wakeup 141#endif 142 143/* 144 * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does 145 * the right thing. We do not want to reconcile because that goes 146 * through irq tracing which we don't want in NMI. 147 * 148 * Save PACAIRQHAPPENED because some code will do a hard disable 149 * (e.g., xmon). So we want to restore this back to where it was 150 * when we return. DAR is unused in the stack, so save it there. 151 */ 152#define ADD_RECONCILE_NMI \ 153 li r10,IRQS_ALL_DISABLED; \ 154 stb r10,PACAIRQSOFTMASK(r13); \ 155 lbz r10,PACAIRQHAPPENED(r13); \ 156 std r10,_DAR(r1) 157 158EXC_COMMON_BEGIN(system_reset_common) 159 /* 160 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 161 * to recover, but nested NMI will notice in_nmi and not recover 162 * because of the use of the NMI stack. in_nmi reentrancy is tested in 163 * system_reset_exception. 164 */ 165 lhz r10,PACA_IN_NMI(r13) 166 addi r10,r10,1 167 sth r10,PACA_IN_NMI(r13) 168 li r10,MSR_RI 169 mtmsrd r10,1 170 171 mr r10,r1 172 ld r1,PACA_NMI_EMERG_SP(r13) 173 subi r1,r1,INT_FRAME_SIZE 174 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, 175 system_reset, system_reset_exception, 176 ADD_NVGPRS;ADD_RECONCILE_NMI) 177 178 /* This (and MCE) can be simplified with mtmsrd L=1 */ 179 /* Clear MSR_RI before setting SRR0 and SRR1. */ 180 li r0,MSR_RI 181 mfmsr r9 182 andc r9,r9,r0 183 mtmsrd r9,1 184 185 /* 186 * MSR_RI is clear, now we can decrement paca->in_nmi. 187 */ 188 lhz r10,PACA_IN_NMI(r13) 189 subi r10,r10,1 190 sth r10,PACA_IN_NMI(r13) 191 192 /* 193 * Restore soft mask settings. 194 */ 195 ld r10,_DAR(r1) 196 stb r10,PACAIRQHAPPENED(r13) 197 ld r10,SOFTE(r1) 198 stb r10,PACAIRQSOFTMASK(r13) 199 200 /* 201 * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP. 202 * Should share common bits... 203 */ 204 205 /* Move original SRR0 and SRR1 into the respective regs */ 206 ld r9,_MSR(r1) 207 mtspr SPRN_SRR1,r9 208 ld r3,_NIP(r1) 209 mtspr SPRN_SRR0,r3 210 ld r9,_CTR(r1) 211 mtctr r9 212 ld r9,_XER(r1) 213 mtxer r9 214 ld r9,_LINK(r1) 215 mtlr r9 216 REST_GPR(0, r1) 217 REST_8GPRS(2, r1) 218 REST_GPR(10, r1) 219 ld r11,_CCR(r1) 220 mtcr r11 221 REST_GPR(11, r1) 222 REST_2GPRS(12, r1) 223 /* restore original r1. */ 224 ld r1,GPR1(r1) 225 RFI_TO_USER_OR_KERNEL 226 227#ifdef CONFIG_PPC_PSERIES 228/* 229 * Vectors for the FWNMI option. Share common code. 230 */ 231TRAMP_REAL_BEGIN(system_reset_fwnmi) 232 SET_SCRATCH0(r13) /* save r13 */ 233 /* See comment at system_reset exception */ 234 EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, 235 NOTEST, 0x100) 236#endif /* CONFIG_PPC_PSERIES */ 237 238 239EXC_REAL_BEGIN(machine_check, 0x200, 0x100) 240 /* This is moved out of line as it can be patched by FW, but 241 * some code path might still want to branch into the original 242 * vector 243 */ 244 SET_SCRATCH0(r13) /* save r13 */ 245 EXCEPTION_PROLOG_0(PACA_EXMC) 246BEGIN_FTR_SECTION 247 b machine_check_common_early 248FTR_SECTION_ELSE 249 b machine_check_pSeries_0 250ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 251EXC_REAL_END(machine_check, 0x200, 0x100) 252EXC_VIRT_NONE(0x4200, 0x100) 253TRAMP_REAL_BEGIN(machine_check_common_early) 254 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) 255 /* 256 * Register contents: 257 * R13 = PACA 258 * R9 = CR 259 * Original R9 to R13 is saved on PACA_EXMC 260 * 261 * Switch to mc_emergency stack and handle re-entrancy (we limit 262 * the nested MCE upto level 4 to avoid stack overflow). 263 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 264 * 265 * We use paca->in_mce to check whether this is the first entry or 266 * nested machine check. We increment paca->in_mce to track nested 267 * machine checks. 268 * 269 * If this is the first entry then set stack pointer to 270 * paca->mc_emergency_sp, otherwise r1 is already pointing to 271 * stack frame on mc_emergency stack. 272 * 273 * NOTE: We are here with MSR_ME=0 (off), which means we risk a 274 * checkstop if we get another machine check exception before we do 275 * rfid with MSR_ME=1. 276 * 277 * This interrupt can wake directly from idle. If that is the case, 278 * the machine check is handled then the idle wakeup code is called 279 * to restore state. 280 */ 281 mr r11,r1 /* Save r1 */ 282 lhz r10,PACA_IN_MCE(r13) 283 cmpwi r10,0 /* Are we in nested machine check */ 284 bne 0f /* Yes, we are. */ 285 /* First machine check entry */ 286 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 2870: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 288 addi r10,r10,1 /* increment paca->in_mce */ 289 sth r10,PACA_IN_MCE(r13) 290 /* Limit nested MCE to level 4 to avoid stack overflow */ 291 cmpwi r10,MAX_MCE_DEPTH 292 bgt 2f /* Check if we hit limit of 4 */ 293 std r11,GPR1(r1) /* Save r1 on the stack. */ 294 std r11,0(r1) /* make stack chain pointer */ 295 mfspr r11,SPRN_SRR0 /* Save SRR0 */ 296 std r11,_NIP(r1) 297 mfspr r11,SPRN_SRR1 /* Save SRR1 */ 298 std r11,_MSR(r1) 299 mfspr r11,SPRN_DAR /* Save DAR */ 300 std r11,_DAR(r1) 301 mfspr r11,SPRN_DSISR /* Save DSISR */ 302 std r11,_DSISR(r1) 303 std r9,_CCR(r1) /* Save CR in stackframe */ 304 /* Save r9 through r13 from EXMC save area to stack frame. */ 305 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 306 mfmsr r11 /* get MSR value */ 307BEGIN_FTR_SECTION 308 ori r11,r11,MSR_ME /* turn on ME bit */ 309END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 310 ori r11,r11,MSR_RI /* turn on RI bit */ 311 LOAD_HANDLER(r12, machine_check_handle_early) 3121: mtspr SPRN_SRR0,r12 313 mtspr SPRN_SRR1,r11 314 RFI_TO_KERNEL 315 b . /* prevent speculative execution */ 3162: 317 /* Stack overflow. Stay on emergency stack and panic. 318 * Keep the ME bit off while panic-ing, so that if we hit 319 * another machine check we checkstop. 320 */ 321 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 322 ld r11,PACAKMSR(r13) 323 LOAD_HANDLER(r12, unrecover_mce) 324 li r10,MSR_ME 325 andc r11,r11,r10 /* Turn off MSR_ME */ 326 b 1b 327 b . /* prevent speculative execution */ 328 329TRAMP_REAL_BEGIN(machine_check_pSeries) 330 .globl machine_check_fwnmi 331machine_check_fwnmi: 332 SET_SCRATCH0(r13) /* save r13 */ 333 EXCEPTION_PROLOG_0(PACA_EXMC) 334BEGIN_FTR_SECTION 335 b machine_check_common_early 336END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 337machine_check_pSeries_0: 338 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) 339 /* 340 * MSR_RI is not enabled, because PACA_EXMC is being used, so a 341 * nested machine check corrupts it. machine_check_common enables 342 * MSR_RI. 343 */ 344 EXCEPTION_PROLOG_2_NORI(machine_check_common, EXC_STD) 345 346TRAMP_KVM_SKIP(PACA_EXMC, 0x200) 347 348EXC_COMMON_BEGIN(machine_check_common) 349 /* 350 * Machine check is different because we use a different 351 * save area: PACA_EXMC instead of PACA_EXGEN. 352 */ 353 mfspr r10,SPRN_DAR 354 std r10,PACA_EXMC+EX_DAR(r13) 355 mfspr r10,SPRN_DSISR 356 stw r10,PACA_EXMC+EX_DSISR(r13) 357 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 358 FINISH_NAP 359 RECONCILE_IRQ_STATE(r10, r11) 360 ld r3,PACA_EXMC+EX_DAR(r13) 361 lwz r4,PACA_EXMC+EX_DSISR(r13) 362 /* Enable MSR_RI when finished with PACA_EXMC */ 363 li r10,MSR_RI 364 mtmsrd r10,1 365 std r3,_DAR(r1) 366 std r4,_DSISR(r1) 367 bl save_nvgprs 368 addi r3,r1,STACK_FRAME_OVERHEAD 369 bl machine_check_exception 370 b ret_from_except 371 372#define MACHINE_CHECK_HANDLER_WINDUP \ 373 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 374 li r0,MSR_RI; \ 375 mfmsr r9; /* get MSR value */ \ 376 andc r9,r9,r0; \ 377 mtmsrd r9,1; /* Clear MSR_RI */ \ 378 /* Move original SRR0 and SRR1 into the respective regs */ \ 379 ld r9,_MSR(r1); \ 380 mtspr SPRN_SRR1,r9; \ 381 ld r3,_NIP(r1); \ 382 mtspr SPRN_SRR0,r3; \ 383 ld r9,_CTR(r1); \ 384 mtctr r9; \ 385 ld r9,_XER(r1); \ 386 mtxer r9; \ 387 ld r9,_LINK(r1); \ 388 mtlr r9; \ 389 REST_GPR(0, r1); \ 390 REST_8GPRS(2, r1); \ 391 REST_GPR(10, r1); \ 392 ld r11,_CCR(r1); \ 393 mtcr r11; \ 394 /* Decrement paca->in_mce. */ \ 395 lhz r12,PACA_IN_MCE(r13); \ 396 subi r12,r12,1; \ 397 sth r12,PACA_IN_MCE(r13); \ 398 REST_GPR(11, r1); \ 399 REST_2GPRS(12, r1); \ 400 /* restore original r1. */ \ 401 ld r1,GPR1(r1) 402 403#ifdef CONFIG_PPC_P7_NAP 404/* 405 * This is an idle wakeup. Low level machine check has already been 406 * done. Queue the event then call the idle code to do the wake up. 407 */ 408EXC_COMMON_BEGIN(machine_check_idle_common) 409 bl machine_check_queue_event 410 411 /* 412 * We have not used any non-volatile GPRs here, and as a rule 413 * most exception code including machine check does not. 414 * Therefore PACA_NAPSTATELOST does not need to be set. Idle 415 * wakeup will restore volatile registers. 416 * 417 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. 418 * 419 * Then decrement MCE nesting after finishing with the stack. 420 */ 421 ld r3,_MSR(r1) 422 423 lhz r11,PACA_IN_MCE(r13) 424 subi r11,r11,1 425 sth r11,PACA_IN_MCE(r13) 426 427 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ 428 /* Recoverability could be improved by reducing the use of SRR1. */ 429 li r11,0 430 mtmsrd r11,1 431 432 b pnv_powersave_wakeup_mce 433#endif 434 /* 435 * Handle machine check early in real mode. We come here with 436 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 437 */ 438EXC_COMMON_BEGIN(machine_check_handle_early) 439 std r0,GPR0(r1) /* Save r0 */ 440 EXCEPTION_PROLOG_COMMON_3(0x200) 441 bl save_nvgprs 442 addi r3,r1,STACK_FRAME_OVERHEAD 443 bl machine_check_early 444 std r3,RESULT(r1) /* Save result */ 445 ld r12,_MSR(r1) 446BEGIN_FTR_SECTION 447 b 4f 448END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 449 450#ifdef CONFIG_PPC_P7_NAP 451 /* 452 * Check if thread was in power saving mode. We come here when any 453 * of the following is true: 454 * a. thread wasn't in power saving mode 455 * b. thread was in power saving mode with no state loss, 456 * supervisor state loss or hypervisor state loss. 457 * 458 * Go back to nap/sleep/winkle mode again if (b) is true. 459 */ 460 BEGIN_FTR_SECTION 461 rlwinm. r11,r12,47-31,30,31 462 bne machine_check_idle_common 463 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 464#endif 465 466 /* 467 * Check if we are coming from hypervisor userspace. If yes then we 468 * continue in host kernel in V mode to deliver the MC event. 469 */ 470 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 471 beq 5f 4724: andi. r11,r12,MSR_PR /* See if coming from user. */ 473 bne 9f /* continue in V mode if we are. */ 474 4755: 476#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 477BEGIN_FTR_SECTION 478 /* 479 * We are coming from kernel context. Check if we are coming from 480 * guest. if yes, then we can continue. We will fall through 481 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 482 */ 483 lbz r11,HSTATE_IN_GUEST(r13) 484 cmpwi r11,0 /* Check if coming from guest */ 485 bne 9f /* continue if we are. */ 486END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 487#endif 488 /* 489 * At this point we are not sure about what context we come from. 490 * Queue up the MCE event and return from the interrupt. 491 * But before that, check if this is an un-recoverable exception. 492 * If yes, then stay on emergency stack and panic. 493 */ 494 andi. r11,r12,MSR_RI 495 bne 2f 4961: mfspr r11,SPRN_SRR0 497 LOAD_HANDLER(r10,unrecover_mce) 498 mtspr SPRN_SRR0,r10 499 ld r10,PACAKMSR(r13) 500 /* 501 * We are going down. But there are chances that we might get hit by 502 * another MCE during panic path and we may run into unstable state 503 * with no way out. Hence, turn ME bit off while going down, so that 504 * when another MCE is hit during panic path, system will checkstop 505 * and hypervisor will get restarted cleanly by SP. 506 */ 507 li r3,MSR_ME 508 andc r10,r10,r3 /* Turn off MSR_ME */ 509 mtspr SPRN_SRR1,r10 510 RFI_TO_KERNEL 511 b . 5122: 513 /* 514 * Check if we have successfully handled/recovered from error, if not 515 * then stay on emergency stack and panic. 516 */ 517 ld r3,RESULT(r1) /* Load result */ 518 cmpdi r3,0 /* see if we handled MCE successfully */ 519 520 beq 1b /* if !handled then panic */ 521BEGIN_FTR_SECTION 522 /* 523 * Return from MC interrupt. 524 * Queue up the MCE event so that we can log it later, while 525 * returning from kernel or opal call. 526 */ 527 bl machine_check_queue_event 528 MACHINE_CHECK_HANDLER_WINDUP 529 RFI_TO_USER_OR_KERNEL 530FTR_SECTION_ELSE 531 /* 532 * pSeries: Return from MC interrupt. Before that stay on emergency 533 * stack and call machine_check_exception to log the MCE event. 534 */ 535 LOAD_HANDLER(r10,mce_return) 536 mtspr SPRN_SRR0,r10 537 ld r10,PACAKMSR(r13) 538 mtspr SPRN_SRR1,r10 539 RFI_TO_KERNEL 540 b . 541ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 5429: 543 /* Deliver the machine check to host kernel in V mode. */ 544 MACHINE_CHECK_HANDLER_WINDUP 545 SET_SCRATCH0(r13) /* save r13 */ 546 EXCEPTION_PROLOG_0(PACA_EXMC) 547 b machine_check_pSeries_0 548 549EXC_COMMON_BEGIN(unrecover_mce) 550 /* Invoke machine_check_exception to print MCE event and panic. */ 551 addi r3,r1,STACK_FRAME_OVERHEAD 552 bl machine_check_exception 553 /* 554 * We will not reach here. Even if we did, there is no way out. Call 555 * unrecoverable_exception and die. 556 */ 5571: addi r3,r1,STACK_FRAME_OVERHEAD 558 bl unrecoverable_exception 559 b 1b 560 561EXC_COMMON_BEGIN(mce_return) 562 /* Invoke machine_check_exception to print MCE event and return. */ 563 addi r3,r1,STACK_FRAME_OVERHEAD 564 bl machine_check_exception 565 MACHINE_CHECK_HANDLER_WINDUP 566 RFI_TO_KERNEL 567 b . 568 569EXC_REAL(data_access, 0x300, 0x80) 570EXC_VIRT(data_access, 0x4300, 0x80, 0x300) 571TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 572 573EXC_COMMON_BEGIN(data_access_common) 574 /* 575 * Here r13 points to the paca, r9 contains the saved CR, 576 * SRR0 and SRR1 are saved in r11 and r12, 577 * r9 - r13 are saved in paca->exgen. 578 */ 579 mfspr r10,SPRN_DAR 580 std r10,PACA_EXGEN+EX_DAR(r13) 581 mfspr r10,SPRN_DSISR 582 stw r10,PACA_EXGEN+EX_DSISR(r13) 583 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 584 RECONCILE_IRQ_STATE(r10, r11) 585 ld r12,_MSR(r1) 586 ld r3,PACA_EXGEN+EX_DAR(r13) 587 lwz r4,PACA_EXGEN+EX_DSISR(r13) 588 li r5,0x300 589 std r3,_DAR(r1) 590 std r4,_DSISR(r1) 591BEGIN_MMU_FTR_SECTION 592 b do_hash_page /* Try to handle as hpte fault */ 593MMU_FTR_SECTION_ELSE 594 b handle_page_fault 595ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 596 597 598EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 599EXCEPTION_PROLOG(PACA_EXSLB, data_access_slb_common, EXC_STD, KVMTEST_PR, 0x380); 600EXC_REAL_END(data_access_slb, 0x380, 0x80) 601 602EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 603EXCEPTION_RELON_PROLOG(PACA_EXSLB, data_access_slb_common, EXC_STD, NOTEST, 0x380); 604EXC_VIRT_END(data_access_slb, 0x4380, 0x80) 605 606TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 607 608EXC_COMMON_BEGIN(data_access_slb_common) 609 mfspr r10,SPRN_DAR 610 std r10,PACA_EXSLB+EX_DAR(r13) 611 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) 612 ld r4,PACA_EXSLB+EX_DAR(r13) 613 std r4,_DAR(r1) 614 addi r3,r1,STACK_FRAME_OVERHEAD 615 bl do_slb_fault 616 cmpdi r3,0 617 bne- 1f 618 b fast_exception_return 6191: /* Error case */ 620 std r3,RESULT(r1) 621 bl save_nvgprs 622 RECONCILE_IRQ_STATE(r10, r11) 623 ld r4,_DAR(r1) 624 ld r5,RESULT(r1) 625 addi r3,r1,STACK_FRAME_OVERHEAD 626 bl do_bad_slb_fault 627 b ret_from_except 628 629 630EXC_REAL(instruction_access, 0x400, 0x80) 631EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 632TRAMP_KVM(PACA_EXGEN, 0x400) 633 634EXC_COMMON_BEGIN(instruction_access_common) 635 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 636 RECONCILE_IRQ_STATE(r10, r11) 637 ld r12,_MSR(r1) 638 ld r3,_NIP(r1) 639 andis. r4,r12,DSISR_SRR1_MATCH_64S@h 640 li r5,0x400 641 std r3,_DAR(r1) 642 std r4,_DSISR(r1) 643BEGIN_MMU_FTR_SECTION 644 b do_hash_page /* Try to handle as hpte fault */ 645MMU_FTR_SECTION_ELSE 646 b handle_page_fault 647ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 648 649 650EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) 651EXCEPTION_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, KVMTEST_PR, 0x480); 652EXC_REAL_END(instruction_access_slb, 0x480, 0x80) 653 654EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) 655EXCEPTION_RELON_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, NOTEST, 0x480); 656EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) 657 658TRAMP_KVM(PACA_EXSLB, 0x480) 659 660EXC_COMMON_BEGIN(instruction_access_slb_common) 661 EXCEPTION_PROLOG_COMMON(0x480, PACA_EXSLB) 662 ld r4,_NIP(r1) 663 addi r3,r1,STACK_FRAME_OVERHEAD 664 bl do_slb_fault 665 cmpdi r3,0 666 bne- 1f 667 b fast_exception_return 6681: /* Error case */ 669 std r3,RESULT(r1) 670 bl save_nvgprs 671 RECONCILE_IRQ_STATE(r10, r11) 672 ld r4,_NIP(r1) 673 ld r5,RESULT(r1) 674 addi r3,r1,STACK_FRAME_OVERHEAD 675 bl do_bad_slb_fault 676 b ret_from_except 677 678 679EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 680 .globl hardware_interrupt_hv; 681hardware_interrupt_hv: 682 BEGIN_FTR_SECTION 683 MASKABLE_EXCEPTION_HV(0x500, hardware_interrupt_common, IRQS_DISABLED) 684 FTR_SECTION_ELSE 685 MASKABLE_EXCEPTION(0x500, hardware_interrupt_common, IRQS_DISABLED) 686 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 687EXC_REAL_END(hardware_interrupt, 0x500, 0x100) 688 689EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 690 .globl hardware_interrupt_relon_hv; 691hardware_interrupt_relon_hv: 692 BEGIN_FTR_SECTION 693 MASKABLE_RELON_EXCEPTION_HV(0x500, hardware_interrupt_common, 694 IRQS_DISABLED) 695 FTR_SECTION_ELSE 696 __MASKABLE_RELON_EXCEPTION(0x500, hardware_interrupt_common, 697 EXC_STD, SOFTEN_TEST_PR, IRQS_DISABLED) 698 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 699EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 700 701TRAMP_KVM(PACA_EXGEN, 0x500) 702TRAMP_KVM_HV(PACA_EXGEN, 0x500) 703EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 704 705 706EXC_REAL(alignment, 0x600, 0x100) 707EXC_VIRT(alignment, 0x4600, 0x100, 0x600) 708TRAMP_KVM(PACA_EXGEN, 0x600) 709EXC_COMMON_BEGIN(alignment_common) 710 mfspr r10,SPRN_DAR 711 std r10,PACA_EXGEN+EX_DAR(r13) 712 mfspr r10,SPRN_DSISR 713 stw r10,PACA_EXGEN+EX_DSISR(r13) 714 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 715 ld r3,PACA_EXGEN+EX_DAR(r13) 716 lwz r4,PACA_EXGEN+EX_DSISR(r13) 717 std r3,_DAR(r1) 718 std r4,_DSISR(r1) 719 bl save_nvgprs 720 RECONCILE_IRQ_STATE(r10, r11) 721 addi r3,r1,STACK_FRAME_OVERHEAD 722 bl alignment_exception 723 b ret_from_except 724 725 726EXC_REAL(program_check, 0x700, 0x100) 727EXC_VIRT(program_check, 0x4700, 0x100, 0x700) 728TRAMP_KVM(PACA_EXGEN, 0x700) 729EXC_COMMON_BEGIN(program_check_common) 730 /* 731 * It's possible to receive a TM Bad Thing type program check with 732 * userspace register values (in particular r1), but with SRR1 reporting 733 * that we came from the kernel. Normally that would confuse the bad 734 * stack logic, and we would report a bad kernel stack pointer. Instead 735 * we switch to the emergency stack if we're taking a TM Bad Thing from 736 * the kernel. 737 */ 738 li r10,MSR_PR /* Build a mask of MSR_PR .. */ 739 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ 740 and r10,r10,r12 /* Mask SRR1 with that. */ 741 srdi r10,r10,8 /* Shift it so we can compare */ 742 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ 743 bne 1f /* If != go to normal path. */ 744 745 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ 746 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ 747 /* 3 in EXCEPTION_PROLOG_COMMON */ 748 mr r10,r1 /* Save r1 */ 749 ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 750 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 751 b 3f /* Jump into the macro !! */ 7521: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 753 bl save_nvgprs 754 RECONCILE_IRQ_STATE(r10, r11) 755 addi r3,r1,STACK_FRAME_OVERHEAD 756 bl program_check_exception 757 b ret_from_except 758 759 760EXC_REAL(fp_unavailable, 0x800, 0x100) 761EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 762TRAMP_KVM(PACA_EXGEN, 0x800) 763EXC_COMMON_BEGIN(fp_unavailable_common) 764 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 765 bne 1f /* if from user, just load it up */ 766 bl save_nvgprs 767 RECONCILE_IRQ_STATE(r10, r11) 768 addi r3,r1,STACK_FRAME_OVERHEAD 769 bl kernel_fp_unavailable_exception 770 BUG_OPCODE 7711: 772#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 773BEGIN_FTR_SECTION 774 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 775 * transaction), go do TM stuff 776 */ 777 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 778 bne- 2f 779END_FTR_SECTION_IFSET(CPU_FTR_TM) 780#endif 781 bl load_up_fpu 782 b fast_exception_return 783#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 7842: /* User process was in a transaction */ 785 bl save_nvgprs 786 RECONCILE_IRQ_STATE(r10, r11) 787 addi r3,r1,STACK_FRAME_OVERHEAD 788 bl fp_unavailable_tm 789 b ret_from_except 790#endif 791 792 793EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) 794EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) 795TRAMP_KVM(PACA_EXGEN, 0x900) 796EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 797 798 799EXC_REAL_HV(hdecrementer, 0x980, 0x80) 800EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 801TRAMP_KVM_HV(PACA_EXGEN, 0x980) 802EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 803 804 805EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) 806EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) 807TRAMP_KVM(PACA_EXGEN, 0xa00) 808#ifdef CONFIG_PPC_DOORBELL 809EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 810#else 811EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 812#endif 813 814 815EXC_REAL(trap_0b, 0xb00, 0x100) 816EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 817TRAMP_KVM(PACA_EXGEN, 0xb00) 818EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 819 820/* 821 * system call / hypercall (0xc00, 0x4c00) 822 * 823 * The system call exception is invoked with "sc 0" and does not alter HV bit. 824 * There is support for kernel code to invoke system calls but there are no 825 * in-tree users. 826 * 827 * The hypercall is invoked with "sc 1" and sets HV=1. 828 * 829 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 830 * 0x4c00 virtual mode. 831 * 832 * Call convention: 833 * 834 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt 835 * 836 * For hypercalls, the register convention is as follows: 837 * r0 volatile 838 * r1-2 nonvolatile 839 * r3 volatile parameter and return value for status 840 * r4-r10 volatile input and output value 841 * r11 volatile hypercall number and output value 842 * r12 volatile input and output value 843 * r13-r31 nonvolatile 844 * LR nonvolatile 845 * CTR volatile 846 * XER volatile 847 * CR0-1 CR5-7 volatile 848 * CR2-4 nonvolatile 849 * Other registers nonvolatile 850 * 851 * The intersection of volatile registers that don't contain possible 852 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 853 * without saving, though xer is not a good idea to use, as hardware may 854 * interpret some bits so it may be costly to change them. 855 */ 856#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 857 /* 858 * There is a little bit of juggling to get syscall and hcall 859 * working well. Save r13 in ctr to avoid using SPRG scratch 860 * register. 861 * 862 * Userspace syscalls have already saved the PPR, hcalls must save 863 * it before setting HMT_MEDIUM. 864 */ 865#define SYSCALL_KVMTEST \ 866 mtctr r13; \ 867 GET_PACA(r13); \ 868 std r10,PACA_EXGEN+EX_R10(r13); \ 869 INTERRUPT_TO_KERNEL; \ 870 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \ 871 HMT_MEDIUM; \ 872 mfctr r9; 873 874#else 875#define SYSCALL_KVMTEST \ 876 HMT_MEDIUM; \ 877 mr r9,r13; \ 878 GET_PACA(r13); \ 879 INTERRUPT_TO_KERNEL; 880#endif 881 882#define LOAD_SYSCALL_HANDLER(reg) \ 883 __LOAD_HANDLER(reg, system_call_common) 884 885/* 886 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, 887 * and HMT_MEDIUM. 888 */ 889#define SYSCALL_REAL \ 890 mfspr r11,SPRN_SRR0 ; \ 891 mfspr r12,SPRN_SRR1 ; \ 892 LOAD_SYSCALL_HANDLER(r10) ; \ 893 mtspr SPRN_SRR0,r10 ; \ 894 ld r10,PACAKMSR(r13) ; \ 895 mtspr SPRN_SRR1,r10 ; \ 896 RFI_TO_KERNEL ; \ 897 b . ; /* prevent speculative execution */ 898 899#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 900#define SYSCALL_FASTENDIAN_TEST \ 901BEGIN_FTR_SECTION \ 902 cmpdi r0,0x1ebe ; \ 903 beq- 1f ; \ 904END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 905 906#define SYSCALL_FASTENDIAN \ 907 /* Fast LE/BE switch system call */ \ 9081: mfspr r12,SPRN_SRR1 ; \ 909 xori r12,r12,MSR_LE ; \ 910 mtspr SPRN_SRR1,r12 ; \ 911 mr r13,r9 ; \ 912 RFI_TO_USER ; /* return to userspace */ \ 913 b . ; /* prevent speculative execution */ 914#else 915#define SYSCALL_FASTENDIAN_TEST 916#define SYSCALL_FASTENDIAN 917#endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */ 918 919#if defined(CONFIG_RELOCATABLE) 920 /* 921 * We can't branch directly so we do it via the CTR which 922 * is volatile across system calls. 923 */ 924#define SYSCALL_VIRT \ 925 LOAD_SYSCALL_HANDLER(r10) ; \ 926 mtctr r10 ; \ 927 mfspr r11,SPRN_SRR0 ; \ 928 mfspr r12,SPRN_SRR1 ; \ 929 li r10,MSR_RI ; \ 930 mtmsrd r10,1 ; \ 931 bctr ; 932#else 933 /* We can branch directly */ 934#define SYSCALL_VIRT \ 935 mfspr r11,SPRN_SRR0 ; \ 936 mfspr r12,SPRN_SRR1 ; \ 937 li r10,MSR_RI ; \ 938 mtmsrd r10,1 ; /* Set RI (EE=0) */ \ 939 b system_call_common ; 940#endif 941 942EXC_REAL_BEGIN(system_call, 0xc00, 0x100) 943 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 944 SYSCALL_FASTENDIAN_TEST 945 SYSCALL_REAL 946 SYSCALL_FASTENDIAN 947EXC_REAL_END(system_call, 0xc00, 0x100) 948 949EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 950 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 951 SYSCALL_FASTENDIAN_TEST 952 SYSCALL_VIRT 953 SYSCALL_FASTENDIAN 954EXC_VIRT_END(system_call, 0x4c00, 0x100) 955 956#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 957 /* 958 * This is a hcall, so register convention is as above, with these 959 * differences: 960 * r13 = PACA 961 * ctr = orig r13 962 * orig r10 saved in PACA 963 */ 964TRAMP_KVM_BEGIN(do_kvm_0xc00) 965 /* 966 * Save the PPR (on systems that support it) before changing to 967 * HMT_MEDIUM. That allows the KVM code to save that value into the 968 * guest state (it is the guest's PPR value). 969 */ 970 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) 971 HMT_MEDIUM 972 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) 973 mfctr r10 974 SET_SCRATCH0(r10) 975 std r9,PACA_EXGEN+EX_R9(r13) 976 mfcr r9 977 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) 978#endif 979 980 981EXC_REAL(single_step, 0xd00, 0x100) 982EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 983TRAMP_KVM(PACA_EXGEN, 0xd00) 984EXC_COMMON(single_step_common, 0xd00, single_step_exception) 985 986EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 987EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 988TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 989EXC_COMMON_BEGIN(h_data_storage_common) 990 mfspr r10,SPRN_HDAR 991 std r10,PACA_EXGEN+EX_DAR(r13) 992 mfspr r10,SPRN_HDSISR 993 stw r10,PACA_EXGEN+EX_DSISR(r13) 994 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) 995 bl save_nvgprs 996 RECONCILE_IRQ_STATE(r10, r11) 997 addi r3,r1,STACK_FRAME_OVERHEAD 998 bl unknown_exception 999 b ret_from_except 1000 1001 1002EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 1003EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 1004TRAMP_KVM_HV(PACA_EXGEN, 0xe20) 1005EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 1006 1007 1008EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 1009EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 1010TRAMP_KVM_HV(PACA_EXGEN, 0xe40) 1011EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 1012 1013 1014/* 1015 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 1016 * first, and then eventaully from there to the trampoline to get into virtual 1017 * mode. 1018 */ 1019__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) 1020__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) 1021EXC_VIRT_NONE(0x4e60, 0x20) 1022TRAMP_KVM_HV(PACA_EXGEN, 0xe60) 1023TRAMP_REAL_BEGIN(hmi_exception_early) 1024 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) 1025 mr r10,r1 /* Save r1 */ 1026 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 1027 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1028 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 1029 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ 1030 EXCEPTION_PROLOG_COMMON_1() 1031 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 1032 EXCEPTION_PROLOG_COMMON_3(0xe60) 1033 addi r3,r1,STACK_FRAME_OVERHEAD 1034 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */ 1035 cmpdi cr0,r3,0 1036 1037 /* Windup the stack. */ 1038 /* Move original HSRR0 and HSRR1 into the respective regs */ 1039 ld r9,_MSR(r1) 1040 mtspr SPRN_HSRR1,r9 1041 ld r3,_NIP(r1) 1042 mtspr SPRN_HSRR0,r3 1043 ld r9,_CTR(r1) 1044 mtctr r9 1045 ld r9,_XER(r1) 1046 mtxer r9 1047 ld r9,_LINK(r1) 1048 mtlr r9 1049 REST_GPR(0, r1) 1050 REST_8GPRS(2, r1) 1051 REST_GPR(10, r1) 1052 ld r11,_CCR(r1) 1053 REST_2GPRS(12, r1) 1054 bne 1f 1055 mtcr r11 1056 REST_GPR(11, r1) 1057 ld r1,GPR1(r1) 1058 HRFI_TO_USER_OR_KERNEL 1059 10601: mtcr r11 1061 REST_GPR(11, r1) 1062 ld r1,GPR1(r1) 1063 1064 /* 1065 * Go to virtual mode and pull the HMI event information from 1066 * firmware. 1067 */ 1068 .globl hmi_exception_after_realmode 1069hmi_exception_after_realmode: 1070 SET_SCRATCH0(r13) 1071 EXCEPTION_PROLOG_0(PACA_EXGEN) 1072 b tramp_real_hmi_exception 1073 1074EXC_COMMON_BEGIN(hmi_exception_common) 1075EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception, 1076 ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON) 1077 1078EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) 1079EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) 1080TRAMP_KVM_HV(PACA_EXGEN, 0xe80) 1081#ifdef CONFIG_PPC_DOORBELL 1082EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 1083#else 1084EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 1085#endif 1086 1087 1088EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) 1089EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) 1090TRAMP_KVM_HV(PACA_EXGEN, 0xea0) 1091EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 1092 1093 1094EXC_REAL_NONE(0xec0, 0x20) 1095EXC_VIRT_NONE(0x4ec0, 0x20) 1096EXC_REAL_NONE(0xee0, 0x20) 1097EXC_VIRT_NONE(0x4ee0, 0x20) 1098 1099 1100EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) 1101EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) 1102TRAMP_KVM(PACA_EXGEN, 0xf00) 1103EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1104 1105 1106EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 1107EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1108TRAMP_KVM(PACA_EXGEN, 0xf20) 1109EXC_COMMON_BEGIN(altivec_unavailable_common) 1110 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1111#ifdef CONFIG_ALTIVEC 1112BEGIN_FTR_SECTION 1113 beq 1f 1114#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1115 BEGIN_FTR_SECTION_NESTED(69) 1116 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1117 * transaction), go do TM stuff 1118 */ 1119 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1120 bne- 2f 1121 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1122#endif 1123 bl load_up_altivec 1124 b fast_exception_return 1125#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 11262: /* User process was in a transaction */ 1127 bl save_nvgprs 1128 RECONCILE_IRQ_STATE(r10, r11) 1129 addi r3,r1,STACK_FRAME_OVERHEAD 1130 bl altivec_unavailable_tm 1131 b ret_from_except 1132#endif 11331: 1134END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1135#endif 1136 bl save_nvgprs 1137 RECONCILE_IRQ_STATE(r10, r11) 1138 addi r3,r1,STACK_FRAME_OVERHEAD 1139 bl altivec_unavailable_exception 1140 b ret_from_except 1141 1142 1143EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 1144EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1145TRAMP_KVM(PACA_EXGEN, 0xf40) 1146EXC_COMMON_BEGIN(vsx_unavailable_common) 1147 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 1148#ifdef CONFIG_VSX 1149BEGIN_FTR_SECTION 1150 beq 1f 1151#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1152 BEGIN_FTR_SECTION_NESTED(69) 1153 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1154 * transaction), go do TM stuff 1155 */ 1156 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1157 bne- 2f 1158 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1159#endif 1160 b load_up_vsx 1161#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 11622: /* User process was in a transaction */ 1163 bl save_nvgprs 1164 RECONCILE_IRQ_STATE(r10, r11) 1165 addi r3,r1,STACK_FRAME_OVERHEAD 1166 bl vsx_unavailable_tm 1167 b ret_from_except 1168#endif 11691: 1170END_FTR_SECTION_IFSET(CPU_FTR_VSX) 1171#endif 1172 bl save_nvgprs 1173 RECONCILE_IRQ_STATE(r10, r11) 1174 addi r3,r1,STACK_FRAME_OVERHEAD 1175 bl vsx_unavailable_exception 1176 b ret_from_except 1177 1178 1179EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 1180EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 1181TRAMP_KVM(PACA_EXGEN, 0xf60) 1182EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 1183 1184 1185EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 1186EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 1187TRAMP_KVM_HV(PACA_EXGEN, 0xf80) 1188EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 1189 1190 1191EXC_REAL_NONE(0xfa0, 0x20) 1192EXC_VIRT_NONE(0x4fa0, 0x20) 1193EXC_REAL_NONE(0xfc0, 0x20) 1194EXC_VIRT_NONE(0x4fc0, 0x20) 1195EXC_REAL_NONE(0xfe0, 0x20) 1196EXC_VIRT_NONE(0x4fe0, 0x20) 1197 1198EXC_REAL_NONE(0x1000, 0x100) 1199EXC_VIRT_NONE(0x5000, 0x100) 1200EXC_REAL_NONE(0x1100, 0x100) 1201EXC_VIRT_NONE(0x5100, 0x100) 1202 1203#ifdef CONFIG_CBE_RAS 1204EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 1205EXC_VIRT_NONE(0x5200, 0x100) 1206TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1207EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1208#else /* CONFIG_CBE_RAS */ 1209EXC_REAL_NONE(0x1200, 0x100) 1210EXC_VIRT_NONE(0x5200, 0x100) 1211#endif 1212 1213 1214EXC_REAL(instruction_breakpoint, 0x1300, 0x100) 1215EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1216TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 1217EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 1218 1219EXC_REAL_NONE(0x1400, 0x100) 1220EXC_VIRT_NONE(0x5400, 0x100) 1221 1222EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 1223 mtspr SPRN_SPRG_HSCRATCH0,r13 1224 EXCEPTION_PROLOG_0(PACA_EXGEN) 1225 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) 1226 1227#ifdef CONFIG_PPC_DENORMALISATION 1228 mfspr r10,SPRN_HSRR1 1229 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1230 bne+ denorm_assist 1231#endif 1232 1233 KVMTEST_HV(0x1500) 1234 EXCEPTION_PROLOG_2(denorm_common, EXC_HV) 1235EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1236 1237#ifdef CONFIG_PPC_DENORMALISATION 1238EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1239 b exc_real_0x1500_denorm_exception_hv 1240EXC_VIRT_END(denorm_exception, 0x5500, 0x100) 1241#else 1242EXC_VIRT_NONE(0x5500, 0x100) 1243#endif 1244 1245TRAMP_KVM_HV(PACA_EXGEN, 0x1500) 1246 1247#ifdef CONFIG_PPC_DENORMALISATION 1248TRAMP_REAL_BEGIN(denorm_assist) 1249BEGIN_FTR_SECTION 1250/* 1251 * To denormalise we need to move a copy of the register to itself. 1252 * For POWER6 do that here for all FP regs. 1253 */ 1254 mfmsr r10 1255 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1256 xori r10,r10,(MSR_FE0|MSR_FE1) 1257 mtmsrd r10 1258 sync 1259 1260#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 1261#define FMR4(n) FMR2(n) ; FMR2(n+2) 1262#define FMR8(n) FMR4(n) ; FMR4(n+4) 1263#define FMR16(n) FMR8(n) ; FMR8(n+8) 1264#define FMR32(n) FMR16(n) ; FMR16(n+16) 1265 FMR32(0) 1266 1267FTR_SECTION_ELSE 1268/* 1269 * To denormalise we need to move a copy of the register to itself. 1270 * For POWER7 do that here for the first 32 VSX registers only. 1271 */ 1272 mfmsr r10 1273 oris r10,r10,MSR_VSX@h 1274 mtmsrd r10 1275 sync 1276 1277#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) 1278#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) 1279#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) 1280#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) 1281#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) 1282 XVCPSGNDP32(0) 1283 1284ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1285 1286BEGIN_FTR_SECTION 1287 b denorm_done 1288END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1289/* 1290 * To denormalise we need to move a copy of the register to itself. 1291 * For POWER8 we need to do that for all 64 VSX registers 1292 */ 1293 XVCPSGNDP32(32) 1294denorm_done: 1295 mfspr r11,SPRN_HSRR0 1296 subi r11,r11,4 1297 mtspr SPRN_HSRR0,r11 1298 mtcrf 0x80,r9 1299 ld r9,PACA_EXGEN+EX_R9(r13) 1300 RESTORE_PPR_PACA(PACA_EXGEN, r10) 1301BEGIN_FTR_SECTION 1302 ld r10,PACA_EXGEN+EX_CFAR(r13) 1303 mtspr SPRN_CFAR,r10 1304END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1305 ld r10,PACA_EXGEN+EX_R10(r13) 1306 ld r11,PACA_EXGEN+EX_R11(r13) 1307 ld r12,PACA_EXGEN+EX_R12(r13) 1308 ld r13,PACA_EXGEN+EX_R13(r13) 1309 HRFI_TO_UNKNOWN 1310 b . 1311#endif 1312 1313EXC_COMMON(denorm_common, 0x1500, unknown_exception) 1314 1315 1316#ifdef CONFIG_CBE_RAS 1317EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 1318EXC_VIRT_NONE(0x5600, 0x100) 1319TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 1320EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1321#else /* CONFIG_CBE_RAS */ 1322EXC_REAL_NONE(0x1600, 0x100) 1323EXC_VIRT_NONE(0x5600, 0x100) 1324#endif 1325 1326 1327EXC_REAL(altivec_assist, 0x1700, 0x100) 1328EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 1329TRAMP_KVM(PACA_EXGEN, 0x1700) 1330#ifdef CONFIG_ALTIVEC 1331EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 1332#else 1333EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 1334#endif 1335 1336 1337#ifdef CONFIG_CBE_RAS 1338EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 1339EXC_VIRT_NONE(0x5800, 0x100) 1340TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 1341EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 1342#else /* CONFIG_CBE_RAS */ 1343EXC_REAL_NONE(0x1800, 0x100) 1344EXC_VIRT_NONE(0x5800, 0x100) 1345#endif 1346 1347#ifdef CONFIG_PPC_WATCHDOG 1348 1349#define MASKED_DEC_HANDLER_LABEL 3f 1350 1351#define MASKED_DEC_HANDLER(_H) \ 13523: /* soft-nmi */ \ 1353 std r12,PACA_EXGEN+EX_R12(r13); \ 1354 GET_SCRATCH0(r10); \ 1355 std r10,PACA_EXGEN+EX_R13(r13); \ 1356 EXCEPTION_PROLOG_2(soft_nmi_common, _H) 1357 1358/* 1359 * Branch to soft_nmi_interrupt using the emergency stack. The emergency 1360 * stack is one that is usable by maskable interrupts so long as MSR_EE 1361 * remains off. It is used for recovery when something has corrupted the 1362 * normal kernel stack, for example. The "soft NMI" must not use the process 1363 * stack because we want irq disabled sections to avoid touching the stack 1364 * at all (other than PMU interrupts), so use the emergency stack for this, 1365 * and run it entirely with interrupts hard disabled. 1366 */ 1367EXC_COMMON_BEGIN(soft_nmi_common) 1368 mr r10,r1 1369 ld r1,PACAEMERGSP(r13) 1370 subi r1,r1,INT_FRAME_SIZE 1371 EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, 1372 system_reset, soft_nmi_interrupt, 1373 ADD_NVGPRS;ADD_RECONCILE) 1374 b ret_from_except 1375 1376#else /* CONFIG_PPC_WATCHDOG */ 1377#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ 1378#define MASKED_DEC_HANDLER(_H) 1379#endif /* CONFIG_PPC_WATCHDOG */ 1380 1381/* 1382 * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 1383 * - If it was a decrementer interrupt, we bump the dec to max and and return. 1384 * - If it was a doorbell we return immediately since doorbells are edge 1385 * triggered and won't automatically refire. 1386 * - If it was a HMI we return immediately since we handled it in realmode 1387 * and it won't refire. 1388 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. 1389 * This is called with r10 containing the value to OR to the paca field. 1390 */ 1391#define MASKED_INTERRUPT(_H) \ 1392masked_##_H##interrupt: \ 1393 std r11,PACA_EXGEN+EX_R11(r13); \ 1394 lbz r11,PACAIRQHAPPENED(r13); \ 1395 or r11,r11,r10; \ 1396 stb r11,PACAIRQHAPPENED(r13); \ 1397 cmpwi r10,PACA_IRQ_DEC; \ 1398 bne 1f; \ 1399 lis r10,0x7fff; \ 1400 ori r10,r10,0xffff; \ 1401 mtspr SPRN_DEC,r10; \ 1402 b MASKED_DEC_HANDLER_LABEL; \ 14031: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK; \ 1404 beq 2f; \ 1405 mfspr r10,SPRN_##_H##SRR1; \ 1406 xori r10,r10,MSR_EE; /* clear MSR_EE */ \ 1407 mtspr SPRN_##_H##SRR1,r10; \ 1408 ori r11,r11,PACA_IRQ_HARD_DIS; \ 1409 stb r11,PACAIRQHAPPENED(r13); \ 14102: /* done */ \ 1411 mtcrf 0x80,r9; \ 1412 std r1,PACAR1(r13); \ 1413 ld r9,PACA_EXGEN+EX_R9(r13); \ 1414 ld r10,PACA_EXGEN+EX_R10(r13); \ 1415 ld r11,PACA_EXGEN+EX_R11(r13); \ 1416 /* returns to kernel where r13 must be set up, so don't restore it */ \ 1417 ##_H##RFI_TO_KERNEL; \ 1418 b .; \ 1419 MASKED_DEC_HANDLER(_H) 1420 1421TRAMP_REAL_BEGIN(stf_barrier_fallback) 1422 std r9,PACA_EXRFI+EX_R9(r13) 1423 std r10,PACA_EXRFI+EX_R10(r13) 1424 sync 1425 ld r9,PACA_EXRFI+EX_R9(r13) 1426 ld r10,PACA_EXRFI+EX_R10(r13) 1427 ori 31,31,0 1428 .rept 14 1429 b 1f 14301: 1431 .endr 1432 blr 1433 1434TRAMP_REAL_BEGIN(rfi_flush_fallback) 1435 SET_SCRATCH0(r13); 1436 GET_PACA(r13); 1437 std r1,PACA_EXRFI+EX_R12(r13) 1438 ld r1,PACAKSAVE(r13) 1439 std r9,PACA_EXRFI+EX_R9(r13) 1440 std r10,PACA_EXRFI+EX_R10(r13) 1441 std r11,PACA_EXRFI+EX_R11(r13) 1442 mfctr r9 1443 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 1444 ld r11,PACA_L1D_FLUSH_SIZE(r13) 1445 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 1446 mtctr r11 1447 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 1448 1449 /* order ld/st prior to dcbt stop all streams with flushing */ 1450 sync 1451 1452 /* 1453 * The load adresses are at staggered offsets within cachelines, 1454 * which suits some pipelines better (on others it should not 1455 * hurt). 1456 */ 14571: 1458 ld r11,(0x80 + 8)*0(r10) 1459 ld r11,(0x80 + 8)*1(r10) 1460 ld r11,(0x80 + 8)*2(r10) 1461 ld r11,(0x80 + 8)*3(r10) 1462 ld r11,(0x80 + 8)*4(r10) 1463 ld r11,(0x80 + 8)*5(r10) 1464 ld r11,(0x80 + 8)*6(r10) 1465 ld r11,(0x80 + 8)*7(r10) 1466 addi r10,r10,0x80*8 1467 bdnz 1b 1468 1469 mtctr r9 1470 ld r9,PACA_EXRFI+EX_R9(r13) 1471 ld r10,PACA_EXRFI+EX_R10(r13) 1472 ld r11,PACA_EXRFI+EX_R11(r13) 1473 ld r1,PACA_EXRFI+EX_R12(r13) 1474 GET_SCRATCH0(r13); 1475 rfid 1476 1477TRAMP_REAL_BEGIN(hrfi_flush_fallback) 1478 SET_SCRATCH0(r13); 1479 GET_PACA(r13); 1480 std r1,PACA_EXRFI+EX_R12(r13) 1481 ld r1,PACAKSAVE(r13) 1482 std r9,PACA_EXRFI+EX_R9(r13) 1483 std r10,PACA_EXRFI+EX_R10(r13) 1484 std r11,PACA_EXRFI+EX_R11(r13) 1485 mfctr r9 1486 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 1487 ld r11,PACA_L1D_FLUSH_SIZE(r13) 1488 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 1489 mtctr r11 1490 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 1491 1492 /* order ld/st prior to dcbt stop all streams with flushing */ 1493 sync 1494 1495 /* 1496 * The load adresses are at staggered offsets within cachelines, 1497 * which suits some pipelines better (on others it should not 1498 * hurt). 1499 */ 15001: 1501 ld r11,(0x80 + 8)*0(r10) 1502 ld r11,(0x80 + 8)*1(r10) 1503 ld r11,(0x80 + 8)*2(r10) 1504 ld r11,(0x80 + 8)*3(r10) 1505 ld r11,(0x80 + 8)*4(r10) 1506 ld r11,(0x80 + 8)*5(r10) 1507 ld r11,(0x80 + 8)*6(r10) 1508 ld r11,(0x80 + 8)*7(r10) 1509 addi r10,r10,0x80*8 1510 bdnz 1b 1511 1512 mtctr r9 1513 ld r9,PACA_EXRFI+EX_R9(r13) 1514 ld r10,PACA_EXRFI+EX_R10(r13) 1515 ld r11,PACA_EXRFI+EX_R11(r13) 1516 ld r1,PACA_EXRFI+EX_R12(r13) 1517 GET_SCRATCH0(r13); 1518 hrfid 1519 1520/* 1521 * Real mode exceptions actually use this too, but alternate 1522 * instruction code patches (which end up in the common .text area) 1523 * cannot reach these if they are put there. 1524 */ 1525USE_FIXED_SECTION(virt_trampolines) 1526 MASKED_INTERRUPT() 1527 MASKED_INTERRUPT(H) 1528 1529#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1530TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 1531 /* 1532 * Here all GPRs are unchanged from when the interrupt happened 1533 * except for r13, which is saved in SPRG_SCRATCH0. 1534 */ 1535 mfspr r13, SPRN_SRR0 1536 addi r13, r13, 4 1537 mtspr SPRN_SRR0, r13 1538 GET_SCRATCH0(r13) 1539 RFI_TO_KERNEL 1540 b . 1541 1542TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 1543 /* 1544 * Here all GPRs are unchanged from when the interrupt happened 1545 * except for r13, which is saved in SPRG_SCRATCH0. 1546 */ 1547 mfspr r13, SPRN_HSRR0 1548 addi r13, r13, 4 1549 mtspr SPRN_HSRR0, r13 1550 GET_SCRATCH0(r13) 1551 HRFI_TO_KERNEL 1552 b . 1553#endif 1554 1555/* 1556 * Ensure that any handlers that get invoked from the exception prologs 1557 * above are below the first 64KB (0x10000) of the kernel image because 1558 * the prologs assemble the addresses of these handlers using the 1559 * LOAD_HANDLER macro, which uses an ori instruction. 1560 */ 1561 1562/*** Common interrupt handlers ***/ 1563 1564 1565 /* 1566 * Relocation-on interrupts: A subset of the interrupts can be delivered 1567 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 1568 * it. Addresses are the same as the original interrupt addresses, but 1569 * offset by 0xc000000000004000. 1570 * It's impossible to receive interrupts below 0x300 via this mechanism. 1571 * KVM: None of these traps are from the guest ; anything that escalated 1572 * to HV=1 from HV=0 is delivered via real mode handlers. 1573 */ 1574 1575 /* 1576 * This uses the standard macro, since the original 0x300 vector 1577 * only has extra guff for STAB-based processors -- which never 1578 * come here. 1579 */ 1580 1581EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 1582 b __ppc64_runlatch_on 1583 1584USE_FIXED_SECTION(virt_trampolines) 1585 /* 1586 * The __end_interrupts marker must be past the out-of-line (OOL) 1587 * handlers, so that they are copied to real address 0x100 when running 1588 * a relocatable kernel. This ensures they can be reached from the short 1589 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 1590 * directly, without using LOAD_HANDLER(). 1591 */ 1592 .align 7 1593 .globl __end_interrupts 1594__end_interrupts: 1595DEFINE_FIXED_SYMBOL(__end_interrupts) 1596 1597#ifdef CONFIG_PPC_970_NAP 1598EXC_COMMON_BEGIN(power4_fixup_nap) 1599 andc r9,r9,r10 1600 std r9,TI_LOCAL_FLAGS(r11) 1601 ld r10,_LINK(r1) /* make idle task do the */ 1602 std r10,_NIP(r1) /* equivalent of a blr */ 1603 blr 1604#endif 1605 1606CLOSE_FIXED_SECTION(real_vectors); 1607CLOSE_FIXED_SECTION(real_trampolines); 1608CLOSE_FIXED_SECTION(virt_vectors); 1609CLOSE_FIXED_SECTION(virt_trampolines); 1610 1611USE_TEXT_SECTION() 1612 1613/* 1614 * Hash table stuff 1615 */ 1616 .balign IFETCH_ALIGN_BYTES 1617do_hash_page: 1618#ifdef CONFIG_PPC_BOOK3S_64 1619 lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h 1620 ori r0,r0,DSISR_BAD_FAULT_64S@l 1621 and. r0,r4,r0 /* weird error? */ 1622 bne- handle_page_fault /* if not, try to insert a HPTE */ 1623 CURRENT_THREAD_INFO(r11, r1) 1624 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 1625 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 1626 bne 77f /* then don't call hash_page now */ 1627 1628 /* 1629 * r3 contains the faulting address 1630 * r4 msr 1631 * r5 contains the trap number 1632 * r6 contains dsisr 1633 * 1634 * at return r3 = 0 for success, 1 for page fault, negative for error 1635 */ 1636 mr r4,r12 1637 ld r6,_DSISR(r1) 1638 bl __hash_page /* build HPTE if possible */ 1639 cmpdi r3,0 /* see if __hash_page succeeded */ 1640 1641 /* Success */ 1642 beq fast_exc_return_irq /* Return from exception on success */ 1643 1644 /* Error */ 1645 blt- 13f 1646 1647 /* Reload DSISR into r4 for the DABR check below */ 1648 ld r4,_DSISR(r1) 1649#endif /* CONFIG_PPC_BOOK3S_64 */ 1650 1651/* Here we have a page fault that hash_page can't handle. */ 1652handle_page_fault: 165311: andis. r0,r4,DSISR_DABRMATCH@h 1654 bne- handle_dabr_fault 1655 ld r4,_DAR(r1) 1656 ld r5,_DSISR(r1) 1657 addi r3,r1,STACK_FRAME_OVERHEAD 1658 bl do_page_fault 1659 cmpdi r3,0 1660 beq+ 12f 1661 bl save_nvgprs 1662 mr r5,r3 1663 addi r3,r1,STACK_FRAME_OVERHEAD 1664 lwz r4,_DAR(r1) 1665 bl bad_page_fault 1666 b ret_from_except 1667 1668/* We have a data breakpoint exception - handle it */ 1669handle_dabr_fault: 1670 bl save_nvgprs 1671 ld r4,_DAR(r1) 1672 ld r5,_DSISR(r1) 1673 addi r3,r1,STACK_FRAME_OVERHEAD 1674 bl do_break 167512: b ret_from_except_lite 1676 1677 1678#ifdef CONFIG_PPC_BOOK3S_64 1679/* We have a page fault that hash_page could handle but HV refused 1680 * the PTE insertion 1681 */ 168213: bl save_nvgprs 1683 mr r5,r3 1684 addi r3,r1,STACK_FRAME_OVERHEAD 1685 ld r4,_DAR(r1) 1686 bl low_hash_fault 1687 b ret_from_except 1688#endif 1689 1690/* 1691 * We come here as a result of a DSI at a point where we don't want 1692 * to call hash_page, such as when we are accessing memory (possibly 1693 * user memory) inside a PMU interrupt that occurred while interrupts 1694 * were soft-disabled. We want to invoke the exception handler for 1695 * the access, or panic if there isn't a handler. 1696 */ 169777: bl save_nvgprs 1698 mr r4,r3 1699 addi r3,r1,STACK_FRAME_OVERHEAD 1700 li r5,SIGSEGV 1701 bl bad_page_fault 1702 b ret_from_except 1703 1704/* 1705 * Here we have detected that the kernel stack pointer is bad. 1706 * R9 contains the saved CR, r13 points to the paca, 1707 * r10 contains the (bad) kernel stack pointer, 1708 * r11 and r12 contain the saved SRR0 and SRR1. 1709 * We switch to using an emergency stack, save the registers there, 1710 * and call kernel_bad_stack(), which panics. 1711 */ 1712bad_stack: 1713 ld r1,PACAEMERGSP(r13) 1714 subi r1,r1,64+INT_FRAME_SIZE 1715 std r9,_CCR(r1) 1716 std r10,GPR1(r1) 1717 std r11,_NIP(r1) 1718 std r12,_MSR(r1) 1719 mfspr r11,SPRN_DAR 1720 mfspr r12,SPRN_DSISR 1721 std r11,_DAR(r1) 1722 std r12,_DSISR(r1) 1723 mflr r10 1724 mfctr r11 1725 mfxer r12 1726 std r10,_LINK(r1) 1727 std r11,_CTR(r1) 1728 std r12,_XER(r1) 1729 SAVE_GPR(0,r1) 1730 SAVE_GPR(2,r1) 1731 ld r10,EX_R3(r3) 1732 std r10,GPR3(r1) 1733 SAVE_GPR(4,r1) 1734 SAVE_4GPRS(5,r1) 1735 ld r9,EX_R9(r3) 1736 ld r10,EX_R10(r3) 1737 SAVE_2GPRS(9,r1) 1738 ld r9,EX_R11(r3) 1739 ld r10,EX_R12(r3) 1740 ld r11,EX_R13(r3) 1741 std r9,GPR11(r1) 1742 std r10,GPR12(r1) 1743 std r11,GPR13(r1) 1744BEGIN_FTR_SECTION 1745 ld r10,EX_CFAR(r3) 1746 std r10,ORIG_GPR3(r1) 1747END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1748 SAVE_8GPRS(14,r1) 1749 SAVE_10GPRS(22,r1) 1750 lhz r12,PACA_TRAP_SAVE(r13) 1751 std r12,_TRAP(r1) 1752 addi r11,r1,INT_FRAME_SIZE 1753 std r11,0(r1) 1754 li r12,0 1755 std r12,0(r11) 1756 ld r2,PACATOC(r13) 1757 ld r11,exception_marker@toc(r2) 1758 std r12,RESULT(r1) 1759 std r11,STACK_FRAME_OVERHEAD-16(r1) 17601: addi r3,r1,STACK_FRAME_OVERHEAD 1761 bl kernel_bad_stack 1762 b 1b 1763_ASM_NOKPROBE_SYMBOL(bad_stack); 1764 1765/* 1766 * When doorbell is triggered from system reset wakeup, the message is 1767 * not cleared, so it would fire again when EE is enabled. 1768 * 1769 * When coming from local_irq_enable, there may be the same problem if 1770 * we were hard disabled. 1771 * 1772 * Execute msgclr to clear pending exceptions before handling it. 1773 */ 1774h_doorbell_common_msgclr: 1775 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1776 PPC_MSGCLR(3) 1777 b h_doorbell_common 1778 1779doorbell_super_common_msgclr: 1780 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1781 PPC_MSGCLRP(3) 1782 b doorbell_super_common 1783 1784/* 1785 * Called from arch_local_irq_enable when an interrupt needs 1786 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 1787 * which kind of interrupt. MSR:EE is already off. We generate a 1788 * stackframe like if a real interrupt had happened. 1789 * 1790 * Note: While MSR:EE is off, we need to make sure that _MSR 1791 * in the generated frame has EE set to 1 or the exception 1792 * handler will not properly re-enable them. 1793 * 1794 * Note that we don't specify LR as the NIP (return address) for 1795 * the interrupt because that would unbalance the return branch 1796 * predictor. 1797 */ 1798_GLOBAL(__replay_interrupt) 1799 /* We are going to jump to the exception common code which 1800 * will retrieve various register values from the PACA which 1801 * we don't give a damn about, so we don't bother storing them. 1802 */ 1803 mfmsr r12 1804 LOAD_REG_ADDR(r11, replay_interrupt_return) 1805 mfcr r9 1806 ori r12,r12,MSR_EE 1807 cmpwi r3,0x900 1808 beq decrementer_common 1809 cmpwi r3,0x500 1810BEGIN_FTR_SECTION 1811 beq h_virt_irq_common 1812FTR_SECTION_ELSE 1813 beq hardware_interrupt_common 1814ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) 1815 cmpwi r3,0xf00 1816 beq performance_monitor_common 1817BEGIN_FTR_SECTION 1818 cmpwi r3,0xa00 1819 beq h_doorbell_common_msgclr 1820 cmpwi r3,0xe60 1821 beq hmi_exception_common 1822FTR_SECTION_ELSE 1823 cmpwi r3,0xa00 1824 beq doorbell_super_common_msgclr 1825ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1826replay_interrupt_return: 1827 blr 1828 1829_ASM_NOKPROBE_SYMBOL(__replay_interrupt) 1830